1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * File: drivers/pci/pcie/aspm.c 4 * Enabling PCIe link L0s/L1 state and Clock Power Management 5 * 6 * Copyright (C) 2007 Intel 7 * Copyright (C) Zhang Yanmin (yanmin.zhang@intel.com) 8 * Copyright (C) Shaohua Li (shaohua.li@intel.com) 9 */ 10 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/moduleparam.h> 14 #include <linux/pci.h> 15 #include <linux/pci_regs.h> 16 #include <linux/errno.h> 17 #include <linux/pm.h> 18 #include <linux/init.h> 19 #include <linux/slab.h> 20 #include <linux/jiffies.h> 21 #include <linux/delay.h> 22 #include <linux/pci-aspm.h> 23 #include "../pci.h" 24 25 #ifdef MODULE_PARAM_PREFIX 26 #undef MODULE_PARAM_PREFIX 27 #endif 28 #define MODULE_PARAM_PREFIX "pcie_aspm." 29 30 /* Note: those are not register definitions */ 31 #define ASPM_STATE_L0S_UP (1) /* Upstream direction L0s state */ 32 #define ASPM_STATE_L0S_DW (2) /* Downstream direction L0s state */ 33 #define ASPM_STATE_L1 (4) /* L1 state */ 34 #define ASPM_STATE_L1_1 (8) /* ASPM L1.1 state */ 35 #define ASPM_STATE_L1_2 (0x10) /* ASPM L1.2 state */ 36 #define ASPM_STATE_L1_1_PCIPM (0x20) /* PCI PM L1.1 state */ 37 #define ASPM_STATE_L1_2_PCIPM (0x40) /* PCI PM L1.2 state */ 38 #define ASPM_STATE_L1_SS_PCIPM (ASPM_STATE_L1_1_PCIPM | ASPM_STATE_L1_2_PCIPM) 39 #define ASPM_STATE_L1_2_MASK (ASPM_STATE_L1_2 | ASPM_STATE_L1_2_PCIPM) 40 #define ASPM_STATE_L1SS (ASPM_STATE_L1_1 | ASPM_STATE_L1_1_PCIPM |\ 41 ASPM_STATE_L1_2_MASK) 42 #define ASPM_STATE_L0S (ASPM_STATE_L0S_UP | ASPM_STATE_L0S_DW) 43 #define ASPM_STATE_ALL (ASPM_STATE_L0S | ASPM_STATE_L1 | \ 44 ASPM_STATE_L1SS) 45 46 /* 47 * When L1 substates are enabled, the LTR L1.2 threshold is a timing parameter 48 * that decides whether L1.1 or L1.2 is entered (Refer PCIe spec for details). 49 * Not sure is there is a way to "calculate" this on the fly, but maybe we 50 * could turn it into a parameter in future. This value has been taken from 51 * the following files from Intel's coreboot (which is the only code I found 52 * to have used this): 53 * https://www.coreboot.org/pipermail/coreboot-gerrit/2015-March/021134.html 54 * https://review.coreboot.org/#/c/8832/ 55 */ 56 #define LTR_L1_2_THRESHOLD_BITS ((1 << 21) | (1 << 23) | (1 << 30)) 57 58 struct aspm_latency { 59 u32 l0s; /* L0s latency (nsec) */ 60 u32 l1; /* L1 latency (nsec) */ 61 }; 62 63 struct pcie_link_state { 64 struct pci_dev *pdev; /* Upstream component of the Link */ 65 struct pci_dev *downstream; /* Downstream component, function 0 */ 66 struct pcie_link_state *root; /* pointer to the root port link */ 67 struct pcie_link_state *parent; /* pointer to the parent Link state */ 68 struct list_head sibling; /* node in link_list */ 69 struct list_head children; /* list of child link states */ 70 struct list_head link; /* node in parent's children list */ 71 72 /* ASPM state */ 73 u32 aspm_support:7; /* Supported ASPM state */ 74 u32 aspm_enabled:7; /* Enabled ASPM state */ 75 u32 aspm_capable:7; /* Capable ASPM state with latency */ 76 u32 aspm_default:7; /* Default ASPM state by BIOS */ 77 u32 aspm_disable:7; /* Disabled ASPM state */ 78 79 /* Clock PM state */ 80 u32 clkpm_capable:1; /* Clock PM capable? */ 81 u32 clkpm_enabled:1; /* Current Clock PM state */ 82 u32 clkpm_default:1; /* Default Clock PM state by BIOS */ 83 84 /* Exit latencies */ 85 struct aspm_latency latency_up; /* Upstream direction exit latency */ 86 struct aspm_latency latency_dw; /* Downstream direction exit latency */ 87 /* 88 * Endpoint acceptable latencies. A pcie downstream port only 89 * has one slot under it, so at most there are 8 functions. 90 */ 91 struct aspm_latency acceptable[8]; 92 93 /* L1 PM Substate info */ 94 struct { 95 u32 up_cap_ptr; /* L1SS cap ptr in upstream dev */ 96 u32 dw_cap_ptr; /* L1SS cap ptr in downstream dev */ 97 u32 ctl1; /* value to be programmed in ctl1 */ 98 u32 ctl2; /* value to be programmed in ctl2 */ 99 } l1ss; 100 }; 101 102 static int aspm_disabled, aspm_force; 103 static bool aspm_support_enabled = true; 104 static DEFINE_MUTEX(aspm_lock); 105 static LIST_HEAD(link_list); 106 107 #define POLICY_DEFAULT 0 /* BIOS default setting */ 108 #define POLICY_PERFORMANCE 1 /* high performance */ 109 #define POLICY_POWERSAVE 2 /* high power saving */ 110 #define POLICY_POWER_SUPERSAVE 3 /* possibly even more power saving */ 111 112 #ifdef CONFIG_PCIEASPM_PERFORMANCE 113 static int aspm_policy = POLICY_PERFORMANCE; 114 #elif defined CONFIG_PCIEASPM_POWERSAVE 115 static int aspm_policy = POLICY_POWERSAVE; 116 #elif defined CONFIG_PCIEASPM_POWER_SUPERSAVE 117 static int aspm_policy = POLICY_POWER_SUPERSAVE; 118 #else 119 static int aspm_policy; 120 #endif 121 122 static const char *policy_str[] = { 123 [POLICY_DEFAULT] = "default", 124 [POLICY_PERFORMANCE] = "performance", 125 [POLICY_POWERSAVE] = "powersave", 126 [POLICY_POWER_SUPERSAVE] = "powersupersave" 127 }; 128 129 #define LINK_RETRAIN_TIMEOUT HZ 130 131 static int policy_to_aspm_state(struct pcie_link_state *link) 132 { 133 switch (aspm_policy) { 134 case POLICY_PERFORMANCE: 135 /* Disable ASPM and Clock PM */ 136 return 0; 137 case POLICY_POWERSAVE: 138 /* Enable ASPM L0s/L1 */ 139 return (ASPM_STATE_L0S | ASPM_STATE_L1); 140 case POLICY_POWER_SUPERSAVE: 141 /* Enable Everything */ 142 return ASPM_STATE_ALL; 143 case POLICY_DEFAULT: 144 return link->aspm_default; 145 } 146 return 0; 147 } 148 149 static int policy_to_clkpm_state(struct pcie_link_state *link) 150 { 151 switch (aspm_policy) { 152 case POLICY_PERFORMANCE: 153 /* Disable ASPM and Clock PM */ 154 return 0; 155 case POLICY_POWERSAVE: 156 case POLICY_POWER_SUPERSAVE: 157 /* Enable Clock PM */ 158 return 1; 159 case POLICY_DEFAULT: 160 return link->clkpm_default; 161 } 162 return 0; 163 } 164 165 static void pcie_set_clkpm_nocheck(struct pcie_link_state *link, int enable) 166 { 167 struct pci_dev *child; 168 struct pci_bus *linkbus = link->pdev->subordinate; 169 u32 val = enable ? PCI_EXP_LNKCTL_CLKREQ_EN : 0; 170 171 list_for_each_entry(child, &linkbus->devices, bus_list) 172 pcie_capability_clear_and_set_word(child, PCI_EXP_LNKCTL, 173 PCI_EXP_LNKCTL_CLKREQ_EN, 174 val); 175 link->clkpm_enabled = !!enable; 176 } 177 178 static void pcie_set_clkpm(struct pcie_link_state *link, int enable) 179 { 180 /* Don't enable Clock PM if the link is not Clock PM capable */ 181 if (!link->clkpm_capable) 182 enable = 0; 183 /* Need nothing if the specified equals to current state */ 184 if (link->clkpm_enabled == enable) 185 return; 186 pcie_set_clkpm_nocheck(link, enable); 187 } 188 189 static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist) 190 { 191 int capable = 1, enabled = 1; 192 u32 reg32; 193 u16 reg16; 194 struct pci_dev *child; 195 struct pci_bus *linkbus = link->pdev->subordinate; 196 197 /* All functions should have the same cap and state, take the worst */ 198 list_for_each_entry(child, &linkbus->devices, bus_list) { 199 pcie_capability_read_dword(child, PCI_EXP_LNKCAP, ®32); 200 if (!(reg32 & PCI_EXP_LNKCAP_CLKPM)) { 201 capable = 0; 202 enabled = 0; 203 break; 204 } 205 pcie_capability_read_word(child, PCI_EXP_LNKCTL, ®16); 206 if (!(reg16 & PCI_EXP_LNKCTL_CLKREQ_EN)) 207 enabled = 0; 208 } 209 link->clkpm_enabled = enabled; 210 link->clkpm_default = enabled; 211 link->clkpm_capable = (blacklist) ? 0 : capable; 212 } 213 214 /* 215 * pcie_aspm_configure_common_clock: check if the 2 ends of a link 216 * could use common clock. If they are, configure them to use the 217 * common clock. That will reduce the ASPM state exit latency. 218 */ 219 static void pcie_aspm_configure_common_clock(struct pcie_link_state *link) 220 { 221 int same_clock = 1; 222 u16 reg16, parent_reg, child_reg[8]; 223 unsigned long start_jiffies; 224 struct pci_dev *child, *parent = link->pdev; 225 struct pci_bus *linkbus = parent->subordinate; 226 /* 227 * All functions of a slot should have the same Slot Clock 228 * Configuration, so just check one function 229 */ 230 child = list_entry(linkbus->devices.next, struct pci_dev, bus_list); 231 BUG_ON(!pci_is_pcie(child)); 232 233 /* Check downstream component if bit Slot Clock Configuration is 1 */ 234 pcie_capability_read_word(child, PCI_EXP_LNKSTA, ®16); 235 if (!(reg16 & PCI_EXP_LNKSTA_SLC)) 236 same_clock = 0; 237 238 /* Check upstream component if bit Slot Clock Configuration is 1 */ 239 pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16); 240 if (!(reg16 & PCI_EXP_LNKSTA_SLC)) 241 same_clock = 0; 242 243 /* Configure downstream component, all functions */ 244 list_for_each_entry(child, &linkbus->devices, bus_list) { 245 pcie_capability_read_word(child, PCI_EXP_LNKCTL, ®16); 246 child_reg[PCI_FUNC(child->devfn)] = reg16; 247 if (same_clock) 248 reg16 |= PCI_EXP_LNKCTL_CCC; 249 else 250 reg16 &= ~PCI_EXP_LNKCTL_CCC; 251 pcie_capability_write_word(child, PCI_EXP_LNKCTL, reg16); 252 } 253 254 /* Configure upstream component */ 255 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16); 256 parent_reg = reg16; 257 if (same_clock) 258 reg16 |= PCI_EXP_LNKCTL_CCC; 259 else 260 reg16 &= ~PCI_EXP_LNKCTL_CCC; 261 pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16); 262 263 /* Retrain link */ 264 reg16 |= PCI_EXP_LNKCTL_RL; 265 pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16); 266 267 /* Wait for link training end. Break out after waiting for timeout */ 268 start_jiffies = jiffies; 269 for (;;) { 270 pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16); 271 if (!(reg16 & PCI_EXP_LNKSTA_LT)) 272 break; 273 if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT)) 274 break; 275 msleep(1); 276 } 277 if (!(reg16 & PCI_EXP_LNKSTA_LT)) 278 return; 279 280 /* Training failed. Restore common clock configurations */ 281 dev_err(&parent->dev, "ASPM: Could not configure common clock\n"); 282 list_for_each_entry(child, &linkbus->devices, bus_list) 283 pcie_capability_write_word(child, PCI_EXP_LNKCTL, 284 child_reg[PCI_FUNC(child->devfn)]); 285 pcie_capability_write_word(parent, PCI_EXP_LNKCTL, parent_reg); 286 } 287 288 /* Convert L0s latency encoding to ns */ 289 static u32 calc_l0s_latency(u32 encoding) 290 { 291 if (encoding == 0x7) 292 return (5 * 1000); /* > 4us */ 293 return (64 << encoding); 294 } 295 296 /* Convert L0s acceptable latency encoding to ns */ 297 static u32 calc_l0s_acceptable(u32 encoding) 298 { 299 if (encoding == 0x7) 300 return -1U; 301 return (64 << encoding); 302 } 303 304 /* Convert L1 latency encoding to ns */ 305 static u32 calc_l1_latency(u32 encoding) 306 { 307 if (encoding == 0x7) 308 return (65 * 1000); /* > 64us */ 309 return (1000 << encoding); 310 } 311 312 /* Convert L1 acceptable latency encoding to ns */ 313 static u32 calc_l1_acceptable(u32 encoding) 314 { 315 if (encoding == 0x7) 316 return -1U; 317 return (1000 << encoding); 318 } 319 320 /* Convert L1SS T_pwr encoding to usec */ 321 static u32 calc_l1ss_pwron(struct pci_dev *pdev, u32 scale, u32 val) 322 { 323 switch (scale) { 324 case 0: 325 return val * 2; 326 case 1: 327 return val * 10; 328 case 2: 329 return val * 100; 330 } 331 dev_err(&pdev->dev, "%s: Invalid T_PwrOn scale: %u\n", 332 __func__, scale); 333 return 0; 334 } 335 336 struct aspm_register_info { 337 u32 support:2; 338 u32 enabled:2; 339 u32 latency_encoding_l0s; 340 u32 latency_encoding_l1; 341 342 /* L1 substates */ 343 u32 l1ss_cap_ptr; 344 u32 l1ss_cap; 345 u32 l1ss_ctl1; 346 u32 l1ss_ctl2; 347 }; 348 349 static void pcie_get_aspm_reg(struct pci_dev *pdev, 350 struct aspm_register_info *info) 351 { 352 u16 reg16; 353 u32 reg32; 354 355 pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, ®32); 356 info->support = (reg32 & PCI_EXP_LNKCAP_ASPMS) >> 10; 357 info->latency_encoding_l0s = (reg32 & PCI_EXP_LNKCAP_L0SEL) >> 12; 358 info->latency_encoding_l1 = (reg32 & PCI_EXP_LNKCAP_L1EL) >> 15; 359 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, ®16); 360 info->enabled = reg16 & PCI_EXP_LNKCTL_ASPMC; 361 362 /* Read L1 PM substate capabilities */ 363 info->l1ss_cap = info->l1ss_ctl1 = info->l1ss_ctl2 = 0; 364 info->l1ss_cap_ptr = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS); 365 if (!info->l1ss_cap_ptr) 366 return; 367 pci_read_config_dword(pdev, info->l1ss_cap_ptr + PCI_L1SS_CAP, 368 &info->l1ss_cap); 369 if (!(info->l1ss_cap & PCI_L1SS_CAP_L1_PM_SS)) { 370 info->l1ss_cap = 0; 371 return; 372 } 373 pci_read_config_dword(pdev, info->l1ss_cap_ptr + PCI_L1SS_CTL1, 374 &info->l1ss_ctl1); 375 pci_read_config_dword(pdev, info->l1ss_cap_ptr + PCI_L1SS_CTL2, 376 &info->l1ss_ctl2); 377 } 378 379 static void pcie_aspm_check_latency(struct pci_dev *endpoint) 380 { 381 u32 latency, l1_switch_latency = 0; 382 struct aspm_latency *acceptable; 383 struct pcie_link_state *link; 384 385 /* Device not in D0 doesn't need latency check */ 386 if ((endpoint->current_state != PCI_D0) && 387 (endpoint->current_state != PCI_UNKNOWN)) 388 return; 389 390 link = endpoint->bus->self->link_state; 391 acceptable = &link->acceptable[PCI_FUNC(endpoint->devfn)]; 392 393 while (link) { 394 /* Check upstream direction L0s latency */ 395 if ((link->aspm_capable & ASPM_STATE_L0S_UP) && 396 (link->latency_up.l0s > acceptable->l0s)) 397 link->aspm_capable &= ~ASPM_STATE_L0S_UP; 398 399 /* Check downstream direction L0s latency */ 400 if ((link->aspm_capable & ASPM_STATE_L0S_DW) && 401 (link->latency_dw.l0s > acceptable->l0s)) 402 link->aspm_capable &= ~ASPM_STATE_L0S_DW; 403 /* 404 * Check L1 latency. 405 * Every switch on the path to root complex need 1 406 * more microsecond for L1. Spec doesn't mention L0s. 407 * 408 * The exit latencies for L1 substates are not advertised 409 * by a device. Since the spec also doesn't mention a way 410 * to determine max latencies introduced by enabling L1 411 * substates on the components, it is not clear how to do 412 * a L1 substate exit latency check. We assume that the 413 * L1 exit latencies advertised by a device include L1 414 * substate latencies (and hence do not do any check). 415 */ 416 latency = max_t(u32, link->latency_up.l1, link->latency_dw.l1); 417 if ((link->aspm_capable & ASPM_STATE_L1) && 418 (latency + l1_switch_latency > acceptable->l1)) 419 link->aspm_capable &= ~ASPM_STATE_L1; 420 l1_switch_latency += 1000; 421 422 link = link->parent; 423 } 424 } 425 426 /* 427 * The L1 PM substate capability is only implemented in function 0 in a 428 * multi function device. 429 */ 430 static struct pci_dev *pci_function_0(struct pci_bus *linkbus) 431 { 432 struct pci_dev *child; 433 434 list_for_each_entry(child, &linkbus->devices, bus_list) 435 if (PCI_FUNC(child->devfn) == 0) 436 return child; 437 return NULL; 438 } 439 440 /* Calculate L1.2 PM substate timing parameters */ 441 static void aspm_calc_l1ss_info(struct pcie_link_state *link, 442 struct aspm_register_info *upreg, 443 struct aspm_register_info *dwreg) 444 { 445 u32 val1, val2, scale1, scale2; 446 447 link->l1ss.up_cap_ptr = upreg->l1ss_cap_ptr; 448 link->l1ss.dw_cap_ptr = dwreg->l1ss_cap_ptr; 449 link->l1ss.ctl1 = link->l1ss.ctl2 = 0; 450 451 if (!(link->aspm_support & ASPM_STATE_L1_2_MASK)) 452 return; 453 454 /* Choose the greater of the two Port Common_Mode_Restore_Times */ 455 val1 = (upreg->l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8; 456 val2 = (dwreg->l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8; 457 if (val1 > val2) 458 link->l1ss.ctl1 |= val1 << 8; 459 else 460 link->l1ss.ctl1 |= val2 << 8; 461 462 /* 463 * We currently use LTR L1.2 threshold to be fixed constant picked from 464 * Intel's coreboot. 465 */ 466 link->l1ss.ctl1 |= LTR_L1_2_THRESHOLD_BITS; 467 468 /* Choose the greater of the two Port T_POWER_ON times */ 469 val1 = (upreg->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_VALUE) >> 19; 470 scale1 = (upreg->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_SCALE) >> 16; 471 val2 = (dwreg->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_VALUE) >> 19; 472 scale2 = (dwreg->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_SCALE) >> 16; 473 474 if (calc_l1ss_pwron(link->pdev, scale1, val1) > 475 calc_l1ss_pwron(link->downstream, scale2, val2)) 476 link->l1ss.ctl2 |= scale1 | (val1 << 3); 477 else 478 link->l1ss.ctl2 |= scale2 | (val2 << 3); 479 } 480 481 static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) 482 { 483 struct pci_dev *child = link->downstream, *parent = link->pdev; 484 struct pci_bus *linkbus = parent->subordinate; 485 struct aspm_register_info upreg, dwreg; 486 487 if (blacklist) { 488 /* Set enabled/disable so that we will disable ASPM later */ 489 link->aspm_enabled = ASPM_STATE_ALL; 490 link->aspm_disable = ASPM_STATE_ALL; 491 return; 492 } 493 494 /* Get upstream/downstream components' register state */ 495 pcie_get_aspm_reg(parent, &upreg); 496 pcie_get_aspm_reg(child, &dwreg); 497 498 /* 499 * If ASPM not supported, don't mess with the clocks and link, 500 * bail out now. 501 */ 502 if (!(upreg.support & dwreg.support)) 503 return; 504 505 /* Configure common clock before checking latencies */ 506 pcie_aspm_configure_common_clock(link); 507 508 /* 509 * Re-read upstream/downstream components' register state 510 * after clock configuration 511 */ 512 pcie_get_aspm_reg(parent, &upreg); 513 pcie_get_aspm_reg(child, &dwreg); 514 515 /* 516 * Setup L0s state 517 * 518 * Note that we must not enable L0s in either direction on a 519 * given link unless components on both sides of the link each 520 * support L0s. 521 */ 522 if (dwreg.support & upreg.support & PCIE_LINK_STATE_L0S) 523 link->aspm_support |= ASPM_STATE_L0S; 524 if (dwreg.enabled & PCIE_LINK_STATE_L0S) 525 link->aspm_enabled |= ASPM_STATE_L0S_UP; 526 if (upreg.enabled & PCIE_LINK_STATE_L0S) 527 link->aspm_enabled |= ASPM_STATE_L0S_DW; 528 link->latency_up.l0s = calc_l0s_latency(upreg.latency_encoding_l0s); 529 link->latency_dw.l0s = calc_l0s_latency(dwreg.latency_encoding_l0s); 530 531 /* Setup L1 state */ 532 if (upreg.support & dwreg.support & PCIE_LINK_STATE_L1) 533 link->aspm_support |= ASPM_STATE_L1; 534 if (upreg.enabled & dwreg.enabled & PCIE_LINK_STATE_L1) 535 link->aspm_enabled |= ASPM_STATE_L1; 536 link->latency_up.l1 = calc_l1_latency(upreg.latency_encoding_l1); 537 link->latency_dw.l1 = calc_l1_latency(dwreg.latency_encoding_l1); 538 539 /* Setup L1 substate */ 540 if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_ASPM_L1_1) 541 link->aspm_support |= ASPM_STATE_L1_1; 542 if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_ASPM_L1_2) 543 link->aspm_support |= ASPM_STATE_L1_2; 544 if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_1) 545 link->aspm_support |= ASPM_STATE_L1_1_PCIPM; 546 if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_2) 547 link->aspm_support |= ASPM_STATE_L1_2_PCIPM; 548 549 if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_1) 550 link->aspm_enabled |= ASPM_STATE_L1_1; 551 if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_2) 552 link->aspm_enabled |= ASPM_STATE_L1_2; 553 if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_1) 554 link->aspm_enabled |= ASPM_STATE_L1_1_PCIPM; 555 if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_2) 556 link->aspm_enabled |= ASPM_STATE_L1_2_PCIPM; 557 558 if (link->aspm_support & ASPM_STATE_L1SS) 559 aspm_calc_l1ss_info(link, &upreg, &dwreg); 560 561 /* Save default state */ 562 link->aspm_default = link->aspm_enabled; 563 564 /* Setup initial capable state. Will be updated later */ 565 link->aspm_capable = link->aspm_support; 566 /* 567 * If the downstream component has pci bridge function, don't 568 * do ASPM for now. 569 */ 570 list_for_each_entry(child, &linkbus->devices, bus_list) { 571 if (pci_pcie_type(child) == PCI_EXP_TYPE_PCI_BRIDGE) { 572 link->aspm_disable = ASPM_STATE_ALL; 573 break; 574 } 575 } 576 577 /* Get and check endpoint acceptable latencies */ 578 list_for_each_entry(child, &linkbus->devices, bus_list) { 579 u32 reg32, encoding; 580 struct aspm_latency *acceptable = 581 &link->acceptable[PCI_FUNC(child->devfn)]; 582 583 if (pci_pcie_type(child) != PCI_EXP_TYPE_ENDPOINT && 584 pci_pcie_type(child) != PCI_EXP_TYPE_LEG_END) 585 continue; 586 587 pcie_capability_read_dword(child, PCI_EXP_DEVCAP, ®32); 588 /* Calculate endpoint L0s acceptable latency */ 589 encoding = (reg32 & PCI_EXP_DEVCAP_L0S) >> 6; 590 acceptable->l0s = calc_l0s_acceptable(encoding); 591 /* Calculate endpoint L1 acceptable latency */ 592 encoding = (reg32 & PCI_EXP_DEVCAP_L1) >> 9; 593 acceptable->l1 = calc_l1_acceptable(encoding); 594 595 pcie_aspm_check_latency(child); 596 } 597 } 598 599 static void pci_clear_and_set_dword(struct pci_dev *pdev, int pos, 600 u32 clear, u32 set) 601 { 602 u32 val; 603 604 pci_read_config_dword(pdev, pos, &val); 605 val &= ~clear; 606 val |= set; 607 pci_write_config_dword(pdev, pos, val); 608 } 609 610 /* Configure the ASPM L1 substates */ 611 static void pcie_config_aspm_l1ss(struct pcie_link_state *link, u32 state) 612 { 613 u32 val, enable_req; 614 struct pci_dev *child = link->downstream, *parent = link->pdev; 615 u32 up_cap_ptr = link->l1ss.up_cap_ptr; 616 u32 dw_cap_ptr = link->l1ss.dw_cap_ptr; 617 618 enable_req = (link->aspm_enabled ^ state) & state; 619 620 /* 621 * Here are the rules specified in the PCIe spec for enabling L1SS: 622 * - When enabling L1.x, enable bit at parent first, then at child 623 * - When disabling L1.x, disable bit at child first, then at parent 624 * - When enabling ASPM L1.x, need to disable L1 625 * (at child followed by parent). 626 * - The ASPM/PCIPM L1.2 must be disabled while programming timing 627 * parameters 628 * 629 * To keep it simple, disable all L1SS bits first, and later enable 630 * what is needed. 631 */ 632 633 /* Disable all L1 substates */ 634 pci_clear_and_set_dword(child, dw_cap_ptr + PCI_L1SS_CTL1, 635 PCI_L1SS_CTL1_L1SS_MASK, 0); 636 pci_clear_and_set_dword(parent, up_cap_ptr + PCI_L1SS_CTL1, 637 PCI_L1SS_CTL1_L1SS_MASK, 0); 638 /* 639 * If needed, disable L1, and it gets enabled later 640 * in pcie_config_aspm_link(). 641 */ 642 if (enable_req & (ASPM_STATE_L1_1 | ASPM_STATE_L1_2)) { 643 pcie_capability_clear_and_set_word(child, PCI_EXP_LNKCTL, 644 PCI_EXP_LNKCTL_ASPM_L1, 0); 645 pcie_capability_clear_and_set_word(parent, PCI_EXP_LNKCTL, 646 PCI_EXP_LNKCTL_ASPM_L1, 0); 647 } 648 649 if (enable_req & ASPM_STATE_L1_2_MASK) { 650 651 /* Program T_POWER_ON times in both ports */ 652 pci_write_config_dword(parent, up_cap_ptr + PCI_L1SS_CTL2, 653 link->l1ss.ctl2); 654 pci_write_config_dword(child, dw_cap_ptr + PCI_L1SS_CTL2, 655 link->l1ss.ctl2); 656 657 /* Program Common_Mode_Restore_Time in upstream device */ 658 pci_clear_and_set_dword(parent, up_cap_ptr + PCI_L1SS_CTL1, 659 PCI_L1SS_CTL1_CM_RESTORE_TIME, 660 link->l1ss.ctl1); 661 662 /* Program LTR_L1.2_THRESHOLD time in both ports */ 663 pci_clear_and_set_dword(parent, up_cap_ptr + PCI_L1SS_CTL1, 664 PCI_L1SS_CTL1_LTR_L12_TH_VALUE | 665 PCI_L1SS_CTL1_LTR_L12_TH_SCALE, 666 link->l1ss.ctl1); 667 pci_clear_and_set_dword(child, dw_cap_ptr + PCI_L1SS_CTL1, 668 PCI_L1SS_CTL1_LTR_L12_TH_VALUE | 669 PCI_L1SS_CTL1_LTR_L12_TH_SCALE, 670 link->l1ss.ctl1); 671 } 672 673 val = 0; 674 if (state & ASPM_STATE_L1_1) 675 val |= PCI_L1SS_CTL1_ASPM_L1_1; 676 if (state & ASPM_STATE_L1_2) 677 val |= PCI_L1SS_CTL1_ASPM_L1_2; 678 if (state & ASPM_STATE_L1_1_PCIPM) 679 val |= PCI_L1SS_CTL1_PCIPM_L1_1; 680 if (state & ASPM_STATE_L1_2_PCIPM) 681 val |= PCI_L1SS_CTL1_PCIPM_L1_2; 682 683 /* Enable what we need to enable */ 684 pci_clear_and_set_dword(parent, up_cap_ptr + PCI_L1SS_CTL1, 685 PCI_L1SS_CAP_L1_PM_SS, val); 686 pci_clear_and_set_dword(child, dw_cap_ptr + PCI_L1SS_CTL1, 687 PCI_L1SS_CAP_L1_PM_SS, val); 688 } 689 690 static void pcie_config_aspm_dev(struct pci_dev *pdev, u32 val) 691 { 692 pcie_capability_clear_and_set_word(pdev, PCI_EXP_LNKCTL, 693 PCI_EXP_LNKCTL_ASPMC, val); 694 } 695 696 static void pcie_config_aspm_link(struct pcie_link_state *link, u32 state) 697 { 698 u32 upstream = 0, dwstream = 0; 699 struct pci_dev *child = link->downstream, *parent = link->pdev; 700 struct pci_bus *linkbus = parent->subordinate; 701 702 /* Enable only the states that were not explicitly disabled */ 703 state &= (link->aspm_capable & ~link->aspm_disable); 704 705 /* Can't enable any substates if L1 is not enabled */ 706 if (!(state & ASPM_STATE_L1)) 707 state &= ~ASPM_STATE_L1SS; 708 709 /* Spec says both ports must be in D0 before enabling PCI PM substates*/ 710 if (parent->current_state != PCI_D0 || child->current_state != PCI_D0) { 711 state &= ~ASPM_STATE_L1_SS_PCIPM; 712 state |= (link->aspm_enabled & ASPM_STATE_L1_SS_PCIPM); 713 } 714 715 /* Nothing to do if the link is already in the requested state */ 716 if (link->aspm_enabled == state) 717 return; 718 /* Convert ASPM state to upstream/downstream ASPM register state */ 719 if (state & ASPM_STATE_L0S_UP) 720 dwstream |= PCI_EXP_LNKCTL_ASPM_L0S; 721 if (state & ASPM_STATE_L0S_DW) 722 upstream |= PCI_EXP_LNKCTL_ASPM_L0S; 723 if (state & ASPM_STATE_L1) { 724 upstream |= PCI_EXP_LNKCTL_ASPM_L1; 725 dwstream |= PCI_EXP_LNKCTL_ASPM_L1; 726 } 727 728 if (link->aspm_capable & ASPM_STATE_L1SS) 729 pcie_config_aspm_l1ss(link, state); 730 731 /* 732 * Spec 2.0 suggests all functions should be configured the 733 * same setting for ASPM. Enabling ASPM L1 should be done in 734 * upstream component first and then downstream, and vice 735 * versa for disabling ASPM L1. Spec doesn't mention L0S. 736 */ 737 if (state & ASPM_STATE_L1) 738 pcie_config_aspm_dev(parent, upstream); 739 list_for_each_entry(child, &linkbus->devices, bus_list) 740 pcie_config_aspm_dev(child, dwstream); 741 if (!(state & ASPM_STATE_L1)) 742 pcie_config_aspm_dev(parent, upstream); 743 744 link->aspm_enabled = state; 745 } 746 747 static void pcie_config_aspm_path(struct pcie_link_state *link) 748 { 749 while (link) { 750 pcie_config_aspm_link(link, policy_to_aspm_state(link)); 751 link = link->parent; 752 } 753 } 754 755 static void free_link_state(struct pcie_link_state *link) 756 { 757 link->pdev->link_state = NULL; 758 kfree(link); 759 } 760 761 static int pcie_aspm_sanity_check(struct pci_dev *pdev) 762 { 763 struct pci_dev *child; 764 u32 reg32; 765 766 /* 767 * Some functions in a slot might not all be PCIe functions, 768 * very strange. Disable ASPM for the whole slot 769 */ 770 list_for_each_entry(child, &pdev->subordinate->devices, bus_list) { 771 if (!pci_is_pcie(child)) 772 return -EINVAL; 773 774 /* 775 * If ASPM is disabled then we're not going to change 776 * the BIOS state. It's safe to continue even if it's a 777 * pre-1.1 device 778 */ 779 780 if (aspm_disabled) 781 continue; 782 783 /* 784 * Disable ASPM for pre-1.1 PCIe device, we follow MS to use 785 * RBER bit to determine if a function is 1.1 version device 786 */ 787 pcie_capability_read_dword(child, PCI_EXP_DEVCAP, ®32); 788 if (!(reg32 & PCI_EXP_DEVCAP_RBER) && !aspm_force) { 789 dev_info(&child->dev, "disabling ASPM on pre-1.1 PCIe device. You can enable it with 'pcie_aspm=force'\n"); 790 return -EINVAL; 791 } 792 } 793 return 0; 794 } 795 796 static struct pcie_link_state *alloc_pcie_link_state(struct pci_dev *pdev) 797 { 798 struct pcie_link_state *link; 799 800 link = kzalloc(sizeof(*link), GFP_KERNEL); 801 if (!link) 802 return NULL; 803 804 INIT_LIST_HEAD(&link->sibling); 805 INIT_LIST_HEAD(&link->children); 806 INIT_LIST_HEAD(&link->link); 807 link->pdev = pdev; 808 link->downstream = pci_function_0(pdev->subordinate); 809 810 /* 811 * Root Ports and PCI/PCI-X to PCIe Bridges are roots of PCIe 812 * hierarchies. Note that some PCIe host implementations omit 813 * the root ports entirely, in which case a downstream port on 814 * a switch may become the root of the link state chain for all 815 * its subordinate endpoints. 816 */ 817 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT || 818 pci_pcie_type(pdev) == PCI_EXP_TYPE_PCIE_BRIDGE || 819 !pdev->bus->parent->self) { 820 link->root = link; 821 } else { 822 struct pcie_link_state *parent; 823 824 parent = pdev->bus->parent->self->link_state; 825 if (!parent) { 826 kfree(link); 827 return NULL; 828 } 829 830 link->parent = parent; 831 link->root = link->parent->root; 832 list_add(&link->link, &parent->children); 833 } 834 835 list_add(&link->sibling, &link_list); 836 pdev->link_state = link; 837 return link; 838 } 839 840 /* 841 * pcie_aspm_init_link_state: Initiate PCI express link state. 842 * It is called after the pcie and its children devices are scanned. 843 * @pdev: the root port or switch downstream port 844 */ 845 void pcie_aspm_init_link_state(struct pci_dev *pdev) 846 { 847 struct pcie_link_state *link; 848 int blacklist = !!pcie_aspm_sanity_check(pdev); 849 850 if (!aspm_support_enabled) 851 return; 852 853 if (pdev->link_state) 854 return; 855 856 /* 857 * We allocate pcie_link_state for the component on the upstream 858 * end of a Link, so there's nothing to do unless this device has a 859 * Link on its secondary side. 860 */ 861 if (!pdev->has_secondary_link) 862 return; 863 864 /* VIA has a strange chipset, root port is under a bridge */ 865 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT && 866 pdev->bus->self) 867 return; 868 869 down_read(&pci_bus_sem); 870 if (list_empty(&pdev->subordinate->devices)) 871 goto out; 872 873 mutex_lock(&aspm_lock); 874 link = alloc_pcie_link_state(pdev); 875 if (!link) 876 goto unlock; 877 /* 878 * Setup initial ASPM state. Note that we need to configure 879 * upstream links also because capable state of them can be 880 * update through pcie_aspm_cap_init(). 881 */ 882 pcie_aspm_cap_init(link, blacklist); 883 884 /* Setup initial Clock PM state */ 885 pcie_clkpm_cap_init(link, blacklist); 886 887 /* 888 * At this stage drivers haven't had an opportunity to change the 889 * link policy setting. Enabling ASPM on broken hardware can cripple 890 * it even before the driver has had a chance to disable ASPM, so 891 * default to a safe level right now. If we're enabling ASPM beyond 892 * the BIOS's expectation, we'll do so once pci_enable_device() is 893 * called. 894 */ 895 if (aspm_policy != POLICY_POWERSAVE && 896 aspm_policy != POLICY_POWER_SUPERSAVE) { 897 pcie_config_aspm_path(link); 898 pcie_set_clkpm(link, policy_to_clkpm_state(link)); 899 } 900 901 unlock: 902 mutex_unlock(&aspm_lock); 903 out: 904 up_read(&pci_bus_sem); 905 } 906 907 /* Recheck latencies and update aspm_capable for links under the root */ 908 static void pcie_update_aspm_capable(struct pcie_link_state *root) 909 { 910 struct pcie_link_state *link; 911 BUG_ON(root->parent); 912 list_for_each_entry(link, &link_list, sibling) { 913 if (link->root != root) 914 continue; 915 link->aspm_capable = link->aspm_support; 916 } 917 list_for_each_entry(link, &link_list, sibling) { 918 struct pci_dev *child; 919 struct pci_bus *linkbus = link->pdev->subordinate; 920 if (link->root != root) 921 continue; 922 list_for_each_entry(child, &linkbus->devices, bus_list) { 923 if ((pci_pcie_type(child) != PCI_EXP_TYPE_ENDPOINT) && 924 (pci_pcie_type(child) != PCI_EXP_TYPE_LEG_END)) 925 continue; 926 pcie_aspm_check_latency(child); 927 } 928 } 929 } 930 931 /* @pdev: the endpoint device */ 932 void pcie_aspm_exit_link_state(struct pci_dev *pdev) 933 { 934 struct pci_dev *parent = pdev->bus->self; 935 struct pcie_link_state *link, *root, *parent_link; 936 937 if (!parent || !parent->link_state) 938 return; 939 940 down_read(&pci_bus_sem); 941 mutex_lock(&aspm_lock); 942 /* 943 * All PCIe functions are in one slot, remove one function will remove 944 * the whole slot, so just wait until we are the last function left. 945 */ 946 if (!list_is_last(&pdev->bus_list, &parent->subordinate->devices)) 947 goto out; 948 949 link = parent->link_state; 950 root = link->root; 951 parent_link = link->parent; 952 953 /* All functions are removed, so just disable ASPM for the link */ 954 pcie_config_aspm_link(link, 0); 955 list_del(&link->sibling); 956 list_del(&link->link); 957 /* Clock PM is for endpoint device */ 958 free_link_state(link); 959 960 /* Recheck latencies and configure upstream links */ 961 if (parent_link) { 962 pcie_update_aspm_capable(root); 963 pcie_config_aspm_path(parent_link); 964 } 965 out: 966 mutex_unlock(&aspm_lock); 967 up_read(&pci_bus_sem); 968 } 969 970 /* @pdev: the root port or switch downstream port */ 971 void pcie_aspm_pm_state_change(struct pci_dev *pdev) 972 { 973 struct pcie_link_state *link = pdev->link_state; 974 975 if (aspm_disabled || !link) 976 return; 977 /* 978 * Devices changed PM state, we should recheck if latency 979 * meets all functions' requirement 980 */ 981 down_read(&pci_bus_sem); 982 mutex_lock(&aspm_lock); 983 pcie_update_aspm_capable(link->root); 984 pcie_config_aspm_path(link); 985 mutex_unlock(&aspm_lock); 986 up_read(&pci_bus_sem); 987 } 988 989 void pcie_aspm_powersave_config_link(struct pci_dev *pdev) 990 { 991 struct pcie_link_state *link = pdev->link_state; 992 993 if (aspm_disabled || !link) 994 return; 995 996 if (aspm_policy != POLICY_POWERSAVE && 997 aspm_policy != POLICY_POWER_SUPERSAVE) 998 return; 999 1000 down_read(&pci_bus_sem); 1001 mutex_lock(&aspm_lock); 1002 pcie_config_aspm_path(link); 1003 pcie_set_clkpm(link, policy_to_clkpm_state(link)); 1004 mutex_unlock(&aspm_lock); 1005 up_read(&pci_bus_sem); 1006 } 1007 1008 static void __pci_disable_link_state(struct pci_dev *pdev, int state, bool sem) 1009 { 1010 struct pci_dev *parent = pdev->bus->self; 1011 struct pcie_link_state *link; 1012 1013 if (!pci_is_pcie(pdev)) 1014 return; 1015 1016 if (pdev->has_secondary_link) 1017 parent = pdev; 1018 if (!parent || !parent->link_state) 1019 return; 1020 1021 /* 1022 * A driver requested that ASPM be disabled on this device, but 1023 * if we don't have permission to manage ASPM (e.g., on ACPI 1024 * systems we have to observe the FADT ACPI_FADT_NO_ASPM bit and 1025 * the _OSC method), we can't honor that request. Windows has 1026 * a similar mechanism using "PciASPMOptOut", which is also 1027 * ignored in this situation. 1028 */ 1029 if (aspm_disabled) { 1030 dev_warn(&pdev->dev, "can't disable ASPM; OS doesn't have ASPM control\n"); 1031 return; 1032 } 1033 1034 if (sem) 1035 down_read(&pci_bus_sem); 1036 mutex_lock(&aspm_lock); 1037 link = parent->link_state; 1038 if (state & PCIE_LINK_STATE_L0S) 1039 link->aspm_disable |= ASPM_STATE_L0S; 1040 if (state & PCIE_LINK_STATE_L1) 1041 link->aspm_disable |= ASPM_STATE_L1; 1042 pcie_config_aspm_link(link, policy_to_aspm_state(link)); 1043 1044 if (state & PCIE_LINK_STATE_CLKPM) { 1045 link->clkpm_capable = 0; 1046 pcie_set_clkpm(link, 0); 1047 } 1048 mutex_unlock(&aspm_lock); 1049 if (sem) 1050 up_read(&pci_bus_sem); 1051 } 1052 1053 void pci_disable_link_state_locked(struct pci_dev *pdev, int state) 1054 { 1055 __pci_disable_link_state(pdev, state, false); 1056 } 1057 EXPORT_SYMBOL(pci_disable_link_state_locked); 1058 1059 /** 1060 * pci_disable_link_state - Disable device's link state, so the link will 1061 * never enter specific states. Note that if the BIOS didn't grant ASPM 1062 * control to the OS, this does nothing because we can't touch the LNKCTL 1063 * register. 1064 * 1065 * @pdev: PCI device 1066 * @state: ASPM link state to disable 1067 */ 1068 void pci_disable_link_state(struct pci_dev *pdev, int state) 1069 { 1070 __pci_disable_link_state(pdev, state, true); 1071 } 1072 EXPORT_SYMBOL(pci_disable_link_state); 1073 1074 static int pcie_aspm_set_policy(const char *val, 1075 const struct kernel_param *kp) 1076 { 1077 int i; 1078 struct pcie_link_state *link; 1079 1080 if (aspm_disabled) 1081 return -EPERM; 1082 for (i = 0; i < ARRAY_SIZE(policy_str); i++) 1083 if (!strncmp(val, policy_str[i], strlen(policy_str[i]))) 1084 break; 1085 if (i >= ARRAY_SIZE(policy_str)) 1086 return -EINVAL; 1087 if (i == aspm_policy) 1088 return 0; 1089 1090 down_read(&pci_bus_sem); 1091 mutex_lock(&aspm_lock); 1092 aspm_policy = i; 1093 list_for_each_entry(link, &link_list, sibling) { 1094 pcie_config_aspm_link(link, policy_to_aspm_state(link)); 1095 pcie_set_clkpm(link, policy_to_clkpm_state(link)); 1096 } 1097 mutex_unlock(&aspm_lock); 1098 up_read(&pci_bus_sem); 1099 return 0; 1100 } 1101 1102 static int pcie_aspm_get_policy(char *buffer, const struct kernel_param *kp) 1103 { 1104 int i, cnt = 0; 1105 for (i = 0; i < ARRAY_SIZE(policy_str); i++) 1106 if (i == aspm_policy) 1107 cnt += sprintf(buffer + cnt, "[%s] ", policy_str[i]); 1108 else 1109 cnt += sprintf(buffer + cnt, "%s ", policy_str[i]); 1110 return cnt; 1111 } 1112 1113 module_param_call(policy, pcie_aspm_set_policy, pcie_aspm_get_policy, 1114 NULL, 0644); 1115 1116 #ifdef CONFIG_PCIEASPM_DEBUG 1117 static ssize_t link_state_show(struct device *dev, 1118 struct device_attribute *attr, 1119 char *buf) 1120 { 1121 struct pci_dev *pci_device = to_pci_dev(dev); 1122 struct pcie_link_state *link_state = pci_device->link_state; 1123 1124 return sprintf(buf, "%d\n", link_state->aspm_enabled); 1125 } 1126 1127 static ssize_t link_state_store(struct device *dev, 1128 struct device_attribute *attr, 1129 const char *buf, 1130 size_t n) 1131 { 1132 struct pci_dev *pdev = to_pci_dev(dev); 1133 struct pcie_link_state *link, *root = pdev->link_state->root; 1134 u32 state; 1135 1136 if (aspm_disabled) 1137 return -EPERM; 1138 1139 if (kstrtouint(buf, 10, &state)) 1140 return -EINVAL; 1141 if ((state & ~ASPM_STATE_ALL) != 0) 1142 return -EINVAL; 1143 1144 down_read(&pci_bus_sem); 1145 mutex_lock(&aspm_lock); 1146 list_for_each_entry(link, &link_list, sibling) { 1147 if (link->root != root) 1148 continue; 1149 pcie_config_aspm_link(link, state); 1150 } 1151 mutex_unlock(&aspm_lock); 1152 up_read(&pci_bus_sem); 1153 return n; 1154 } 1155 1156 static ssize_t clk_ctl_show(struct device *dev, 1157 struct device_attribute *attr, 1158 char *buf) 1159 { 1160 struct pci_dev *pci_device = to_pci_dev(dev); 1161 struct pcie_link_state *link_state = pci_device->link_state; 1162 1163 return sprintf(buf, "%d\n", link_state->clkpm_enabled); 1164 } 1165 1166 static ssize_t clk_ctl_store(struct device *dev, 1167 struct device_attribute *attr, 1168 const char *buf, 1169 size_t n) 1170 { 1171 struct pci_dev *pdev = to_pci_dev(dev); 1172 bool state; 1173 1174 if (strtobool(buf, &state)) 1175 return -EINVAL; 1176 1177 down_read(&pci_bus_sem); 1178 mutex_lock(&aspm_lock); 1179 pcie_set_clkpm_nocheck(pdev->link_state, state); 1180 mutex_unlock(&aspm_lock); 1181 up_read(&pci_bus_sem); 1182 1183 return n; 1184 } 1185 1186 static DEVICE_ATTR_RW(link_state); 1187 static DEVICE_ATTR_RW(clk_ctl); 1188 1189 static char power_group[] = "power"; 1190 void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev) 1191 { 1192 struct pcie_link_state *link_state = pdev->link_state; 1193 1194 if (!link_state) 1195 return; 1196 1197 if (link_state->aspm_support) 1198 sysfs_add_file_to_group(&pdev->dev.kobj, 1199 &dev_attr_link_state.attr, power_group); 1200 if (link_state->clkpm_capable) 1201 sysfs_add_file_to_group(&pdev->dev.kobj, 1202 &dev_attr_clk_ctl.attr, power_group); 1203 } 1204 1205 void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev) 1206 { 1207 struct pcie_link_state *link_state = pdev->link_state; 1208 1209 if (!link_state) 1210 return; 1211 1212 if (link_state->aspm_support) 1213 sysfs_remove_file_from_group(&pdev->dev.kobj, 1214 &dev_attr_link_state.attr, power_group); 1215 if (link_state->clkpm_capable) 1216 sysfs_remove_file_from_group(&pdev->dev.kobj, 1217 &dev_attr_clk_ctl.attr, power_group); 1218 } 1219 #endif 1220 1221 static int __init pcie_aspm_disable(char *str) 1222 { 1223 if (!strcmp(str, "off")) { 1224 aspm_policy = POLICY_DEFAULT; 1225 aspm_disabled = 1; 1226 aspm_support_enabled = false; 1227 printk(KERN_INFO "PCIe ASPM is disabled\n"); 1228 } else if (!strcmp(str, "force")) { 1229 aspm_force = 1; 1230 printk(KERN_INFO "PCIe ASPM is forcibly enabled\n"); 1231 } 1232 return 1; 1233 } 1234 1235 __setup("pcie_aspm=", pcie_aspm_disable); 1236 1237 void pcie_no_aspm(void) 1238 { 1239 /* 1240 * Disabling ASPM is intended to prevent the kernel from modifying 1241 * existing hardware state, not to clear existing state. To that end: 1242 * (a) set policy to POLICY_DEFAULT in order to avoid changing state 1243 * (b) prevent userspace from changing policy 1244 */ 1245 if (!aspm_force) { 1246 aspm_policy = POLICY_DEFAULT; 1247 aspm_disabled = 1; 1248 } 1249 } 1250 1251 bool pcie_aspm_support_enabled(void) 1252 { 1253 return aspm_support_enabled; 1254 } 1255 EXPORT_SYMBOL(pcie_aspm_support_enabled); 1256