1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Implement the AER root port service driver. The driver registers an IRQ 4 * handler. When a root port triggers an AER interrupt, the IRQ handler 5 * collects root port status and schedules work. 6 * 7 * Copyright (C) 2006 Intel Corp. 8 * Tom Long Nguyen (tom.l.nguyen@intel.com) 9 * Zhang Yanmin (yanmin.zhang@intel.com) 10 * 11 * (C) Copyright 2009 Hewlett-Packard Development Company, L.P. 12 * Andrew Patterson <andrew.patterson@hp.com> 13 */ 14 15 #define pr_fmt(fmt) "AER: " fmt 16 #define dev_fmt pr_fmt 17 18 #include <linux/bitops.h> 19 #include <linux/cper.h> 20 #include <linux/pci.h> 21 #include <linux/pci-acpi.h> 22 #include <linux/sched.h> 23 #include <linux/kernel.h> 24 #include <linux/errno.h> 25 #include <linux/pm.h> 26 #include <linux/init.h> 27 #include <linux/interrupt.h> 28 #include <linux/delay.h> 29 #include <linux/kfifo.h> 30 #include <linux/slab.h> 31 #include <acpi/apei.h> 32 #include <ras/ras_event.h> 33 34 #include "../pci.h" 35 #include "portdrv.h" 36 37 #define AER_ERROR_SOURCES_MAX 128 38 39 #define AER_MAX_TYPEOF_COR_ERRS 16 /* as per PCI_ERR_COR_STATUS */ 40 #define AER_MAX_TYPEOF_UNCOR_ERRS 27 /* as per PCI_ERR_UNCOR_STATUS*/ 41 42 struct aer_err_source { 43 unsigned int status; 44 unsigned int id; 45 }; 46 47 struct aer_rpc { 48 struct pci_dev *rpd; /* Root Port device */ 49 DECLARE_KFIFO(aer_fifo, struct aer_err_source, AER_ERROR_SOURCES_MAX); 50 }; 51 52 /* AER stats for the device */ 53 struct aer_stats { 54 55 /* 56 * Fields for all AER capable devices. They indicate the errors 57 * "as seen by this device". Note that this may mean that if an 58 * end point is causing problems, the AER counters may increment 59 * at its link partner (e.g. root port) because the errors will be 60 * "seen" by the link partner and not the problematic end point 61 * itself (which may report all counters as 0 as it never saw any 62 * problems). 63 */ 64 /* Counters for different type of correctable errors */ 65 u64 dev_cor_errs[AER_MAX_TYPEOF_COR_ERRS]; 66 /* Counters for different type of fatal uncorrectable errors */ 67 u64 dev_fatal_errs[AER_MAX_TYPEOF_UNCOR_ERRS]; 68 /* Counters for different type of nonfatal uncorrectable errors */ 69 u64 dev_nonfatal_errs[AER_MAX_TYPEOF_UNCOR_ERRS]; 70 /* Total number of ERR_COR sent by this device */ 71 u64 dev_total_cor_errs; 72 /* Total number of ERR_FATAL sent by this device */ 73 u64 dev_total_fatal_errs; 74 /* Total number of ERR_NONFATAL sent by this device */ 75 u64 dev_total_nonfatal_errs; 76 77 /* 78 * Fields for Root ports & root complex event collectors only, these 79 * indicate the total number of ERR_COR, ERR_FATAL, and ERR_NONFATAL 80 * messages received by the root port / event collector, INCLUDING the 81 * ones that are generated internally (by the rootport itself) 82 */ 83 u64 rootport_total_cor_errs; 84 u64 rootport_total_fatal_errs; 85 u64 rootport_total_nonfatal_errs; 86 }; 87 88 #define AER_LOG_TLP_MASKS (PCI_ERR_UNC_POISON_TLP| \ 89 PCI_ERR_UNC_ECRC| \ 90 PCI_ERR_UNC_UNSUP| \ 91 PCI_ERR_UNC_COMP_ABORT| \ 92 PCI_ERR_UNC_UNX_COMP| \ 93 PCI_ERR_UNC_MALF_TLP) 94 95 #define SYSTEM_ERROR_INTR_ON_MESG_MASK (PCI_EXP_RTCTL_SECEE| \ 96 PCI_EXP_RTCTL_SENFEE| \ 97 PCI_EXP_RTCTL_SEFEE) 98 #define ROOT_PORT_INTR_ON_MESG_MASK (PCI_ERR_ROOT_CMD_COR_EN| \ 99 PCI_ERR_ROOT_CMD_NONFATAL_EN| \ 100 PCI_ERR_ROOT_CMD_FATAL_EN) 101 #define ERR_COR_ID(d) (d & 0xffff) 102 #define ERR_UNCOR_ID(d) (d >> 16) 103 104 #define AER_ERR_STATUS_MASK (PCI_ERR_ROOT_UNCOR_RCV | \ 105 PCI_ERR_ROOT_COR_RCV | \ 106 PCI_ERR_ROOT_MULTI_COR_RCV | \ 107 PCI_ERR_ROOT_MULTI_UNCOR_RCV) 108 109 static int pcie_aer_disable; 110 static pci_ers_result_t aer_root_reset(struct pci_dev *dev); 111 112 void pci_no_aer(void) 113 { 114 pcie_aer_disable = 1; 115 } 116 117 bool pci_aer_available(void) 118 { 119 return !pcie_aer_disable && pci_msi_enabled(); 120 } 121 122 #ifdef CONFIG_PCIE_ECRC 123 124 #define ECRC_POLICY_DEFAULT 0 /* ECRC set by BIOS */ 125 #define ECRC_POLICY_OFF 1 /* ECRC off for performance */ 126 #define ECRC_POLICY_ON 2 /* ECRC on for data integrity */ 127 128 static int ecrc_policy = ECRC_POLICY_DEFAULT; 129 130 static const char * const ecrc_policy_str[] = { 131 [ECRC_POLICY_DEFAULT] = "bios", 132 [ECRC_POLICY_OFF] = "off", 133 [ECRC_POLICY_ON] = "on" 134 }; 135 136 /** 137 * enable_ecrc_checking - enable PCIe ECRC checking for a device 138 * @dev: the PCI device 139 * 140 * Returns 0 on success, or negative on failure. 141 */ 142 static int enable_ecrc_checking(struct pci_dev *dev) 143 { 144 int aer = dev->aer_cap; 145 u32 reg32; 146 147 if (!aer) 148 return -ENODEV; 149 150 pci_read_config_dword(dev, aer + PCI_ERR_CAP, ®32); 151 if (reg32 & PCI_ERR_CAP_ECRC_GENC) 152 reg32 |= PCI_ERR_CAP_ECRC_GENE; 153 if (reg32 & PCI_ERR_CAP_ECRC_CHKC) 154 reg32 |= PCI_ERR_CAP_ECRC_CHKE; 155 pci_write_config_dword(dev, aer + PCI_ERR_CAP, reg32); 156 157 return 0; 158 } 159 160 /** 161 * disable_ecrc_checking - disables PCIe ECRC checking for a device 162 * @dev: the PCI device 163 * 164 * Returns 0 on success, or negative on failure. 165 */ 166 static int disable_ecrc_checking(struct pci_dev *dev) 167 { 168 int aer = dev->aer_cap; 169 u32 reg32; 170 171 if (!aer) 172 return -ENODEV; 173 174 pci_read_config_dword(dev, aer + PCI_ERR_CAP, ®32); 175 reg32 &= ~(PCI_ERR_CAP_ECRC_GENE | PCI_ERR_CAP_ECRC_CHKE); 176 pci_write_config_dword(dev, aer + PCI_ERR_CAP, reg32); 177 178 return 0; 179 } 180 181 /** 182 * pcie_set_ecrc_checking - set/unset PCIe ECRC checking for a device based on global policy 183 * @dev: the PCI device 184 */ 185 void pcie_set_ecrc_checking(struct pci_dev *dev) 186 { 187 if (!pcie_aer_is_native(dev)) 188 return; 189 190 switch (ecrc_policy) { 191 case ECRC_POLICY_DEFAULT: 192 return; 193 case ECRC_POLICY_OFF: 194 disable_ecrc_checking(dev); 195 break; 196 case ECRC_POLICY_ON: 197 enable_ecrc_checking(dev); 198 break; 199 default: 200 return; 201 } 202 } 203 204 /** 205 * pcie_ecrc_get_policy - parse kernel command-line ecrc option 206 * @str: ECRC policy from kernel command line to use 207 */ 208 void pcie_ecrc_get_policy(char *str) 209 { 210 int i; 211 212 i = match_string(ecrc_policy_str, ARRAY_SIZE(ecrc_policy_str), str); 213 if (i < 0) 214 return; 215 216 ecrc_policy = i; 217 } 218 #endif /* CONFIG_PCIE_ECRC */ 219 220 #define PCI_EXP_AER_FLAGS (PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE | \ 221 PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE) 222 223 int pcie_aer_is_native(struct pci_dev *dev) 224 { 225 struct pci_host_bridge *host = pci_find_host_bridge(dev->bus); 226 227 if (!dev->aer_cap) 228 return 0; 229 230 return pcie_ports_native || host->native_aer; 231 } 232 233 static int pci_enable_pcie_error_reporting(struct pci_dev *dev) 234 { 235 int rc; 236 237 if (!pcie_aer_is_native(dev)) 238 return -EIO; 239 240 rc = pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_AER_FLAGS); 241 return pcibios_err_to_errno(rc); 242 } 243 244 int pci_aer_clear_nonfatal_status(struct pci_dev *dev) 245 { 246 int aer = dev->aer_cap; 247 u32 status, sev; 248 249 if (!pcie_aer_is_native(dev)) 250 return -EIO; 251 252 /* Clear status bits for ERR_NONFATAL errors only */ 253 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status); 254 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, &sev); 255 status &= ~sev; 256 if (status) 257 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, status); 258 259 return 0; 260 } 261 EXPORT_SYMBOL_GPL(pci_aer_clear_nonfatal_status); 262 263 void pci_aer_clear_fatal_status(struct pci_dev *dev) 264 { 265 int aer = dev->aer_cap; 266 u32 status, sev; 267 268 if (!pcie_aer_is_native(dev)) 269 return; 270 271 /* Clear status bits for ERR_FATAL errors only */ 272 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status); 273 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, &sev); 274 status &= sev; 275 if (status) 276 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, status); 277 } 278 279 /** 280 * pci_aer_raw_clear_status - Clear AER error registers. 281 * @dev: the PCI device 282 * 283 * Clearing AER error status registers unconditionally, regardless of 284 * whether they're owned by firmware or the OS. 285 * 286 * Returns 0 on success, or negative on failure. 287 */ 288 int pci_aer_raw_clear_status(struct pci_dev *dev) 289 { 290 int aer = dev->aer_cap; 291 u32 status; 292 int port_type; 293 294 if (!aer) 295 return -EIO; 296 297 port_type = pci_pcie_type(dev); 298 if (port_type == PCI_EXP_TYPE_ROOT_PORT || 299 port_type == PCI_EXP_TYPE_RC_EC) { 300 pci_read_config_dword(dev, aer + PCI_ERR_ROOT_STATUS, &status); 301 pci_write_config_dword(dev, aer + PCI_ERR_ROOT_STATUS, status); 302 } 303 304 pci_read_config_dword(dev, aer + PCI_ERR_COR_STATUS, &status); 305 pci_write_config_dword(dev, aer + PCI_ERR_COR_STATUS, status); 306 307 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status); 308 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, status); 309 310 return 0; 311 } 312 313 int pci_aer_clear_status(struct pci_dev *dev) 314 { 315 if (!pcie_aer_is_native(dev)) 316 return -EIO; 317 318 return pci_aer_raw_clear_status(dev); 319 } 320 321 void pci_save_aer_state(struct pci_dev *dev) 322 { 323 int aer = dev->aer_cap; 324 struct pci_cap_saved_state *save_state; 325 u32 *cap; 326 327 if (!aer) 328 return; 329 330 save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_ERR); 331 if (!save_state) 332 return; 333 334 cap = &save_state->cap.data[0]; 335 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, cap++); 336 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, cap++); 337 pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK, cap++); 338 pci_read_config_dword(dev, aer + PCI_ERR_CAP, cap++); 339 if (pcie_cap_has_rtctl(dev)) 340 pci_read_config_dword(dev, aer + PCI_ERR_ROOT_COMMAND, cap++); 341 } 342 343 void pci_restore_aer_state(struct pci_dev *dev) 344 { 345 int aer = dev->aer_cap; 346 struct pci_cap_saved_state *save_state; 347 u32 *cap; 348 349 if (!aer) 350 return; 351 352 save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_ERR); 353 if (!save_state) 354 return; 355 356 cap = &save_state->cap.data[0]; 357 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, *cap++); 358 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, *cap++); 359 pci_write_config_dword(dev, aer + PCI_ERR_COR_MASK, *cap++); 360 pci_write_config_dword(dev, aer + PCI_ERR_CAP, *cap++); 361 if (pcie_cap_has_rtctl(dev)) 362 pci_write_config_dword(dev, aer + PCI_ERR_ROOT_COMMAND, *cap++); 363 } 364 365 void pci_aer_init(struct pci_dev *dev) 366 { 367 int n; 368 369 dev->aer_cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); 370 if (!dev->aer_cap) 371 return; 372 373 dev->aer_stats = kzalloc(sizeof(struct aer_stats), GFP_KERNEL); 374 375 /* 376 * We save/restore PCI_ERR_UNCOR_MASK, PCI_ERR_UNCOR_SEVER, 377 * PCI_ERR_COR_MASK, and PCI_ERR_CAP. Root and Root Complex Event 378 * Collectors also implement PCI_ERR_ROOT_COMMAND (PCIe r5.0, sec 379 * 7.8.4). 380 */ 381 n = pcie_cap_has_rtctl(dev) ? 5 : 4; 382 pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_ERR, sizeof(u32) * n); 383 384 pci_aer_clear_status(dev); 385 386 if (pci_aer_available()) 387 pci_enable_pcie_error_reporting(dev); 388 389 pcie_set_ecrc_checking(dev); 390 } 391 392 void pci_aer_exit(struct pci_dev *dev) 393 { 394 kfree(dev->aer_stats); 395 dev->aer_stats = NULL; 396 } 397 398 #define AER_AGENT_RECEIVER 0 399 #define AER_AGENT_REQUESTER 1 400 #define AER_AGENT_COMPLETER 2 401 #define AER_AGENT_TRANSMITTER 3 402 403 #define AER_AGENT_REQUESTER_MASK(t) ((t == AER_CORRECTABLE) ? \ 404 0 : (PCI_ERR_UNC_COMP_TIME|PCI_ERR_UNC_UNSUP)) 405 #define AER_AGENT_COMPLETER_MASK(t) ((t == AER_CORRECTABLE) ? \ 406 0 : PCI_ERR_UNC_COMP_ABORT) 407 #define AER_AGENT_TRANSMITTER_MASK(t) ((t == AER_CORRECTABLE) ? \ 408 (PCI_ERR_COR_REP_ROLL|PCI_ERR_COR_REP_TIMER) : 0) 409 410 #define AER_GET_AGENT(t, e) \ 411 ((e & AER_AGENT_COMPLETER_MASK(t)) ? AER_AGENT_COMPLETER : \ 412 (e & AER_AGENT_REQUESTER_MASK(t)) ? AER_AGENT_REQUESTER : \ 413 (e & AER_AGENT_TRANSMITTER_MASK(t)) ? AER_AGENT_TRANSMITTER : \ 414 AER_AGENT_RECEIVER) 415 416 #define AER_PHYSICAL_LAYER_ERROR 0 417 #define AER_DATA_LINK_LAYER_ERROR 1 418 #define AER_TRANSACTION_LAYER_ERROR 2 419 420 #define AER_PHYSICAL_LAYER_ERROR_MASK(t) ((t == AER_CORRECTABLE) ? \ 421 PCI_ERR_COR_RCVR : 0) 422 #define AER_DATA_LINK_LAYER_ERROR_MASK(t) ((t == AER_CORRECTABLE) ? \ 423 (PCI_ERR_COR_BAD_TLP| \ 424 PCI_ERR_COR_BAD_DLLP| \ 425 PCI_ERR_COR_REP_ROLL| \ 426 PCI_ERR_COR_REP_TIMER) : PCI_ERR_UNC_DLP) 427 428 #define AER_GET_LAYER_ERROR(t, e) \ 429 ((e & AER_PHYSICAL_LAYER_ERROR_MASK(t)) ? AER_PHYSICAL_LAYER_ERROR : \ 430 (e & AER_DATA_LINK_LAYER_ERROR_MASK(t)) ? AER_DATA_LINK_LAYER_ERROR : \ 431 AER_TRANSACTION_LAYER_ERROR) 432 433 /* 434 * AER error strings 435 */ 436 static const char *aer_error_severity_string[] = { 437 "Uncorrected (Non-Fatal)", 438 "Uncorrected (Fatal)", 439 "Corrected" 440 }; 441 442 static const char *aer_error_layer[] = { 443 "Physical Layer", 444 "Data Link Layer", 445 "Transaction Layer" 446 }; 447 448 static const char *aer_correctable_error_string[] = { 449 "RxErr", /* Bit Position 0 */ 450 NULL, 451 NULL, 452 NULL, 453 NULL, 454 NULL, 455 "BadTLP", /* Bit Position 6 */ 456 "BadDLLP", /* Bit Position 7 */ 457 "Rollover", /* Bit Position 8 */ 458 NULL, 459 NULL, 460 NULL, 461 "Timeout", /* Bit Position 12 */ 462 "NonFatalErr", /* Bit Position 13 */ 463 "CorrIntErr", /* Bit Position 14 */ 464 "HeaderOF", /* Bit Position 15 */ 465 NULL, /* Bit Position 16 */ 466 NULL, /* Bit Position 17 */ 467 NULL, /* Bit Position 18 */ 468 NULL, /* Bit Position 19 */ 469 NULL, /* Bit Position 20 */ 470 NULL, /* Bit Position 21 */ 471 NULL, /* Bit Position 22 */ 472 NULL, /* Bit Position 23 */ 473 NULL, /* Bit Position 24 */ 474 NULL, /* Bit Position 25 */ 475 NULL, /* Bit Position 26 */ 476 NULL, /* Bit Position 27 */ 477 NULL, /* Bit Position 28 */ 478 NULL, /* Bit Position 29 */ 479 NULL, /* Bit Position 30 */ 480 NULL, /* Bit Position 31 */ 481 }; 482 483 static const char *aer_uncorrectable_error_string[] = { 484 "Undefined", /* Bit Position 0 */ 485 NULL, 486 NULL, 487 NULL, 488 "DLP", /* Bit Position 4 */ 489 "SDES", /* Bit Position 5 */ 490 NULL, 491 NULL, 492 NULL, 493 NULL, 494 NULL, 495 NULL, 496 "TLP", /* Bit Position 12 */ 497 "FCP", /* Bit Position 13 */ 498 "CmpltTO", /* Bit Position 14 */ 499 "CmpltAbrt", /* Bit Position 15 */ 500 "UnxCmplt", /* Bit Position 16 */ 501 "RxOF", /* Bit Position 17 */ 502 "MalfTLP", /* Bit Position 18 */ 503 "ECRC", /* Bit Position 19 */ 504 "UnsupReq", /* Bit Position 20 */ 505 "ACSViol", /* Bit Position 21 */ 506 "UncorrIntErr", /* Bit Position 22 */ 507 "BlockedTLP", /* Bit Position 23 */ 508 "AtomicOpBlocked", /* Bit Position 24 */ 509 "TLPBlockedErr", /* Bit Position 25 */ 510 "PoisonTLPBlocked", /* Bit Position 26 */ 511 NULL, /* Bit Position 27 */ 512 NULL, /* Bit Position 28 */ 513 NULL, /* Bit Position 29 */ 514 NULL, /* Bit Position 30 */ 515 NULL, /* Bit Position 31 */ 516 }; 517 518 static const char *aer_agent_string[] = { 519 "Receiver ID", 520 "Requester ID", 521 "Completer ID", 522 "Transmitter ID" 523 }; 524 525 #define aer_stats_dev_attr(name, stats_array, strings_array, \ 526 total_string, total_field) \ 527 static ssize_t \ 528 name##_show(struct device *dev, struct device_attribute *attr, \ 529 char *buf) \ 530 { \ 531 unsigned int i; \ 532 struct pci_dev *pdev = to_pci_dev(dev); \ 533 u64 *stats = pdev->aer_stats->stats_array; \ 534 size_t len = 0; \ 535 \ 536 for (i = 0; i < ARRAY_SIZE(pdev->aer_stats->stats_array); i++) {\ 537 if (strings_array[i]) \ 538 len += sysfs_emit_at(buf, len, "%s %llu\n", \ 539 strings_array[i], \ 540 stats[i]); \ 541 else if (stats[i]) \ 542 len += sysfs_emit_at(buf, len, \ 543 #stats_array "_bit[%d] %llu\n",\ 544 i, stats[i]); \ 545 } \ 546 len += sysfs_emit_at(buf, len, "TOTAL_%s %llu\n", total_string, \ 547 pdev->aer_stats->total_field); \ 548 return len; \ 549 } \ 550 static DEVICE_ATTR_RO(name) 551 552 aer_stats_dev_attr(aer_dev_correctable, dev_cor_errs, 553 aer_correctable_error_string, "ERR_COR", 554 dev_total_cor_errs); 555 aer_stats_dev_attr(aer_dev_fatal, dev_fatal_errs, 556 aer_uncorrectable_error_string, "ERR_FATAL", 557 dev_total_fatal_errs); 558 aer_stats_dev_attr(aer_dev_nonfatal, dev_nonfatal_errs, 559 aer_uncorrectable_error_string, "ERR_NONFATAL", 560 dev_total_nonfatal_errs); 561 562 #define aer_stats_rootport_attr(name, field) \ 563 static ssize_t \ 564 name##_show(struct device *dev, struct device_attribute *attr, \ 565 char *buf) \ 566 { \ 567 struct pci_dev *pdev = to_pci_dev(dev); \ 568 return sysfs_emit(buf, "%llu\n", pdev->aer_stats->field); \ 569 } \ 570 static DEVICE_ATTR_RO(name) 571 572 aer_stats_rootport_attr(aer_rootport_total_err_cor, 573 rootport_total_cor_errs); 574 aer_stats_rootport_attr(aer_rootport_total_err_fatal, 575 rootport_total_fatal_errs); 576 aer_stats_rootport_attr(aer_rootport_total_err_nonfatal, 577 rootport_total_nonfatal_errs); 578 579 static struct attribute *aer_stats_attrs[] __ro_after_init = { 580 &dev_attr_aer_dev_correctable.attr, 581 &dev_attr_aer_dev_fatal.attr, 582 &dev_attr_aer_dev_nonfatal.attr, 583 &dev_attr_aer_rootport_total_err_cor.attr, 584 &dev_attr_aer_rootport_total_err_fatal.attr, 585 &dev_attr_aer_rootport_total_err_nonfatal.attr, 586 NULL 587 }; 588 589 static umode_t aer_stats_attrs_are_visible(struct kobject *kobj, 590 struct attribute *a, int n) 591 { 592 struct device *dev = kobj_to_dev(kobj); 593 struct pci_dev *pdev = to_pci_dev(dev); 594 595 if (!pdev->aer_stats) 596 return 0; 597 598 if ((a == &dev_attr_aer_rootport_total_err_cor.attr || 599 a == &dev_attr_aer_rootport_total_err_fatal.attr || 600 a == &dev_attr_aer_rootport_total_err_nonfatal.attr) && 601 ((pci_pcie_type(pdev) != PCI_EXP_TYPE_ROOT_PORT) && 602 (pci_pcie_type(pdev) != PCI_EXP_TYPE_RC_EC))) 603 return 0; 604 605 return a->mode; 606 } 607 608 const struct attribute_group aer_stats_attr_group = { 609 .attrs = aer_stats_attrs, 610 .is_visible = aer_stats_attrs_are_visible, 611 }; 612 613 static void pci_dev_aer_stats_incr(struct pci_dev *pdev, 614 struct aer_err_info *info) 615 { 616 unsigned long status = info->status & ~info->mask; 617 int i, max = -1; 618 u64 *counter = NULL; 619 struct aer_stats *aer_stats = pdev->aer_stats; 620 621 if (!aer_stats) 622 return; 623 624 switch (info->severity) { 625 case AER_CORRECTABLE: 626 aer_stats->dev_total_cor_errs++; 627 counter = &aer_stats->dev_cor_errs[0]; 628 max = AER_MAX_TYPEOF_COR_ERRS; 629 break; 630 case AER_NONFATAL: 631 aer_stats->dev_total_nonfatal_errs++; 632 counter = &aer_stats->dev_nonfatal_errs[0]; 633 max = AER_MAX_TYPEOF_UNCOR_ERRS; 634 break; 635 case AER_FATAL: 636 aer_stats->dev_total_fatal_errs++; 637 counter = &aer_stats->dev_fatal_errs[0]; 638 max = AER_MAX_TYPEOF_UNCOR_ERRS; 639 break; 640 } 641 642 for_each_set_bit(i, &status, max) 643 counter[i]++; 644 } 645 646 static void pci_rootport_aer_stats_incr(struct pci_dev *pdev, 647 struct aer_err_source *e_src) 648 { 649 struct aer_stats *aer_stats = pdev->aer_stats; 650 651 if (!aer_stats) 652 return; 653 654 if (e_src->status & PCI_ERR_ROOT_COR_RCV) 655 aer_stats->rootport_total_cor_errs++; 656 657 if (e_src->status & PCI_ERR_ROOT_UNCOR_RCV) { 658 if (e_src->status & PCI_ERR_ROOT_FATAL_RCV) 659 aer_stats->rootport_total_fatal_errs++; 660 else 661 aer_stats->rootport_total_nonfatal_errs++; 662 } 663 } 664 665 static void __print_tlp_header(struct pci_dev *dev, 666 struct aer_header_log_regs *t) 667 { 668 pci_err(dev, " TLP Header: %08x %08x %08x %08x\n", 669 t->dw0, t->dw1, t->dw2, t->dw3); 670 } 671 672 static void __aer_print_error(struct pci_dev *dev, 673 struct aer_err_info *info) 674 { 675 const char **strings; 676 unsigned long status = info->status & ~info->mask; 677 const char *level, *errmsg; 678 int i; 679 680 if (info->severity == AER_CORRECTABLE) { 681 strings = aer_correctable_error_string; 682 level = KERN_WARNING; 683 } else { 684 strings = aer_uncorrectable_error_string; 685 level = KERN_ERR; 686 } 687 688 for_each_set_bit(i, &status, 32) { 689 errmsg = strings[i]; 690 if (!errmsg) 691 errmsg = "Unknown Error Bit"; 692 693 pci_printk(level, dev, " [%2d] %-22s%s\n", i, errmsg, 694 info->first_error == i ? " (First)" : ""); 695 } 696 pci_dev_aer_stats_incr(dev, info); 697 } 698 699 void aer_print_error(struct pci_dev *dev, struct aer_err_info *info) 700 { 701 int layer, agent; 702 int id = pci_dev_id(dev); 703 const char *level; 704 705 if (!info->status) { 706 pci_err(dev, "PCIe Bus Error: severity=%s, type=Inaccessible, (Unregistered Agent ID)\n", 707 aer_error_severity_string[info->severity]); 708 goto out; 709 } 710 711 layer = AER_GET_LAYER_ERROR(info->severity, info->status); 712 agent = AER_GET_AGENT(info->severity, info->status); 713 714 level = (info->severity == AER_CORRECTABLE) ? KERN_WARNING : KERN_ERR; 715 716 pci_printk(level, dev, "PCIe Bus Error: severity=%s, type=%s, (%s)\n", 717 aer_error_severity_string[info->severity], 718 aer_error_layer[layer], aer_agent_string[agent]); 719 720 pci_printk(level, dev, " device [%04x:%04x] error status/mask=%08x/%08x\n", 721 dev->vendor, dev->device, info->status, info->mask); 722 723 __aer_print_error(dev, info); 724 725 if (info->tlp_header_valid) 726 __print_tlp_header(dev, &info->tlp); 727 728 out: 729 if (info->id && info->error_dev_num > 1 && info->id == id) 730 pci_err(dev, " Error of this Agent is reported first\n"); 731 732 trace_aer_event(dev_name(&dev->dev), (info->status & ~info->mask), 733 info->severity, info->tlp_header_valid, &info->tlp); 734 } 735 736 static void aer_print_port_info(struct pci_dev *dev, struct aer_err_info *info) 737 { 738 u8 bus = info->id >> 8; 739 u8 devfn = info->id & 0xff; 740 741 pci_info(dev, "%s%s error received: %04x:%02x:%02x.%d\n", 742 info->multi_error_valid ? "Multiple " : "", 743 aer_error_severity_string[info->severity], 744 pci_domain_nr(dev->bus), bus, PCI_SLOT(devfn), 745 PCI_FUNC(devfn)); 746 } 747 748 #ifdef CONFIG_ACPI_APEI_PCIEAER 749 int cper_severity_to_aer(int cper_severity) 750 { 751 switch (cper_severity) { 752 case CPER_SEV_RECOVERABLE: 753 return AER_NONFATAL; 754 case CPER_SEV_FATAL: 755 return AER_FATAL; 756 default: 757 return AER_CORRECTABLE; 758 } 759 } 760 EXPORT_SYMBOL_GPL(cper_severity_to_aer); 761 762 void cper_print_aer(struct pci_dev *dev, int aer_severity, 763 struct aer_capability_regs *aer) 764 { 765 int layer, agent, tlp_header_valid = 0; 766 u32 status, mask; 767 struct aer_err_info info; 768 769 if (aer_severity == AER_CORRECTABLE) { 770 status = aer->cor_status; 771 mask = aer->cor_mask; 772 } else { 773 status = aer->uncor_status; 774 mask = aer->uncor_mask; 775 tlp_header_valid = status & AER_LOG_TLP_MASKS; 776 } 777 778 layer = AER_GET_LAYER_ERROR(aer_severity, status); 779 agent = AER_GET_AGENT(aer_severity, status); 780 781 memset(&info, 0, sizeof(info)); 782 info.severity = aer_severity; 783 info.status = status; 784 info.mask = mask; 785 info.first_error = PCI_ERR_CAP_FEP(aer->cap_control); 786 787 pci_err(dev, "aer_status: 0x%08x, aer_mask: 0x%08x\n", status, mask); 788 __aer_print_error(dev, &info); 789 pci_err(dev, "aer_layer=%s, aer_agent=%s\n", 790 aer_error_layer[layer], aer_agent_string[agent]); 791 792 if (aer_severity != AER_CORRECTABLE) 793 pci_err(dev, "aer_uncor_severity: 0x%08x\n", 794 aer->uncor_severity); 795 796 if (tlp_header_valid) 797 __print_tlp_header(dev, &aer->header_log); 798 799 trace_aer_event(dev_name(&dev->dev), (status & ~mask), 800 aer_severity, tlp_header_valid, &aer->header_log); 801 } 802 #endif 803 804 /** 805 * add_error_device - list device to be handled 806 * @e_info: pointer to error info 807 * @dev: pointer to pci_dev to be added 808 */ 809 static int add_error_device(struct aer_err_info *e_info, struct pci_dev *dev) 810 { 811 if (e_info->error_dev_num < AER_MAX_MULTI_ERR_DEVICES) { 812 e_info->dev[e_info->error_dev_num] = pci_dev_get(dev); 813 e_info->error_dev_num++; 814 return 0; 815 } 816 return -ENOSPC; 817 } 818 819 /** 820 * is_error_source - check whether the device is source of reported error 821 * @dev: pointer to pci_dev to be checked 822 * @e_info: pointer to reported error info 823 */ 824 static bool is_error_source(struct pci_dev *dev, struct aer_err_info *e_info) 825 { 826 int aer = dev->aer_cap; 827 u32 status, mask; 828 u16 reg16; 829 830 /* 831 * When bus id is equal to 0, it might be a bad id 832 * reported by root port. 833 */ 834 if ((PCI_BUS_NUM(e_info->id) != 0) && 835 !(dev->bus->bus_flags & PCI_BUS_FLAGS_NO_AERSID)) { 836 /* Device ID match? */ 837 if (e_info->id == pci_dev_id(dev)) 838 return true; 839 840 /* Continue id comparing if there is no multiple error */ 841 if (!e_info->multi_error_valid) 842 return false; 843 } 844 845 /* 846 * When either 847 * 1) bus id is equal to 0. Some ports might lose the bus 848 * id of error source id; 849 * 2) bus flag PCI_BUS_FLAGS_NO_AERSID is set 850 * 3) There are multiple errors and prior ID comparing fails; 851 * We check AER status registers to find possible reporter. 852 */ 853 if (atomic_read(&dev->enable_cnt) == 0) 854 return false; 855 856 /* Check if AER is enabled */ 857 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, ®16); 858 if (!(reg16 & PCI_EXP_AER_FLAGS)) 859 return false; 860 861 if (!aer) 862 return false; 863 864 /* Check if error is recorded */ 865 if (e_info->severity == AER_CORRECTABLE) { 866 pci_read_config_dword(dev, aer + PCI_ERR_COR_STATUS, &status); 867 pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK, &mask); 868 } else { 869 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status); 870 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, &mask); 871 } 872 if (status & ~mask) 873 return true; 874 875 return false; 876 } 877 878 static int find_device_iter(struct pci_dev *dev, void *data) 879 { 880 struct aer_err_info *e_info = (struct aer_err_info *)data; 881 882 if (is_error_source(dev, e_info)) { 883 /* List this device */ 884 if (add_error_device(e_info, dev)) { 885 /* We cannot handle more... Stop iteration */ 886 /* TODO: Should print error message here? */ 887 return 1; 888 } 889 890 /* If there is only a single error, stop iteration */ 891 if (!e_info->multi_error_valid) 892 return 1; 893 } 894 return 0; 895 } 896 897 /** 898 * find_source_device - search through device hierarchy for source device 899 * @parent: pointer to Root Port pci_dev data structure 900 * @e_info: including detailed error information such like id 901 * 902 * Return true if found. 903 * 904 * Invoked by DPC when error is detected at the Root Port. 905 * Caller of this function must set id, severity, and multi_error_valid of 906 * struct aer_err_info pointed by @e_info properly. This function must fill 907 * e_info->error_dev_num and e_info->dev[], based on the given information. 908 */ 909 static bool find_source_device(struct pci_dev *parent, 910 struct aer_err_info *e_info) 911 { 912 struct pci_dev *dev = parent; 913 int result; 914 915 /* Must reset in this function */ 916 e_info->error_dev_num = 0; 917 918 /* Is Root Port an agent that sends error message? */ 919 result = find_device_iter(dev, e_info); 920 if (result) 921 return true; 922 923 if (pci_pcie_type(parent) == PCI_EXP_TYPE_RC_EC) 924 pcie_walk_rcec(parent, find_device_iter, e_info); 925 else 926 pci_walk_bus(parent->subordinate, find_device_iter, e_info); 927 928 if (!e_info->error_dev_num) { 929 pci_info(parent, "can't find device of ID%04x\n", e_info->id); 930 return false; 931 } 932 return true; 933 } 934 935 /** 936 * handle_error_source - handle logging error into an event log 937 * @dev: pointer to pci_dev data structure of error source device 938 * @info: comprehensive error information 939 * 940 * Invoked when an error being detected by Root Port. 941 */ 942 static void handle_error_source(struct pci_dev *dev, struct aer_err_info *info) 943 { 944 int aer = dev->aer_cap; 945 946 if (info->severity == AER_CORRECTABLE) { 947 /* 948 * Correctable error does not need software intervention. 949 * No need to go through error recovery process. 950 */ 951 if (aer) 952 pci_write_config_dword(dev, aer + PCI_ERR_COR_STATUS, 953 info->status); 954 if (pcie_aer_is_native(dev)) { 955 struct pci_driver *pdrv = dev->driver; 956 957 if (pdrv && pdrv->err_handler && 958 pdrv->err_handler->cor_error_detected) 959 pdrv->err_handler->cor_error_detected(dev); 960 pcie_clear_device_status(dev); 961 } 962 } else if (info->severity == AER_NONFATAL) 963 pcie_do_recovery(dev, pci_channel_io_normal, aer_root_reset); 964 else if (info->severity == AER_FATAL) 965 pcie_do_recovery(dev, pci_channel_io_frozen, aer_root_reset); 966 pci_dev_put(dev); 967 } 968 969 #ifdef CONFIG_ACPI_APEI_PCIEAER 970 971 #define AER_RECOVER_RING_SIZE 16 972 973 struct aer_recover_entry { 974 u8 bus; 975 u8 devfn; 976 u16 domain; 977 int severity; 978 struct aer_capability_regs *regs; 979 }; 980 981 static DEFINE_KFIFO(aer_recover_ring, struct aer_recover_entry, 982 AER_RECOVER_RING_SIZE); 983 984 static void aer_recover_work_func(struct work_struct *work) 985 { 986 struct aer_recover_entry entry; 987 struct pci_dev *pdev; 988 989 while (kfifo_get(&aer_recover_ring, &entry)) { 990 pdev = pci_get_domain_bus_and_slot(entry.domain, entry.bus, 991 entry.devfn); 992 if (!pdev) { 993 pr_err("no pci_dev for %04x:%02x:%02x.%x\n", 994 entry.domain, entry.bus, 995 PCI_SLOT(entry.devfn), PCI_FUNC(entry.devfn)); 996 continue; 997 } 998 cper_print_aer(pdev, entry.severity, entry.regs); 999 if (entry.severity == AER_NONFATAL) 1000 pcie_do_recovery(pdev, pci_channel_io_normal, 1001 aer_root_reset); 1002 else if (entry.severity == AER_FATAL) 1003 pcie_do_recovery(pdev, pci_channel_io_frozen, 1004 aer_root_reset); 1005 pci_dev_put(pdev); 1006 } 1007 } 1008 1009 /* 1010 * Mutual exclusion for writers of aer_recover_ring, reader side don't 1011 * need lock, because there is only one reader and lock is not needed 1012 * between reader and writer. 1013 */ 1014 static DEFINE_SPINLOCK(aer_recover_ring_lock); 1015 static DECLARE_WORK(aer_recover_work, aer_recover_work_func); 1016 1017 void aer_recover_queue(int domain, unsigned int bus, unsigned int devfn, 1018 int severity, struct aer_capability_regs *aer_regs) 1019 { 1020 struct aer_recover_entry entry = { 1021 .bus = bus, 1022 .devfn = devfn, 1023 .domain = domain, 1024 .severity = severity, 1025 .regs = aer_regs, 1026 }; 1027 1028 if (kfifo_in_spinlocked(&aer_recover_ring, &entry, 1, 1029 &aer_recover_ring_lock)) 1030 schedule_work(&aer_recover_work); 1031 else 1032 pr_err("buffer overflow in recovery for %04x:%02x:%02x.%x\n", 1033 domain, bus, PCI_SLOT(devfn), PCI_FUNC(devfn)); 1034 } 1035 EXPORT_SYMBOL_GPL(aer_recover_queue); 1036 #endif 1037 1038 /** 1039 * aer_get_device_error_info - read error status from dev and store it to info 1040 * @dev: pointer to the device expected to have a error record 1041 * @info: pointer to structure to store the error record 1042 * 1043 * Return 1 on success, 0 on error. 1044 * 1045 * Note that @info is reused among all error devices. Clear fields properly. 1046 */ 1047 int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info) 1048 { 1049 int type = pci_pcie_type(dev); 1050 int aer = dev->aer_cap; 1051 int temp; 1052 1053 /* Must reset in this function */ 1054 info->status = 0; 1055 info->tlp_header_valid = 0; 1056 1057 /* The device might not support AER */ 1058 if (!aer) 1059 return 0; 1060 1061 if (info->severity == AER_CORRECTABLE) { 1062 pci_read_config_dword(dev, aer + PCI_ERR_COR_STATUS, 1063 &info->status); 1064 pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK, 1065 &info->mask); 1066 if (!(info->status & ~info->mask)) 1067 return 0; 1068 } else if (type == PCI_EXP_TYPE_ROOT_PORT || 1069 type == PCI_EXP_TYPE_RC_EC || 1070 type == PCI_EXP_TYPE_DOWNSTREAM || 1071 info->severity == AER_NONFATAL) { 1072 1073 /* Link is still healthy for IO reads */ 1074 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, 1075 &info->status); 1076 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, 1077 &info->mask); 1078 if (!(info->status & ~info->mask)) 1079 return 0; 1080 1081 /* Get First Error Pointer */ 1082 pci_read_config_dword(dev, aer + PCI_ERR_CAP, &temp); 1083 info->first_error = PCI_ERR_CAP_FEP(temp); 1084 1085 if (info->status & AER_LOG_TLP_MASKS) { 1086 info->tlp_header_valid = 1; 1087 pci_read_config_dword(dev, 1088 aer + PCI_ERR_HEADER_LOG, &info->tlp.dw0); 1089 pci_read_config_dword(dev, 1090 aer + PCI_ERR_HEADER_LOG + 4, &info->tlp.dw1); 1091 pci_read_config_dword(dev, 1092 aer + PCI_ERR_HEADER_LOG + 8, &info->tlp.dw2); 1093 pci_read_config_dword(dev, 1094 aer + PCI_ERR_HEADER_LOG + 12, &info->tlp.dw3); 1095 } 1096 } 1097 1098 return 1; 1099 } 1100 1101 static inline void aer_process_err_devices(struct aer_err_info *e_info) 1102 { 1103 int i; 1104 1105 /* Report all before handle them, not to lost records by reset etc. */ 1106 for (i = 0; i < e_info->error_dev_num && e_info->dev[i]; i++) { 1107 if (aer_get_device_error_info(e_info->dev[i], e_info)) 1108 aer_print_error(e_info->dev[i], e_info); 1109 } 1110 for (i = 0; i < e_info->error_dev_num && e_info->dev[i]; i++) { 1111 if (aer_get_device_error_info(e_info->dev[i], e_info)) 1112 handle_error_source(e_info->dev[i], e_info); 1113 } 1114 } 1115 1116 /** 1117 * aer_isr_one_error - consume an error detected by root port 1118 * @rpc: pointer to the root port which holds an error 1119 * @e_src: pointer to an error source 1120 */ 1121 static void aer_isr_one_error(struct aer_rpc *rpc, 1122 struct aer_err_source *e_src) 1123 { 1124 struct pci_dev *pdev = rpc->rpd; 1125 struct aer_err_info e_info; 1126 1127 pci_rootport_aer_stats_incr(pdev, e_src); 1128 1129 /* 1130 * There is a possibility that both correctable error and 1131 * uncorrectable error being logged. Report correctable error first. 1132 */ 1133 if (e_src->status & PCI_ERR_ROOT_COR_RCV) { 1134 e_info.id = ERR_COR_ID(e_src->id); 1135 e_info.severity = AER_CORRECTABLE; 1136 1137 if (e_src->status & PCI_ERR_ROOT_MULTI_COR_RCV) 1138 e_info.multi_error_valid = 1; 1139 else 1140 e_info.multi_error_valid = 0; 1141 aer_print_port_info(pdev, &e_info); 1142 1143 if (find_source_device(pdev, &e_info)) 1144 aer_process_err_devices(&e_info); 1145 } 1146 1147 if (e_src->status & PCI_ERR_ROOT_UNCOR_RCV) { 1148 e_info.id = ERR_UNCOR_ID(e_src->id); 1149 1150 if (e_src->status & PCI_ERR_ROOT_FATAL_RCV) 1151 e_info.severity = AER_FATAL; 1152 else 1153 e_info.severity = AER_NONFATAL; 1154 1155 if (e_src->status & PCI_ERR_ROOT_MULTI_UNCOR_RCV) 1156 e_info.multi_error_valid = 1; 1157 else 1158 e_info.multi_error_valid = 0; 1159 1160 aer_print_port_info(pdev, &e_info); 1161 1162 if (find_source_device(pdev, &e_info)) 1163 aer_process_err_devices(&e_info); 1164 } 1165 } 1166 1167 /** 1168 * aer_isr - consume errors detected by root port 1169 * @irq: IRQ assigned to Root Port 1170 * @context: pointer to Root Port data structure 1171 * 1172 * Invoked, as DPC, when root port records new detected error 1173 */ 1174 static irqreturn_t aer_isr(int irq, void *context) 1175 { 1176 struct pcie_device *dev = (struct pcie_device *)context; 1177 struct aer_rpc *rpc = get_service_data(dev); 1178 struct aer_err_source e_src; 1179 1180 if (kfifo_is_empty(&rpc->aer_fifo)) 1181 return IRQ_NONE; 1182 1183 while (kfifo_get(&rpc->aer_fifo, &e_src)) 1184 aer_isr_one_error(rpc, &e_src); 1185 return IRQ_HANDLED; 1186 } 1187 1188 /** 1189 * aer_irq - Root Port's ISR 1190 * @irq: IRQ assigned to Root Port 1191 * @context: pointer to Root Port data structure 1192 * 1193 * Invoked when Root Port detects AER messages. 1194 */ 1195 static irqreturn_t aer_irq(int irq, void *context) 1196 { 1197 struct pcie_device *pdev = (struct pcie_device *)context; 1198 struct aer_rpc *rpc = get_service_data(pdev); 1199 struct pci_dev *rp = rpc->rpd; 1200 int aer = rp->aer_cap; 1201 struct aer_err_source e_src = {}; 1202 1203 pci_read_config_dword(rp, aer + PCI_ERR_ROOT_STATUS, &e_src.status); 1204 if (!(e_src.status & AER_ERR_STATUS_MASK)) 1205 return IRQ_NONE; 1206 1207 pci_read_config_dword(rp, aer + PCI_ERR_ROOT_ERR_SRC, &e_src.id); 1208 pci_write_config_dword(rp, aer + PCI_ERR_ROOT_STATUS, e_src.status); 1209 1210 if (!kfifo_put(&rpc->aer_fifo, e_src)) 1211 return IRQ_HANDLED; 1212 1213 return IRQ_WAKE_THREAD; 1214 } 1215 1216 /** 1217 * aer_enable_rootport - enable Root Port's interrupts when receiving messages 1218 * @rpc: pointer to a Root Port data structure 1219 * 1220 * Invoked when PCIe bus loads AER service driver. 1221 */ 1222 static void aer_enable_rootport(struct aer_rpc *rpc) 1223 { 1224 struct pci_dev *pdev = rpc->rpd; 1225 int aer = pdev->aer_cap; 1226 u16 reg16; 1227 u32 reg32; 1228 1229 /* Clear PCIe Capability's Device Status */ 1230 pcie_capability_read_word(pdev, PCI_EXP_DEVSTA, ®16); 1231 pcie_capability_write_word(pdev, PCI_EXP_DEVSTA, reg16); 1232 1233 /* Disable system error generation in response to error messages */ 1234 pcie_capability_clear_word(pdev, PCI_EXP_RTCTL, 1235 SYSTEM_ERROR_INTR_ON_MESG_MASK); 1236 1237 /* Clear error status */ 1238 pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, ®32); 1239 pci_write_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, reg32); 1240 pci_read_config_dword(pdev, aer + PCI_ERR_COR_STATUS, ®32); 1241 pci_write_config_dword(pdev, aer + PCI_ERR_COR_STATUS, reg32); 1242 pci_read_config_dword(pdev, aer + PCI_ERR_UNCOR_STATUS, ®32); 1243 pci_write_config_dword(pdev, aer + PCI_ERR_UNCOR_STATUS, reg32); 1244 1245 /* Enable Root Port's interrupt in response to error messages */ 1246 pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, ®32); 1247 reg32 |= ROOT_PORT_INTR_ON_MESG_MASK; 1248 pci_write_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, reg32); 1249 } 1250 1251 /** 1252 * aer_disable_rootport - disable Root Port's interrupts when receiving messages 1253 * @rpc: pointer to a Root Port data structure 1254 * 1255 * Invoked when PCIe bus unloads AER service driver. 1256 */ 1257 static void aer_disable_rootport(struct aer_rpc *rpc) 1258 { 1259 struct pci_dev *pdev = rpc->rpd; 1260 int aer = pdev->aer_cap; 1261 u32 reg32; 1262 1263 /* Disable Root's interrupt in response to error messages */ 1264 pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, ®32); 1265 reg32 &= ~ROOT_PORT_INTR_ON_MESG_MASK; 1266 pci_write_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, reg32); 1267 1268 /* Clear Root's error status reg */ 1269 pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, ®32); 1270 pci_write_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, reg32); 1271 } 1272 1273 /** 1274 * aer_remove - clean up resources 1275 * @dev: pointer to the pcie_dev data structure 1276 * 1277 * Invoked when PCI Express bus unloads or AER probe fails. 1278 */ 1279 static void aer_remove(struct pcie_device *dev) 1280 { 1281 struct aer_rpc *rpc = get_service_data(dev); 1282 1283 aer_disable_rootport(rpc); 1284 } 1285 1286 /** 1287 * aer_probe - initialize resources 1288 * @dev: pointer to the pcie_dev data structure 1289 * 1290 * Invoked when PCI Express bus loads AER service driver. 1291 */ 1292 static int aer_probe(struct pcie_device *dev) 1293 { 1294 int status; 1295 struct aer_rpc *rpc; 1296 struct device *device = &dev->device; 1297 struct pci_dev *port = dev->port; 1298 1299 BUILD_BUG_ON(ARRAY_SIZE(aer_correctable_error_string) < 1300 AER_MAX_TYPEOF_COR_ERRS); 1301 BUILD_BUG_ON(ARRAY_SIZE(aer_uncorrectable_error_string) < 1302 AER_MAX_TYPEOF_UNCOR_ERRS); 1303 1304 /* Limit to Root Ports or Root Complex Event Collectors */ 1305 if ((pci_pcie_type(port) != PCI_EXP_TYPE_RC_EC) && 1306 (pci_pcie_type(port) != PCI_EXP_TYPE_ROOT_PORT)) 1307 return -ENODEV; 1308 1309 rpc = devm_kzalloc(device, sizeof(struct aer_rpc), GFP_KERNEL); 1310 if (!rpc) 1311 return -ENOMEM; 1312 1313 rpc->rpd = port; 1314 INIT_KFIFO(rpc->aer_fifo); 1315 set_service_data(dev, rpc); 1316 1317 status = devm_request_threaded_irq(device, dev->irq, aer_irq, aer_isr, 1318 IRQF_SHARED, "aerdrv", dev); 1319 if (status) { 1320 pci_err(port, "request AER IRQ %d failed\n", dev->irq); 1321 return status; 1322 } 1323 1324 aer_enable_rootport(rpc); 1325 pci_info(port, "enabled with IRQ %d\n", dev->irq); 1326 return 0; 1327 } 1328 1329 /** 1330 * aer_root_reset - reset Root Port hierarchy, RCEC, or RCiEP 1331 * @dev: pointer to Root Port, RCEC, or RCiEP 1332 * 1333 * Invoked by Port Bus driver when performing reset. 1334 */ 1335 static pci_ers_result_t aer_root_reset(struct pci_dev *dev) 1336 { 1337 int type = pci_pcie_type(dev); 1338 struct pci_dev *root; 1339 int aer; 1340 struct pci_host_bridge *host = pci_find_host_bridge(dev->bus); 1341 u32 reg32; 1342 int rc; 1343 1344 /* 1345 * Only Root Ports and RCECs have AER Root Command and Root Status 1346 * registers. If "dev" is an RCiEP, the relevant registers are in 1347 * the RCEC. 1348 */ 1349 if (type == PCI_EXP_TYPE_RC_END) 1350 root = dev->rcec; 1351 else 1352 root = pcie_find_root_port(dev); 1353 1354 /* 1355 * If the platform retained control of AER, an RCiEP may not have 1356 * an RCEC visible to us, so dev->rcec ("root") may be NULL. In 1357 * that case, firmware is responsible for these registers. 1358 */ 1359 aer = root ? root->aer_cap : 0; 1360 1361 if ((host->native_aer || pcie_ports_native) && aer) { 1362 /* Disable Root's interrupt in response to error messages */ 1363 pci_read_config_dword(root, aer + PCI_ERR_ROOT_COMMAND, ®32); 1364 reg32 &= ~ROOT_PORT_INTR_ON_MESG_MASK; 1365 pci_write_config_dword(root, aer + PCI_ERR_ROOT_COMMAND, reg32); 1366 } 1367 1368 if (type == PCI_EXP_TYPE_RC_EC || type == PCI_EXP_TYPE_RC_END) { 1369 rc = pcie_reset_flr(dev, PCI_RESET_DO_RESET); 1370 if (!rc) 1371 pci_info(dev, "has been reset\n"); 1372 else 1373 pci_info(dev, "not reset (no FLR support: %d)\n", rc); 1374 } else { 1375 rc = pci_bus_error_reset(dev); 1376 pci_info(dev, "%s Port link has been reset (%d)\n", 1377 pci_is_root_bus(dev->bus) ? "Root" : "Downstream", rc); 1378 } 1379 1380 if ((host->native_aer || pcie_ports_native) && aer) { 1381 /* Clear Root Error Status */ 1382 pci_read_config_dword(root, aer + PCI_ERR_ROOT_STATUS, ®32); 1383 pci_write_config_dword(root, aer + PCI_ERR_ROOT_STATUS, reg32); 1384 1385 /* Enable Root Port's interrupt in response to error messages */ 1386 pci_read_config_dword(root, aer + PCI_ERR_ROOT_COMMAND, ®32); 1387 reg32 |= ROOT_PORT_INTR_ON_MESG_MASK; 1388 pci_write_config_dword(root, aer + PCI_ERR_ROOT_COMMAND, reg32); 1389 } 1390 1391 return rc ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED; 1392 } 1393 1394 static struct pcie_port_service_driver aerdriver = { 1395 .name = "aer", 1396 .port_type = PCIE_ANY_PORT, 1397 .service = PCIE_PORT_SERVICE_AER, 1398 1399 .probe = aer_probe, 1400 .remove = aer_remove, 1401 }; 1402 1403 /** 1404 * pcie_aer_init - register AER root service driver 1405 * 1406 * Invoked when AER root service driver is loaded. 1407 */ 1408 int __init pcie_aer_init(void) 1409 { 1410 if (!pci_aer_available()) 1411 return -ENXIO; 1412 return pcie_port_service_register(&aerdriver); 1413 } 1414