1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Implement the AER root port service driver. The driver registers an IRQ 4 * handler. When a root port triggers an AER interrupt, the IRQ handler 5 * collects root port status and schedules work. 6 * 7 * Copyright (C) 2006 Intel Corp. 8 * Tom Long Nguyen (tom.l.nguyen@intel.com) 9 * Zhang Yanmin (yanmin.zhang@intel.com) 10 * 11 * (C) Copyright 2009 Hewlett-Packard Development Company, L.P. 12 * Andrew Patterson <andrew.patterson@hp.com> 13 */ 14 15 #define pr_fmt(fmt) "AER: " fmt 16 #define dev_fmt pr_fmt 17 18 #include <linux/bitops.h> 19 #include <linux/cper.h> 20 #include <linux/pci.h> 21 #include <linux/pci-acpi.h> 22 #include <linux/sched.h> 23 #include <linux/kernel.h> 24 #include <linux/errno.h> 25 #include <linux/pm.h> 26 #include <linux/init.h> 27 #include <linux/interrupt.h> 28 #include <linux/delay.h> 29 #include <linux/kfifo.h> 30 #include <linux/slab.h> 31 #include <acpi/apei.h> 32 #include <ras/ras_event.h> 33 34 #include "../pci.h" 35 #include "portdrv.h" 36 37 #define AER_ERROR_SOURCES_MAX 128 38 39 #define AER_MAX_TYPEOF_COR_ERRS 16 /* as per PCI_ERR_COR_STATUS */ 40 #define AER_MAX_TYPEOF_UNCOR_ERRS 27 /* as per PCI_ERR_UNCOR_STATUS*/ 41 42 struct aer_err_source { 43 unsigned int status; 44 unsigned int id; 45 }; 46 47 struct aer_rpc { 48 struct pci_dev *rpd; /* Root Port device */ 49 DECLARE_KFIFO(aer_fifo, struct aer_err_source, AER_ERROR_SOURCES_MAX); 50 }; 51 52 /* AER stats for the device */ 53 struct aer_stats { 54 55 /* 56 * Fields for all AER capable devices. They indicate the errors 57 * "as seen by this device". Note that this may mean that if an 58 * end point is causing problems, the AER counters may increment 59 * at its link partner (e.g. root port) because the errors will be 60 * "seen" by the link partner and not the problematic end point 61 * itself (which may report all counters as 0 as it never saw any 62 * problems). 63 */ 64 /* Counters for different type of correctable errors */ 65 u64 dev_cor_errs[AER_MAX_TYPEOF_COR_ERRS]; 66 /* Counters for different type of fatal uncorrectable errors */ 67 u64 dev_fatal_errs[AER_MAX_TYPEOF_UNCOR_ERRS]; 68 /* Counters for different type of nonfatal uncorrectable errors */ 69 u64 dev_nonfatal_errs[AER_MAX_TYPEOF_UNCOR_ERRS]; 70 /* Total number of ERR_COR sent by this device */ 71 u64 dev_total_cor_errs; 72 /* Total number of ERR_FATAL sent by this device */ 73 u64 dev_total_fatal_errs; 74 /* Total number of ERR_NONFATAL sent by this device */ 75 u64 dev_total_nonfatal_errs; 76 77 /* 78 * Fields for Root ports & root complex event collectors only, these 79 * indicate the total number of ERR_COR, ERR_FATAL, and ERR_NONFATAL 80 * messages received by the root port / event collector, INCLUDING the 81 * ones that are generated internally (by the rootport itself) 82 */ 83 u64 rootport_total_cor_errs; 84 u64 rootport_total_fatal_errs; 85 u64 rootport_total_nonfatal_errs; 86 }; 87 88 #define AER_LOG_TLP_MASKS (PCI_ERR_UNC_POISON_TLP| \ 89 PCI_ERR_UNC_ECRC| \ 90 PCI_ERR_UNC_UNSUP| \ 91 PCI_ERR_UNC_COMP_ABORT| \ 92 PCI_ERR_UNC_UNX_COMP| \ 93 PCI_ERR_UNC_MALF_TLP) 94 95 #define SYSTEM_ERROR_INTR_ON_MESG_MASK (PCI_EXP_RTCTL_SECEE| \ 96 PCI_EXP_RTCTL_SENFEE| \ 97 PCI_EXP_RTCTL_SEFEE) 98 #define ROOT_PORT_INTR_ON_MESG_MASK (PCI_ERR_ROOT_CMD_COR_EN| \ 99 PCI_ERR_ROOT_CMD_NONFATAL_EN| \ 100 PCI_ERR_ROOT_CMD_FATAL_EN) 101 #define ERR_COR_ID(d) (d & 0xffff) 102 #define ERR_UNCOR_ID(d) (d >> 16) 103 104 #define AER_ERR_STATUS_MASK (PCI_ERR_ROOT_UNCOR_RCV | \ 105 PCI_ERR_ROOT_COR_RCV | \ 106 PCI_ERR_ROOT_MULTI_COR_RCV | \ 107 PCI_ERR_ROOT_MULTI_UNCOR_RCV) 108 109 static int pcie_aer_disable; 110 static pci_ers_result_t aer_root_reset(struct pci_dev *dev); 111 112 void pci_no_aer(void) 113 { 114 pcie_aer_disable = 1; 115 } 116 117 bool pci_aer_available(void) 118 { 119 return !pcie_aer_disable && pci_msi_enabled(); 120 } 121 122 #ifdef CONFIG_PCIE_ECRC 123 124 #define ECRC_POLICY_DEFAULT 0 /* ECRC set by BIOS */ 125 #define ECRC_POLICY_OFF 1 /* ECRC off for performance */ 126 #define ECRC_POLICY_ON 2 /* ECRC on for data integrity */ 127 128 static int ecrc_policy = ECRC_POLICY_DEFAULT; 129 130 static const char * const ecrc_policy_str[] = { 131 [ECRC_POLICY_DEFAULT] = "bios", 132 [ECRC_POLICY_OFF] = "off", 133 [ECRC_POLICY_ON] = "on" 134 }; 135 136 /** 137 * enable_ecrc_checking - enable PCIe ECRC checking for a device 138 * @dev: the PCI device 139 * 140 * Returns 0 on success, or negative on failure. 141 */ 142 static int enable_ecrc_checking(struct pci_dev *dev) 143 { 144 int aer = dev->aer_cap; 145 u32 reg32; 146 147 if (!aer) 148 return -ENODEV; 149 150 pci_read_config_dword(dev, aer + PCI_ERR_CAP, ®32); 151 if (reg32 & PCI_ERR_CAP_ECRC_GENC) 152 reg32 |= PCI_ERR_CAP_ECRC_GENE; 153 if (reg32 & PCI_ERR_CAP_ECRC_CHKC) 154 reg32 |= PCI_ERR_CAP_ECRC_CHKE; 155 pci_write_config_dword(dev, aer + PCI_ERR_CAP, reg32); 156 157 return 0; 158 } 159 160 /** 161 * disable_ecrc_checking - disables PCIe ECRC checking for a device 162 * @dev: the PCI device 163 * 164 * Returns 0 on success, or negative on failure. 165 */ 166 static int disable_ecrc_checking(struct pci_dev *dev) 167 { 168 int aer = dev->aer_cap; 169 u32 reg32; 170 171 if (!aer) 172 return -ENODEV; 173 174 pci_read_config_dword(dev, aer + PCI_ERR_CAP, ®32); 175 reg32 &= ~(PCI_ERR_CAP_ECRC_GENE | PCI_ERR_CAP_ECRC_CHKE); 176 pci_write_config_dword(dev, aer + PCI_ERR_CAP, reg32); 177 178 return 0; 179 } 180 181 /** 182 * pcie_set_ecrc_checking - set/unset PCIe ECRC checking for a device based on global policy 183 * @dev: the PCI device 184 */ 185 void pcie_set_ecrc_checking(struct pci_dev *dev) 186 { 187 if (!pcie_aer_is_native(dev)) 188 return; 189 190 switch (ecrc_policy) { 191 case ECRC_POLICY_DEFAULT: 192 return; 193 case ECRC_POLICY_OFF: 194 disable_ecrc_checking(dev); 195 break; 196 case ECRC_POLICY_ON: 197 enable_ecrc_checking(dev); 198 break; 199 default: 200 return; 201 } 202 } 203 204 /** 205 * pcie_ecrc_get_policy - parse kernel command-line ecrc option 206 * @str: ECRC policy from kernel command line to use 207 */ 208 void pcie_ecrc_get_policy(char *str) 209 { 210 int i; 211 212 i = match_string(ecrc_policy_str, ARRAY_SIZE(ecrc_policy_str), str); 213 if (i < 0) 214 return; 215 216 ecrc_policy = i; 217 } 218 #endif /* CONFIG_PCIE_ECRC */ 219 220 #define PCI_EXP_AER_FLAGS (PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE | \ 221 PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE) 222 223 int pcie_aer_is_native(struct pci_dev *dev) 224 { 225 struct pci_host_bridge *host = pci_find_host_bridge(dev->bus); 226 227 if (!dev->aer_cap) 228 return 0; 229 230 return pcie_ports_native || host->native_aer; 231 } 232 EXPORT_SYMBOL_NS_GPL(pcie_aer_is_native, CXL); 233 234 static int pci_enable_pcie_error_reporting(struct pci_dev *dev) 235 { 236 int rc; 237 238 if (!pcie_aer_is_native(dev)) 239 return -EIO; 240 241 rc = pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_AER_FLAGS); 242 return pcibios_err_to_errno(rc); 243 } 244 245 int pci_aer_clear_nonfatal_status(struct pci_dev *dev) 246 { 247 int aer = dev->aer_cap; 248 u32 status, sev; 249 250 if (!pcie_aer_is_native(dev)) 251 return -EIO; 252 253 /* Clear status bits for ERR_NONFATAL errors only */ 254 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status); 255 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, &sev); 256 status &= ~sev; 257 if (status) 258 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, status); 259 260 return 0; 261 } 262 EXPORT_SYMBOL_GPL(pci_aer_clear_nonfatal_status); 263 264 void pci_aer_clear_fatal_status(struct pci_dev *dev) 265 { 266 int aer = dev->aer_cap; 267 u32 status, sev; 268 269 if (!pcie_aer_is_native(dev)) 270 return; 271 272 /* Clear status bits for ERR_FATAL errors only */ 273 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status); 274 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, &sev); 275 status &= sev; 276 if (status) 277 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, status); 278 } 279 280 /** 281 * pci_aer_raw_clear_status - Clear AER error registers. 282 * @dev: the PCI device 283 * 284 * Clearing AER error status registers unconditionally, regardless of 285 * whether they're owned by firmware or the OS. 286 * 287 * Returns 0 on success, or negative on failure. 288 */ 289 int pci_aer_raw_clear_status(struct pci_dev *dev) 290 { 291 int aer = dev->aer_cap; 292 u32 status; 293 int port_type; 294 295 if (!aer) 296 return -EIO; 297 298 port_type = pci_pcie_type(dev); 299 if (port_type == PCI_EXP_TYPE_ROOT_PORT || 300 port_type == PCI_EXP_TYPE_RC_EC) { 301 pci_read_config_dword(dev, aer + PCI_ERR_ROOT_STATUS, &status); 302 pci_write_config_dword(dev, aer + PCI_ERR_ROOT_STATUS, status); 303 } 304 305 pci_read_config_dword(dev, aer + PCI_ERR_COR_STATUS, &status); 306 pci_write_config_dword(dev, aer + PCI_ERR_COR_STATUS, status); 307 308 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status); 309 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, status); 310 311 return 0; 312 } 313 314 int pci_aer_clear_status(struct pci_dev *dev) 315 { 316 if (!pcie_aer_is_native(dev)) 317 return -EIO; 318 319 return pci_aer_raw_clear_status(dev); 320 } 321 322 void pci_save_aer_state(struct pci_dev *dev) 323 { 324 int aer = dev->aer_cap; 325 struct pci_cap_saved_state *save_state; 326 u32 *cap; 327 328 if (!aer) 329 return; 330 331 save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_ERR); 332 if (!save_state) 333 return; 334 335 cap = &save_state->cap.data[0]; 336 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, cap++); 337 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, cap++); 338 pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK, cap++); 339 pci_read_config_dword(dev, aer + PCI_ERR_CAP, cap++); 340 if (pcie_cap_has_rtctl(dev)) 341 pci_read_config_dword(dev, aer + PCI_ERR_ROOT_COMMAND, cap++); 342 } 343 344 void pci_restore_aer_state(struct pci_dev *dev) 345 { 346 int aer = dev->aer_cap; 347 struct pci_cap_saved_state *save_state; 348 u32 *cap; 349 350 if (!aer) 351 return; 352 353 save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_ERR); 354 if (!save_state) 355 return; 356 357 cap = &save_state->cap.data[0]; 358 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, *cap++); 359 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, *cap++); 360 pci_write_config_dword(dev, aer + PCI_ERR_COR_MASK, *cap++); 361 pci_write_config_dword(dev, aer + PCI_ERR_CAP, *cap++); 362 if (pcie_cap_has_rtctl(dev)) 363 pci_write_config_dword(dev, aer + PCI_ERR_ROOT_COMMAND, *cap++); 364 } 365 366 void pci_aer_init(struct pci_dev *dev) 367 { 368 int n; 369 370 dev->aer_cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); 371 if (!dev->aer_cap) 372 return; 373 374 dev->aer_stats = kzalloc(sizeof(struct aer_stats), GFP_KERNEL); 375 376 /* 377 * We save/restore PCI_ERR_UNCOR_MASK, PCI_ERR_UNCOR_SEVER, 378 * PCI_ERR_COR_MASK, and PCI_ERR_CAP. Root and Root Complex Event 379 * Collectors also implement PCI_ERR_ROOT_COMMAND (PCIe r5.0, sec 380 * 7.8.4). 381 */ 382 n = pcie_cap_has_rtctl(dev) ? 5 : 4; 383 pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_ERR, sizeof(u32) * n); 384 385 pci_aer_clear_status(dev); 386 387 if (pci_aer_available()) 388 pci_enable_pcie_error_reporting(dev); 389 390 pcie_set_ecrc_checking(dev); 391 } 392 393 void pci_aer_exit(struct pci_dev *dev) 394 { 395 kfree(dev->aer_stats); 396 dev->aer_stats = NULL; 397 } 398 399 #define AER_AGENT_RECEIVER 0 400 #define AER_AGENT_REQUESTER 1 401 #define AER_AGENT_COMPLETER 2 402 #define AER_AGENT_TRANSMITTER 3 403 404 #define AER_AGENT_REQUESTER_MASK(t) ((t == AER_CORRECTABLE) ? \ 405 0 : (PCI_ERR_UNC_COMP_TIME|PCI_ERR_UNC_UNSUP)) 406 #define AER_AGENT_COMPLETER_MASK(t) ((t == AER_CORRECTABLE) ? \ 407 0 : PCI_ERR_UNC_COMP_ABORT) 408 #define AER_AGENT_TRANSMITTER_MASK(t) ((t == AER_CORRECTABLE) ? \ 409 (PCI_ERR_COR_REP_ROLL|PCI_ERR_COR_REP_TIMER) : 0) 410 411 #define AER_GET_AGENT(t, e) \ 412 ((e & AER_AGENT_COMPLETER_MASK(t)) ? AER_AGENT_COMPLETER : \ 413 (e & AER_AGENT_REQUESTER_MASK(t)) ? AER_AGENT_REQUESTER : \ 414 (e & AER_AGENT_TRANSMITTER_MASK(t)) ? AER_AGENT_TRANSMITTER : \ 415 AER_AGENT_RECEIVER) 416 417 #define AER_PHYSICAL_LAYER_ERROR 0 418 #define AER_DATA_LINK_LAYER_ERROR 1 419 #define AER_TRANSACTION_LAYER_ERROR 2 420 421 #define AER_PHYSICAL_LAYER_ERROR_MASK(t) ((t == AER_CORRECTABLE) ? \ 422 PCI_ERR_COR_RCVR : 0) 423 #define AER_DATA_LINK_LAYER_ERROR_MASK(t) ((t == AER_CORRECTABLE) ? \ 424 (PCI_ERR_COR_BAD_TLP| \ 425 PCI_ERR_COR_BAD_DLLP| \ 426 PCI_ERR_COR_REP_ROLL| \ 427 PCI_ERR_COR_REP_TIMER) : PCI_ERR_UNC_DLP) 428 429 #define AER_GET_LAYER_ERROR(t, e) \ 430 ((e & AER_PHYSICAL_LAYER_ERROR_MASK(t)) ? AER_PHYSICAL_LAYER_ERROR : \ 431 (e & AER_DATA_LINK_LAYER_ERROR_MASK(t)) ? AER_DATA_LINK_LAYER_ERROR : \ 432 AER_TRANSACTION_LAYER_ERROR) 433 434 /* 435 * AER error strings 436 */ 437 static const char *aer_error_severity_string[] = { 438 "Uncorrected (Non-Fatal)", 439 "Uncorrected (Fatal)", 440 "Corrected" 441 }; 442 443 static const char *aer_error_layer[] = { 444 "Physical Layer", 445 "Data Link Layer", 446 "Transaction Layer" 447 }; 448 449 static const char *aer_correctable_error_string[] = { 450 "RxErr", /* Bit Position 0 */ 451 NULL, 452 NULL, 453 NULL, 454 NULL, 455 NULL, 456 "BadTLP", /* Bit Position 6 */ 457 "BadDLLP", /* Bit Position 7 */ 458 "Rollover", /* Bit Position 8 */ 459 NULL, 460 NULL, 461 NULL, 462 "Timeout", /* Bit Position 12 */ 463 "NonFatalErr", /* Bit Position 13 */ 464 "CorrIntErr", /* Bit Position 14 */ 465 "HeaderOF", /* Bit Position 15 */ 466 NULL, /* Bit Position 16 */ 467 NULL, /* Bit Position 17 */ 468 NULL, /* Bit Position 18 */ 469 NULL, /* Bit Position 19 */ 470 NULL, /* Bit Position 20 */ 471 NULL, /* Bit Position 21 */ 472 NULL, /* Bit Position 22 */ 473 NULL, /* Bit Position 23 */ 474 NULL, /* Bit Position 24 */ 475 NULL, /* Bit Position 25 */ 476 NULL, /* Bit Position 26 */ 477 NULL, /* Bit Position 27 */ 478 NULL, /* Bit Position 28 */ 479 NULL, /* Bit Position 29 */ 480 NULL, /* Bit Position 30 */ 481 NULL, /* Bit Position 31 */ 482 }; 483 484 static const char *aer_uncorrectable_error_string[] = { 485 "Undefined", /* Bit Position 0 */ 486 NULL, 487 NULL, 488 NULL, 489 "DLP", /* Bit Position 4 */ 490 "SDES", /* Bit Position 5 */ 491 NULL, 492 NULL, 493 NULL, 494 NULL, 495 NULL, 496 NULL, 497 "TLP", /* Bit Position 12 */ 498 "FCP", /* Bit Position 13 */ 499 "CmpltTO", /* Bit Position 14 */ 500 "CmpltAbrt", /* Bit Position 15 */ 501 "UnxCmplt", /* Bit Position 16 */ 502 "RxOF", /* Bit Position 17 */ 503 "MalfTLP", /* Bit Position 18 */ 504 "ECRC", /* Bit Position 19 */ 505 "UnsupReq", /* Bit Position 20 */ 506 "ACSViol", /* Bit Position 21 */ 507 "UncorrIntErr", /* Bit Position 22 */ 508 "BlockedTLP", /* Bit Position 23 */ 509 "AtomicOpBlocked", /* Bit Position 24 */ 510 "TLPBlockedErr", /* Bit Position 25 */ 511 "PoisonTLPBlocked", /* Bit Position 26 */ 512 NULL, /* Bit Position 27 */ 513 NULL, /* Bit Position 28 */ 514 NULL, /* Bit Position 29 */ 515 NULL, /* Bit Position 30 */ 516 NULL, /* Bit Position 31 */ 517 }; 518 519 static const char *aer_agent_string[] = { 520 "Receiver ID", 521 "Requester ID", 522 "Completer ID", 523 "Transmitter ID" 524 }; 525 526 #define aer_stats_dev_attr(name, stats_array, strings_array, \ 527 total_string, total_field) \ 528 static ssize_t \ 529 name##_show(struct device *dev, struct device_attribute *attr, \ 530 char *buf) \ 531 { \ 532 unsigned int i; \ 533 struct pci_dev *pdev = to_pci_dev(dev); \ 534 u64 *stats = pdev->aer_stats->stats_array; \ 535 size_t len = 0; \ 536 \ 537 for (i = 0; i < ARRAY_SIZE(pdev->aer_stats->stats_array); i++) {\ 538 if (strings_array[i]) \ 539 len += sysfs_emit_at(buf, len, "%s %llu\n", \ 540 strings_array[i], \ 541 stats[i]); \ 542 else if (stats[i]) \ 543 len += sysfs_emit_at(buf, len, \ 544 #stats_array "_bit[%d] %llu\n",\ 545 i, stats[i]); \ 546 } \ 547 len += sysfs_emit_at(buf, len, "TOTAL_%s %llu\n", total_string, \ 548 pdev->aer_stats->total_field); \ 549 return len; \ 550 } \ 551 static DEVICE_ATTR_RO(name) 552 553 aer_stats_dev_attr(aer_dev_correctable, dev_cor_errs, 554 aer_correctable_error_string, "ERR_COR", 555 dev_total_cor_errs); 556 aer_stats_dev_attr(aer_dev_fatal, dev_fatal_errs, 557 aer_uncorrectable_error_string, "ERR_FATAL", 558 dev_total_fatal_errs); 559 aer_stats_dev_attr(aer_dev_nonfatal, dev_nonfatal_errs, 560 aer_uncorrectable_error_string, "ERR_NONFATAL", 561 dev_total_nonfatal_errs); 562 563 #define aer_stats_rootport_attr(name, field) \ 564 static ssize_t \ 565 name##_show(struct device *dev, struct device_attribute *attr, \ 566 char *buf) \ 567 { \ 568 struct pci_dev *pdev = to_pci_dev(dev); \ 569 return sysfs_emit(buf, "%llu\n", pdev->aer_stats->field); \ 570 } \ 571 static DEVICE_ATTR_RO(name) 572 573 aer_stats_rootport_attr(aer_rootport_total_err_cor, 574 rootport_total_cor_errs); 575 aer_stats_rootport_attr(aer_rootport_total_err_fatal, 576 rootport_total_fatal_errs); 577 aer_stats_rootport_attr(aer_rootport_total_err_nonfatal, 578 rootport_total_nonfatal_errs); 579 580 static struct attribute *aer_stats_attrs[] __ro_after_init = { 581 &dev_attr_aer_dev_correctable.attr, 582 &dev_attr_aer_dev_fatal.attr, 583 &dev_attr_aer_dev_nonfatal.attr, 584 &dev_attr_aer_rootport_total_err_cor.attr, 585 &dev_attr_aer_rootport_total_err_fatal.attr, 586 &dev_attr_aer_rootport_total_err_nonfatal.attr, 587 NULL 588 }; 589 590 static umode_t aer_stats_attrs_are_visible(struct kobject *kobj, 591 struct attribute *a, int n) 592 { 593 struct device *dev = kobj_to_dev(kobj); 594 struct pci_dev *pdev = to_pci_dev(dev); 595 596 if (!pdev->aer_stats) 597 return 0; 598 599 if ((a == &dev_attr_aer_rootport_total_err_cor.attr || 600 a == &dev_attr_aer_rootport_total_err_fatal.attr || 601 a == &dev_attr_aer_rootport_total_err_nonfatal.attr) && 602 ((pci_pcie_type(pdev) != PCI_EXP_TYPE_ROOT_PORT) && 603 (pci_pcie_type(pdev) != PCI_EXP_TYPE_RC_EC))) 604 return 0; 605 606 return a->mode; 607 } 608 609 const struct attribute_group aer_stats_attr_group = { 610 .attrs = aer_stats_attrs, 611 .is_visible = aer_stats_attrs_are_visible, 612 }; 613 614 static void pci_dev_aer_stats_incr(struct pci_dev *pdev, 615 struct aer_err_info *info) 616 { 617 unsigned long status = info->status & ~info->mask; 618 int i, max = -1; 619 u64 *counter = NULL; 620 struct aer_stats *aer_stats = pdev->aer_stats; 621 622 if (!aer_stats) 623 return; 624 625 switch (info->severity) { 626 case AER_CORRECTABLE: 627 aer_stats->dev_total_cor_errs++; 628 counter = &aer_stats->dev_cor_errs[0]; 629 max = AER_MAX_TYPEOF_COR_ERRS; 630 break; 631 case AER_NONFATAL: 632 aer_stats->dev_total_nonfatal_errs++; 633 counter = &aer_stats->dev_nonfatal_errs[0]; 634 max = AER_MAX_TYPEOF_UNCOR_ERRS; 635 break; 636 case AER_FATAL: 637 aer_stats->dev_total_fatal_errs++; 638 counter = &aer_stats->dev_fatal_errs[0]; 639 max = AER_MAX_TYPEOF_UNCOR_ERRS; 640 break; 641 } 642 643 for_each_set_bit(i, &status, max) 644 counter[i]++; 645 } 646 647 static void pci_rootport_aer_stats_incr(struct pci_dev *pdev, 648 struct aer_err_source *e_src) 649 { 650 struct aer_stats *aer_stats = pdev->aer_stats; 651 652 if (!aer_stats) 653 return; 654 655 if (e_src->status & PCI_ERR_ROOT_COR_RCV) 656 aer_stats->rootport_total_cor_errs++; 657 658 if (e_src->status & PCI_ERR_ROOT_UNCOR_RCV) { 659 if (e_src->status & PCI_ERR_ROOT_FATAL_RCV) 660 aer_stats->rootport_total_fatal_errs++; 661 else 662 aer_stats->rootport_total_nonfatal_errs++; 663 } 664 } 665 666 static void __print_tlp_header(struct pci_dev *dev, 667 struct aer_header_log_regs *t) 668 { 669 pci_err(dev, " TLP Header: %08x %08x %08x %08x\n", 670 t->dw0, t->dw1, t->dw2, t->dw3); 671 } 672 673 static void __aer_print_error(struct pci_dev *dev, 674 struct aer_err_info *info) 675 { 676 const char **strings; 677 unsigned long status = info->status & ~info->mask; 678 const char *level, *errmsg; 679 int i; 680 681 if (info->severity == AER_CORRECTABLE) { 682 strings = aer_correctable_error_string; 683 level = KERN_WARNING; 684 } else { 685 strings = aer_uncorrectable_error_string; 686 level = KERN_ERR; 687 } 688 689 for_each_set_bit(i, &status, 32) { 690 errmsg = strings[i]; 691 if (!errmsg) 692 errmsg = "Unknown Error Bit"; 693 694 pci_printk(level, dev, " [%2d] %-22s%s\n", i, errmsg, 695 info->first_error == i ? " (First)" : ""); 696 } 697 pci_dev_aer_stats_incr(dev, info); 698 } 699 700 void aer_print_error(struct pci_dev *dev, struct aer_err_info *info) 701 { 702 int layer, agent; 703 int id = pci_dev_id(dev); 704 const char *level; 705 706 if (!info->status) { 707 pci_err(dev, "PCIe Bus Error: severity=%s, type=Inaccessible, (Unregistered Agent ID)\n", 708 aer_error_severity_string[info->severity]); 709 goto out; 710 } 711 712 layer = AER_GET_LAYER_ERROR(info->severity, info->status); 713 agent = AER_GET_AGENT(info->severity, info->status); 714 715 level = (info->severity == AER_CORRECTABLE) ? KERN_WARNING : KERN_ERR; 716 717 pci_printk(level, dev, "PCIe Bus Error: severity=%s, type=%s, (%s)\n", 718 aer_error_severity_string[info->severity], 719 aer_error_layer[layer], aer_agent_string[agent]); 720 721 pci_printk(level, dev, " device [%04x:%04x] error status/mask=%08x/%08x\n", 722 dev->vendor, dev->device, info->status, info->mask); 723 724 __aer_print_error(dev, info); 725 726 if (info->tlp_header_valid) 727 __print_tlp_header(dev, &info->tlp); 728 729 out: 730 if (info->id && info->error_dev_num > 1 && info->id == id) 731 pci_err(dev, " Error of this Agent is reported first\n"); 732 733 trace_aer_event(dev_name(&dev->dev), (info->status & ~info->mask), 734 info->severity, info->tlp_header_valid, &info->tlp); 735 } 736 737 static void aer_print_port_info(struct pci_dev *dev, struct aer_err_info *info) 738 { 739 u8 bus = info->id >> 8; 740 u8 devfn = info->id & 0xff; 741 742 pci_info(dev, "%s%s error received: %04x:%02x:%02x.%d\n", 743 info->multi_error_valid ? "Multiple " : "", 744 aer_error_severity_string[info->severity], 745 pci_domain_nr(dev->bus), bus, PCI_SLOT(devfn), 746 PCI_FUNC(devfn)); 747 } 748 749 #ifdef CONFIG_ACPI_APEI_PCIEAER 750 int cper_severity_to_aer(int cper_severity) 751 { 752 switch (cper_severity) { 753 case CPER_SEV_RECOVERABLE: 754 return AER_NONFATAL; 755 case CPER_SEV_FATAL: 756 return AER_FATAL; 757 default: 758 return AER_CORRECTABLE; 759 } 760 } 761 EXPORT_SYMBOL_GPL(cper_severity_to_aer); 762 763 void cper_print_aer(struct pci_dev *dev, int aer_severity, 764 struct aer_capability_regs *aer) 765 { 766 int layer, agent, tlp_header_valid = 0; 767 u32 status, mask; 768 struct aer_err_info info; 769 770 if (aer_severity == AER_CORRECTABLE) { 771 status = aer->cor_status; 772 mask = aer->cor_mask; 773 } else { 774 status = aer->uncor_status; 775 mask = aer->uncor_mask; 776 tlp_header_valid = status & AER_LOG_TLP_MASKS; 777 } 778 779 layer = AER_GET_LAYER_ERROR(aer_severity, status); 780 agent = AER_GET_AGENT(aer_severity, status); 781 782 memset(&info, 0, sizeof(info)); 783 info.severity = aer_severity; 784 info.status = status; 785 info.mask = mask; 786 info.first_error = PCI_ERR_CAP_FEP(aer->cap_control); 787 788 pci_err(dev, "aer_status: 0x%08x, aer_mask: 0x%08x\n", status, mask); 789 __aer_print_error(dev, &info); 790 pci_err(dev, "aer_layer=%s, aer_agent=%s\n", 791 aer_error_layer[layer], aer_agent_string[agent]); 792 793 if (aer_severity != AER_CORRECTABLE) 794 pci_err(dev, "aer_uncor_severity: 0x%08x\n", 795 aer->uncor_severity); 796 797 if (tlp_header_valid) 798 __print_tlp_header(dev, &aer->header_log); 799 800 trace_aer_event(dev_name(&dev->dev), (status & ~mask), 801 aer_severity, tlp_header_valid, &aer->header_log); 802 } 803 #endif 804 805 /** 806 * add_error_device - list device to be handled 807 * @e_info: pointer to error info 808 * @dev: pointer to pci_dev to be added 809 */ 810 static int add_error_device(struct aer_err_info *e_info, struct pci_dev *dev) 811 { 812 if (e_info->error_dev_num < AER_MAX_MULTI_ERR_DEVICES) { 813 e_info->dev[e_info->error_dev_num] = pci_dev_get(dev); 814 e_info->error_dev_num++; 815 return 0; 816 } 817 return -ENOSPC; 818 } 819 820 /** 821 * is_error_source - check whether the device is source of reported error 822 * @dev: pointer to pci_dev to be checked 823 * @e_info: pointer to reported error info 824 */ 825 static bool is_error_source(struct pci_dev *dev, struct aer_err_info *e_info) 826 { 827 int aer = dev->aer_cap; 828 u32 status, mask; 829 u16 reg16; 830 831 /* 832 * When bus id is equal to 0, it might be a bad id 833 * reported by root port. 834 */ 835 if ((PCI_BUS_NUM(e_info->id) != 0) && 836 !(dev->bus->bus_flags & PCI_BUS_FLAGS_NO_AERSID)) { 837 /* Device ID match? */ 838 if (e_info->id == pci_dev_id(dev)) 839 return true; 840 841 /* Continue id comparing if there is no multiple error */ 842 if (!e_info->multi_error_valid) 843 return false; 844 } 845 846 /* 847 * When either 848 * 1) bus id is equal to 0. Some ports might lose the bus 849 * id of error source id; 850 * 2) bus flag PCI_BUS_FLAGS_NO_AERSID is set 851 * 3) There are multiple errors and prior ID comparing fails; 852 * We check AER status registers to find possible reporter. 853 */ 854 if (atomic_read(&dev->enable_cnt) == 0) 855 return false; 856 857 /* Check if AER is enabled */ 858 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, ®16); 859 if (!(reg16 & PCI_EXP_AER_FLAGS)) 860 return false; 861 862 if (!aer) 863 return false; 864 865 /* Check if error is recorded */ 866 if (e_info->severity == AER_CORRECTABLE) { 867 pci_read_config_dword(dev, aer + PCI_ERR_COR_STATUS, &status); 868 pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK, &mask); 869 } else { 870 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status); 871 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, &mask); 872 } 873 if (status & ~mask) 874 return true; 875 876 return false; 877 } 878 879 static int find_device_iter(struct pci_dev *dev, void *data) 880 { 881 struct aer_err_info *e_info = (struct aer_err_info *)data; 882 883 if (is_error_source(dev, e_info)) { 884 /* List this device */ 885 if (add_error_device(e_info, dev)) { 886 /* We cannot handle more... Stop iteration */ 887 /* TODO: Should print error message here? */ 888 return 1; 889 } 890 891 /* If there is only a single error, stop iteration */ 892 if (!e_info->multi_error_valid) 893 return 1; 894 } 895 return 0; 896 } 897 898 /** 899 * find_source_device - search through device hierarchy for source device 900 * @parent: pointer to Root Port pci_dev data structure 901 * @e_info: including detailed error information such like id 902 * 903 * Return true if found. 904 * 905 * Invoked by DPC when error is detected at the Root Port. 906 * Caller of this function must set id, severity, and multi_error_valid of 907 * struct aer_err_info pointed by @e_info properly. This function must fill 908 * e_info->error_dev_num and e_info->dev[], based on the given information. 909 */ 910 static bool find_source_device(struct pci_dev *parent, 911 struct aer_err_info *e_info) 912 { 913 struct pci_dev *dev = parent; 914 int result; 915 916 /* Must reset in this function */ 917 e_info->error_dev_num = 0; 918 919 /* Is Root Port an agent that sends error message? */ 920 result = find_device_iter(dev, e_info); 921 if (result) 922 return true; 923 924 if (pci_pcie_type(parent) == PCI_EXP_TYPE_RC_EC) 925 pcie_walk_rcec(parent, find_device_iter, e_info); 926 else 927 pci_walk_bus(parent->subordinate, find_device_iter, e_info); 928 929 if (!e_info->error_dev_num) { 930 pci_info(parent, "can't find device of ID%04x\n", e_info->id); 931 return false; 932 } 933 return true; 934 } 935 936 /** 937 * handle_error_source - handle logging error into an event log 938 * @dev: pointer to pci_dev data structure of error source device 939 * @info: comprehensive error information 940 * 941 * Invoked when an error being detected by Root Port. 942 */ 943 static void handle_error_source(struct pci_dev *dev, struct aer_err_info *info) 944 { 945 int aer = dev->aer_cap; 946 947 if (info->severity == AER_CORRECTABLE) { 948 /* 949 * Correctable error does not need software intervention. 950 * No need to go through error recovery process. 951 */ 952 if (aer) 953 pci_write_config_dword(dev, aer + PCI_ERR_COR_STATUS, 954 info->status); 955 if (pcie_aer_is_native(dev)) { 956 struct pci_driver *pdrv = dev->driver; 957 958 if (pdrv && pdrv->err_handler && 959 pdrv->err_handler->cor_error_detected) 960 pdrv->err_handler->cor_error_detected(dev); 961 pcie_clear_device_status(dev); 962 } 963 } else if (info->severity == AER_NONFATAL) 964 pcie_do_recovery(dev, pci_channel_io_normal, aer_root_reset); 965 else if (info->severity == AER_FATAL) 966 pcie_do_recovery(dev, pci_channel_io_frozen, aer_root_reset); 967 pci_dev_put(dev); 968 } 969 970 #ifdef CONFIG_ACPI_APEI_PCIEAER 971 972 #define AER_RECOVER_RING_SIZE 16 973 974 struct aer_recover_entry { 975 u8 bus; 976 u8 devfn; 977 u16 domain; 978 int severity; 979 struct aer_capability_regs *regs; 980 }; 981 982 static DEFINE_KFIFO(aer_recover_ring, struct aer_recover_entry, 983 AER_RECOVER_RING_SIZE); 984 985 static void aer_recover_work_func(struct work_struct *work) 986 { 987 struct aer_recover_entry entry; 988 struct pci_dev *pdev; 989 990 while (kfifo_get(&aer_recover_ring, &entry)) { 991 pdev = pci_get_domain_bus_and_slot(entry.domain, entry.bus, 992 entry.devfn); 993 if (!pdev) { 994 pr_err("no pci_dev for %04x:%02x:%02x.%x\n", 995 entry.domain, entry.bus, 996 PCI_SLOT(entry.devfn), PCI_FUNC(entry.devfn)); 997 continue; 998 } 999 cper_print_aer(pdev, entry.severity, entry.regs); 1000 if (entry.severity == AER_NONFATAL) 1001 pcie_do_recovery(pdev, pci_channel_io_normal, 1002 aer_root_reset); 1003 else if (entry.severity == AER_FATAL) 1004 pcie_do_recovery(pdev, pci_channel_io_frozen, 1005 aer_root_reset); 1006 pci_dev_put(pdev); 1007 } 1008 } 1009 1010 /* 1011 * Mutual exclusion for writers of aer_recover_ring, reader side don't 1012 * need lock, because there is only one reader and lock is not needed 1013 * between reader and writer. 1014 */ 1015 static DEFINE_SPINLOCK(aer_recover_ring_lock); 1016 static DECLARE_WORK(aer_recover_work, aer_recover_work_func); 1017 1018 void aer_recover_queue(int domain, unsigned int bus, unsigned int devfn, 1019 int severity, struct aer_capability_regs *aer_regs) 1020 { 1021 struct aer_recover_entry entry = { 1022 .bus = bus, 1023 .devfn = devfn, 1024 .domain = domain, 1025 .severity = severity, 1026 .regs = aer_regs, 1027 }; 1028 1029 if (kfifo_in_spinlocked(&aer_recover_ring, &entry, 1, 1030 &aer_recover_ring_lock)) 1031 schedule_work(&aer_recover_work); 1032 else 1033 pr_err("buffer overflow in recovery for %04x:%02x:%02x.%x\n", 1034 domain, bus, PCI_SLOT(devfn), PCI_FUNC(devfn)); 1035 } 1036 EXPORT_SYMBOL_GPL(aer_recover_queue); 1037 #endif 1038 1039 /** 1040 * aer_get_device_error_info - read error status from dev and store it to info 1041 * @dev: pointer to the device expected to have a error record 1042 * @info: pointer to structure to store the error record 1043 * 1044 * Return 1 on success, 0 on error. 1045 * 1046 * Note that @info is reused among all error devices. Clear fields properly. 1047 */ 1048 int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info) 1049 { 1050 int type = pci_pcie_type(dev); 1051 int aer = dev->aer_cap; 1052 int temp; 1053 1054 /* Must reset in this function */ 1055 info->status = 0; 1056 info->tlp_header_valid = 0; 1057 1058 /* The device might not support AER */ 1059 if (!aer) 1060 return 0; 1061 1062 if (info->severity == AER_CORRECTABLE) { 1063 pci_read_config_dword(dev, aer + PCI_ERR_COR_STATUS, 1064 &info->status); 1065 pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK, 1066 &info->mask); 1067 if (!(info->status & ~info->mask)) 1068 return 0; 1069 } else if (type == PCI_EXP_TYPE_ROOT_PORT || 1070 type == PCI_EXP_TYPE_RC_EC || 1071 type == PCI_EXP_TYPE_DOWNSTREAM || 1072 info->severity == AER_NONFATAL) { 1073 1074 /* Link is still healthy for IO reads */ 1075 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, 1076 &info->status); 1077 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, 1078 &info->mask); 1079 if (!(info->status & ~info->mask)) 1080 return 0; 1081 1082 /* Get First Error Pointer */ 1083 pci_read_config_dword(dev, aer + PCI_ERR_CAP, &temp); 1084 info->first_error = PCI_ERR_CAP_FEP(temp); 1085 1086 if (info->status & AER_LOG_TLP_MASKS) { 1087 info->tlp_header_valid = 1; 1088 pci_read_config_dword(dev, 1089 aer + PCI_ERR_HEADER_LOG, &info->tlp.dw0); 1090 pci_read_config_dword(dev, 1091 aer + PCI_ERR_HEADER_LOG + 4, &info->tlp.dw1); 1092 pci_read_config_dword(dev, 1093 aer + PCI_ERR_HEADER_LOG + 8, &info->tlp.dw2); 1094 pci_read_config_dword(dev, 1095 aer + PCI_ERR_HEADER_LOG + 12, &info->tlp.dw3); 1096 } 1097 } 1098 1099 return 1; 1100 } 1101 1102 static inline void aer_process_err_devices(struct aer_err_info *e_info) 1103 { 1104 int i; 1105 1106 /* Report all before handle them, not to lost records by reset etc. */ 1107 for (i = 0; i < e_info->error_dev_num && e_info->dev[i]; i++) { 1108 if (aer_get_device_error_info(e_info->dev[i], e_info)) 1109 aer_print_error(e_info->dev[i], e_info); 1110 } 1111 for (i = 0; i < e_info->error_dev_num && e_info->dev[i]; i++) { 1112 if (aer_get_device_error_info(e_info->dev[i], e_info)) 1113 handle_error_source(e_info->dev[i], e_info); 1114 } 1115 } 1116 1117 /** 1118 * aer_isr_one_error - consume an error detected by root port 1119 * @rpc: pointer to the root port which holds an error 1120 * @e_src: pointer to an error source 1121 */ 1122 static void aer_isr_one_error(struct aer_rpc *rpc, 1123 struct aer_err_source *e_src) 1124 { 1125 struct pci_dev *pdev = rpc->rpd; 1126 struct aer_err_info e_info; 1127 1128 pci_rootport_aer_stats_incr(pdev, e_src); 1129 1130 /* 1131 * There is a possibility that both correctable error and 1132 * uncorrectable error being logged. Report correctable error first. 1133 */ 1134 if (e_src->status & PCI_ERR_ROOT_COR_RCV) { 1135 e_info.id = ERR_COR_ID(e_src->id); 1136 e_info.severity = AER_CORRECTABLE; 1137 1138 if (e_src->status & PCI_ERR_ROOT_MULTI_COR_RCV) 1139 e_info.multi_error_valid = 1; 1140 else 1141 e_info.multi_error_valid = 0; 1142 aer_print_port_info(pdev, &e_info); 1143 1144 if (find_source_device(pdev, &e_info)) 1145 aer_process_err_devices(&e_info); 1146 } 1147 1148 if (e_src->status & PCI_ERR_ROOT_UNCOR_RCV) { 1149 e_info.id = ERR_UNCOR_ID(e_src->id); 1150 1151 if (e_src->status & PCI_ERR_ROOT_FATAL_RCV) 1152 e_info.severity = AER_FATAL; 1153 else 1154 e_info.severity = AER_NONFATAL; 1155 1156 if (e_src->status & PCI_ERR_ROOT_MULTI_UNCOR_RCV) 1157 e_info.multi_error_valid = 1; 1158 else 1159 e_info.multi_error_valid = 0; 1160 1161 aer_print_port_info(pdev, &e_info); 1162 1163 if (find_source_device(pdev, &e_info)) 1164 aer_process_err_devices(&e_info); 1165 } 1166 } 1167 1168 /** 1169 * aer_isr - consume errors detected by root port 1170 * @irq: IRQ assigned to Root Port 1171 * @context: pointer to Root Port data structure 1172 * 1173 * Invoked, as DPC, when root port records new detected error 1174 */ 1175 static irqreturn_t aer_isr(int irq, void *context) 1176 { 1177 struct pcie_device *dev = (struct pcie_device *)context; 1178 struct aer_rpc *rpc = get_service_data(dev); 1179 struct aer_err_source e_src; 1180 1181 if (kfifo_is_empty(&rpc->aer_fifo)) 1182 return IRQ_NONE; 1183 1184 while (kfifo_get(&rpc->aer_fifo, &e_src)) 1185 aer_isr_one_error(rpc, &e_src); 1186 return IRQ_HANDLED; 1187 } 1188 1189 /** 1190 * aer_irq - Root Port's ISR 1191 * @irq: IRQ assigned to Root Port 1192 * @context: pointer to Root Port data structure 1193 * 1194 * Invoked when Root Port detects AER messages. 1195 */ 1196 static irqreturn_t aer_irq(int irq, void *context) 1197 { 1198 struct pcie_device *pdev = (struct pcie_device *)context; 1199 struct aer_rpc *rpc = get_service_data(pdev); 1200 struct pci_dev *rp = rpc->rpd; 1201 int aer = rp->aer_cap; 1202 struct aer_err_source e_src = {}; 1203 1204 pci_read_config_dword(rp, aer + PCI_ERR_ROOT_STATUS, &e_src.status); 1205 if (!(e_src.status & AER_ERR_STATUS_MASK)) 1206 return IRQ_NONE; 1207 1208 pci_read_config_dword(rp, aer + PCI_ERR_ROOT_ERR_SRC, &e_src.id); 1209 pci_write_config_dword(rp, aer + PCI_ERR_ROOT_STATUS, e_src.status); 1210 1211 if (!kfifo_put(&rpc->aer_fifo, e_src)) 1212 return IRQ_HANDLED; 1213 1214 return IRQ_WAKE_THREAD; 1215 } 1216 1217 /** 1218 * aer_enable_rootport - enable Root Port's interrupts when receiving messages 1219 * @rpc: pointer to a Root Port data structure 1220 * 1221 * Invoked when PCIe bus loads AER service driver. 1222 */ 1223 static void aer_enable_rootport(struct aer_rpc *rpc) 1224 { 1225 struct pci_dev *pdev = rpc->rpd; 1226 int aer = pdev->aer_cap; 1227 u16 reg16; 1228 u32 reg32; 1229 1230 /* Clear PCIe Capability's Device Status */ 1231 pcie_capability_read_word(pdev, PCI_EXP_DEVSTA, ®16); 1232 pcie_capability_write_word(pdev, PCI_EXP_DEVSTA, reg16); 1233 1234 /* Disable system error generation in response to error messages */ 1235 pcie_capability_clear_word(pdev, PCI_EXP_RTCTL, 1236 SYSTEM_ERROR_INTR_ON_MESG_MASK); 1237 1238 /* Clear error status */ 1239 pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, ®32); 1240 pci_write_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, reg32); 1241 pci_read_config_dword(pdev, aer + PCI_ERR_COR_STATUS, ®32); 1242 pci_write_config_dword(pdev, aer + PCI_ERR_COR_STATUS, reg32); 1243 pci_read_config_dword(pdev, aer + PCI_ERR_UNCOR_STATUS, ®32); 1244 pci_write_config_dword(pdev, aer + PCI_ERR_UNCOR_STATUS, reg32); 1245 1246 /* Enable Root Port's interrupt in response to error messages */ 1247 pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, ®32); 1248 reg32 |= ROOT_PORT_INTR_ON_MESG_MASK; 1249 pci_write_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, reg32); 1250 } 1251 1252 /** 1253 * aer_disable_rootport - disable Root Port's interrupts when receiving messages 1254 * @rpc: pointer to a Root Port data structure 1255 * 1256 * Invoked when PCIe bus unloads AER service driver. 1257 */ 1258 static void aer_disable_rootport(struct aer_rpc *rpc) 1259 { 1260 struct pci_dev *pdev = rpc->rpd; 1261 int aer = pdev->aer_cap; 1262 u32 reg32; 1263 1264 /* Disable Root's interrupt in response to error messages */ 1265 pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, ®32); 1266 reg32 &= ~ROOT_PORT_INTR_ON_MESG_MASK; 1267 pci_write_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, reg32); 1268 1269 /* Clear Root's error status reg */ 1270 pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, ®32); 1271 pci_write_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, reg32); 1272 } 1273 1274 /** 1275 * aer_remove - clean up resources 1276 * @dev: pointer to the pcie_dev data structure 1277 * 1278 * Invoked when PCI Express bus unloads or AER probe fails. 1279 */ 1280 static void aer_remove(struct pcie_device *dev) 1281 { 1282 struct aer_rpc *rpc = get_service_data(dev); 1283 1284 aer_disable_rootport(rpc); 1285 } 1286 1287 /** 1288 * aer_probe - initialize resources 1289 * @dev: pointer to the pcie_dev data structure 1290 * 1291 * Invoked when PCI Express bus loads AER service driver. 1292 */ 1293 static int aer_probe(struct pcie_device *dev) 1294 { 1295 int status; 1296 struct aer_rpc *rpc; 1297 struct device *device = &dev->device; 1298 struct pci_dev *port = dev->port; 1299 1300 BUILD_BUG_ON(ARRAY_SIZE(aer_correctable_error_string) < 1301 AER_MAX_TYPEOF_COR_ERRS); 1302 BUILD_BUG_ON(ARRAY_SIZE(aer_uncorrectable_error_string) < 1303 AER_MAX_TYPEOF_UNCOR_ERRS); 1304 1305 /* Limit to Root Ports or Root Complex Event Collectors */ 1306 if ((pci_pcie_type(port) != PCI_EXP_TYPE_RC_EC) && 1307 (pci_pcie_type(port) != PCI_EXP_TYPE_ROOT_PORT)) 1308 return -ENODEV; 1309 1310 rpc = devm_kzalloc(device, sizeof(struct aer_rpc), GFP_KERNEL); 1311 if (!rpc) 1312 return -ENOMEM; 1313 1314 rpc->rpd = port; 1315 INIT_KFIFO(rpc->aer_fifo); 1316 set_service_data(dev, rpc); 1317 1318 status = devm_request_threaded_irq(device, dev->irq, aer_irq, aer_isr, 1319 IRQF_SHARED, "aerdrv", dev); 1320 if (status) { 1321 pci_err(port, "request AER IRQ %d failed\n", dev->irq); 1322 return status; 1323 } 1324 1325 aer_enable_rootport(rpc); 1326 pci_info(port, "enabled with IRQ %d\n", dev->irq); 1327 return 0; 1328 } 1329 1330 /** 1331 * aer_root_reset - reset Root Port hierarchy, RCEC, or RCiEP 1332 * @dev: pointer to Root Port, RCEC, or RCiEP 1333 * 1334 * Invoked by Port Bus driver when performing reset. 1335 */ 1336 static pci_ers_result_t aer_root_reset(struct pci_dev *dev) 1337 { 1338 int type = pci_pcie_type(dev); 1339 struct pci_dev *root; 1340 int aer; 1341 struct pci_host_bridge *host = pci_find_host_bridge(dev->bus); 1342 u32 reg32; 1343 int rc; 1344 1345 /* 1346 * Only Root Ports and RCECs have AER Root Command and Root Status 1347 * registers. If "dev" is an RCiEP, the relevant registers are in 1348 * the RCEC. 1349 */ 1350 if (type == PCI_EXP_TYPE_RC_END) 1351 root = dev->rcec; 1352 else 1353 root = pcie_find_root_port(dev); 1354 1355 /* 1356 * If the platform retained control of AER, an RCiEP may not have 1357 * an RCEC visible to us, so dev->rcec ("root") may be NULL. In 1358 * that case, firmware is responsible for these registers. 1359 */ 1360 aer = root ? root->aer_cap : 0; 1361 1362 if ((host->native_aer || pcie_ports_native) && aer) { 1363 /* Disable Root's interrupt in response to error messages */ 1364 pci_read_config_dword(root, aer + PCI_ERR_ROOT_COMMAND, ®32); 1365 reg32 &= ~ROOT_PORT_INTR_ON_MESG_MASK; 1366 pci_write_config_dword(root, aer + PCI_ERR_ROOT_COMMAND, reg32); 1367 } 1368 1369 if (type == PCI_EXP_TYPE_RC_EC || type == PCI_EXP_TYPE_RC_END) { 1370 rc = pcie_reset_flr(dev, PCI_RESET_DO_RESET); 1371 if (!rc) 1372 pci_info(dev, "has been reset\n"); 1373 else 1374 pci_info(dev, "not reset (no FLR support: %d)\n", rc); 1375 } else { 1376 rc = pci_bus_error_reset(dev); 1377 pci_info(dev, "%s Port link has been reset (%d)\n", 1378 pci_is_root_bus(dev->bus) ? "Root" : "Downstream", rc); 1379 } 1380 1381 if ((host->native_aer || pcie_ports_native) && aer) { 1382 /* Clear Root Error Status */ 1383 pci_read_config_dword(root, aer + PCI_ERR_ROOT_STATUS, ®32); 1384 pci_write_config_dword(root, aer + PCI_ERR_ROOT_STATUS, reg32); 1385 1386 /* Enable Root Port's interrupt in response to error messages */ 1387 pci_read_config_dword(root, aer + PCI_ERR_ROOT_COMMAND, ®32); 1388 reg32 |= ROOT_PORT_INTR_ON_MESG_MASK; 1389 pci_write_config_dword(root, aer + PCI_ERR_ROOT_COMMAND, reg32); 1390 } 1391 1392 return rc ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED; 1393 } 1394 1395 static struct pcie_port_service_driver aerdriver = { 1396 .name = "aer", 1397 .port_type = PCIE_ANY_PORT, 1398 .service = PCIE_PORT_SERVICE_AER, 1399 1400 .probe = aer_probe, 1401 .remove = aer_remove, 1402 }; 1403 1404 /** 1405 * pcie_aer_init - register AER root service driver 1406 * 1407 * Invoked when AER root service driver is loaded. 1408 */ 1409 int __init pcie_aer_init(void) 1410 { 1411 if (!pci_aer_available()) 1412 return -ENXIO; 1413 return pcie_port_service_register(&aerdriver); 1414 } 1415