1 #ifndef DRIVERS_PCI_H 2 #define DRIVERS_PCI_H 3 4 #define PCI_CFG_SPACE_SIZE 256 5 #define PCI_CFG_SPACE_EXP_SIZE 4096 6 7 extern const unsigned char pcie_link_speed[]; 8 9 bool pcie_cap_has_lnkctl(const struct pci_dev *dev); 10 11 /* Functions internal to the PCI core code */ 12 13 int pci_create_sysfs_dev_files(struct pci_dev *pdev); 14 void pci_remove_sysfs_dev_files(struct pci_dev *pdev); 15 #if !defined(CONFIG_DMI) && !defined(CONFIG_ACPI) 16 static inline void pci_create_firmware_label_files(struct pci_dev *pdev) 17 { return; } 18 static inline void pci_remove_firmware_label_files(struct pci_dev *pdev) 19 { return; } 20 #else 21 void pci_create_firmware_label_files(struct pci_dev *pdev); 22 void pci_remove_firmware_label_files(struct pci_dev *pdev); 23 #endif 24 void pci_cleanup_rom(struct pci_dev *dev); 25 #ifdef HAVE_PCI_MMAP 26 enum pci_mmap_api { 27 PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */ 28 PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */ 29 }; 30 int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai, 31 enum pci_mmap_api mmap_api); 32 #endif 33 int pci_probe_reset_function(struct pci_dev *dev); 34 35 /** 36 * struct pci_platform_pm_ops - Firmware PM callbacks 37 * 38 * @is_manageable: returns 'true' if given device is power manageable by the 39 * platform firmware 40 * 41 * @set_state: invokes the platform firmware to set the device's power state 42 * 43 * @choose_state: returns PCI power state of given device preferred by the 44 * platform; to be used during system-wide transitions from a 45 * sleeping state to the working state and vice versa 46 * 47 * @sleep_wake: enables/disables the system wake up capability of given device 48 * 49 * @run_wake: enables/disables the platform to generate run-time wake-up events 50 * for given device (the device's wake-up capability has to be 51 * enabled by @sleep_wake for this feature to work) 52 * 53 * @need_resume: returns 'true' if the given device (which is currently 54 * suspended) needs to be resumed to be configured for system 55 * wakeup. 56 * 57 * If given platform is generally capable of power managing PCI devices, all of 58 * these callbacks are mandatory. 59 */ 60 struct pci_platform_pm_ops { 61 bool (*is_manageable)(struct pci_dev *dev); 62 int (*set_state)(struct pci_dev *dev, pci_power_t state); 63 pci_power_t (*choose_state)(struct pci_dev *dev); 64 int (*sleep_wake)(struct pci_dev *dev, bool enable); 65 int (*run_wake)(struct pci_dev *dev, bool enable); 66 bool (*need_resume)(struct pci_dev *dev); 67 }; 68 69 int pci_set_platform_pm(struct pci_platform_pm_ops *ops); 70 void pci_update_current_state(struct pci_dev *dev, pci_power_t state); 71 void pci_power_up(struct pci_dev *dev); 72 void pci_disable_enabled_device(struct pci_dev *dev); 73 int pci_finish_runtime_suspend(struct pci_dev *dev); 74 int __pci_pme_wakeup(struct pci_dev *dev, void *ign); 75 bool pci_dev_keep_suspended(struct pci_dev *dev); 76 void pci_config_pm_runtime_get(struct pci_dev *dev); 77 void pci_config_pm_runtime_put(struct pci_dev *dev); 78 void pci_pm_init(struct pci_dev *dev); 79 void pci_allocate_cap_save_buffers(struct pci_dev *dev); 80 void pci_free_cap_save_buffers(struct pci_dev *dev); 81 82 static inline void pci_wakeup_event(struct pci_dev *dev) 83 { 84 /* Wait 100 ms before the system can be put into a sleep state. */ 85 pm_wakeup_event(&dev->dev, 100); 86 } 87 88 static inline bool pci_has_subordinate(struct pci_dev *pci_dev) 89 { 90 return !!(pci_dev->subordinate); 91 } 92 93 struct pci_vpd_ops { 94 ssize_t (*read)(struct pci_dev *dev, loff_t pos, size_t count, void *buf); 95 ssize_t (*write)(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); 96 void (*release)(struct pci_dev *dev); 97 }; 98 99 struct pci_vpd { 100 unsigned int len; 101 const struct pci_vpd_ops *ops; 102 struct bin_attribute *attr; /* descriptor for sysfs VPD entry */ 103 }; 104 105 int pci_vpd_pci22_init(struct pci_dev *dev); 106 static inline void pci_vpd_release(struct pci_dev *dev) 107 { 108 if (dev->vpd) 109 dev->vpd->ops->release(dev); 110 } 111 112 /* PCI /proc functions */ 113 #ifdef CONFIG_PROC_FS 114 int pci_proc_attach_device(struct pci_dev *dev); 115 int pci_proc_detach_device(struct pci_dev *dev); 116 int pci_proc_detach_bus(struct pci_bus *bus); 117 #else 118 static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; } 119 static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; } 120 static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; } 121 #endif 122 123 /* Functions for PCI Hotplug drivers to use */ 124 int pci_hp_add_bridge(struct pci_dev *dev); 125 126 #ifdef HAVE_PCI_LEGACY 127 void pci_create_legacy_files(struct pci_bus *bus); 128 void pci_remove_legacy_files(struct pci_bus *bus); 129 #else 130 static inline void pci_create_legacy_files(struct pci_bus *bus) { return; } 131 static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; } 132 #endif 133 134 /* Lock for read/write access to pci device and bus lists */ 135 extern struct rw_semaphore pci_bus_sem; 136 137 extern raw_spinlock_t pci_lock; 138 139 extern unsigned int pci_pm_d3_delay; 140 141 #ifdef CONFIG_PCI_MSI 142 void pci_no_msi(void); 143 void pci_msi_init_pci_dev(struct pci_dev *dev); 144 #else 145 static inline void pci_no_msi(void) { } 146 static inline void pci_msi_init_pci_dev(struct pci_dev *dev) { } 147 #endif 148 149 static inline void pci_msi_set_enable(struct pci_dev *dev, int enable) 150 { 151 u16 control; 152 153 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); 154 control &= ~PCI_MSI_FLAGS_ENABLE; 155 if (enable) 156 control |= PCI_MSI_FLAGS_ENABLE; 157 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); 158 } 159 160 static inline void pci_msix_clear_and_set_ctrl(struct pci_dev *dev, u16 clear, u16 set) 161 { 162 u16 ctrl; 163 164 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl); 165 ctrl &= ~clear; 166 ctrl |= set; 167 pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, ctrl); 168 } 169 170 void pci_realloc_get_opt(char *); 171 172 static inline int pci_no_d1d2(struct pci_dev *dev) 173 { 174 unsigned int parent_dstates = 0; 175 176 if (dev->bus->self) 177 parent_dstates = dev->bus->self->no_d1d2; 178 return (dev->no_d1d2 || parent_dstates); 179 180 } 181 extern const struct attribute_group *pci_dev_groups[]; 182 extern const struct attribute_group *pcibus_groups[]; 183 extern struct device_type pci_dev_type; 184 extern const struct attribute_group *pci_bus_groups[]; 185 186 187 /** 188 * pci_match_one_device - Tell if a PCI device structure has a matching 189 * PCI device id structure 190 * @id: single PCI device id structure to match 191 * @dev: the PCI device structure to match against 192 * 193 * Returns the matching pci_device_id structure or %NULL if there is no match. 194 */ 195 static inline const struct pci_device_id * 196 pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev) 197 { 198 if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) && 199 (id->device == PCI_ANY_ID || id->device == dev->device) && 200 (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) && 201 (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) && 202 !((id->class ^ dev->class) & id->class_mask)) 203 return id; 204 return NULL; 205 } 206 207 /* PCI slot sysfs helper code */ 208 #define to_pci_slot(s) container_of(s, struct pci_slot, kobj) 209 210 extern struct kset *pci_slots_kset; 211 212 struct pci_slot_attribute { 213 struct attribute attr; 214 ssize_t (*show)(struct pci_slot *, char *); 215 ssize_t (*store)(struct pci_slot *, const char *, size_t); 216 }; 217 #define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr) 218 219 enum pci_bar_type { 220 pci_bar_unknown, /* Standard PCI BAR probe */ 221 pci_bar_io, /* An io port BAR */ 222 pci_bar_mem32, /* A 32-bit memory BAR */ 223 pci_bar_mem64, /* A 64-bit memory BAR */ 224 }; 225 226 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, 227 int crs_timeout); 228 int pci_setup_device(struct pci_dev *dev); 229 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, 230 struct resource *res, unsigned int reg); 231 int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type); 232 void pci_configure_ari(struct pci_dev *dev); 233 void __pci_bus_size_bridges(struct pci_bus *bus, 234 struct list_head *realloc_head); 235 void __pci_bus_assign_resources(const struct pci_bus *bus, 236 struct list_head *realloc_head, 237 struct list_head *fail_head); 238 bool pci_bus_clip_resource(struct pci_dev *dev, int idx); 239 240 void pci_reassigndev_resource_alignment(struct pci_dev *dev); 241 void pci_disable_bridge_window(struct pci_dev *dev); 242 243 /* Single Root I/O Virtualization */ 244 struct pci_sriov { 245 int pos; /* capability position */ 246 int nres; /* number of resources */ 247 u32 cap; /* SR-IOV Capabilities */ 248 u16 ctrl; /* SR-IOV Control */ 249 u16 total_VFs; /* total VFs associated with the PF */ 250 u16 initial_VFs; /* initial VFs associated with the PF */ 251 u16 num_VFs; /* number of VFs available */ 252 u16 offset; /* first VF Routing ID offset */ 253 u16 stride; /* following VF stride */ 254 u32 pgsz; /* page size for BAR alignment */ 255 u8 link; /* Function Dependency Link */ 256 u8 max_VF_buses; /* max buses consumed by VFs */ 257 u16 driver_max_VFs; /* max num VFs driver supports */ 258 struct pci_dev *dev; /* lowest numbered PF */ 259 struct pci_dev *self; /* this PF */ 260 struct mutex lock; /* lock for VF bus */ 261 resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */ 262 }; 263 264 #ifdef CONFIG_PCI_ATS 265 void pci_restore_ats_state(struct pci_dev *dev); 266 #else 267 static inline void pci_restore_ats_state(struct pci_dev *dev) 268 { 269 } 270 #endif /* CONFIG_PCI_ATS */ 271 272 #ifdef CONFIG_PCI_IOV 273 int pci_iov_init(struct pci_dev *dev); 274 void pci_iov_release(struct pci_dev *dev); 275 int pci_iov_resource_bar(struct pci_dev *dev, int resno); 276 resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno); 277 void pci_restore_iov_state(struct pci_dev *dev); 278 int pci_iov_bus_range(struct pci_bus *bus); 279 280 #else 281 static inline int pci_iov_init(struct pci_dev *dev) 282 { 283 return -ENODEV; 284 } 285 static inline void pci_iov_release(struct pci_dev *dev) 286 287 { 288 } 289 static inline int pci_iov_resource_bar(struct pci_dev *dev, int resno) 290 { 291 return 0; 292 } 293 static inline void pci_restore_iov_state(struct pci_dev *dev) 294 { 295 } 296 static inline int pci_iov_bus_range(struct pci_bus *bus) 297 { 298 return 0; 299 } 300 301 #endif /* CONFIG_PCI_IOV */ 302 303 unsigned long pci_cardbus_resource_alignment(struct resource *); 304 305 static inline resource_size_t pci_resource_alignment(struct pci_dev *dev, 306 struct resource *res) 307 { 308 #ifdef CONFIG_PCI_IOV 309 int resno = res - dev->resource; 310 311 if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END) 312 return pci_sriov_resource_alignment(dev, resno); 313 #endif 314 if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS) 315 return pci_cardbus_resource_alignment(res); 316 return resource_alignment(res); 317 } 318 319 void pci_enable_acs(struct pci_dev *dev); 320 321 struct pci_dev_reset_methods { 322 u16 vendor; 323 u16 device; 324 int (*reset)(struct pci_dev *dev, int probe); 325 }; 326 327 #ifdef CONFIG_PCI_QUIRKS 328 int pci_dev_specific_reset(struct pci_dev *dev, int probe); 329 #else 330 static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe) 331 { 332 return -ENOTTY; 333 } 334 #endif 335 336 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus); 337 338 #endif /* DRIVERS_PCI_H */ 339