1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef DRIVERS_PCI_H 3 #define DRIVERS_PCI_H 4 5 #include <linux/pci.h> 6 7 /* Number of possible devfns: 0.0 to 1f.7 inclusive */ 8 #define MAX_NR_DEVFNS 256 9 10 #define PCI_FIND_CAP_TTL 48 11 12 #define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */ 13 14 extern const unsigned char pcie_link_speed[]; 15 extern bool pci_early_dump; 16 17 bool pcie_cap_has_lnkctl(const struct pci_dev *dev); 18 bool pcie_cap_has_rtctl(const struct pci_dev *dev); 19 20 /* Functions internal to the PCI core code */ 21 22 int pci_create_sysfs_dev_files(struct pci_dev *pdev); 23 void pci_remove_sysfs_dev_files(struct pci_dev *pdev); 24 void pci_cleanup_rom(struct pci_dev *dev); 25 #ifdef CONFIG_DMI 26 extern const struct attribute_group pci_dev_smbios_attr_group; 27 #endif 28 29 enum pci_mmap_api { 30 PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */ 31 PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */ 32 }; 33 int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai, 34 enum pci_mmap_api mmap_api); 35 36 int pci_probe_reset_function(struct pci_dev *dev); 37 int pci_bridge_secondary_bus_reset(struct pci_dev *dev); 38 int pci_bus_error_reset(struct pci_dev *dev); 39 40 #define PCI_PM_D2_DELAY 200 /* usec; see PCIe r4.0, sec 5.9.1 */ 41 #define PCI_PM_D3HOT_WAIT 10 /* msec */ 42 #define PCI_PM_D3COLD_WAIT 100 /* msec */ 43 44 /** 45 * struct pci_platform_pm_ops - Firmware PM callbacks 46 * 47 * @bridge_d3: Does the bridge allow entering into D3 48 * 49 * @is_manageable: returns 'true' if given device is power manageable by the 50 * platform firmware 51 * 52 * @set_state: invokes the platform firmware to set the device's power state 53 * 54 * @get_state: queries the platform firmware for a device's current power state 55 * 56 * @refresh_state: asks the platform to refresh the device's power state data 57 * 58 * @choose_state: returns PCI power state of given device preferred by the 59 * platform; to be used during system-wide transitions from a 60 * sleeping state to the working state and vice versa 61 * 62 * @set_wakeup: enables/disables wakeup capability for the device 63 * 64 * @need_resume: returns 'true' if the given device (which is currently 65 * suspended) needs to be resumed to be configured for system 66 * wakeup. 67 * 68 * If given platform is generally capable of power managing PCI devices, all of 69 * these callbacks are mandatory. 70 */ 71 struct pci_platform_pm_ops { 72 bool (*bridge_d3)(struct pci_dev *dev); 73 bool (*is_manageable)(struct pci_dev *dev); 74 int (*set_state)(struct pci_dev *dev, pci_power_t state); 75 pci_power_t (*get_state)(struct pci_dev *dev); 76 void (*refresh_state)(struct pci_dev *dev); 77 pci_power_t (*choose_state)(struct pci_dev *dev); 78 int (*set_wakeup)(struct pci_dev *dev, bool enable); 79 bool (*need_resume)(struct pci_dev *dev); 80 }; 81 82 int pci_set_platform_pm(const struct pci_platform_pm_ops *ops); 83 void pci_update_current_state(struct pci_dev *dev, pci_power_t state); 84 void pci_refresh_power_state(struct pci_dev *dev); 85 int pci_power_up(struct pci_dev *dev); 86 void pci_disable_enabled_device(struct pci_dev *dev); 87 int pci_finish_runtime_suspend(struct pci_dev *dev); 88 void pcie_clear_device_status(struct pci_dev *dev); 89 void pcie_clear_root_pme_status(struct pci_dev *dev); 90 bool pci_check_pme_status(struct pci_dev *dev); 91 void pci_pme_wakeup_bus(struct pci_bus *bus); 92 int __pci_pme_wakeup(struct pci_dev *dev, void *ign); 93 void pci_pme_restore(struct pci_dev *dev); 94 bool pci_dev_need_resume(struct pci_dev *dev); 95 void pci_dev_adjust_pme(struct pci_dev *dev); 96 void pci_dev_complete_resume(struct pci_dev *pci_dev); 97 void pci_config_pm_runtime_get(struct pci_dev *dev); 98 void pci_config_pm_runtime_put(struct pci_dev *dev); 99 void pci_pm_init(struct pci_dev *dev); 100 void pci_ea_init(struct pci_dev *dev); 101 void pci_msi_init(struct pci_dev *dev); 102 void pci_msix_init(struct pci_dev *dev); 103 void pci_allocate_cap_save_buffers(struct pci_dev *dev); 104 void pci_free_cap_save_buffers(struct pci_dev *dev); 105 bool pci_bridge_d3_possible(struct pci_dev *dev); 106 void pci_bridge_d3_update(struct pci_dev *dev); 107 void pci_bridge_wait_for_secondary_bus(struct pci_dev *dev); 108 109 static inline void pci_wakeup_event(struct pci_dev *dev) 110 { 111 /* Wait 100 ms before the system can be put into a sleep state. */ 112 pm_wakeup_event(&dev->dev, 100); 113 } 114 115 static inline bool pci_has_subordinate(struct pci_dev *pci_dev) 116 { 117 return !!(pci_dev->subordinate); 118 } 119 120 static inline bool pci_power_manageable(struct pci_dev *pci_dev) 121 { 122 /* 123 * Currently we allow normal PCI devices and PCI bridges transition 124 * into D3 if their bridge_d3 is set. 125 */ 126 return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3; 127 } 128 129 static inline bool pcie_downstream_port(const struct pci_dev *dev) 130 { 131 int type = pci_pcie_type(dev); 132 133 return type == PCI_EXP_TYPE_ROOT_PORT || 134 type == PCI_EXP_TYPE_DOWNSTREAM || 135 type == PCI_EXP_TYPE_PCIE_BRIDGE; 136 } 137 138 void pci_vpd_init(struct pci_dev *dev); 139 void pci_vpd_release(struct pci_dev *dev); 140 extern const struct attribute_group pci_dev_vpd_attr_group; 141 142 /* PCI Virtual Channel */ 143 int pci_save_vc_state(struct pci_dev *dev); 144 void pci_restore_vc_state(struct pci_dev *dev); 145 void pci_allocate_vc_save_buffers(struct pci_dev *dev); 146 147 /* PCI /proc functions */ 148 #ifdef CONFIG_PROC_FS 149 int pci_proc_attach_device(struct pci_dev *dev); 150 int pci_proc_detach_device(struct pci_dev *dev); 151 int pci_proc_detach_bus(struct pci_bus *bus); 152 #else 153 static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; } 154 static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; } 155 static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; } 156 #endif 157 158 /* Functions for PCI Hotplug drivers to use */ 159 int pci_hp_add_bridge(struct pci_dev *dev); 160 161 #ifdef HAVE_PCI_LEGACY 162 void pci_create_legacy_files(struct pci_bus *bus); 163 void pci_remove_legacy_files(struct pci_bus *bus); 164 #else 165 static inline void pci_create_legacy_files(struct pci_bus *bus) { return; } 166 static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; } 167 #endif 168 169 /* Lock for read/write access to pci device and bus lists */ 170 extern struct rw_semaphore pci_bus_sem; 171 extern struct mutex pci_slot_mutex; 172 173 extern raw_spinlock_t pci_lock; 174 175 extern unsigned int pci_pm_d3hot_delay; 176 177 #ifdef CONFIG_PCI_MSI 178 void pci_no_msi(void); 179 #else 180 static inline void pci_no_msi(void) { } 181 #endif 182 183 void pci_realloc_get_opt(char *); 184 185 static inline int pci_no_d1d2(struct pci_dev *dev) 186 { 187 unsigned int parent_dstates = 0; 188 189 if (dev->bus->self) 190 parent_dstates = dev->bus->self->no_d1d2; 191 return (dev->no_d1d2 || parent_dstates); 192 193 } 194 extern const struct attribute_group *pci_dev_groups[]; 195 extern const struct attribute_group *pcibus_groups[]; 196 extern const struct device_type pci_dev_type; 197 extern const struct attribute_group *pci_bus_groups[]; 198 199 extern unsigned long pci_hotplug_io_size; 200 extern unsigned long pci_hotplug_mmio_size; 201 extern unsigned long pci_hotplug_mmio_pref_size; 202 extern unsigned long pci_hotplug_bus_size; 203 204 /** 205 * pci_match_one_device - Tell if a PCI device structure has a matching 206 * PCI device id structure 207 * @id: single PCI device id structure to match 208 * @dev: the PCI device structure to match against 209 * 210 * Returns the matching pci_device_id structure or %NULL if there is no match. 211 */ 212 static inline const struct pci_device_id * 213 pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev) 214 { 215 if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) && 216 (id->device == PCI_ANY_ID || id->device == dev->device) && 217 (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) && 218 (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) && 219 !((id->class ^ dev->class) & id->class_mask)) 220 return id; 221 return NULL; 222 } 223 224 /* PCI slot sysfs helper code */ 225 #define to_pci_slot(s) container_of(s, struct pci_slot, kobj) 226 227 extern struct kset *pci_slots_kset; 228 229 struct pci_slot_attribute { 230 struct attribute attr; 231 ssize_t (*show)(struct pci_slot *, char *); 232 ssize_t (*store)(struct pci_slot *, const char *, size_t); 233 }; 234 #define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr) 235 236 enum pci_bar_type { 237 pci_bar_unknown, /* Standard PCI BAR probe */ 238 pci_bar_io, /* An I/O port BAR */ 239 pci_bar_mem32, /* A 32-bit memory BAR */ 240 pci_bar_mem64, /* A 64-bit memory BAR */ 241 }; 242 243 struct device *pci_get_host_bridge_device(struct pci_dev *dev); 244 void pci_put_host_bridge_device(struct device *dev); 245 246 int pci_configure_extended_tags(struct pci_dev *dev, void *ign); 247 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, 248 int crs_timeout); 249 bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, 250 int crs_timeout); 251 int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int crs_timeout); 252 253 int pci_setup_device(struct pci_dev *dev); 254 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, 255 struct resource *res, unsigned int reg); 256 void pci_configure_ari(struct pci_dev *dev); 257 void __pci_bus_size_bridges(struct pci_bus *bus, 258 struct list_head *realloc_head); 259 void __pci_bus_assign_resources(const struct pci_bus *bus, 260 struct list_head *realloc_head, 261 struct list_head *fail_head); 262 bool pci_bus_clip_resource(struct pci_dev *dev, int idx); 263 264 void pci_reassigndev_resource_alignment(struct pci_dev *dev); 265 void pci_disable_bridge_window(struct pci_dev *dev); 266 struct pci_bus *pci_bus_get(struct pci_bus *bus); 267 void pci_bus_put(struct pci_bus *bus); 268 269 /* PCIe link information from Link Capabilities 2 */ 270 #define PCIE_LNKCAP2_SLS2SPEED(lnkcap2) \ 271 ((lnkcap2) & PCI_EXP_LNKCAP2_SLS_64_0GB ? PCIE_SPEED_64_0GT : \ 272 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_32_0GB ? PCIE_SPEED_32_0GT : \ 273 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_16_0GB ? PCIE_SPEED_16_0GT : \ 274 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_8_0GB ? PCIE_SPEED_8_0GT : \ 275 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_5_0GB ? PCIE_SPEED_5_0GT : \ 276 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_2_5GB ? PCIE_SPEED_2_5GT : \ 277 PCI_SPEED_UNKNOWN) 278 279 /* PCIe speed to Mb/s reduced by encoding overhead */ 280 #define PCIE_SPEED2MBS_ENC(speed) \ 281 ((speed) == PCIE_SPEED_64_0GT ? 64000*128/130 : \ 282 (speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \ 283 (speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \ 284 (speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \ 285 (speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \ 286 (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \ 287 0) 288 289 const char *pci_speed_string(enum pci_bus_speed speed); 290 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev); 291 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev); 292 u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed, 293 enum pcie_link_width *width); 294 void __pcie_print_link_status(struct pci_dev *dev, bool verbose); 295 void pcie_report_downtraining(struct pci_dev *dev); 296 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status); 297 298 /* Single Root I/O Virtualization */ 299 struct pci_sriov { 300 int pos; /* Capability position */ 301 int nres; /* Number of resources */ 302 u32 cap; /* SR-IOV Capabilities */ 303 u16 ctrl; /* SR-IOV Control */ 304 u16 total_VFs; /* Total VFs associated with the PF */ 305 u16 initial_VFs; /* Initial VFs associated with the PF */ 306 u16 num_VFs; /* Number of VFs available */ 307 u16 offset; /* First VF Routing ID offset */ 308 u16 stride; /* Following VF stride */ 309 u16 vf_device; /* VF device ID */ 310 u32 pgsz; /* Page size for BAR alignment */ 311 u8 link; /* Function Dependency Link */ 312 u8 max_VF_buses; /* Max buses consumed by VFs */ 313 u16 driver_max_VFs; /* Max num VFs driver supports */ 314 struct pci_dev *dev; /* Lowest numbered PF */ 315 struct pci_dev *self; /* This PF */ 316 u32 class; /* VF device */ 317 u8 hdr_type; /* VF header type */ 318 u16 subsystem_vendor; /* VF subsystem vendor */ 319 u16 subsystem_device; /* VF subsystem device */ 320 resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */ 321 bool drivers_autoprobe; /* Auto probing of VFs by driver */ 322 }; 323 324 /** 325 * pci_dev_set_io_state - Set the new error state if possible. 326 * 327 * @dev - pci device to set new error_state 328 * @new - the state we want dev to be in 329 * 330 * Must be called with device_lock held. 331 * 332 * Returns true if state has been changed to the requested state. 333 */ 334 static inline bool pci_dev_set_io_state(struct pci_dev *dev, 335 pci_channel_state_t new) 336 { 337 bool changed = false; 338 339 device_lock_assert(&dev->dev); 340 switch (new) { 341 case pci_channel_io_perm_failure: 342 switch (dev->error_state) { 343 case pci_channel_io_frozen: 344 case pci_channel_io_normal: 345 case pci_channel_io_perm_failure: 346 changed = true; 347 break; 348 } 349 break; 350 case pci_channel_io_frozen: 351 switch (dev->error_state) { 352 case pci_channel_io_frozen: 353 case pci_channel_io_normal: 354 changed = true; 355 break; 356 } 357 break; 358 case pci_channel_io_normal: 359 switch (dev->error_state) { 360 case pci_channel_io_frozen: 361 case pci_channel_io_normal: 362 changed = true; 363 break; 364 } 365 break; 366 } 367 if (changed) 368 dev->error_state = new; 369 return changed; 370 } 371 372 static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused) 373 { 374 device_lock(&dev->dev); 375 pci_dev_set_io_state(dev, pci_channel_io_perm_failure); 376 device_unlock(&dev->dev); 377 378 return 0; 379 } 380 381 static inline bool pci_dev_is_disconnected(const struct pci_dev *dev) 382 { 383 return dev->error_state == pci_channel_io_perm_failure; 384 } 385 386 /* pci_dev priv_flags */ 387 #define PCI_DEV_ADDED 0 388 389 static inline void pci_dev_assign_added(struct pci_dev *dev, bool added) 390 { 391 assign_bit(PCI_DEV_ADDED, &dev->priv_flags, added); 392 } 393 394 static inline bool pci_dev_is_added(const struct pci_dev *dev) 395 { 396 return test_bit(PCI_DEV_ADDED, &dev->priv_flags); 397 } 398 399 #ifdef CONFIG_PCIEAER 400 #include <linux/aer.h> 401 402 #define AER_MAX_MULTI_ERR_DEVICES 5 /* Not likely to have more */ 403 404 struct aer_err_info { 405 struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES]; 406 int error_dev_num; 407 408 unsigned int id:16; 409 410 unsigned int severity:2; /* 0:NONFATAL | 1:FATAL | 2:COR */ 411 unsigned int __pad1:5; 412 unsigned int multi_error_valid:1; 413 414 unsigned int first_error:5; 415 unsigned int __pad2:2; 416 unsigned int tlp_header_valid:1; 417 418 unsigned int status; /* COR/UNCOR Error Status */ 419 unsigned int mask; /* COR/UNCOR Error Mask */ 420 struct aer_header_log_regs tlp; /* TLP Header */ 421 }; 422 423 int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info); 424 void aer_print_error(struct pci_dev *dev, struct aer_err_info *info); 425 #endif /* CONFIG_PCIEAER */ 426 427 #ifdef CONFIG_PCIEPORTBUS 428 /* Cached RCEC Endpoint Association */ 429 struct rcec_ea { 430 u8 nextbusn; 431 u8 lastbusn; 432 u32 bitmap; 433 }; 434 #endif 435 436 #ifdef CONFIG_PCIE_DPC 437 void pci_save_dpc_state(struct pci_dev *dev); 438 void pci_restore_dpc_state(struct pci_dev *dev); 439 void pci_dpc_init(struct pci_dev *pdev); 440 void dpc_process_error(struct pci_dev *pdev); 441 pci_ers_result_t dpc_reset_link(struct pci_dev *pdev); 442 #else 443 static inline void pci_save_dpc_state(struct pci_dev *dev) {} 444 static inline void pci_restore_dpc_state(struct pci_dev *dev) {} 445 static inline void pci_dpc_init(struct pci_dev *pdev) {} 446 #endif 447 448 #ifdef CONFIG_PCIEPORTBUS 449 void pci_rcec_init(struct pci_dev *dev); 450 void pci_rcec_exit(struct pci_dev *dev); 451 void pcie_link_rcec(struct pci_dev *rcec); 452 void pcie_walk_rcec(struct pci_dev *rcec, 453 int (*cb)(struct pci_dev *, void *), 454 void *userdata); 455 #else 456 static inline void pci_rcec_init(struct pci_dev *dev) {} 457 static inline void pci_rcec_exit(struct pci_dev *dev) {} 458 static inline void pcie_link_rcec(struct pci_dev *rcec) {} 459 static inline void pcie_walk_rcec(struct pci_dev *rcec, 460 int (*cb)(struct pci_dev *, void *), 461 void *userdata) {} 462 #endif 463 464 #ifdef CONFIG_PCI_ATS 465 /* Address Translation Service */ 466 void pci_ats_init(struct pci_dev *dev); 467 void pci_restore_ats_state(struct pci_dev *dev); 468 #else 469 static inline void pci_ats_init(struct pci_dev *d) { } 470 static inline void pci_restore_ats_state(struct pci_dev *dev) { } 471 #endif /* CONFIG_PCI_ATS */ 472 473 #ifdef CONFIG_PCI_PRI 474 void pci_pri_init(struct pci_dev *dev); 475 void pci_restore_pri_state(struct pci_dev *pdev); 476 #else 477 static inline void pci_pri_init(struct pci_dev *dev) { } 478 static inline void pci_restore_pri_state(struct pci_dev *pdev) { } 479 #endif 480 481 #ifdef CONFIG_PCI_PASID 482 void pci_pasid_init(struct pci_dev *dev); 483 void pci_restore_pasid_state(struct pci_dev *pdev); 484 #else 485 static inline void pci_pasid_init(struct pci_dev *dev) { } 486 static inline void pci_restore_pasid_state(struct pci_dev *pdev) { } 487 #endif 488 489 #ifdef CONFIG_PCI_IOV 490 int pci_iov_init(struct pci_dev *dev); 491 void pci_iov_release(struct pci_dev *dev); 492 void pci_iov_remove(struct pci_dev *dev); 493 void pci_iov_update_resource(struct pci_dev *dev, int resno); 494 resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno); 495 void pci_restore_iov_state(struct pci_dev *dev); 496 int pci_iov_bus_range(struct pci_bus *bus); 497 extern const struct attribute_group sriov_pf_dev_attr_group; 498 extern const struct attribute_group sriov_vf_dev_attr_group; 499 #else 500 static inline int pci_iov_init(struct pci_dev *dev) 501 { 502 return -ENODEV; 503 } 504 static inline void pci_iov_release(struct pci_dev *dev) 505 506 { 507 } 508 static inline void pci_iov_remove(struct pci_dev *dev) 509 { 510 } 511 static inline void pci_restore_iov_state(struct pci_dev *dev) 512 { 513 } 514 static inline int pci_iov_bus_range(struct pci_bus *bus) 515 { 516 return 0; 517 } 518 519 #endif /* CONFIG_PCI_IOV */ 520 521 #ifdef CONFIG_PCIE_PTM 522 void pci_save_ptm_state(struct pci_dev *dev); 523 void pci_restore_ptm_state(struct pci_dev *dev); 524 void pci_disable_ptm(struct pci_dev *dev); 525 #else 526 static inline void pci_save_ptm_state(struct pci_dev *dev) { } 527 static inline void pci_restore_ptm_state(struct pci_dev *dev) { } 528 static inline void pci_disable_ptm(struct pci_dev *dev) { } 529 #endif 530 531 unsigned long pci_cardbus_resource_alignment(struct resource *); 532 533 static inline resource_size_t pci_resource_alignment(struct pci_dev *dev, 534 struct resource *res) 535 { 536 #ifdef CONFIG_PCI_IOV 537 int resno = res - dev->resource; 538 539 if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END) 540 return pci_sriov_resource_alignment(dev, resno); 541 #endif 542 if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS) 543 return pci_cardbus_resource_alignment(res); 544 return resource_alignment(res); 545 } 546 547 void pci_acs_init(struct pci_dev *dev); 548 #ifdef CONFIG_PCI_QUIRKS 549 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags); 550 int pci_dev_specific_enable_acs(struct pci_dev *dev); 551 int pci_dev_specific_disable_acs_redir(struct pci_dev *dev); 552 #else 553 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev, 554 u16 acs_flags) 555 { 556 return -ENOTTY; 557 } 558 static inline int pci_dev_specific_enable_acs(struct pci_dev *dev) 559 { 560 return -ENOTTY; 561 } 562 static inline int pci_dev_specific_disable_acs_redir(struct pci_dev *dev) 563 { 564 return -ENOTTY; 565 } 566 #endif 567 568 /* PCI error reporting and recovery */ 569 pci_ers_result_t pcie_do_recovery(struct pci_dev *dev, 570 pci_channel_state_t state, 571 pci_ers_result_t (*reset_subordinates)(struct pci_dev *pdev)); 572 573 bool pcie_wait_for_link(struct pci_dev *pdev, bool active); 574 #ifdef CONFIG_PCIEASPM 575 void pcie_aspm_init_link_state(struct pci_dev *pdev); 576 void pcie_aspm_exit_link_state(struct pci_dev *pdev); 577 void pcie_aspm_pm_state_change(struct pci_dev *pdev); 578 void pcie_aspm_powersave_config_link(struct pci_dev *pdev); 579 #else 580 static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { } 581 static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { } 582 static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev) { } 583 static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { } 584 #endif 585 586 #ifdef CONFIG_PCIE_ECRC 587 void pcie_set_ecrc_checking(struct pci_dev *dev); 588 void pcie_ecrc_get_policy(char *str); 589 #else 590 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { } 591 static inline void pcie_ecrc_get_policy(char *str) { } 592 #endif 593 594 #ifdef CONFIG_PCIE_PTM 595 void pci_ptm_init(struct pci_dev *dev); 596 int pci_enable_ptm(struct pci_dev *dev, u8 *granularity); 597 #else 598 static inline void pci_ptm_init(struct pci_dev *dev) { } 599 static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity) 600 { return -EINVAL; } 601 #endif 602 603 struct pci_dev_reset_methods { 604 u16 vendor; 605 u16 device; 606 int (*reset)(struct pci_dev *dev, int probe); 607 }; 608 609 #ifdef CONFIG_PCI_QUIRKS 610 int pci_dev_specific_reset(struct pci_dev *dev, int probe); 611 #else 612 static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe) 613 { 614 return -ENOTTY; 615 } 616 #endif 617 618 #if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64) 619 int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment, 620 struct resource *res); 621 #else 622 static inline int acpi_get_rc_resources(struct device *dev, const char *hid, 623 u16 segment, struct resource *res) 624 { 625 return -ENODEV; 626 } 627 #endif 628 629 int pci_rebar_get_current_size(struct pci_dev *pdev, int bar); 630 int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size); 631 static inline u64 pci_rebar_size_to_bytes(int size) 632 { 633 return 1ULL << (size + 20); 634 } 635 636 struct device_node; 637 638 #ifdef CONFIG_OF 639 int of_pci_parse_bus_range(struct device_node *node, struct resource *res); 640 int of_get_pci_domain_nr(struct device_node *node); 641 int of_pci_get_max_link_speed(struct device_node *node); 642 void pci_set_of_node(struct pci_dev *dev); 643 void pci_release_of_node(struct pci_dev *dev); 644 void pci_set_bus_of_node(struct pci_bus *bus); 645 void pci_release_bus_of_node(struct pci_bus *bus); 646 647 int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge); 648 649 #else 650 static inline int 651 of_pci_parse_bus_range(struct device_node *node, struct resource *res) 652 { 653 return -EINVAL; 654 } 655 656 static inline int 657 of_get_pci_domain_nr(struct device_node *node) 658 { 659 return -1; 660 } 661 662 static inline int 663 of_pci_get_max_link_speed(struct device_node *node) 664 { 665 return -EINVAL; 666 } 667 668 static inline void pci_set_of_node(struct pci_dev *dev) { } 669 static inline void pci_release_of_node(struct pci_dev *dev) { } 670 static inline void pci_set_bus_of_node(struct pci_bus *bus) { } 671 static inline void pci_release_bus_of_node(struct pci_bus *bus) { } 672 673 static inline int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge) 674 { 675 return 0; 676 } 677 678 #endif /* CONFIG_OF */ 679 680 #ifdef CONFIG_PCIEAER 681 void pci_no_aer(void); 682 void pci_aer_init(struct pci_dev *dev); 683 void pci_aer_exit(struct pci_dev *dev); 684 extern const struct attribute_group aer_stats_attr_group; 685 void pci_aer_clear_fatal_status(struct pci_dev *dev); 686 int pci_aer_clear_status(struct pci_dev *dev); 687 int pci_aer_raw_clear_status(struct pci_dev *dev); 688 #else 689 static inline void pci_no_aer(void) { } 690 static inline void pci_aer_init(struct pci_dev *d) { } 691 static inline void pci_aer_exit(struct pci_dev *d) { } 692 static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { } 693 static inline int pci_aer_clear_status(struct pci_dev *dev) { return -EINVAL; } 694 static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -EINVAL; } 695 #endif 696 697 #ifdef CONFIG_ACPI 698 int pci_acpi_program_hp_params(struct pci_dev *dev); 699 extern const struct attribute_group pci_dev_acpi_attr_group; 700 #else 701 static inline int pci_acpi_program_hp_params(struct pci_dev *dev) 702 { 703 return -ENODEV; 704 } 705 #endif 706 707 #ifdef CONFIG_PCIEASPM 708 extern const struct attribute_group aspm_ctrl_attr_group; 709 #endif 710 711 #endif /* DRIVERS_PCI_H */ 712