1 #ifndef DRIVERS_PCI_H 2 #define DRIVERS_PCI_H 3 4 #define PCI_CFG_SPACE_SIZE 256 5 #define PCI_CFG_SPACE_EXP_SIZE 4096 6 7 #define PCI_FIND_CAP_TTL 48 8 9 extern const unsigned char pcie_link_speed[]; 10 11 bool pcie_cap_has_lnkctl(const struct pci_dev *dev); 12 13 /* Functions internal to the PCI core code */ 14 15 int pci_create_sysfs_dev_files(struct pci_dev *pdev); 16 void pci_remove_sysfs_dev_files(struct pci_dev *pdev); 17 #if !defined(CONFIG_DMI) && !defined(CONFIG_ACPI) 18 static inline void pci_create_firmware_label_files(struct pci_dev *pdev) 19 { return; } 20 static inline void pci_remove_firmware_label_files(struct pci_dev *pdev) 21 { return; } 22 #else 23 void pci_create_firmware_label_files(struct pci_dev *pdev); 24 void pci_remove_firmware_label_files(struct pci_dev *pdev); 25 #endif 26 void pci_cleanup_rom(struct pci_dev *dev); 27 #ifdef HAVE_PCI_MMAP 28 enum pci_mmap_api { 29 PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */ 30 PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */ 31 }; 32 int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai, 33 enum pci_mmap_api mmap_api); 34 #endif 35 int pci_probe_reset_function(struct pci_dev *dev); 36 37 /** 38 * struct pci_platform_pm_ops - Firmware PM callbacks 39 * 40 * @is_manageable: returns 'true' if given device is power manageable by the 41 * platform firmware 42 * 43 * @set_state: invokes the platform firmware to set the device's power state 44 * 45 * @choose_state: returns PCI power state of given device preferred by the 46 * platform; to be used during system-wide transitions from a 47 * sleeping state to the working state and vice versa 48 * 49 * @sleep_wake: enables/disables the system wake up capability of given device 50 * 51 * @run_wake: enables/disables the platform to generate run-time wake-up events 52 * for given device (the device's wake-up capability has to be 53 * enabled by @sleep_wake for this feature to work) 54 * 55 * @need_resume: returns 'true' if the given device (which is currently 56 * suspended) needs to be resumed to be configured for system 57 * wakeup. 58 * 59 * If given platform is generally capable of power managing PCI devices, all of 60 * these callbacks are mandatory. 61 */ 62 struct pci_platform_pm_ops { 63 bool (*is_manageable)(struct pci_dev *dev); 64 int (*set_state)(struct pci_dev *dev, pci_power_t state); 65 pci_power_t (*choose_state)(struct pci_dev *dev); 66 int (*sleep_wake)(struct pci_dev *dev, bool enable); 67 int (*run_wake)(struct pci_dev *dev, bool enable); 68 bool (*need_resume)(struct pci_dev *dev); 69 }; 70 71 int pci_set_platform_pm(struct pci_platform_pm_ops *ops); 72 void pci_update_current_state(struct pci_dev *dev, pci_power_t state); 73 void pci_power_up(struct pci_dev *dev); 74 void pci_disable_enabled_device(struct pci_dev *dev); 75 int pci_finish_runtime_suspend(struct pci_dev *dev); 76 int __pci_pme_wakeup(struct pci_dev *dev, void *ign); 77 bool pci_dev_keep_suspended(struct pci_dev *dev); 78 void pci_dev_complete_resume(struct pci_dev *pci_dev); 79 void pci_config_pm_runtime_get(struct pci_dev *dev); 80 void pci_config_pm_runtime_put(struct pci_dev *dev); 81 void pci_pm_init(struct pci_dev *dev); 82 void pci_ea_init(struct pci_dev *dev); 83 void pci_allocate_cap_save_buffers(struct pci_dev *dev); 84 void pci_free_cap_save_buffers(struct pci_dev *dev); 85 86 static inline void pci_wakeup_event(struct pci_dev *dev) 87 { 88 /* Wait 100 ms before the system can be put into a sleep state. */ 89 pm_wakeup_event(&dev->dev, 100); 90 } 91 92 static inline bool pci_has_subordinate(struct pci_dev *pci_dev) 93 { 94 return !!(pci_dev->subordinate); 95 } 96 97 struct pci_vpd_ops { 98 ssize_t (*read)(struct pci_dev *dev, loff_t pos, size_t count, void *buf); 99 ssize_t (*write)(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); 100 void (*release)(struct pci_dev *dev); 101 }; 102 103 struct pci_vpd { 104 unsigned int len; 105 const struct pci_vpd_ops *ops; 106 struct bin_attribute *attr; /* descriptor for sysfs VPD entry */ 107 }; 108 109 int pci_vpd_pci22_init(struct pci_dev *dev); 110 static inline void pci_vpd_release(struct pci_dev *dev) 111 { 112 if (dev->vpd) 113 dev->vpd->ops->release(dev); 114 } 115 116 /* PCI /proc functions */ 117 #ifdef CONFIG_PROC_FS 118 int pci_proc_attach_device(struct pci_dev *dev); 119 int pci_proc_detach_device(struct pci_dev *dev); 120 int pci_proc_detach_bus(struct pci_bus *bus); 121 #else 122 static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; } 123 static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; } 124 static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; } 125 #endif 126 127 /* Functions for PCI Hotplug drivers to use */ 128 int pci_hp_add_bridge(struct pci_dev *dev); 129 130 #ifdef HAVE_PCI_LEGACY 131 void pci_create_legacy_files(struct pci_bus *bus); 132 void pci_remove_legacy_files(struct pci_bus *bus); 133 #else 134 static inline void pci_create_legacy_files(struct pci_bus *bus) { return; } 135 static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; } 136 #endif 137 138 /* Lock for read/write access to pci device and bus lists */ 139 extern struct rw_semaphore pci_bus_sem; 140 141 extern raw_spinlock_t pci_lock; 142 143 extern unsigned int pci_pm_d3_delay; 144 145 #ifdef CONFIG_PCI_MSI 146 void pci_no_msi(void); 147 void pci_msi_init_pci_dev(struct pci_dev *dev); 148 #else 149 static inline void pci_no_msi(void) { } 150 static inline void pci_msi_init_pci_dev(struct pci_dev *dev) { } 151 #endif 152 153 static inline void pci_msi_set_enable(struct pci_dev *dev, int enable) 154 { 155 u16 control; 156 157 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); 158 control &= ~PCI_MSI_FLAGS_ENABLE; 159 if (enable) 160 control |= PCI_MSI_FLAGS_ENABLE; 161 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); 162 } 163 164 static inline void pci_msix_clear_and_set_ctrl(struct pci_dev *dev, u16 clear, u16 set) 165 { 166 u16 ctrl; 167 168 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl); 169 ctrl &= ~clear; 170 ctrl |= set; 171 pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, ctrl); 172 } 173 174 void pci_realloc_get_opt(char *); 175 176 static inline int pci_no_d1d2(struct pci_dev *dev) 177 { 178 unsigned int parent_dstates = 0; 179 180 if (dev->bus->self) 181 parent_dstates = dev->bus->self->no_d1d2; 182 return (dev->no_d1d2 || parent_dstates); 183 184 } 185 extern const struct attribute_group *pci_dev_groups[]; 186 extern const struct attribute_group *pcibus_groups[]; 187 extern struct device_type pci_dev_type; 188 extern const struct attribute_group *pci_bus_groups[]; 189 190 191 /** 192 * pci_match_one_device - Tell if a PCI device structure has a matching 193 * PCI device id structure 194 * @id: single PCI device id structure to match 195 * @dev: the PCI device structure to match against 196 * 197 * Returns the matching pci_device_id structure or %NULL if there is no match. 198 */ 199 static inline const struct pci_device_id * 200 pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev) 201 { 202 if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) && 203 (id->device == PCI_ANY_ID || id->device == dev->device) && 204 (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) && 205 (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) && 206 !((id->class ^ dev->class) & id->class_mask)) 207 return id; 208 return NULL; 209 } 210 211 /* PCI slot sysfs helper code */ 212 #define to_pci_slot(s) container_of(s, struct pci_slot, kobj) 213 214 extern struct kset *pci_slots_kset; 215 216 struct pci_slot_attribute { 217 struct attribute attr; 218 ssize_t (*show)(struct pci_slot *, char *); 219 ssize_t (*store)(struct pci_slot *, const char *, size_t); 220 }; 221 #define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr) 222 223 enum pci_bar_type { 224 pci_bar_unknown, /* Standard PCI BAR probe */ 225 pci_bar_io, /* An io port BAR */ 226 pci_bar_mem32, /* A 32-bit memory BAR */ 227 pci_bar_mem64, /* A 64-bit memory BAR */ 228 }; 229 230 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, 231 int crs_timeout); 232 int pci_setup_device(struct pci_dev *dev); 233 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, 234 struct resource *res, unsigned int reg); 235 int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type); 236 void pci_configure_ari(struct pci_dev *dev); 237 void __pci_bus_size_bridges(struct pci_bus *bus, 238 struct list_head *realloc_head); 239 void __pci_bus_assign_resources(const struct pci_bus *bus, 240 struct list_head *realloc_head, 241 struct list_head *fail_head); 242 bool pci_bus_clip_resource(struct pci_dev *dev, int idx); 243 244 void pci_reassigndev_resource_alignment(struct pci_dev *dev); 245 void pci_disable_bridge_window(struct pci_dev *dev); 246 247 /* Single Root I/O Virtualization */ 248 struct pci_sriov { 249 int pos; /* capability position */ 250 int nres; /* number of resources */ 251 u32 cap; /* SR-IOV Capabilities */ 252 u16 ctrl; /* SR-IOV Control */ 253 u16 total_VFs; /* total VFs associated with the PF */ 254 u16 initial_VFs; /* initial VFs associated with the PF */ 255 u16 num_VFs; /* number of VFs available */ 256 u16 offset; /* first VF Routing ID offset */ 257 u16 stride; /* following VF stride */ 258 u32 pgsz; /* page size for BAR alignment */ 259 u8 link; /* Function Dependency Link */ 260 u8 max_VF_buses; /* max buses consumed by VFs */ 261 u16 driver_max_VFs; /* max num VFs driver supports */ 262 struct pci_dev *dev; /* lowest numbered PF */ 263 struct pci_dev *self; /* this PF */ 264 struct mutex lock; /* lock for VF bus */ 265 resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */ 266 }; 267 268 #ifdef CONFIG_PCI_ATS 269 void pci_restore_ats_state(struct pci_dev *dev); 270 #else 271 static inline void pci_restore_ats_state(struct pci_dev *dev) 272 { 273 } 274 #endif /* CONFIG_PCI_ATS */ 275 276 #ifdef CONFIG_PCI_IOV 277 int pci_iov_init(struct pci_dev *dev); 278 void pci_iov_release(struct pci_dev *dev); 279 int pci_iov_resource_bar(struct pci_dev *dev, int resno); 280 resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno); 281 void pci_restore_iov_state(struct pci_dev *dev); 282 int pci_iov_bus_range(struct pci_bus *bus); 283 284 #else 285 static inline int pci_iov_init(struct pci_dev *dev) 286 { 287 return -ENODEV; 288 } 289 static inline void pci_iov_release(struct pci_dev *dev) 290 291 { 292 } 293 static inline int pci_iov_resource_bar(struct pci_dev *dev, int resno) 294 { 295 return 0; 296 } 297 static inline void pci_restore_iov_state(struct pci_dev *dev) 298 { 299 } 300 static inline int pci_iov_bus_range(struct pci_bus *bus) 301 { 302 return 0; 303 } 304 305 #endif /* CONFIG_PCI_IOV */ 306 307 unsigned long pci_cardbus_resource_alignment(struct resource *); 308 309 static inline resource_size_t pci_resource_alignment(struct pci_dev *dev, 310 struct resource *res) 311 { 312 #ifdef CONFIG_PCI_IOV 313 int resno = res - dev->resource; 314 315 if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END) 316 return pci_sriov_resource_alignment(dev, resno); 317 #endif 318 if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS) 319 return pci_cardbus_resource_alignment(res); 320 return resource_alignment(res); 321 } 322 323 void pci_enable_acs(struct pci_dev *dev); 324 325 struct pci_dev_reset_methods { 326 u16 vendor; 327 u16 device; 328 int (*reset)(struct pci_dev *dev, int probe); 329 }; 330 331 #ifdef CONFIG_PCI_QUIRKS 332 int pci_dev_specific_reset(struct pci_dev *dev, int probe); 333 #else 334 static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe) 335 { 336 return -ENOTTY; 337 } 338 #endif 339 340 #endif /* DRIVERS_PCI_H */ 341