1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef DRIVERS_PCI_H 3 #define DRIVERS_PCI_H 4 5 #include <linux/pci.h> 6 7 /* Number of possible devfns: 0.0 to 1f.7 inclusive */ 8 #define MAX_NR_DEVFNS 256 9 10 #define PCI_FIND_CAP_TTL 48 11 12 #define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */ 13 14 extern const unsigned char pcie_link_speed[]; 15 extern bool pci_early_dump; 16 17 bool pcie_cap_has_lnkctl(const struct pci_dev *dev); 18 bool pcie_cap_has_lnkctl2(const struct pci_dev *dev); 19 bool pcie_cap_has_rtctl(const struct pci_dev *dev); 20 21 /* Functions internal to the PCI core code */ 22 23 int pci_create_sysfs_dev_files(struct pci_dev *pdev); 24 void pci_remove_sysfs_dev_files(struct pci_dev *pdev); 25 void pci_cleanup_rom(struct pci_dev *dev); 26 #ifdef CONFIG_DMI 27 extern const struct attribute_group pci_dev_smbios_attr_group; 28 #endif 29 30 enum pci_mmap_api { 31 PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */ 32 PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */ 33 }; 34 int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai, 35 enum pci_mmap_api mmap_api); 36 37 bool pci_reset_supported(struct pci_dev *dev); 38 void pci_init_reset_methods(struct pci_dev *dev); 39 int pci_bridge_secondary_bus_reset(struct pci_dev *dev); 40 int pci_bus_error_reset(struct pci_dev *dev); 41 42 struct pci_cap_saved_data { 43 u16 cap_nr; 44 bool cap_extended; 45 unsigned int size; 46 u32 data[]; 47 }; 48 49 struct pci_cap_saved_state { 50 struct hlist_node next; 51 struct pci_cap_saved_data cap; 52 }; 53 54 void pci_allocate_cap_save_buffers(struct pci_dev *dev); 55 void pci_free_cap_save_buffers(struct pci_dev *dev); 56 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size); 57 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, 58 u16 cap, unsigned int size); 59 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap); 60 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, 61 u16 cap); 62 63 #define PCI_PM_D2_DELAY 200 /* usec; see PCIe r4.0, sec 5.9.1 */ 64 #define PCI_PM_D3HOT_WAIT 10 /* msec */ 65 #define PCI_PM_D3COLD_WAIT 100 /* msec */ 66 67 void pci_update_current_state(struct pci_dev *dev, pci_power_t state); 68 void pci_refresh_power_state(struct pci_dev *dev); 69 int pci_power_up(struct pci_dev *dev); 70 void pci_disable_enabled_device(struct pci_dev *dev); 71 int pci_finish_runtime_suspend(struct pci_dev *dev); 72 void pcie_clear_device_status(struct pci_dev *dev); 73 void pcie_clear_root_pme_status(struct pci_dev *dev); 74 bool pci_check_pme_status(struct pci_dev *dev); 75 void pci_pme_wakeup_bus(struct pci_bus *bus); 76 int __pci_pme_wakeup(struct pci_dev *dev, void *ign); 77 void pci_pme_restore(struct pci_dev *dev); 78 bool pci_dev_need_resume(struct pci_dev *dev); 79 void pci_dev_adjust_pme(struct pci_dev *dev); 80 void pci_dev_complete_resume(struct pci_dev *pci_dev); 81 void pci_config_pm_runtime_get(struct pci_dev *dev); 82 void pci_config_pm_runtime_put(struct pci_dev *dev); 83 void pci_pm_init(struct pci_dev *dev); 84 void pci_ea_init(struct pci_dev *dev); 85 void pci_msi_init(struct pci_dev *dev); 86 void pci_msix_init(struct pci_dev *dev); 87 bool pci_bridge_d3_possible(struct pci_dev *dev); 88 void pci_bridge_d3_update(struct pci_dev *dev); 89 void pci_bridge_wait_for_secondary_bus(struct pci_dev *dev); 90 void pci_bridge_reconfigure_ltr(struct pci_dev *dev); 91 92 static inline void pci_wakeup_event(struct pci_dev *dev) 93 { 94 /* Wait 100 ms before the system can be put into a sleep state. */ 95 pm_wakeup_event(&dev->dev, 100); 96 } 97 98 static inline bool pci_has_subordinate(struct pci_dev *pci_dev) 99 { 100 return !!(pci_dev->subordinate); 101 } 102 103 static inline bool pci_power_manageable(struct pci_dev *pci_dev) 104 { 105 /* 106 * Currently we allow normal PCI devices and PCI bridges transition 107 * into D3 if their bridge_d3 is set. 108 */ 109 return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3; 110 } 111 112 static inline bool pcie_downstream_port(const struct pci_dev *dev) 113 { 114 int type = pci_pcie_type(dev); 115 116 return type == PCI_EXP_TYPE_ROOT_PORT || 117 type == PCI_EXP_TYPE_DOWNSTREAM || 118 type == PCI_EXP_TYPE_PCIE_BRIDGE; 119 } 120 121 void pci_vpd_init(struct pci_dev *dev); 122 void pci_vpd_release(struct pci_dev *dev); 123 extern const struct attribute_group pci_dev_vpd_attr_group; 124 125 /* PCI Virtual Channel */ 126 int pci_save_vc_state(struct pci_dev *dev); 127 void pci_restore_vc_state(struct pci_dev *dev); 128 void pci_allocate_vc_save_buffers(struct pci_dev *dev); 129 130 /* PCI /proc functions */ 131 #ifdef CONFIG_PROC_FS 132 int pci_proc_attach_device(struct pci_dev *dev); 133 int pci_proc_detach_device(struct pci_dev *dev); 134 int pci_proc_detach_bus(struct pci_bus *bus); 135 #else 136 static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; } 137 static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; } 138 static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; } 139 #endif 140 141 /* Functions for PCI Hotplug drivers to use */ 142 int pci_hp_add_bridge(struct pci_dev *dev); 143 144 #ifdef HAVE_PCI_LEGACY 145 void pci_create_legacy_files(struct pci_bus *bus); 146 void pci_remove_legacy_files(struct pci_bus *bus); 147 #else 148 static inline void pci_create_legacy_files(struct pci_bus *bus) { return; } 149 static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; } 150 #endif 151 152 /* Lock for read/write access to pci device and bus lists */ 153 extern struct rw_semaphore pci_bus_sem; 154 extern struct mutex pci_slot_mutex; 155 156 extern raw_spinlock_t pci_lock; 157 158 extern unsigned int pci_pm_d3hot_delay; 159 160 #ifdef CONFIG_PCI_MSI 161 void pci_no_msi(void); 162 #else 163 static inline void pci_no_msi(void) { } 164 #endif 165 166 void pci_realloc_get_opt(char *); 167 168 static inline int pci_no_d1d2(struct pci_dev *dev) 169 { 170 unsigned int parent_dstates = 0; 171 172 if (dev->bus->self) 173 parent_dstates = dev->bus->self->no_d1d2; 174 return (dev->no_d1d2 || parent_dstates); 175 176 } 177 extern const struct attribute_group *pci_dev_groups[]; 178 extern const struct attribute_group *pcibus_groups[]; 179 extern const struct device_type pci_dev_type; 180 extern const struct attribute_group *pci_bus_groups[]; 181 182 extern unsigned long pci_hotplug_io_size; 183 extern unsigned long pci_hotplug_mmio_size; 184 extern unsigned long pci_hotplug_mmio_pref_size; 185 extern unsigned long pci_hotplug_bus_size; 186 187 /** 188 * pci_match_one_device - Tell if a PCI device structure has a matching 189 * PCI device id structure 190 * @id: single PCI device id structure to match 191 * @dev: the PCI device structure to match against 192 * 193 * Returns the matching pci_device_id structure or %NULL if there is no match. 194 */ 195 static inline const struct pci_device_id * 196 pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev) 197 { 198 if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) && 199 (id->device == PCI_ANY_ID || id->device == dev->device) && 200 (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) && 201 (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) && 202 !((id->class ^ dev->class) & id->class_mask)) 203 return id; 204 return NULL; 205 } 206 207 /* PCI slot sysfs helper code */ 208 #define to_pci_slot(s) container_of(s, struct pci_slot, kobj) 209 210 extern struct kset *pci_slots_kset; 211 212 struct pci_slot_attribute { 213 struct attribute attr; 214 ssize_t (*show)(struct pci_slot *, char *); 215 ssize_t (*store)(struct pci_slot *, const char *, size_t); 216 }; 217 #define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr) 218 219 enum pci_bar_type { 220 pci_bar_unknown, /* Standard PCI BAR probe */ 221 pci_bar_io, /* An I/O port BAR */ 222 pci_bar_mem32, /* A 32-bit memory BAR */ 223 pci_bar_mem64, /* A 64-bit memory BAR */ 224 }; 225 226 struct device *pci_get_host_bridge_device(struct pci_dev *dev); 227 void pci_put_host_bridge_device(struct device *dev); 228 229 int pci_configure_extended_tags(struct pci_dev *dev, void *ign); 230 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, 231 int crs_timeout); 232 bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, 233 int crs_timeout); 234 int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int crs_timeout); 235 236 int pci_setup_device(struct pci_dev *dev); 237 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, 238 struct resource *res, unsigned int reg); 239 void pci_configure_ari(struct pci_dev *dev); 240 void __pci_bus_size_bridges(struct pci_bus *bus, 241 struct list_head *realloc_head); 242 void __pci_bus_assign_resources(const struct pci_bus *bus, 243 struct list_head *realloc_head, 244 struct list_head *fail_head); 245 bool pci_bus_clip_resource(struct pci_dev *dev, int idx); 246 247 void pci_reassigndev_resource_alignment(struct pci_dev *dev); 248 void pci_disable_bridge_window(struct pci_dev *dev); 249 struct pci_bus *pci_bus_get(struct pci_bus *bus); 250 void pci_bus_put(struct pci_bus *bus); 251 252 /* PCIe link information from Link Capabilities 2 */ 253 #define PCIE_LNKCAP2_SLS2SPEED(lnkcap2) \ 254 ((lnkcap2) & PCI_EXP_LNKCAP2_SLS_64_0GB ? PCIE_SPEED_64_0GT : \ 255 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_32_0GB ? PCIE_SPEED_32_0GT : \ 256 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_16_0GB ? PCIE_SPEED_16_0GT : \ 257 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_8_0GB ? PCIE_SPEED_8_0GT : \ 258 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_5_0GB ? PCIE_SPEED_5_0GT : \ 259 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_2_5GB ? PCIE_SPEED_2_5GT : \ 260 PCI_SPEED_UNKNOWN) 261 262 /* PCIe speed to Mb/s reduced by encoding overhead */ 263 #define PCIE_SPEED2MBS_ENC(speed) \ 264 ((speed) == PCIE_SPEED_64_0GT ? 64000*128/130 : \ 265 (speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \ 266 (speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \ 267 (speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \ 268 (speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \ 269 (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \ 270 0) 271 272 const char *pci_speed_string(enum pci_bus_speed speed); 273 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev); 274 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev); 275 u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed, 276 enum pcie_link_width *width); 277 void __pcie_print_link_status(struct pci_dev *dev, bool verbose); 278 void pcie_report_downtraining(struct pci_dev *dev); 279 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status); 280 281 /* Single Root I/O Virtualization */ 282 struct pci_sriov { 283 int pos; /* Capability position */ 284 int nres; /* Number of resources */ 285 u32 cap; /* SR-IOV Capabilities */ 286 u16 ctrl; /* SR-IOV Control */ 287 u16 total_VFs; /* Total VFs associated with the PF */ 288 u16 initial_VFs; /* Initial VFs associated with the PF */ 289 u16 num_VFs; /* Number of VFs available */ 290 u16 offset; /* First VF Routing ID offset */ 291 u16 stride; /* Following VF stride */ 292 u16 vf_device; /* VF device ID */ 293 u32 pgsz; /* Page size for BAR alignment */ 294 u8 link; /* Function Dependency Link */ 295 u8 max_VF_buses; /* Max buses consumed by VFs */ 296 u16 driver_max_VFs; /* Max num VFs driver supports */ 297 struct pci_dev *dev; /* Lowest numbered PF */ 298 struct pci_dev *self; /* This PF */ 299 u32 class; /* VF device */ 300 u8 hdr_type; /* VF header type */ 301 u16 subsystem_vendor; /* VF subsystem vendor */ 302 u16 subsystem_device; /* VF subsystem device */ 303 resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */ 304 bool drivers_autoprobe; /* Auto probing of VFs by driver */ 305 }; 306 307 /** 308 * pci_dev_set_io_state - Set the new error state if possible. 309 * 310 * @dev: PCI device to set new error_state 311 * @new: the state we want dev to be in 312 * 313 * Must be called with device_lock held. 314 * 315 * Returns true if state has been changed to the requested state. 316 */ 317 static inline bool pci_dev_set_io_state(struct pci_dev *dev, 318 pci_channel_state_t new) 319 { 320 bool changed = false; 321 322 device_lock_assert(&dev->dev); 323 switch (new) { 324 case pci_channel_io_perm_failure: 325 switch (dev->error_state) { 326 case pci_channel_io_frozen: 327 case pci_channel_io_normal: 328 case pci_channel_io_perm_failure: 329 changed = true; 330 break; 331 } 332 break; 333 case pci_channel_io_frozen: 334 switch (dev->error_state) { 335 case pci_channel_io_frozen: 336 case pci_channel_io_normal: 337 changed = true; 338 break; 339 } 340 break; 341 case pci_channel_io_normal: 342 switch (dev->error_state) { 343 case pci_channel_io_frozen: 344 case pci_channel_io_normal: 345 changed = true; 346 break; 347 } 348 break; 349 } 350 if (changed) 351 dev->error_state = new; 352 return changed; 353 } 354 355 static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused) 356 { 357 device_lock(&dev->dev); 358 pci_dev_set_io_state(dev, pci_channel_io_perm_failure); 359 device_unlock(&dev->dev); 360 361 return 0; 362 } 363 364 static inline bool pci_dev_is_disconnected(const struct pci_dev *dev) 365 { 366 return dev->error_state == pci_channel_io_perm_failure; 367 } 368 369 /* pci_dev priv_flags */ 370 #define PCI_DEV_ADDED 0 371 #define PCI_DPC_RECOVERED 1 372 #define PCI_DPC_RECOVERING 2 373 374 static inline void pci_dev_assign_added(struct pci_dev *dev, bool added) 375 { 376 assign_bit(PCI_DEV_ADDED, &dev->priv_flags, added); 377 } 378 379 static inline bool pci_dev_is_added(const struct pci_dev *dev) 380 { 381 return test_bit(PCI_DEV_ADDED, &dev->priv_flags); 382 } 383 384 #ifdef CONFIG_PCIEAER 385 #include <linux/aer.h> 386 387 #define AER_MAX_MULTI_ERR_DEVICES 5 /* Not likely to have more */ 388 389 struct aer_err_info { 390 struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES]; 391 int error_dev_num; 392 393 unsigned int id:16; 394 395 unsigned int severity:2; /* 0:NONFATAL | 1:FATAL | 2:COR */ 396 unsigned int __pad1:5; 397 unsigned int multi_error_valid:1; 398 399 unsigned int first_error:5; 400 unsigned int __pad2:2; 401 unsigned int tlp_header_valid:1; 402 403 unsigned int status; /* COR/UNCOR Error Status */ 404 unsigned int mask; /* COR/UNCOR Error Mask */ 405 struct aer_header_log_regs tlp; /* TLP Header */ 406 }; 407 408 int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info); 409 void aer_print_error(struct pci_dev *dev, struct aer_err_info *info); 410 #endif /* CONFIG_PCIEAER */ 411 412 #ifdef CONFIG_PCIEPORTBUS 413 /* Cached RCEC Endpoint Association */ 414 struct rcec_ea { 415 u8 nextbusn; 416 u8 lastbusn; 417 u32 bitmap; 418 }; 419 #endif 420 421 #ifdef CONFIG_PCIE_DPC 422 void pci_save_dpc_state(struct pci_dev *dev); 423 void pci_restore_dpc_state(struct pci_dev *dev); 424 void pci_dpc_init(struct pci_dev *pdev); 425 void dpc_process_error(struct pci_dev *pdev); 426 pci_ers_result_t dpc_reset_link(struct pci_dev *pdev); 427 bool pci_dpc_recovered(struct pci_dev *pdev); 428 #else 429 static inline void pci_save_dpc_state(struct pci_dev *dev) {} 430 static inline void pci_restore_dpc_state(struct pci_dev *dev) {} 431 static inline void pci_dpc_init(struct pci_dev *pdev) {} 432 static inline bool pci_dpc_recovered(struct pci_dev *pdev) { return false; } 433 #endif 434 435 #ifdef CONFIG_PCIEPORTBUS 436 void pci_rcec_init(struct pci_dev *dev); 437 void pci_rcec_exit(struct pci_dev *dev); 438 void pcie_link_rcec(struct pci_dev *rcec); 439 void pcie_walk_rcec(struct pci_dev *rcec, 440 int (*cb)(struct pci_dev *, void *), 441 void *userdata); 442 #else 443 static inline void pci_rcec_init(struct pci_dev *dev) {} 444 static inline void pci_rcec_exit(struct pci_dev *dev) {} 445 static inline void pcie_link_rcec(struct pci_dev *rcec) {} 446 static inline void pcie_walk_rcec(struct pci_dev *rcec, 447 int (*cb)(struct pci_dev *, void *), 448 void *userdata) {} 449 #endif 450 451 #ifdef CONFIG_PCI_ATS 452 /* Address Translation Service */ 453 void pci_ats_init(struct pci_dev *dev); 454 void pci_restore_ats_state(struct pci_dev *dev); 455 #else 456 static inline void pci_ats_init(struct pci_dev *d) { } 457 static inline void pci_restore_ats_state(struct pci_dev *dev) { } 458 #endif /* CONFIG_PCI_ATS */ 459 460 #ifdef CONFIG_PCI_PRI 461 void pci_pri_init(struct pci_dev *dev); 462 void pci_restore_pri_state(struct pci_dev *pdev); 463 #else 464 static inline void pci_pri_init(struct pci_dev *dev) { } 465 static inline void pci_restore_pri_state(struct pci_dev *pdev) { } 466 #endif 467 468 #ifdef CONFIG_PCI_PASID 469 void pci_pasid_init(struct pci_dev *dev); 470 void pci_restore_pasid_state(struct pci_dev *pdev); 471 #else 472 static inline void pci_pasid_init(struct pci_dev *dev) { } 473 static inline void pci_restore_pasid_state(struct pci_dev *pdev) { } 474 #endif 475 476 #ifdef CONFIG_PCI_IOV 477 int pci_iov_init(struct pci_dev *dev); 478 void pci_iov_release(struct pci_dev *dev); 479 void pci_iov_remove(struct pci_dev *dev); 480 void pci_iov_update_resource(struct pci_dev *dev, int resno); 481 resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno); 482 void pci_restore_iov_state(struct pci_dev *dev); 483 int pci_iov_bus_range(struct pci_bus *bus); 484 extern const struct attribute_group sriov_pf_dev_attr_group; 485 extern const struct attribute_group sriov_vf_dev_attr_group; 486 #else 487 static inline int pci_iov_init(struct pci_dev *dev) 488 { 489 return -ENODEV; 490 } 491 static inline void pci_iov_release(struct pci_dev *dev) 492 493 { 494 } 495 static inline void pci_iov_remove(struct pci_dev *dev) 496 { 497 } 498 static inline void pci_restore_iov_state(struct pci_dev *dev) 499 { 500 } 501 static inline int pci_iov_bus_range(struct pci_bus *bus) 502 { 503 return 0; 504 } 505 506 #endif /* CONFIG_PCI_IOV */ 507 508 #ifdef CONFIG_PCIE_PTM 509 void pci_ptm_init(struct pci_dev *dev); 510 void pci_save_ptm_state(struct pci_dev *dev); 511 void pci_restore_ptm_state(struct pci_dev *dev); 512 void pci_suspend_ptm(struct pci_dev *dev); 513 void pci_resume_ptm(struct pci_dev *dev); 514 #else 515 static inline void pci_ptm_init(struct pci_dev *dev) { } 516 static inline void pci_save_ptm_state(struct pci_dev *dev) { } 517 static inline void pci_restore_ptm_state(struct pci_dev *dev) { } 518 static inline void pci_suspend_ptm(struct pci_dev *dev) { } 519 static inline void pci_resume_ptm(struct pci_dev *dev) { } 520 #endif 521 522 unsigned long pci_cardbus_resource_alignment(struct resource *); 523 524 static inline resource_size_t pci_resource_alignment(struct pci_dev *dev, 525 struct resource *res) 526 { 527 #ifdef CONFIG_PCI_IOV 528 int resno = res - dev->resource; 529 530 if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END) 531 return pci_sriov_resource_alignment(dev, resno); 532 #endif 533 if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS) 534 return pci_cardbus_resource_alignment(res); 535 return resource_alignment(res); 536 } 537 538 void pci_acs_init(struct pci_dev *dev); 539 #ifdef CONFIG_PCI_QUIRKS 540 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags); 541 int pci_dev_specific_enable_acs(struct pci_dev *dev); 542 int pci_dev_specific_disable_acs_redir(struct pci_dev *dev); 543 #else 544 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev, 545 u16 acs_flags) 546 { 547 return -ENOTTY; 548 } 549 static inline int pci_dev_specific_enable_acs(struct pci_dev *dev) 550 { 551 return -ENOTTY; 552 } 553 static inline int pci_dev_specific_disable_acs_redir(struct pci_dev *dev) 554 { 555 return -ENOTTY; 556 } 557 #endif 558 559 /* PCI error reporting and recovery */ 560 pci_ers_result_t pcie_do_recovery(struct pci_dev *dev, 561 pci_channel_state_t state, 562 pci_ers_result_t (*reset_subordinates)(struct pci_dev *pdev)); 563 564 bool pcie_wait_for_link(struct pci_dev *pdev, bool active); 565 #ifdef CONFIG_PCIEASPM 566 void pcie_aspm_init_link_state(struct pci_dev *pdev); 567 void pcie_aspm_exit_link_state(struct pci_dev *pdev); 568 void pcie_aspm_powersave_config_link(struct pci_dev *pdev); 569 void pci_save_aspm_l1ss_state(struct pci_dev *dev); 570 void pci_restore_aspm_l1ss_state(struct pci_dev *dev); 571 #else 572 static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { } 573 static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { } 574 static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { } 575 static inline void pci_save_aspm_l1ss_state(struct pci_dev *dev) { } 576 static inline void pci_restore_aspm_l1ss_state(struct pci_dev *dev) { } 577 #endif 578 579 #ifdef CONFIG_PCIE_ECRC 580 void pcie_set_ecrc_checking(struct pci_dev *dev); 581 void pcie_ecrc_get_policy(char *str); 582 #else 583 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { } 584 static inline void pcie_ecrc_get_policy(char *str) { } 585 #endif 586 587 struct pci_dev_reset_methods { 588 u16 vendor; 589 u16 device; 590 int (*reset)(struct pci_dev *dev, bool probe); 591 }; 592 593 struct pci_reset_fn_method { 594 int (*reset_fn)(struct pci_dev *pdev, bool probe); 595 char *name; 596 }; 597 598 #ifdef CONFIG_PCI_QUIRKS 599 int pci_dev_specific_reset(struct pci_dev *dev, bool probe); 600 #else 601 static inline int pci_dev_specific_reset(struct pci_dev *dev, bool probe) 602 { 603 return -ENOTTY; 604 } 605 #endif 606 607 #if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64) 608 int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment, 609 struct resource *res); 610 #else 611 static inline int acpi_get_rc_resources(struct device *dev, const char *hid, 612 u16 segment, struct resource *res) 613 { 614 return -ENODEV; 615 } 616 #endif 617 618 int pci_rebar_get_current_size(struct pci_dev *pdev, int bar); 619 int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size); 620 static inline u64 pci_rebar_size_to_bytes(int size) 621 { 622 return 1ULL << (size + 20); 623 } 624 625 struct device_node; 626 627 #ifdef CONFIG_OF 628 int of_pci_parse_bus_range(struct device_node *node, struct resource *res); 629 int of_get_pci_domain_nr(struct device_node *node); 630 int of_pci_get_max_link_speed(struct device_node *node); 631 u32 of_pci_get_slot_power_limit(struct device_node *node, 632 u8 *slot_power_limit_value, 633 u8 *slot_power_limit_scale); 634 void pci_set_of_node(struct pci_dev *dev); 635 void pci_release_of_node(struct pci_dev *dev); 636 void pci_set_bus_of_node(struct pci_bus *bus); 637 void pci_release_bus_of_node(struct pci_bus *bus); 638 639 int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge); 640 641 #else 642 static inline int 643 of_pci_parse_bus_range(struct device_node *node, struct resource *res) 644 { 645 return -EINVAL; 646 } 647 648 static inline int 649 of_get_pci_domain_nr(struct device_node *node) 650 { 651 return -1; 652 } 653 654 static inline int 655 of_pci_get_max_link_speed(struct device_node *node) 656 { 657 return -EINVAL; 658 } 659 660 static inline u32 661 of_pci_get_slot_power_limit(struct device_node *node, 662 u8 *slot_power_limit_value, 663 u8 *slot_power_limit_scale) 664 { 665 if (slot_power_limit_value) 666 *slot_power_limit_value = 0; 667 if (slot_power_limit_scale) 668 *slot_power_limit_scale = 0; 669 return 0; 670 } 671 672 static inline void pci_set_of_node(struct pci_dev *dev) { } 673 static inline void pci_release_of_node(struct pci_dev *dev) { } 674 static inline void pci_set_bus_of_node(struct pci_bus *bus) { } 675 static inline void pci_release_bus_of_node(struct pci_bus *bus) { } 676 677 static inline int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge) 678 { 679 return 0; 680 } 681 682 #endif /* CONFIG_OF */ 683 684 #ifdef CONFIG_PCIEAER 685 void pci_no_aer(void); 686 void pci_aer_init(struct pci_dev *dev); 687 void pci_aer_exit(struct pci_dev *dev); 688 extern const struct attribute_group aer_stats_attr_group; 689 void pci_aer_clear_fatal_status(struct pci_dev *dev); 690 int pci_aer_clear_status(struct pci_dev *dev); 691 int pci_aer_raw_clear_status(struct pci_dev *dev); 692 #else 693 static inline void pci_no_aer(void) { } 694 static inline void pci_aer_init(struct pci_dev *d) { } 695 static inline void pci_aer_exit(struct pci_dev *d) { } 696 static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { } 697 static inline int pci_aer_clear_status(struct pci_dev *dev) { return -EINVAL; } 698 static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -EINVAL; } 699 #endif 700 701 #ifdef CONFIG_ACPI 702 int pci_acpi_program_hp_params(struct pci_dev *dev); 703 extern const struct attribute_group pci_dev_acpi_attr_group; 704 void pci_set_acpi_fwnode(struct pci_dev *dev); 705 int pci_dev_acpi_reset(struct pci_dev *dev, bool probe); 706 bool acpi_pci_power_manageable(struct pci_dev *dev); 707 bool acpi_pci_bridge_d3(struct pci_dev *dev); 708 int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state); 709 pci_power_t acpi_pci_get_power_state(struct pci_dev *dev); 710 void acpi_pci_refresh_power_state(struct pci_dev *dev); 711 int acpi_pci_wakeup(struct pci_dev *dev, bool enable); 712 bool acpi_pci_need_resume(struct pci_dev *dev); 713 pci_power_t acpi_pci_choose_state(struct pci_dev *pdev); 714 #else 715 static inline int pci_dev_acpi_reset(struct pci_dev *dev, bool probe) 716 { 717 return -ENOTTY; 718 } 719 static inline void pci_set_acpi_fwnode(struct pci_dev *dev) {} 720 static inline int pci_acpi_program_hp_params(struct pci_dev *dev) 721 { 722 return -ENODEV; 723 } 724 static inline bool acpi_pci_power_manageable(struct pci_dev *dev) 725 { 726 return false; 727 } 728 static inline bool acpi_pci_bridge_d3(struct pci_dev *dev) 729 { 730 return false; 731 } 732 static inline int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state) 733 { 734 return -ENODEV; 735 } 736 static inline pci_power_t acpi_pci_get_power_state(struct pci_dev *dev) 737 { 738 return PCI_UNKNOWN; 739 } 740 static inline void acpi_pci_refresh_power_state(struct pci_dev *dev) {} 741 static inline int acpi_pci_wakeup(struct pci_dev *dev, bool enable) 742 { 743 return -ENODEV; 744 } 745 static inline bool acpi_pci_need_resume(struct pci_dev *dev) 746 { 747 return false; 748 } 749 static inline pci_power_t acpi_pci_choose_state(struct pci_dev *pdev) 750 { 751 return PCI_POWER_ERROR; 752 } 753 #endif 754 755 #ifdef CONFIG_PCIEASPM 756 extern const struct attribute_group aspm_ctrl_attr_group; 757 #endif 758 759 extern const struct attribute_group pci_dev_reset_method_attr_group; 760 761 #ifdef CONFIG_X86_INTEL_MID 762 bool pci_use_mid_pm(void); 763 int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state); 764 pci_power_t mid_pci_get_power_state(struct pci_dev *pdev); 765 #else 766 static inline bool pci_use_mid_pm(void) 767 { 768 return false; 769 } 770 static inline int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state) 771 { 772 return -ENODEV; 773 } 774 static inline pci_power_t mid_pci_get_power_state(struct pci_dev *pdev) 775 { 776 return PCI_UNKNOWN; 777 } 778 #endif 779 780 /* 781 * Config Address for PCI Configuration Mechanism #1 782 * 783 * See PCI Local Bus Specification, Revision 3.0, 784 * Section 3.2.2.3.2, Figure 3-2, p. 50. 785 */ 786 787 #define PCI_CONF1_BUS_SHIFT 16 /* Bus number */ 788 #define PCI_CONF1_DEV_SHIFT 11 /* Device number */ 789 #define PCI_CONF1_FUNC_SHIFT 8 /* Function number */ 790 791 #define PCI_CONF1_BUS_MASK 0xff 792 #define PCI_CONF1_DEV_MASK 0x1f 793 #define PCI_CONF1_FUNC_MASK 0x7 794 #define PCI_CONF1_REG_MASK 0xfc /* Limit aligned offset to a maximum of 256B */ 795 796 #define PCI_CONF1_ENABLE BIT(31) 797 #define PCI_CONF1_BUS(x) (((x) & PCI_CONF1_BUS_MASK) << PCI_CONF1_BUS_SHIFT) 798 #define PCI_CONF1_DEV(x) (((x) & PCI_CONF1_DEV_MASK) << PCI_CONF1_DEV_SHIFT) 799 #define PCI_CONF1_FUNC(x) (((x) & PCI_CONF1_FUNC_MASK) << PCI_CONF1_FUNC_SHIFT) 800 #define PCI_CONF1_REG(x) ((x) & PCI_CONF1_REG_MASK) 801 802 #define PCI_CONF1_ADDRESS(bus, dev, func, reg) \ 803 (PCI_CONF1_ENABLE | \ 804 PCI_CONF1_BUS(bus) | \ 805 PCI_CONF1_DEV(dev) | \ 806 PCI_CONF1_FUNC(func) | \ 807 PCI_CONF1_REG(reg)) 808 809 /* 810 * Extension of PCI Config Address for accessing extended PCIe registers 811 * 812 * No standardized specification, but used on lot of non-ECAM-compliant ARM SoCs 813 * or on AMD Barcelona and new CPUs. Reserved bits [27:24] of PCI Config Address 814 * are used for specifying additional 4 high bits of PCI Express register. 815 */ 816 817 #define PCI_CONF1_EXT_REG_SHIFT 16 818 #define PCI_CONF1_EXT_REG_MASK 0xf00 819 #define PCI_CONF1_EXT_REG(x) (((x) & PCI_CONF1_EXT_REG_MASK) << PCI_CONF1_EXT_REG_SHIFT) 820 821 #define PCI_CONF1_EXT_ADDRESS(bus, dev, func, reg) \ 822 (PCI_CONF1_ADDRESS(bus, dev, func, reg) | \ 823 PCI_CONF1_EXT_REG(reg)) 824 825 #endif /* DRIVERS_PCI_H */ 826