1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef DRIVERS_PCI_H 3 #define DRIVERS_PCI_H 4 5 #include <linux/pci.h> 6 7 /* Number of possible devfns: 0.0 to 1f.7 inclusive */ 8 #define MAX_NR_DEVFNS 256 9 10 #define PCI_FIND_CAP_TTL 48 11 12 #define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */ 13 14 #define PCIE_LINK_RETRAIN_TIMEOUT_MS 1000 15 16 /* 17 * PCIe r6.0, sec 5.3.3.2.1 <PME Synchronization> 18 * Recommends 1ms to 10ms timeout to check L2 ready. 19 */ 20 #define PCIE_PME_TO_L2_TIMEOUT_US 10000 21 22 extern const unsigned char pcie_link_speed[]; 23 extern bool pci_early_dump; 24 25 bool pcie_cap_has_lnkctl(const struct pci_dev *dev); 26 bool pcie_cap_has_lnkctl2(const struct pci_dev *dev); 27 bool pcie_cap_has_rtctl(const struct pci_dev *dev); 28 29 /* Functions internal to the PCI core code */ 30 31 int pci_create_sysfs_dev_files(struct pci_dev *pdev); 32 void pci_remove_sysfs_dev_files(struct pci_dev *pdev); 33 void pci_cleanup_rom(struct pci_dev *dev); 34 #ifdef CONFIG_DMI 35 extern const struct attribute_group pci_dev_smbios_attr_group; 36 #endif 37 38 enum pci_mmap_api { 39 PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */ 40 PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */ 41 }; 42 int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai, 43 enum pci_mmap_api mmap_api); 44 45 bool pci_reset_supported(struct pci_dev *dev); 46 void pci_init_reset_methods(struct pci_dev *dev); 47 int pci_bridge_secondary_bus_reset(struct pci_dev *dev); 48 int pci_bus_error_reset(struct pci_dev *dev); 49 50 struct pci_cap_saved_data { 51 u16 cap_nr; 52 bool cap_extended; 53 unsigned int size; 54 u32 data[]; 55 }; 56 57 struct pci_cap_saved_state { 58 struct hlist_node next; 59 struct pci_cap_saved_data cap; 60 }; 61 62 void pci_allocate_cap_save_buffers(struct pci_dev *dev); 63 void pci_free_cap_save_buffers(struct pci_dev *dev); 64 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size); 65 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, 66 u16 cap, unsigned int size); 67 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap); 68 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, 69 u16 cap); 70 71 #define PCI_PM_D2_DELAY 200 /* usec; see PCIe r4.0, sec 5.9.1 */ 72 #define PCI_PM_D3HOT_WAIT 10 /* msec */ 73 #define PCI_PM_D3COLD_WAIT 100 /* msec */ 74 75 void pci_update_current_state(struct pci_dev *dev, pci_power_t state); 76 void pci_refresh_power_state(struct pci_dev *dev); 77 int pci_power_up(struct pci_dev *dev); 78 void pci_disable_enabled_device(struct pci_dev *dev); 79 int pci_finish_runtime_suspend(struct pci_dev *dev); 80 void pcie_clear_device_status(struct pci_dev *dev); 81 void pcie_clear_root_pme_status(struct pci_dev *dev); 82 bool pci_check_pme_status(struct pci_dev *dev); 83 void pci_pme_wakeup_bus(struct pci_bus *bus); 84 int __pci_pme_wakeup(struct pci_dev *dev, void *ign); 85 void pci_pme_restore(struct pci_dev *dev); 86 bool pci_dev_need_resume(struct pci_dev *dev); 87 void pci_dev_adjust_pme(struct pci_dev *dev); 88 void pci_dev_complete_resume(struct pci_dev *pci_dev); 89 void pci_config_pm_runtime_get(struct pci_dev *dev); 90 void pci_config_pm_runtime_put(struct pci_dev *dev); 91 void pci_pm_init(struct pci_dev *dev); 92 void pci_ea_init(struct pci_dev *dev); 93 void pci_msi_init(struct pci_dev *dev); 94 void pci_msix_init(struct pci_dev *dev); 95 bool pci_bridge_d3_possible(struct pci_dev *dev); 96 void pci_bridge_d3_update(struct pci_dev *dev); 97 void pci_bridge_reconfigure_ltr(struct pci_dev *dev); 98 int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type); 99 100 static inline void pci_wakeup_event(struct pci_dev *dev) 101 { 102 /* Wait 100 ms before the system can be put into a sleep state. */ 103 pm_wakeup_event(&dev->dev, 100); 104 } 105 106 static inline bool pci_has_subordinate(struct pci_dev *pci_dev) 107 { 108 return !!(pci_dev->subordinate); 109 } 110 111 static inline bool pci_power_manageable(struct pci_dev *pci_dev) 112 { 113 /* 114 * Currently we allow normal PCI devices and PCI bridges transition 115 * into D3 if their bridge_d3 is set. 116 */ 117 return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3; 118 } 119 120 static inline bool pcie_downstream_port(const struct pci_dev *dev) 121 { 122 int type = pci_pcie_type(dev); 123 124 return type == PCI_EXP_TYPE_ROOT_PORT || 125 type == PCI_EXP_TYPE_DOWNSTREAM || 126 type == PCI_EXP_TYPE_PCIE_BRIDGE; 127 } 128 129 void pci_vpd_init(struct pci_dev *dev); 130 void pci_vpd_release(struct pci_dev *dev); 131 extern const struct attribute_group pci_dev_vpd_attr_group; 132 133 /* PCI Virtual Channel */ 134 int pci_save_vc_state(struct pci_dev *dev); 135 void pci_restore_vc_state(struct pci_dev *dev); 136 void pci_allocate_vc_save_buffers(struct pci_dev *dev); 137 138 /* PCI /proc functions */ 139 #ifdef CONFIG_PROC_FS 140 int pci_proc_attach_device(struct pci_dev *dev); 141 int pci_proc_detach_device(struct pci_dev *dev); 142 int pci_proc_detach_bus(struct pci_bus *bus); 143 #else 144 static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; } 145 static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; } 146 static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; } 147 #endif 148 149 /* Functions for PCI Hotplug drivers to use */ 150 int pci_hp_add_bridge(struct pci_dev *dev); 151 152 #ifdef HAVE_PCI_LEGACY 153 void pci_create_legacy_files(struct pci_bus *bus); 154 void pci_remove_legacy_files(struct pci_bus *bus); 155 #else 156 static inline void pci_create_legacy_files(struct pci_bus *bus) { } 157 static inline void pci_remove_legacy_files(struct pci_bus *bus) { } 158 #endif 159 160 /* Lock for read/write access to pci device and bus lists */ 161 extern struct rw_semaphore pci_bus_sem; 162 extern struct mutex pci_slot_mutex; 163 164 extern raw_spinlock_t pci_lock; 165 166 extern unsigned int pci_pm_d3hot_delay; 167 168 #ifdef CONFIG_PCI_MSI 169 void pci_no_msi(void); 170 #else 171 static inline void pci_no_msi(void) { } 172 #endif 173 174 void pci_realloc_get_opt(char *); 175 176 static inline int pci_no_d1d2(struct pci_dev *dev) 177 { 178 unsigned int parent_dstates = 0; 179 180 if (dev->bus->self) 181 parent_dstates = dev->bus->self->no_d1d2; 182 return (dev->no_d1d2 || parent_dstates); 183 184 } 185 extern const struct attribute_group *pci_dev_groups[]; 186 extern const struct attribute_group *pcibus_groups[]; 187 extern const struct device_type pci_dev_type; 188 extern const struct attribute_group *pci_bus_groups[]; 189 190 extern unsigned long pci_hotplug_io_size; 191 extern unsigned long pci_hotplug_mmio_size; 192 extern unsigned long pci_hotplug_mmio_pref_size; 193 extern unsigned long pci_hotplug_bus_size; 194 195 /** 196 * pci_match_one_device - Tell if a PCI device structure has a matching 197 * PCI device id structure 198 * @id: single PCI device id structure to match 199 * @dev: the PCI device structure to match against 200 * 201 * Returns the matching pci_device_id structure or %NULL if there is no match. 202 */ 203 static inline const struct pci_device_id * 204 pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev) 205 { 206 if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) && 207 (id->device == PCI_ANY_ID || id->device == dev->device) && 208 (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) && 209 (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) && 210 !((id->class ^ dev->class) & id->class_mask)) 211 return id; 212 return NULL; 213 } 214 215 /* PCI slot sysfs helper code */ 216 #define to_pci_slot(s) container_of(s, struct pci_slot, kobj) 217 218 extern struct kset *pci_slots_kset; 219 220 struct pci_slot_attribute { 221 struct attribute attr; 222 ssize_t (*show)(struct pci_slot *, char *); 223 ssize_t (*store)(struct pci_slot *, const char *, size_t); 224 }; 225 #define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr) 226 227 enum pci_bar_type { 228 pci_bar_unknown, /* Standard PCI BAR probe */ 229 pci_bar_io, /* An I/O port BAR */ 230 pci_bar_mem32, /* A 32-bit memory BAR */ 231 pci_bar_mem64, /* A 64-bit memory BAR */ 232 }; 233 234 struct device *pci_get_host_bridge_device(struct pci_dev *dev); 235 void pci_put_host_bridge_device(struct device *dev); 236 237 int pci_configure_extended_tags(struct pci_dev *dev, void *ign); 238 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, 239 int crs_timeout); 240 bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, 241 int crs_timeout); 242 int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int crs_timeout); 243 244 int pci_setup_device(struct pci_dev *dev); 245 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, 246 struct resource *res, unsigned int reg); 247 void pci_configure_ari(struct pci_dev *dev); 248 void __pci_bus_size_bridges(struct pci_bus *bus, 249 struct list_head *realloc_head); 250 void __pci_bus_assign_resources(const struct pci_bus *bus, 251 struct list_head *realloc_head, 252 struct list_head *fail_head); 253 bool pci_bus_clip_resource(struct pci_dev *dev, int idx); 254 255 void pci_reassigndev_resource_alignment(struct pci_dev *dev); 256 void pci_disable_bridge_window(struct pci_dev *dev); 257 struct pci_bus *pci_bus_get(struct pci_bus *bus); 258 void pci_bus_put(struct pci_bus *bus); 259 260 /* PCIe link information from Link Capabilities 2 */ 261 #define PCIE_LNKCAP2_SLS2SPEED(lnkcap2) \ 262 ((lnkcap2) & PCI_EXP_LNKCAP2_SLS_64_0GB ? PCIE_SPEED_64_0GT : \ 263 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_32_0GB ? PCIE_SPEED_32_0GT : \ 264 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_16_0GB ? PCIE_SPEED_16_0GT : \ 265 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_8_0GB ? PCIE_SPEED_8_0GT : \ 266 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_5_0GB ? PCIE_SPEED_5_0GT : \ 267 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_2_5GB ? PCIE_SPEED_2_5GT : \ 268 PCI_SPEED_UNKNOWN) 269 270 /* PCIe speed to Mb/s reduced by encoding overhead */ 271 #define PCIE_SPEED2MBS_ENC(speed) \ 272 ((speed) == PCIE_SPEED_64_0GT ? 64000*1/1 : \ 273 (speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \ 274 (speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \ 275 (speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \ 276 (speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \ 277 (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \ 278 0) 279 280 const char *pci_speed_string(enum pci_bus_speed speed); 281 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev); 282 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev); 283 u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed, 284 enum pcie_link_width *width); 285 void __pcie_print_link_status(struct pci_dev *dev, bool verbose); 286 void pcie_report_downtraining(struct pci_dev *dev); 287 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status); 288 289 /* Single Root I/O Virtualization */ 290 struct pci_sriov { 291 int pos; /* Capability position */ 292 int nres; /* Number of resources */ 293 u32 cap; /* SR-IOV Capabilities */ 294 u16 ctrl; /* SR-IOV Control */ 295 u16 total_VFs; /* Total VFs associated with the PF */ 296 u16 initial_VFs; /* Initial VFs associated with the PF */ 297 u16 num_VFs; /* Number of VFs available */ 298 u16 offset; /* First VF Routing ID offset */ 299 u16 stride; /* Following VF stride */ 300 u16 vf_device; /* VF device ID */ 301 u32 pgsz; /* Page size for BAR alignment */ 302 u8 link; /* Function Dependency Link */ 303 u8 max_VF_buses; /* Max buses consumed by VFs */ 304 u16 driver_max_VFs; /* Max num VFs driver supports */ 305 struct pci_dev *dev; /* Lowest numbered PF */ 306 struct pci_dev *self; /* This PF */ 307 u32 class; /* VF device */ 308 u8 hdr_type; /* VF header type */ 309 u16 subsystem_vendor; /* VF subsystem vendor */ 310 u16 subsystem_device; /* VF subsystem device */ 311 resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */ 312 bool drivers_autoprobe; /* Auto probing of VFs by driver */ 313 }; 314 315 #ifdef CONFIG_PCI_DOE 316 void pci_doe_init(struct pci_dev *pdev); 317 void pci_doe_destroy(struct pci_dev *pdev); 318 void pci_doe_disconnected(struct pci_dev *pdev); 319 #else 320 static inline void pci_doe_init(struct pci_dev *pdev) { } 321 static inline void pci_doe_destroy(struct pci_dev *pdev) { } 322 static inline void pci_doe_disconnected(struct pci_dev *pdev) { } 323 #endif 324 325 /** 326 * pci_dev_set_io_state - Set the new error state if possible. 327 * 328 * @dev: PCI device to set new error_state 329 * @new: the state we want dev to be in 330 * 331 * If the device is experiencing perm_failure, it has to remain in that state. 332 * Any other transition is allowed. 333 * 334 * Returns true if state has been changed to the requested state. 335 */ 336 static inline bool pci_dev_set_io_state(struct pci_dev *dev, 337 pci_channel_state_t new) 338 { 339 pci_channel_state_t old; 340 341 switch (new) { 342 case pci_channel_io_perm_failure: 343 xchg(&dev->error_state, pci_channel_io_perm_failure); 344 return true; 345 case pci_channel_io_frozen: 346 old = cmpxchg(&dev->error_state, pci_channel_io_normal, 347 pci_channel_io_frozen); 348 return old != pci_channel_io_perm_failure; 349 case pci_channel_io_normal: 350 old = cmpxchg(&dev->error_state, pci_channel_io_frozen, 351 pci_channel_io_normal); 352 return old != pci_channel_io_perm_failure; 353 default: 354 return false; 355 } 356 } 357 358 static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused) 359 { 360 pci_dev_set_io_state(dev, pci_channel_io_perm_failure); 361 pci_doe_disconnected(dev); 362 363 return 0; 364 } 365 366 /* pci_dev priv_flags */ 367 #define PCI_DEV_ADDED 0 368 #define PCI_DPC_RECOVERED 1 369 #define PCI_DPC_RECOVERING 2 370 371 static inline void pci_dev_assign_added(struct pci_dev *dev, bool added) 372 { 373 assign_bit(PCI_DEV_ADDED, &dev->priv_flags, added); 374 } 375 376 static inline bool pci_dev_is_added(const struct pci_dev *dev) 377 { 378 return test_bit(PCI_DEV_ADDED, &dev->priv_flags); 379 } 380 381 #ifdef CONFIG_PCIEAER 382 #include <linux/aer.h> 383 384 #define AER_MAX_MULTI_ERR_DEVICES 5 /* Not likely to have more */ 385 386 struct aer_err_info { 387 struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES]; 388 int error_dev_num; 389 390 unsigned int id:16; 391 392 unsigned int severity:2; /* 0:NONFATAL | 1:FATAL | 2:COR */ 393 unsigned int __pad1:5; 394 unsigned int multi_error_valid:1; 395 396 unsigned int first_error:5; 397 unsigned int __pad2:2; 398 unsigned int tlp_header_valid:1; 399 400 unsigned int status; /* COR/UNCOR Error Status */ 401 unsigned int mask; /* COR/UNCOR Error Mask */ 402 struct aer_header_log_regs tlp; /* TLP Header */ 403 }; 404 405 int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info); 406 void aer_print_error(struct pci_dev *dev, struct aer_err_info *info); 407 #endif /* CONFIG_PCIEAER */ 408 409 #ifdef CONFIG_PCIEPORTBUS 410 /* Cached RCEC Endpoint Association */ 411 struct rcec_ea { 412 u8 nextbusn; 413 u8 lastbusn; 414 u32 bitmap; 415 }; 416 #endif 417 418 #ifdef CONFIG_PCIE_DPC 419 void pci_save_dpc_state(struct pci_dev *dev); 420 void pci_restore_dpc_state(struct pci_dev *dev); 421 void pci_dpc_init(struct pci_dev *pdev); 422 void dpc_process_error(struct pci_dev *pdev); 423 pci_ers_result_t dpc_reset_link(struct pci_dev *pdev); 424 bool pci_dpc_recovered(struct pci_dev *pdev); 425 #else 426 static inline void pci_save_dpc_state(struct pci_dev *dev) { } 427 static inline void pci_restore_dpc_state(struct pci_dev *dev) { } 428 static inline void pci_dpc_init(struct pci_dev *pdev) { } 429 static inline bool pci_dpc_recovered(struct pci_dev *pdev) { return false; } 430 #endif 431 432 #ifdef CONFIG_PCIEPORTBUS 433 void pci_rcec_init(struct pci_dev *dev); 434 void pci_rcec_exit(struct pci_dev *dev); 435 void pcie_link_rcec(struct pci_dev *rcec); 436 void pcie_walk_rcec(struct pci_dev *rcec, 437 int (*cb)(struct pci_dev *, void *), 438 void *userdata); 439 #else 440 static inline void pci_rcec_init(struct pci_dev *dev) { } 441 static inline void pci_rcec_exit(struct pci_dev *dev) { } 442 static inline void pcie_link_rcec(struct pci_dev *rcec) { } 443 static inline void pcie_walk_rcec(struct pci_dev *rcec, 444 int (*cb)(struct pci_dev *, void *), 445 void *userdata) { } 446 #endif 447 448 #ifdef CONFIG_PCI_ATS 449 /* Address Translation Service */ 450 void pci_ats_init(struct pci_dev *dev); 451 void pci_restore_ats_state(struct pci_dev *dev); 452 #else 453 static inline void pci_ats_init(struct pci_dev *d) { } 454 static inline void pci_restore_ats_state(struct pci_dev *dev) { } 455 #endif /* CONFIG_PCI_ATS */ 456 457 #ifdef CONFIG_PCI_PRI 458 void pci_pri_init(struct pci_dev *dev); 459 void pci_restore_pri_state(struct pci_dev *pdev); 460 #else 461 static inline void pci_pri_init(struct pci_dev *dev) { } 462 static inline void pci_restore_pri_state(struct pci_dev *pdev) { } 463 #endif 464 465 #ifdef CONFIG_PCI_PASID 466 void pci_pasid_init(struct pci_dev *dev); 467 void pci_restore_pasid_state(struct pci_dev *pdev); 468 #else 469 static inline void pci_pasid_init(struct pci_dev *dev) { } 470 static inline void pci_restore_pasid_state(struct pci_dev *pdev) { } 471 #endif 472 473 #ifdef CONFIG_PCI_IOV 474 int pci_iov_init(struct pci_dev *dev); 475 void pci_iov_release(struct pci_dev *dev); 476 void pci_iov_remove(struct pci_dev *dev); 477 void pci_iov_update_resource(struct pci_dev *dev, int resno); 478 resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno); 479 void pci_restore_iov_state(struct pci_dev *dev); 480 int pci_iov_bus_range(struct pci_bus *bus); 481 extern const struct attribute_group sriov_pf_dev_attr_group; 482 extern const struct attribute_group sriov_vf_dev_attr_group; 483 #else 484 static inline int pci_iov_init(struct pci_dev *dev) 485 { 486 return -ENODEV; 487 } 488 static inline void pci_iov_release(struct pci_dev *dev) { } 489 static inline void pci_iov_remove(struct pci_dev *dev) { } 490 static inline void pci_restore_iov_state(struct pci_dev *dev) { } 491 static inline int pci_iov_bus_range(struct pci_bus *bus) 492 { 493 return 0; 494 } 495 496 #endif /* CONFIG_PCI_IOV */ 497 498 #ifdef CONFIG_PCIE_PTM 499 void pci_ptm_init(struct pci_dev *dev); 500 void pci_save_ptm_state(struct pci_dev *dev); 501 void pci_restore_ptm_state(struct pci_dev *dev); 502 void pci_suspend_ptm(struct pci_dev *dev); 503 void pci_resume_ptm(struct pci_dev *dev); 504 #else 505 static inline void pci_ptm_init(struct pci_dev *dev) { } 506 static inline void pci_save_ptm_state(struct pci_dev *dev) { } 507 static inline void pci_restore_ptm_state(struct pci_dev *dev) { } 508 static inline void pci_suspend_ptm(struct pci_dev *dev) { } 509 static inline void pci_resume_ptm(struct pci_dev *dev) { } 510 #endif 511 512 unsigned long pci_cardbus_resource_alignment(struct resource *); 513 514 static inline resource_size_t pci_resource_alignment(struct pci_dev *dev, 515 struct resource *res) 516 { 517 #ifdef CONFIG_PCI_IOV 518 int resno = res - dev->resource; 519 520 if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END) 521 return pci_sriov_resource_alignment(dev, resno); 522 #endif 523 if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS) 524 return pci_cardbus_resource_alignment(res); 525 return resource_alignment(res); 526 } 527 528 void pci_acs_init(struct pci_dev *dev); 529 #ifdef CONFIG_PCI_QUIRKS 530 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags); 531 int pci_dev_specific_enable_acs(struct pci_dev *dev); 532 int pci_dev_specific_disable_acs_redir(struct pci_dev *dev); 533 bool pcie_failed_link_retrain(struct pci_dev *dev); 534 #else 535 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev, 536 u16 acs_flags) 537 { 538 return -ENOTTY; 539 } 540 static inline int pci_dev_specific_enable_acs(struct pci_dev *dev) 541 { 542 return -ENOTTY; 543 } 544 static inline int pci_dev_specific_disable_acs_redir(struct pci_dev *dev) 545 { 546 return -ENOTTY; 547 } 548 static inline bool pcie_failed_link_retrain(struct pci_dev *dev) 549 { 550 return false; 551 } 552 #endif 553 554 /* PCI error reporting and recovery */ 555 pci_ers_result_t pcie_do_recovery(struct pci_dev *dev, 556 pci_channel_state_t state, 557 pci_ers_result_t (*reset_subordinates)(struct pci_dev *pdev)); 558 559 bool pcie_wait_for_link(struct pci_dev *pdev, bool active); 560 int pcie_retrain_link(struct pci_dev *pdev, bool use_lt); 561 #ifdef CONFIG_PCIEASPM 562 void pcie_aspm_init_link_state(struct pci_dev *pdev); 563 void pcie_aspm_exit_link_state(struct pci_dev *pdev); 564 void pcie_aspm_pm_state_change(struct pci_dev *pdev, bool locked); 565 void pcie_aspm_powersave_config_link(struct pci_dev *pdev); 566 #else 567 static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { } 568 static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { } 569 static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev, bool locked) { } 570 static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { } 571 #endif 572 573 #ifdef CONFIG_PCIE_ECRC 574 void pcie_set_ecrc_checking(struct pci_dev *dev); 575 void pcie_ecrc_get_policy(char *str); 576 #else 577 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { } 578 static inline void pcie_ecrc_get_policy(char *str) { } 579 #endif 580 581 struct pci_dev_reset_methods { 582 u16 vendor; 583 u16 device; 584 int (*reset)(struct pci_dev *dev, bool probe); 585 }; 586 587 struct pci_reset_fn_method { 588 int (*reset_fn)(struct pci_dev *pdev, bool probe); 589 char *name; 590 }; 591 592 #ifdef CONFIG_PCI_QUIRKS 593 int pci_dev_specific_reset(struct pci_dev *dev, bool probe); 594 #else 595 static inline int pci_dev_specific_reset(struct pci_dev *dev, bool probe) 596 { 597 return -ENOTTY; 598 } 599 #endif 600 601 #if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64) 602 int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment, 603 struct resource *res); 604 #else 605 static inline int acpi_get_rc_resources(struct device *dev, const char *hid, 606 u16 segment, struct resource *res) 607 { 608 return -ENODEV; 609 } 610 #endif 611 612 int pci_rebar_get_current_size(struct pci_dev *pdev, int bar); 613 int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size); 614 static inline u64 pci_rebar_size_to_bytes(int size) 615 { 616 return 1ULL << (size + 20); 617 } 618 619 struct device_node; 620 621 #ifdef CONFIG_OF 622 int of_pci_parse_bus_range(struct device_node *node, struct resource *res); 623 int of_get_pci_domain_nr(struct device_node *node); 624 int of_pci_get_max_link_speed(struct device_node *node); 625 u32 of_pci_get_slot_power_limit(struct device_node *node, 626 u8 *slot_power_limit_value, 627 u8 *slot_power_limit_scale); 628 int pci_set_of_node(struct pci_dev *dev); 629 void pci_release_of_node(struct pci_dev *dev); 630 void pci_set_bus_of_node(struct pci_bus *bus); 631 void pci_release_bus_of_node(struct pci_bus *bus); 632 633 int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge); 634 635 #else 636 static inline int 637 of_pci_parse_bus_range(struct device_node *node, struct resource *res) 638 { 639 return -EINVAL; 640 } 641 642 static inline int 643 of_get_pci_domain_nr(struct device_node *node) 644 { 645 return -1; 646 } 647 648 static inline int 649 of_pci_get_max_link_speed(struct device_node *node) 650 { 651 return -EINVAL; 652 } 653 654 static inline u32 655 of_pci_get_slot_power_limit(struct device_node *node, 656 u8 *slot_power_limit_value, 657 u8 *slot_power_limit_scale) 658 { 659 if (slot_power_limit_value) 660 *slot_power_limit_value = 0; 661 if (slot_power_limit_scale) 662 *slot_power_limit_scale = 0; 663 return 0; 664 } 665 666 static inline int pci_set_of_node(struct pci_dev *dev) { return 0; } 667 static inline void pci_release_of_node(struct pci_dev *dev) { } 668 static inline void pci_set_bus_of_node(struct pci_bus *bus) { } 669 static inline void pci_release_bus_of_node(struct pci_bus *bus) { } 670 671 static inline int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge) 672 { 673 return 0; 674 } 675 676 #endif /* CONFIG_OF */ 677 678 struct of_changeset; 679 680 #ifdef CONFIG_PCI_DYNAMIC_OF_NODES 681 void of_pci_make_dev_node(struct pci_dev *pdev); 682 void of_pci_remove_node(struct pci_dev *pdev); 683 int of_pci_add_properties(struct pci_dev *pdev, struct of_changeset *ocs, 684 struct device_node *np); 685 #else 686 static inline void of_pci_make_dev_node(struct pci_dev *pdev) { } 687 static inline void of_pci_remove_node(struct pci_dev *pdev) { } 688 #endif 689 690 #ifdef CONFIG_PCIEAER 691 void pci_no_aer(void); 692 void pci_aer_init(struct pci_dev *dev); 693 void pci_aer_exit(struct pci_dev *dev); 694 extern const struct attribute_group aer_stats_attr_group; 695 void pci_aer_clear_fatal_status(struct pci_dev *dev); 696 int pci_aer_clear_status(struct pci_dev *dev); 697 int pci_aer_raw_clear_status(struct pci_dev *dev); 698 void pci_save_aer_state(struct pci_dev *dev); 699 void pci_restore_aer_state(struct pci_dev *dev); 700 #else 701 static inline void pci_no_aer(void) { } 702 static inline void pci_aer_init(struct pci_dev *d) { } 703 static inline void pci_aer_exit(struct pci_dev *d) { } 704 static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { } 705 static inline int pci_aer_clear_status(struct pci_dev *dev) { return -EINVAL; } 706 static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -EINVAL; } 707 static inline void pci_save_aer_state(struct pci_dev *dev) { } 708 static inline void pci_restore_aer_state(struct pci_dev *dev) { } 709 #endif 710 711 #ifdef CONFIG_ACPI 712 int pci_acpi_program_hp_params(struct pci_dev *dev); 713 extern const struct attribute_group pci_dev_acpi_attr_group; 714 void pci_set_acpi_fwnode(struct pci_dev *dev); 715 int pci_dev_acpi_reset(struct pci_dev *dev, bool probe); 716 bool acpi_pci_power_manageable(struct pci_dev *dev); 717 bool acpi_pci_bridge_d3(struct pci_dev *dev); 718 int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state); 719 pci_power_t acpi_pci_get_power_state(struct pci_dev *dev); 720 void acpi_pci_refresh_power_state(struct pci_dev *dev); 721 int acpi_pci_wakeup(struct pci_dev *dev, bool enable); 722 bool acpi_pci_need_resume(struct pci_dev *dev); 723 pci_power_t acpi_pci_choose_state(struct pci_dev *pdev); 724 #else 725 static inline int pci_dev_acpi_reset(struct pci_dev *dev, bool probe) 726 { 727 return -ENOTTY; 728 } 729 static inline void pci_set_acpi_fwnode(struct pci_dev *dev) { } 730 static inline int pci_acpi_program_hp_params(struct pci_dev *dev) 731 { 732 return -ENODEV; 733 } 734 static inline bool acpi_pci_power_manageable(struct pci_dev *dev) 735 { 736 return false; 737 } 738 static inline bool acpi_pci_bridge_d3(struct pci_dev *dev) 739 { 740 return false; 741 } 742 static inline int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state) 743 { 744 return -ENODEV; 745 } 746 static inline pci_power_t acpi_pci_get_power_state(struct pci_dev *dev) 747 { 748 return PCI_UNKNOWN; 749 } 750 static inline void acpi_pci_refresh_power_state(struct pci_dev *dev) { } 751 static inline int acpi_pci_wakeup(struct pci_dev *dev, bool enable) 752 { 753 return -ENODEV; 754 } 755 static inline bool acpi_pci_need_resume(struct pci_dev *dev) 756 { 757 return false; 758 } 759 static inline pci_power_t acpi_pci_choose_state(struct pci_dev *pdev) 760 { 761 return PCI_POWER_ERROR; 762 } 763 #endif 764 765 #ifdef CONFIG_PCIEASPM 766 extern const struct attribute_group aspm_ctrl_attr_group; 767 #endif 768 769 extern const struct attribute_group pci_dev_reset_method_attr_group; 770 771 #ifdef CONFIG_X86_INTEL_MID 772 bool pci_use_mid_pm(void); 773 int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state); 774 pci_power_t mid_pci_get_power_state(struct pci_dev *pdev); 775 #else 776 static inline bool pci_use_mid_pm(void) 777 { 778 return false; 779 } 780 static inline int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state) 781 { 782 return -ENODEV; 783 } 784 static inline pci_power_t mid_pci_get_power_state(struct pci_dev *pdev) 785 { 786 return PCI_UNKNOWN; 787 } 788 #endif 789 790 /* 791 * Config Address for PCI Configuration Mechanism #1 792 * 793 * See PCI Local Bus Specification, Revision 3.0, 794 * Section 3.2.2.3.2, Figure 3-2, p. 50. 795 */ 796 797 #define PCI_CONF1_BUS_SHIFT 16 /* Bus number */ 798 #define PCI_CONF1_DEV_SHIFT 11 /* Device number */ 799 #define PCI_CONF1_FUNC_SHIFT 8 /* Function number */ 800 801 #define PCI_CONF1_BUS_MASK 0xff 802 #define PCI_CONF1_DEV_MASK 0x1f 803 #define PCI_CONF1_FUNC_MASK 0x7 804 #define PCI_CONF1_REG_MASK 0xfc /* Limit aligned offset to a maximum of 256B */ 805 806 #define PCI_CONF1_ENABLE BIT(31) 807 #define PCI_CONF1_BUS(x) (((x) & PCI_CONF1_BUS_MASK) << PCI_CONF1_BUS_SHIFT) 808 #define PCI_CONF1_DEV(x) (((x) & PCI_CONF1_DEV_MASK) << PCI_CONF1_DEV_SHIFT) 809 #define PCI_CONF1_FUNC(x) (((x) & PCI_CONF1_FUNC_MASK) << PCI_CONF1_FUNC_SHIFT) 810 #define PCI_CONF1_REG(x) ((x) & PCI_CONF1_REG_MASK) 811 812 #define PCI_CONF1_ADDRESS(bus, dev, func, reg) \ 813 (PCI_CONF1_ENABLE | \ 814 PCI_CONF1_BUS(bus) | \ 815 PCI_CONF1_DEV(dev) | \ 816 PCI_CONF1_FUNC(func) | \ 817 PCI_CONF1_REG(reg)) 818 819 /* 820 * Extension of PCI Config Address for accessing extended PCIe registers 821 * 822 * No standardized specification, but used on lot of non-ECAM-compliant ARM SoCs 823 * or on AMD Barcelona and new CPUs. Reserved bits [27:24] of PCI Config Address 824 * are used for specifying additional 4 high bits of PCI Express register. 825 */ 826 827 #define PCI_CONF1_EXT_REG_SHIFT 16 828 #define PCI_CONF1_EXT_REG_MASK 0xf00 829 #define PCI_CONF1_EXT_REG(x) (((x) & PCI_CONF1_EXT_REG_MASK) << PCI_CONF1_EXT_REG_SHIFT) 830 831 #define PCI_CONF1_EXT_ADDRESS(bus, dev, func, reg) \ 832 (PCI_CONF1_ADDRESS(bus, dev, func, reg) | \ 833 PCI_CONF1_EXT_REG(reg)) 834 835 #endif /* DRIVERS_PCI_H */ 836