1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef DRIVERS_PCI_H 3 #define DRIVERS_PCI_H 4 5 #include <linux/pci.h> 6 7 /* Number of possible devfns: 0.0 to 1f.7 inclusive */ 8 #define MAX_NR_DEVFNS 256 9 10 #define PCI_FIND_CAP_TTL 48 11 12 #define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */ 13 14 #define PCIE_LINK_RETRAIN_TIMEOUT_MS 1000 15 16 /* Power stable to PERST# inactive from PCIe card Electromechanical Spec */ 17 #define PCIE_T_PVPERL_MS 100 18 19 /* 20 * PCIe r6.0, sec 5.3.3.2.1 <PME Synchronization> 21 * Recommends 1ms to 10ms timeout to check L2 ready. 22 */ 23 #define PCIE_PME_TO_L2_TIMEOUT_US 10000 24 25 extern const unsigned char pcie_link_speed[]; 26 extern bool pci_early_dump; 27 28 bool pcie_cap_has_lnkctl(const struct pci_dev *dev); 29 bool pcie_cap_has_lnkctl2(const struct pci_dev *dev); 30 bool pcie_cap_has_rtctl(const struct pci_dev *dev); 31 32 /* Functions internal to the PCI core code */ 33 34 int pci_create_sysfs_dev_files(struct pci_dev *pdev); 35 void pci_remove_sysfs_dev_files(struct pci_dev *pdev); 36 void pci_cleanup_rom(struct pci_dev *dev); 37 #ifdef CONFIG_DMI 38 extern const struct attribute_group pci_dev_smbios_attr_group; 39 #endif 40 41 enum pci_mmap_api { 42 PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */ 43 PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */ 44 }; 45 int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai, 46 enum pci_mmap_api mmap_api); 47 48 bool pci_reset_supported(struct pci_dev *dev); 49 void pci_init_reset_methods(struct pci_dev *dev); 50 int pci_bridge_secondary_bus_reset(struct pci_dev *dev); 51 int pci_bus_error_reset(struct pci_dev *dev); 52 int __pci_reset_bus(struct pci_bus *bus); 53 54 struct pci_cap_saved_data { 55 u16 cap_nr; 56 bool cap_extended; 57 unsigned int size; 58 u32 data[]; 59 }; 60 61 struct pci_cap_saved_state { 62 struct hlist_node next; 63 struct pci_cap_saved_data cap; 64 }; 65 66 void pci_allocate_cap_save_buffers(struct pci_dev *dev); 67 void pci_free_cap_save_buffers(struct pci_dev *dev); 68 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size); 69 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, 70 u16 cap, unsigned int size); 71 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap); 72 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, 73 u16 cap); 74 75 #define PCI_PM_D2_DELAY 200 /* usec; see PCIe r4.0, sec 5.9.1 */ 76 #define PCI_PM_D3HOT_WAIT 10 /* msec */ 77 #define PCI_PM_D3COLD_WAIT 100 /* msec */ 78 79 void pci_update_current_state(struct pci_dev *dev, pci_power_t state); 80 void pci_refresh_power_state(struct pci_dev *dev); 81 int pci_power_up(struct pci_dev *dev); 82 void pci_disable_enabled_device(struct pci_dev *dev); 83 int pci_finish_runtime_suspend(struct pci_dev *dev); 84 void pcie_clear_device_status(struct pci_dev *dev); 85 void pcie_clear_root_pme_status(struct pci_dev *dev); 86 bool pci_check_pme_status(struct pci_dev *dev); 87 void pci_pme_wakeup_bus(struct pci_bus *bus); 88 int __pci_pme_wakeup(struct pci_dev *dev, void *ign); 89 void pci_pme_restore(struct pci_dev *dev); 90 bool pci_dev_need_resume(struct pci_dev *dev); 91 void pci_dev_adjust_pme(struct pci_dev *dev); 92 void pci_dev_complete_resume(struct pci_dev *pci_dev); 93 void pci_config_pm_runtime_get(struct pci_dev *dev); 94 void pci_config_pm_runtime_put(struct pci_dev *dev); 95 void pci_pm_init(struct pci_dev *dev); 96 void pci_ea_init(struct pci_dev *dev); 97 void pci_msi_init(struct pci_dev *dev); 98 void pci_msix_init(struct pci_dev *dev); 99 bool pci_bridge_d3_possible(struct pci_dev *dev); 100 void pci_bridge_d3_update(struct pci_dev *dev); 101 void pci_bridge_reconfigure_ltr(struct pci_dev *dev); 102 int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type); 103 104 static inline void pci_wakeup_event(struct pci_dev *dev) 105 { 106 /* Wait 100 ms before the system can be put into a sleep state. */ 107 pm_wakeup_event(&dev->dev, 100); 108 } 109 110 static inline bool pci_has_subordinate(struct pci_dev *pci_dev) 111 { 112 return !!(pci_dev->subordinate); 113 } 114 115 static inline bool pci_power_manageable(struct pci_dev *pci_dev) 116 { 117 /* 118 * Currently we allow normal PCI devices and PCI bridges transition 119 * into D3 if their bridge_d3 is set. 120 */ 121 return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3; 122 } 123 124 static inline bool pcie_downstream_port(const struct pci_dev *dev) 125 { 126 int type = pci_pcie_type(dev); 127 128 return type == PCI_EXP_TYPE_ROOT_PORT || 129 type == PCI_EXP_TYPE_DOWNSTREAM || 130 type == PCI_EXP_TYPE_PCIE_BRIDGE; 131 } 132 133 void pci_vpd_init(struct pci_dev *dev); 134 void pci_vpd_release(struct pci_dev *dev); 135 extern const struct attribute_group pci_dev_vpd_attr_group; 136 137 /* PCI Virtual Channel */ 138 int pci_save_vc_state(struct pci_dev *dev); 139 void pci_restore_vc_state(struct pci_dev *dev); 140 void pci_allocate_vc_save_buffers(struct pci_dev *dev); 141 142 /* PCI /proc functions */ 143 #ifdef CONFIG_PROC_FS 144 int pci_proc_attach_device(struct pci_dev *dev); 145 int pci_proc_detach_device(struct pci_dev *dev); 146 int pci_proc_detach_bus(struct pci_bus *bus); 147 #else 148 static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; } 149 static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; } 150 static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; } 151 #endif 152 153 /* Functions for PCI Hotplug drivers to use */ 154 int pci_hp_add_bridge(struct pci_dev *dev); 155 156 #ifdef HAVE_PCI_LEGACY 157 void pci_create_legacy_files(struct pci_bus *bus); 158 void pci_remove_legacy_files(struct pci_bus *bus); 159 #else 160 static inline void pci_create_legacy_files(struct pci_bus *bus) { } 161 static inline void pci_remove_legacy_files(struct pci_bus *bus) { } 162 #endif 163 164 /* Lock for read/write access to pci device and bus lists */ 165 extern struct rw_semaphore pci_bus_sem; 166 extern struct mutex pci_slot_mutex; 167 168 extern raw_spinlock_t pci_lock; 169 170 extern unsigned int pci_pm_d3hot_delay; 171 172 #ifdef CONFIG_PCI_MSI 173 void pci_no_msi(void); 174 #else 175 static inline void pci_no_msi(void) { } 176 #endif 177 178 void pci_realloc_get_opt(char *); 179 180 static inline int pci_no_d1d2(struct pci_dev *dev) 181 { 182 unsigned int parent_dstates = 0; 183 184 if (dev->bus->self) 185 parent_dstates = dev->bus->self->no_d1d2; 186 return (dev->no_d1d2 || parent_dstates); 187 188 } 189 extern const struct attribute_group *pci_dev_groups[]; 190 extern const struct attribute_group *pcibus_groups[]; 191 extern const struct device_type pci_dev_type; 192 extern const struct attribute_group *pci_bus_groups[]; 193 194 extern unsigned long pci_hotplug_io_size; 195 extern unsigned long pci_hotplug_mmio_size; 196 extern unsigned long pci_hotplug_mmio_pref_size; 197 extern unsigned long pci_hotplug_bus_size; 198 199 /** 200 * pci_match_one_device - Tell if a PCI device structure has a matching 201 * PCI device id structure 202 * @id: single PCI device id structure to match 203 * @dev: the PCI device structure to match against 204 * 205 * Returns the matching pci_device_id structure or %NULL if there is no match. 206 */ 207 static inline const struct pci_device_id * 208 pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev) 209 { 210 if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) && 211 (id->device == PCI_ANY_ID || id->device == dev->device) && 212 (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) && 213 (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) && 214 !((id->class ^ dev->class) & id->class_mask)) 215 return id; 216 return NULL; 217 } 218 219 /* PCI slot sysfs helper code */ 220 #define to_pci_slot(s) container_of(s, struct pci_slot, kobj) 221 222 extern struct kset *pci_slots_kset; 223 224 struct pci_slot_attribute { 225 struct attribute attr; 226 ssize_t (*show)(struct pci_slot *, char *); 227 ssize_t (*store)(struct pci_slot *, const char *, size_t); 228 }; 229 #define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr) 230 231 enum pci_bar_type { 232 pci_bar_unknown, /* Standard PCI BAR probe */ 233 pci_bar_io, /* An I/O port BAR */ 234 pci_bar_mem32, /* A 32-bit memory BAR */ 235 pci_bar_mem64, /* A 64-bit memory BAR */ 236 }; 237 238 struct device *pci_get_host_bridge_device(struct pci_dev *dev); 239 void pci_put_host_bridge_device(struct device *dev); 240 241 int pci_configure_extended_tags(struct pci_dev *dev, void *ign); 242 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, 243 int crs_timeout); 244 bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, 245 int crs_timeout); 246 int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int crs_timeout); 247 248 int pci_setup_device(struct pci_dev *dev); 249 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, 250 struct resource *res, unsigned int reg); 251 void pci_configure_ari(struct pci_dev *dev); 252 void __pci_bus_size_bridges(struct pci_bus *bus, 253 struct list_head *realloc_head); 254 void __pci_bus_assign_resources(const struct pci_bus *bus, 255 struct list_head *realloc_head, 256 struct list_head *fail_head); 257 bool pci_bus_clip_resource(struct pci_dev *dev, int idx); 258 259 void pci_reassigndev_resource_alignment(struct pci_dev *dev); 260 void pci_disable_bridge_window(struct pci_dev *dev); 261 struct pci_bus *pci_bus_get(struct pci_bus *bus); 262 void pci_bus_put(struct pci_bus *bus); 263 264 /* PCIe link information from Link Capabilities 2 */ 265 #define PCIE_LNKCAP2_SLS2SPEED(lnkcap2) \ 266 ((lnkcap2) & PCI_EXP_LNKCAP2_SLS_64_0GB ? PCIE_SPEED_64_0GT : \ 267 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_32_0GB ? PCIE_SPEED_32_0GT : \ 268 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_16_0GB ? PCIE_SPEED_16_0GT : \ 269 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_8_0GB ? PCIE_SPEED_8_0GT : \ 270 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_5_0GB ? PCIE_SPEED_5_0GT : \ 271 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_2_5GB ? PCIE_SPEED_2_5GT : \ 272 PCI_SPEED_UNKNOWN) 273 274 /* PCIe speed to Mb/s reduced by encoding overhead */ 275 #define PCIE_SPEED2MBS_ENC(speed) \ 276 ((speed) == PCIE_SPEED_64_0GT ? 64000*1/1 : \ 277 (speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \ 278 (speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \ 279 (speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \ 280 (speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \ 281 (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \ 282 0) 283 284 const char *pci_speed_string(enum pci_bus_speed speed); 285 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev); 286 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev); 287 u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed, 288 enum pcie_link_width *width); 289 void __pcie_print_link_status(struct pci_dev *dev, bool verbose); 290 void pcie_report_downtraining(struct pci_dev *dev); 291 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status); 292 293 /* Single Root I/O Virtualization */ 294 struct pci_sriov { 295 int pos; /* Capability position */ 296 int nres; /* Number of resources */ 297 u32 cap; /* SR-IOV Capabilities */ 298 u16 ctrl; /* SR-IOV Control */ 299 u16 total_VFs; /* Total VFs associated with the PF */ 300 u16 initial_VFs; /* Initial VFs associated with the PF */ 301 u16 num_VFs; /* Number of VFs available */ 302 u16 offset; /* First VF Routing ID offset */ 303 u16 stride; /* Following VF stride */ 304 u16 vf_device; /* VF device ID */ 305 u32 pgsz; /* Page size for BAR alignment */ 306 u8 link; /* Function Dependency Link */ 307 u8 max_VF_buses; /* Max buses consumed by VFs */ 308 u16 driver_max_VFs; /* Max num VFs driver supports */ 309 struct pci_dev *dev; /* Lowest numbered PF */ 310 struct pci_dev *self; /* This PF */ 311 u32 class; /* VF device */ 312 u8 hdr_type; /* VF header type */ 313 u16 subsystem_vendor; /* VF subsystem vendor */ 314 u16 subsystem_device; /* VF subsystem device */ 315 resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */ 316 bool drivers_autoprobe; /* Auto probing of VFs by driver */ 317 }; 318 319 #ifdef CONFIG_PCI_DOE 320 void pci_doe_init(struct pci_dev *pdev); 321 void pci_doe_destroy(struct pci_dev *pdev); 322 void pci_doe_disconnected(struct pci_dev *pdev); 323 #else 324 static inline void pci_doe_init(struct pci_dev *pdev) { } 325 static inline void pci_doe_destroy(struct pci_dev *pdev) { } 326 static inline void pci_doe_disconnected(struct pci_dev *pdev) { } 327 #endif 328 329 /** 330 * pci_dev_set_io_state - Set the new error state if possible. 331 * 332 * @dev: PCI device to set new error_state 333 * @new: the state we want dev to be in 334 * 335 * If the device is experiencing perm_failure, it has to remain in that state. 336 * Any other transition is allowed. 337 * 338 * Returns true if state has been changed to the requested state. 339 */ 340 static inline bool pci_dev_set_io_state(struct pci_dev *dev, 341 pci_channel_state_t new) 342 { 343 pci_channel_state_t old; 344 345 switch (new) { 346 case pci_channel_io_perm_failure: 347 xchg(&dev->error_state, pci_channel_io_perm_failure); 348 return true; 349 case pci_channel_io_frozen: 350 old = cmpxchg(&dev->error_state, pci_channel_io_normal, 351 pci_channel_io_frozen); 352 return old != pci_channel_io_perm_failure; 353 case pci_channel_io_normal: 354 old = cmpxchg(&dev->error_state, pci_channel_io_frozen, 355 pci_channel_io_normal); 356 return old != pci_channel_io_perm_failure; 357 default: 358 return false; 359 } 360 } 361 362 static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused) 363 { 364 pci_dev_set_io_state(dev, pci_channel_io_perm_failure); 365 pci_doe_disconnected(dev); 366 367 return 0; 368 } 369 370 /* pci_dev priv_flags */ 371 #define PCI_DEV_ADDED 0 372 #define PCI_DPC_RECOVERED 1 373 #define PCI_DPC_RECOVERING 2 374 375 static inline void pci_dev_assign_added(struct pci_dev *dev, bool added) 376 { 377 assign_bit(PCI_DEV_ADDED, &dev->priv_flags, added); 378 } 379 380 static inline bool pci_dev_is_added(const struct pci_dev *dev) 381 { 382 return test_bit(PCI_DEV_ADDED, &dev->priv_flags); 383 } 384 385 #ifdef CONFIG_PCIEAER 386 #include <linux/aer.h> 387 388 #define AER_MAX_MULTI_ERR_DEVICES 5 /* Not likely to have more */ 389 390 struct aer_err_info { 391 struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES]; 392 int error_dev_num; 393 394 unsigned int id:16; 395 396 unsigned int severity:2; /* 0:NONFATAL | 1:FATAL | 2:COR */ 397 unsigned int __pad1:5; 398 unsigned int multi_error_valid:1; 399 400 unsigned int first_error:5; 401 unsigned int __pad2:2; 402 unsigned int tlp_header_valid:1; 403 404 unsigned int status; /* COR/UNCOR Error Status */ 405 unsigned int mask; /* COR/UNCOR Error Mask */ 406 struct aer_header_log_regs tlp; /* TLP Header */ 407 }; 408 409 int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info); 410 void aer_print_error(struct pci_dev *dev, struct aer_err_info *info); 411 #endif /* CONFIG_PCIEAER */ 412 413 #ifdef CONFIG_PCIEPORTBUS 414 /* Cached RCEC Endpoint Association */ 415 struct rcec_ea { 416 u8 nextbusn; 417 u8 lastbusn; 418 u32 bitmap; 419 }; 420 #endif 421 422 #ifdef CONFIG_PCIE_DPC 423 void pci_save_dpc_state(struct pci_dev *dev); 424 void pci_restore_dpc_state(struct pci_dev *dev); 425 void pci_dpc_init(struct pci_dev *pdev); 426 void dpc_process_error(struct pci_dev *pdev); 427 pci_ers_result_t dpc_reset_link(struct pci_dev *pdev); 428 bool pci_dpc_recovered(struct pci_dev *pdev); 429 #else 430 static inline void pci_save_dpc_state(struct pci_dev *dev) { } 431 static inline void pci_restore_dpc_state(struct pci_dev *dev) { } 432 static inline void pci_dpc_init(struct pci_dev *pdev) { } 433 static inline bool pci_dpc_recovered(struct pci_dev *pdev) { return false; } 434 #endif 435 436 #ifdef CONFIG_PCIEPORTBUS 437 void pci_rcec_init(struct pci_dev *dev); 438 void pci_rcec_exit(struct pci_dev *dev); 439 void pcie_link_rcec(struct pci_dev *rcec); 440 void pcie_walk_rcec(struct pci_dev *rcec, 441 int (*cb)(struct pci_dev *, void *), 442 void *userdata); 443 #else 444 static inline void pci_rcec_init(struct pci_dev *dev) { } 445 static inline void pci_rcec_exit(struct pci_dev *dev) { } 446 static inline void pcie_link_rcec(struct pci_dev *rcec) { } 447 static inline void pcie_walk_rcec(struct pci_dev *rcec, 448 int (*cb)(struct pci_dev *, void *), 449 void *userdata) { } 450 #endif 451 452 #ifdef CONFIG_PCI_ATS 453 /* Address Translation Service */ 454 void pci_ats_init(struct pci_dev *dev); 455 void pci_restore_ats_state(struct pci_dev *dev); 456 #else 457 static inline void pci_ats_init(struct pci_dev *d) { } 458 static inline void pci_restore_ats_state(struct pci_dev *dev) { } 459 #endif /* CONFIG_PCI_ATS */ 460 461 #ifdef CONFIG_PCI_PRI 462 void pci_pri_init(struct pci_dev *dev); 463 void pci_restore_pri_state(struct pci_dev *pdev); 464 #else 465 static inline void pci_pri_init(struct pci_dev *dev) { } 466 static inline void pci_restore_pri_state(struct pci_dev *pdev) { } 467 #endif 468 469 #ifdef CONFIG_PCI_PASID 470 void pci_pasid_init(struct pci_dev *dev); 471 void pci_restore_pasid_state(struct pci_dev *pdev); 472 #else 473 static inline void pci_pasid_init(struct pci_dev *dev) { } 474 static inline void pci_restore_pasid_state(struct pci_dev *pdev) { } 475 #endif 476 477 #ifdef CONFIG_PCI_IOV 478 int pci_iov_init(struct pci_dev *dev); 479 void pci_iov_release(struct pci_dev *dev); 480 void pci_iov_remove(struct pci_dev *dev); 481 void pci_iov_update_resource(struct pci_dev *dev, int resno); 482 resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno); 483 void pci_restore_iov_state(struct pci_dev *dev); 484 int pci_iov_bus_range(struct pci_bus *bus); 485 extern const struct attribute_group sriov_pf_dev_attr_group; 486 extern const struct attribute_group sriov_vf_dev_attr_group; 487 #else 488 static inline int pci_iov_init(struct pci_dev *dev) 489 { 490 return -ENODEV; 491 } 492 static inline void pci_iov_release(struct pci_dev *dev) { } 493 static inline void pci_iov_remove(struct pci_dev *dev) { } 494 static inline void pci_restore_iov_state(struct pci_dev *dev) { } 495 static inline int pci_iov_bus_range(struct pci_bus *bus) 496 { 497 return 0; 498 } 499 500 #endif /* CONFIG_PCI_IOV */ 501 502 #ifdef CONFIG_PCIE_PTM 503 void pci_ptm_init(struct pci_dev *dev); 504 void pci_save_ptm_state(struct pci_dev *dev); 505 void pci_restore_ptm_state(struct pci_dev *dev); 506 void pci_suspend_ptm(struct pci_dev *dev); 507 void pci_resume_ptm(struct pci_dev *dev); 508 #else 509 static inline void pci_ptm_init(struct pci_dev *dev) { } 510 static inline void pci_save_ptm_state(struct pci_dev *dev) { } 511 static inline void pci_restore_ptm_state(struct pci_dev *dev) { } 512 static inline void pci_suspend_ptm(struct pci_dev *dev) { } 513 static inline void pci_resume_ptm(struct pci_dev *dev) { } 514 #endif 515 516 unsigned long pci_cardbus_resource_alignment(struct resource *); 517 518 static inline resource_size_t pci_resource_alignment(struct pci_dev *dev, 519 struct resource *res) 520 { 521 #ifdef CONFIG_PCI_IOV 522 int resno = res - dev->resource; 523 524 if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END) 525 return pci_sriov_resource_alignment(dev, resno); 526 #endif 527 if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS) 528 return pci_cardbus_resource_alignment(res); 529 return resource_alignment(res); 530 } 531 532 void pci_acs_init(struct pci_dev *dev); 533 #ifdef CONFIG_PCI_QUIRKS 534 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags); 535 int pci_dev_specific_enable_acs(struct pci_dev *dev); 536 int pci_dev_specific_disable_acs_redir(struct pci_dev *dev); 537 int pcie_failed_link_retrain(struct pci_dev *dev); 538 #else 539 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev, 540 u16 acs_flags) 541 { 542 return -ENOTTY; 543 } 544 static inline int pci_dev_specific_enable_acs(struct pci_dev *dev) 545 { 546 return -ENOTTY; 547 } 548 static inline int pci_dev_specific_disable_acs_redir(struct pci_dev *dev) 549 { 550 return -ENOTTY; 551 } 552 static inline int pcie_failed_link_retrain(struct pci_dev *dev) 553 { 554 return -ENOTTY; 555 } 556 #endif 557 558 /* PCI error reporting and recovery */ 559 pci_ers_result_t pcie_do_recovery(struct pci_dev *dev, 560 pci_channel_state_t state, 561 pci_ers_result_t (*reset_subordinates)(struct pci_dev *pdev)); 562 563 bool pcie_wait_for_link(struct pci_dev *pdev, bool active); 564 int pcie_retrain_link(struct pci_dev *pdev, bool use_lt); 565 #ifdef CONFIG_PCIEASPM 566 void pcie_aspm_init_link_state(struct pci_dev *pdev); 567 void pcie_aspm_exit_link_state(struct pci_dev *pdev); 568 void pcie_aspm_pm_state_change(struct pci_dev *pdev, bool locked); 569 void pcie_aspm_powersave_config_link(struct pci_dev *pdev); 570 #else 571 static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { } 572 static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { } 573 static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev, bool locked) { } 574 static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { } 575 #endif 576 577 #ifdef CONFIG_PCIE_ECRC 578 void pcie_set_ecrc_checking(struct pci_dev *dev); 579 void pcie_ecrc_get_policy(char *str); 580 #else 581 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { } 582 static inline void pcie_ecrc_get_policy(char *str) { } 583 #endif 584 585 struct pci_dev_reset_methods { 586 u16 vendor; 587 u16 device; 588 int (*reset)(struct pci_dev *dev, bool probe); 589 }; 590 591 struct pci_reset_fn_method { 592 int (*reset_fn)(struct pci_dev *pdev, bool probe); 593 char *name; 594 }; 595 596 #ifdef CONFIG_PCI_QUIRKS 597 int pci_dev_specific_reset(struct pci_dev *dev, bool probe); 598 #else 599 static inline int pci_dev_specific_reset(struct pci_dev *dev, bool probe) 600 { 601 return -ENOTTY; 602 } 603 #endif 604 605 #if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64) 606 int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment, 607 struct resource *res); 608 #else 609 static inline int acpi_get_rc_resources(struct device *dev, const char *hid, 610 u16 segment, struct resource *res) 611 { 612 return -ENODEV; 613 } 614 #endif 615 616 int pci_rebar_get_current_size(struct pci_dev *pdev, int bar); 617 int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size); 618 static inline u64 pci_rebar_size_to_bytes(int size) 619 { 620 return 1ULL << (size + 20); 621 } 622 623 struct device_node; 624 625 #ifdef CONFIG_OF 626 int of_pci_parse_bus_range(struct device_node *node, struct resource *res); 627 int of_get_pci_domain_nr(struct device_node *node); 628 int of_pci_get_max_link_speed(struct device_node *node); 629 u32 of_pci_get_slot_power_limit(struct device_node *node, 630 u8 *slot_power_limit_value, 631 u8 *slot_power_limit_scale); 632 int pci_set_of_node(struct pci_dev *dev); 633 void pci_release_of_node(struct pci_dev *dev); 634 void pci_set_bus_of_node(struct pci_bus *bus); 635 void pci_release_bus_of_node(struct pci_bus *bus); 636 637 int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge); 638 639 #else 640 static inline int 641 of_pci_parse_bus_range(struct device_node *node, struct resource *res) 642 { 643 return -EINVAL; 644 } 645 646 static inline int 647 of_get_pci_domain_nr(struct device_node *node) 648 { 649 return -1; 650 } 651 652 static inline int 653 of_pci_get_max_link_speed(struct device_node *node) 654 { 655 return -EINVAL; 656 } 657 658 static inline u32 659 of_pci_get_slot_power_limit(struct device_node *node, 660 u8 *slot_power_limit_value, 661 u8 *slot_power_limit_scale) 662 { 663 if (slot_power_limit_value) 664 *slot_power_limit_value = 0; 665 if (slot_power_limit_scale) 666 *slot_power_limit_scale = 0; 667 return 0; 668 } 669 670 static inline int pci_set_of_node(struct pci_dev *dev) { return 0; } 671 static inline void pci_release_of_node(struct pci_dev *dev) { } 672 static inline void pci_set_bus_of_node(struct pci_bus *bus) { } 673 static inline void pci_release_bus_of_node(struct pci_bus *bus) { } 674 675 static inline int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge) 676 { 677 return 0; 678 } 679 680 #endif /* CONFIG_OF */ 681 682 struct of_changeset; 683 684 #ifdef CONFIG_PCI_DYNAMIC_OF_NODES 685 void of_pci_make_dev_node(struct pci_dev *pdev); 686 void of_pci_remove_node(struct pci_dev *pdev); 687 int of_pci_add_properties(struct pci_dev *pdev, struct of_changeset *ocs, 688 struct device_node *np); 689 #else 690 static inline void of_pci_make_dev_node(struct pci_dev *pdev) { } 691 static inline void of_pci_remove_node(struct pci_dev *pdev) { } 692 #endif 693 694 #ifdef CONFIG_PCIEAER 695 void pci_no_aer(void); 696 void pci_aer_init(struct pci_dev *dev); 697 void pci_aer_exit(struct pci_dev *dev); 698 extern const struct attribute_group aer_stats_attr_group; 699 void pci_aer_clear_fatal_status(struct pci_dev *dev); 700 int pci_aer_clear_status(struct pci_dev *dev); 701 int pci_aer_raw_clear_status(struct pci_dev *dev); 702 void pci_save_aer_state(struct pci_dev *dev); 703 void pci_restore_aer_state(struct pci_dev *dev); 704 #else 705 static inline void pci_no_aer(void) { } 706 static inline void pci_aer_init(struct pci_dev *d) { } 707 static inline void pci_aer_exit(struct pci_dev *d) { } 708 static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { } 709 static inline int pci_aer_clear_status(struct pci_dev *dev) { return -EINVAL; } 710 static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -EINVAL; } 711 static inline void pci_save_aer_state(struct pci_dev *dev) { } 712 static inline void pci_restore_aer_state(struct pci_dev *dev) { } 713 #endif 714 715 #ifdef CONFIG_ACPI 716 int pci_acpi_program_hp_params(struct pci_dev *dev); 717 extern const struct attribute_group pci_dev_acpi_attr_group; 718 void pci_set_acpi_fwnode(struct pci_dev *dev); 719 int pci_dev_acpi_reset(struct pci_dev *dev, bool probe); 720 bool acpi_pci_power_manageable(struct pci_dev *dev); 721 bool acpi_pci_bridge_d3(struct pci_dev *dev); 722 int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state); 723 pci_power_t acpi_pci_get_power_state(struct pci_dev *dev); 724 void acpi_pci_refresh_power_state(struct pci_dev *dev); 725 int acpi_pci_wakeup(struct pci_dev *dev, bool enable); 726 bool acpi_pci_need_resume(struct pci_dev *dev); 727 pci_power_t acpi_pci_choose_state(struct pci_dev *pdev); 728 #else 729 static inline int pci_dev_acpi_reset(struct pci_dev *dev, bool probe) 730 { 731 return -ENOTTY; 732 } 733 static inline void pci_set_acpi_fwnode(struct pci_dev *dev) { } 734 static inline int pci_acpi_program_hp_params(struct pci_dev *dev) 735 { 736 return -ENODEV; 737 } 738 static inline bool acpi_pci_power_manageable(struct pci_dev *dev) 739 { 740 return false; 741 } 742 static inline bool acpi_pci_bridge_d3(struct pci_dev *dev) 743 { 744 return false; 745 } 746 static inline int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state) 747 { 748 return -ENODEV; 749 } 750 static inline pci_power_t acpi_pci_get_power_state(struct pci_dev *dev) 751 { 752 return PCI_UNKNOWN; 753 } 754 static inline void acpi_pci_refresh_power_state(struct pci_dev *dev) { } 755 static inline int acpi_pci_wakeup(struct pci_dev *dev, bool enable) 756 { 757 return -ENODEV; 758 } 759 static inline bool acpi_pci_need_resume(struct pci_dev *dev) 760 { 761 return false; 762 } 763 static inline pci_power_t acpi_pci_choose_state(struct pci_dev *pdev) 764 { 765 return PCI_POWER_ERROR; 766 } 767 #endif 768 769 #ifdef CONFIG_PCIEASPM 770 extern const struct attribute_group aspm_ctrl_attr_group; 771 #endif 772 773 extern const struct attribute_group pci_dev_reset_method_attr_group; 774 775 #ifdef CONFIG_X86_INTEL_MID 776 bool pci_use_mid_pm(void); 777 int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state); 778 pci_power_t mid_pci_get_power_state(struct pci_dev *pdev); 779 #else 780 static inline bool pci_use_mid_pm(void) 781 { 782 return false; 783 } 784 static inline int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state) 785 { 786 return -ENODEV; 787 } 788 static inline pci_power_t mid_pci_get_power_state(struct pci_dev *pdev) 789 { 790 return PCI_UNKNOWN; 791 } 792 #endif 793 794 /* 795 * Config Address for PCI Configuration Mechanism #1 796 * 797 * See PCI Local Bus Specification, Revision 3.0, 798 * Section 3.2.2.3.2, Figure 3-2, p. 50. 799 */ 800 801 #define PCI_CONF1_BUS_SHIFT 16 /* Bus number */ 802 #define PCI_CONF1_DEV_SHIFT 11 /* Device number */ 803 #define PCI_CONF1_FUNC_SHIFT 8 /* Function number */ 804 805 #define PCI_CONF1_BUS_MASK 0xff 806 #define PCI_CONF1_DEV_MASK 0x1f 807 #define PCI_CONF1_FUNC_MASK 0x7 808 #define PCI_CONF1_REG_MASK 0xfc /* Limit aligned offset to a maximum of 256B */ 809 810 #define PCI_CONF1_ENABLE BIT(31) 811 #define PCI_CONF1_BUS(x) (((x) & PCI_CONF1_BUS_MASK) << PCI_CONF1_BUS_SHIFT) 812 #define PCI_CONF1_DEV(x) (((x) & PCI_CONF1_DEV_MASK) << PCI_CONF1_DEV_SHIFT) 813 #define PCI_CONF1_FUNC(x) (((x) & PCI_CONF1_FUNC_MASK) << PCI_CONF1_FUNC_SHIFT) 814 #define PCI_CONF1_REG(x) ((x) & PCI_CONF1_REG_MASK) 815 816 #define PCI_CONF1_ADDRESS(bus, dev, func, reg) \ 817 (PCI_CONF1_ENABLE | \ 818 PCI_CONF1_BUS(bus) | \ 819 PCI_CONF1_DEV(dev) | \ 820 PCI_CONF1_FUNC(func) | \ 821 PCI_CONF1_REG(reg)) 822 823 /* 824 * Extension of PCI Config Address for accessing extended PCIe registers 825 * 826 * No standardized specification, but used on lot of non-ECAM-compliant ARM SoCs 827 * or on AMD Barcelona and new CPUs. Reserved bits [27:24] of PCI Config Address 828 * are used for specifying additional 4 high bits of PCI Express register. 829 */ 830 831 #define PCI_CONF1_EXT_REG_SHIFT 16 832 #define PCI_CONF1_EXT_REG_MASK 0xf00 833 #define PCI_CONF1_EXT_REG(x) (((x) & PCI_CONF1_EXT_REG_MASK) << PCI_CONF1_EXT_REG_SHIFT) 834 835 #define PCI_CONF1_EXT_ADDRESS(bus, dev, func, reg) \ 836 (PCI_CONF1_ADDRESS(bus, dev, func, reg) | \ 837 PCI_CONF1_EXT_REG(reg)) 838 839 #endif /* DRIVERS_PCI_H */ 840