1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef DRIVERS_PCI_H 3 #define DRIVERS_PCI_H 4 5 #include <linux/pci.h> 6 7 #define PCI_FIND_CAP_TTL 48 8 9 #define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */ 10 11 extern const unsigned char pcie_link_speed[]; 12 extern bool pci_early_dump; 13 14 bool pcie_cap_has_lnkctl(const struct pci_dev *dev); 15 16 /* Functions internal to the PCI core code */ 17 18 int pci_create_sysfs_dev_files(struct pci_dev *pdev); 19 void pci_remove_sysfs_dev_files(struct pci_dev *pdev); 20 #if !defined(CONFIG_DMI) && !defined(CONFIG_ACPI) 21 static inline void pci_create_firmware_label_files(struct pci_dev *pdev) 22 { return; } 23 static inline void pci_remove_firmware_label_files(struct pci_dev *pdev) 24 { return; } 25 #else 26 void pci_create_firmware_label_files(struct pci_dev *pdev); 27 void pci_remove_firmware_label_files(struct pci_dev *pdev); 28 #endif 29 void pci_cleanup_rom(struct pci_dev *dev); 30 31 enum pci_mmap_api { 32 PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */ 33 PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */ 34 }; 35 int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai, 36 enum pci_mmap_api mmap_api); 37 38 int pci_probe_reset_function(struct pci_dev *dev); 39 int pci_bridge_secondary_bus_reset(struct pci_dev *dev); 40 int pci_bus_error_reset(struct pci_dev *dev); 41 42 #define PCI_PM_D2_DELAY 200 43 #define PCI_PM_D3_WAIT 10 44 #define PCI_PM_D3COLD_WAIT 100 45 #define PCI_PM_BUS_WAIT 50 46 47 /** 48 * struct pci_platform_pm_ops - Firmware PM callbacks 49 * 50 * @bridge_d3: Does the bridge allow entering into D3 51 * 52 * @is_manageable: returns 'true' if given device is power manageable by the 53 * platform firmware 54 * 55 * @set_state: invokes the platform firmware to set the device's power state 56 * 57 * @get_state: queries the platform firmware for a device's current power state 58 * 59 * @refresh_state: asks the platform to refresh the device's power state data 60 * 61 * @choose_state: returns PCI power state of given device preferred by the 62 * platform; to be used during system-wide transitions from a 63 * sleeping state to the working state and vice versa 64 * 65 * @set_wakeup: enables/disables wakeup capability for the device 66 * 67 * @need_resume: returns 'true' if the given device (which is currently 68 * suspended) needs to be resumed to be configured for system 69 * wakeup. 70 * 71 * If given platform is generally capable of power managing PCI devices, all of 72 * these callbacks are mandatory. 73 */ 74 struct pci_platform_pm_ops { 75 bool (*bridge_d3)(struct pci_dev *dev); 76 bool (*is_manageable)(struct pci_dev *dev); 77 int (*set_state)(struct pci_dev *dev, pci_power_t state); 78 pci_power_t (*get_state)(struct pci_dev *dev); 79 void (*refresh_state)(struct pci_dev *dev); 80 pci_power_t (*choose_state)(struct pci_dev *dev); 81 int (*set_wakeup)(struct pci_dev *dev, bool enable); 82 bool (*need_resume)(struct pci_dev *dev); 83 }; 84 85 int pci_set_platform_pm(const struct pci_platform_pm_ops *ops); 86 void pci_update_current_state(struct pci_dev *dev, pci_power_t state); 87 void pci_refresh_power_state(struct pci_dev *dev); 88 void pci_power_up(struct pci_dev *dev); 89 void pci_disable_enabled_device(struct pci_dev *dev); 90 int pci_finish_runtime_suspend(struct pci_dev *dev); 91 void pcie_clear_root_pme_status(struct pci_dev *dev); 92 bool pci_check_pme_status(struct pci_dev *dev); 93 void pci_pme_wakeup_bus(struct pci_bus *bus); 94 int __pci_pme_wakeup(struct pci_dev *dev, void *ign); 95 void pci_pme_restore(struct pci_dev *dev); 96 bool pci_dev_need_resume(struct pci_dev *dev); 97 void pci_dev_adjust_pme(struct pci_dev *dev); 98 void pci_dev_complete_resume(struct pci_dev *pci_dev); 99 void pci_config_pm_runtime_get(struct pci_dev *dev); 100 void pci_config_pm_runtime_put(struct pci_dev *dev); 101 void pci_pm_init(struct pci_dev *dev); 102 void pci_ea_init(struct pci_dev *dev); 103 void pci_allocate_cap_save_buffers(struct pci_dev *dev); 104 void pci_free_cap_save_buffers(struct pci_dev *dev); 105 bool pci_bridge_d3_possible(struct pci_dev *dev); 106 void pci_bridge_d3_update(struct pci_dev *dev); 107 108 static inline void pci_wakeup_event(struct pci_dev *dev) 109 { 110 /* Wait 100 ms before the system can be put into a sleep state. */ 111 pm_wakeup_event(&dev->dev, 100); 112 } 113 114 static inline bool pci_has_subordinate(struct pci_dev *pci_dev) 115 { 116 return !!(pci_dev->subordinate); 117 } 118 119 static inline bool pci_power_manageable(struct pci_dev *pci_dev) 120 { 121 /* 122 * Currently we allow normal PCI devices and PCI bridges transition 123 * into D3 if their bridge_d3 is set. 124 */ 125 return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3; 126 } 127 128 static inline bool pcie_downstream_port(const struct pci_dev *dev) 129 { 130 int type = pci_pcie_type(dev); 131 132 return type == PCI_EXP_TYPE_ROOT_PORT || 133 type == PCI_EXP_TYPE_DOWNSTREAM || 134 type == PCI_EXP_TYPE_PCIE_BRIDGE; 135 } 136 137 int pci_vpd_init(struct pci_dev *dev); 138 void pci_vpd_release(struct pci_dev *dev); 139 void pcie_vpd_create_sysfs_dev_files(struct pci_dev *dev); 140 void pcie_vpd_remove_sysfs_dev_files(struct pci_dev *dev); 141 142 /* PCI Virtual Channel */ 143 int pci_save_vc_state(struct pci_dev *dev); 144 void pci_restore_vc_state(struct pci_dev *dev); 145 void pci_allocate_vc_save_buffers(struct pci_dev *dev); 146 147 /* PCI /proc functions */ 148 #ifdef CONFIG_PROC_FS 149 int pci_proc_attach_device(struct pci_dev *dev); 150 int pci_proc_detach_device(struct pci_dev *dev); 151 int pci_proc_detach_bus(struct pci_bus *bus); 152 #else 153 static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; } 154 static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; } 155 static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; } 156 #endif 157 158 /* Functions for PCI Hotplug drivers to use */ 159 int pci_hp_add_bridge(struct pci_dev *dev); 160 161 #ifdef HAVE_PCI_LEGACY 162 void pci_create_legacy_files(struct pci_bus *bus); 163 void pci_remove_legacy_files(struct pci_bus *bus); 164 #else 165 static inline void pci_create_legacy_files(struct pci_bus *bus) { return; } 166 static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; } 167 #endif 168 169 /* Lock for read/write access to pci device and bus lists */ 170 extern struct rw_semaphore pci_bus_sem; 171 extern struct mutex pci_slot_mutex; 172 173 extern raw_spinlock_t pci_lock; 174 175 extern unsigned int pci_pm_d3_delay; 176 177 #ifdef CONFIG_PCI_MSI 178 void pci_no_msi(void); 179 #else 180 static inline void pci_no_msi(void) { } 181 #endif 182 183 static inline void pci_msi_set_enable(struct pci_dev *dev, int enable) 184 { 185 u16 control; 186 187 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); 188 control &= ~PCI_MSI_FLAGS_ENABLE; 189 if (enable) 190 control |= PCI_MSI_FLAGS_ENABLE; 191 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); 192 } 193 194 static inline void pci_msix_clear_and_set_ctrl(struct pci_dev *dev, u16 clear, u16 set) 195 { 196 u16 ctrl; 197 198 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl); 199 ctrl &= ~clear; 200 ctrl |= set; 201 pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, ctrl); 202 } 203 204 void pci_realloc_get_opt(char *); 205 206 static inline int pci_no_d1d2(struct pci_dev *dev) 207 { 208 unsigned int parent_dstates = 0; 209 210 if (dev->bus->self) 211 parent_dstates = dev->bus->self->no_d1d2; 212 return (dev->no_d1d2 || parent_dstates); 213 214 } 215 extern const struct attribute_group *pci_dev_groups[]; 216 extern const struct attribute_group *pcibus_groups[]; 217 extern const struct device_type pci_dev_type; 218 extern const struct attribute_group *pci_bus_groups[]; 219 220 extern unsigned long pci_hotplug_io_size; 221 extern unsigned long pci_hotplug_mem_size; 222 extern unsigned long pci_hotplug_bus_size; 223 224 /** 225 * pci_match_one_device - Tell if a PCI device structure has a matching 226 * PCI device id structure 227 * @id: single PCI device id structure to match 228 * @dev: the PCI device structure to match against 229 * 230 * Returns the matching pci_device_id structure or %NULL if there is no match. 231 */ 232 static inline const struct pci_device_id * 233 pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev) 234 { 235 if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) && 236 (id->device == PCI_ANY_ID || id->device == dev->device) && 237 (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) && 238 (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) && 239 !((id->class ^ dev->class) & id->class_mask)) 240 return id; 241 return NULL; 242 } 243 244 /* PCI slot sysfs helper code */ 245 #define to_pci_slot(s) container_of(s, struct pci_slot, kobj) 246 247 extern struct kset *pci_slots_kset; 248 249 struct pci_slot_attribute { 250 struct attribute attr; 251 ssize_t (*show)(struct pci_slot *, char *); 252 ssize_t (*store)(struct pci_slot *, const char *, size_t); 253 }; 254 #define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr) 255 256 enum pci_bar_type { 257 pci_bar_unknown, /* Standard PCI BAR probe */ 258 pci_bar_io, /* An I/O port BAR */ 259 pci_bar_mem32, /* A 32-bit memory BAR */ 260 pci_bar_mem64, /* A 64-bit memory BAR */ 261 }; 262 263 struct device *pci_get_host_bridge_device(struct pci_dev *dev); 264 void pci_put_host_bridge_device(struct device *dev); 265 266 int pci_configure_extended_tags(struct pci_dev *dev, void *ign); 267 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, 268 int crs_timeout); 269 bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, 270 int crs_timeout); 271 int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int crs_timeout); 272 273 int pci_setup_device(struct pci_dev *dev); 274 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, 275 struct resource *res, unsigned int reg); 276 void pci_configure_ari(struct pci_dev *dev); 277 void __pci_bus_size_bridges(struct pci_bus *bus, 278 struct list_head *realloc_head); 279 void __pci_bus_assign_resources(const struct pci_bus *bus, 280 struct list_head *realloc_head, 281 struct list_head *fail_head); 282 bool pci_bus_clip_resource(struct pci_dev *dev, int idx); 283 284 void pci_reassigndev_resource_alignment(struct pci_dev *dev); 285 void pci_disable_bridge_window(struct pci_dev *dev); 286 struct pci_bus *pci_bus_get(struct pci_bus *bus); 287 void pci_bus_put(struct pci_bus *bus); 288 289 /* PCIe link information */ 290 #define PCIE_SPEED2STR(speed) \ 291 ((speed) == PCIE_SPEED_16_0GT ? "16 GT/s" : \ 292 (speed) == PCIE_SPEED_8_0GT ? "8 GT/s" : \ 293 (speed) == PCIE_SPEED_5_0GT ? "5 GT/s" : \ 294 (speed) == PCIE_SPEED_2_5GT ? "2.5 GT/s" : \ 295 "Unknown speed") 296 297 /* PCIe speed to Mb/s reduced by encoding overhead */ 298 #define PCIE_SPEED2MBS_ENC(speed) \ 299 ((speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \ 300 (speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \ 301 (speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \ 302 (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \ 303 0) 304 305 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev); 306 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev); 307 u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed, 308 enum pcie_link_width *width); 309 void __pcie_print_link_status(struct pci_dev *dev, bool verbose); 310 void pcie_report_downtraining(struct pci_dev *dev); 311 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status); 312 313 /* Single Root I/O Virtualization */ 314 struct pci_sriov { 315 int pos; /* Capability position */ 316 int nres; /* Number of resources */ 317 u32 cap; /* SR-IOV Capabilities */ 318 u16 ctrl; /* SR-IOV Control */ 319 u16 total_VFs; /* Total VFs associated with the PF */ 320 u16 initial_VFs; /* Initial VFs associated with the PF */ 321 u16 num_VFs; /* Number of VFs available */ 322 u16 offset; /* First VF Routing ID offset */ 323 u16 stride; /* Following VF stride */ 324 u16 vf_device; /* VF device ID */ 325 u32 pgsz; /* Page size for BAR alignment */ 326 u8 link; /* Function Dependency Link */ 327 u8 max_VF_buses; /* Max buses consumed by VFs */ 328 u16 driver_max_VFs; /* Max num VFs driver supports */ 329 struct pci_dev *dev; /* Lowest numbered PF */ 330 struct pci_dev *self; /* This PF */ 331 u32 class; /* VF device */ 332 u8 hdr_type; /* VF header type */ 333 u16 subsystem_vendor; /* VF subsystem vendor */ 334 u16 subsystem_device; /* VF subsystem device */ 335 resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */ 336 bool drivers_autoprobe; /* Auto probing of VFs by driver */ 337 }; 338 339 /** 340 * pci_dev_set_io_state - Set the new error state if possible. 341 * 342 * @dev - pci device to set new error_state 343 * @new - the state we want dev to be in 344 * 345 * Must be called with device_lock held. 346 * 347 * Returns true if state has been changed to the requested state. 348 */ 349 static inline bool pci_dev_set_io_state(struct pci_dev *dev, 350 pci_channel_state_t new) 351 { 352 bool changed = false; 353 354 device_lock_assert(&dev->dev); 355 switch (new) { 356 case pci_channel_io_perm_failure: 357 switch (dev->error_state) { 358 case pci_channel_io_frozen: 359 case pci_channel_io_normal: 360 case pci_channel_io_perm_failure: 361 changed = true; 362 break; 363 } 364 break; 365 case pci_channel_io_frozen: 366 switch (dev->error_state) { 367 case pci_channel_io_frozen: 368 case pci_channel_io_normal: 369 changed = true; 370 break; 371 } 372 break; 373 case pci_channel_io_normal: 374 switch (dev->error_state) { 375 case pci_channel_io_frozen: 376 case pci_channel_io_normal: 377 changed = true; 378 break; 379 } 380 break; 381 } 382 if (changed) 383 dev->error_state = new; 384 return changed; 385 } 386 387 static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused) 388 { 389 device_lock(&dev->dev); 390 pci_dev_set_io_state(dev, pci_channel_io_perm_failure); 391 device_unlock(&dev->dev); 392 393 return 0; 394 } 395 396 static inline bool pci_dev_is_disconnected(const struct pci_dev *dev) 397 { 398 return dev->error_state == pci_channel_io_perm_failure; 399 } 400 401 /* pci_dev priv_flags */ 402 #define PCI_DEV_ADDED 0 403 404 static inline void pci_dev_assign_added(struct pci_dev *dev, bool added) 405 { 406 assign_bit(PCI_DEV_ADDED, &dev->priv_flags, added); 407 } 408 409 static inline bool pci_dev_is_added(const struct pci_dev *dev) 410 { 411 return test_bit(PCI_DEV_ADDED, &dev->priv_flags); 412 } 413 414 #ifdef CONFIG_PCIEAER 415 #include <linux/aer.h> 416 417 #define AER_MAX_MULTI_ERR_DEVICES 5 /* Not likely to have more */ 418 419 struct aer_err_info { 420 struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES]; 421 int error_dev_num; 422 423 unsigned int id:16; 424 425 unsigned int severity:2; /* 0:NONFATAL | 1:FATAL | 2:COR */ 426 unsigned int __pad1:5; 427 unsigned int multi_error_valid:1; 428 429 unsigned int first_error:5; 430 unsigned int __pad2:2; 431 unsigned int tlp_header_valid:1; 432 433 unsigned int status; /* COR/UNCOR Error Status */ 434 unsigned int mask; /* COR/UNCOR Error Mask */ 435 struct aer_header_log_regs tlp; /* TLP Header */ 436 }; 437 438 int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info); 439 void aer_print_error(struct pci_dev *dev, struct aer_err_info *info); 440 #endif /* CONFIG_PCIEAER */ 441 442 #ifdef CONFIG_PCIE_DPC 443 void pci_save_dpc_state(struct pci_dev *dev); 444 void pci_restore_dpc_state(struct pci_dev *dev); 445 #else 446 static inline void pci_save_dpc_state(struct pci_dev *dev) {} 447 static inline void pci_restore_dpc_state(struct pci_dev *dev) {} 448 #endif 449 450 #ifdef CONFIG_PCI_ATS 451 /* Address Translation Service */ 452 void pci_ats_init(struct pci_dev *dev); 453 void pci_restore_ats_state(struct pci_dev *dev); 454 #else 455 static inline void pci_ats_init(struct pci_dev *d) { } 456 static inline void pci_restore_ats_state(struct pci_dev *dev) { } 457 #endif /* CONFIG_PCI_ATS */ 458 459 #ifdef CONFIG_PCI_IOV 460 int pci_iov_init(struct pci_dev *dev); 461 void pci_iov_release(struct pci_dev *dev); 462 void pci_iov_remove(struct pci_dev *dev); 463 void pci_iov_update_resource(struct pci_dev *dev, int resno); 464 resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno); 465 void pci_restore_iov_state(struct pci_dev *dev); 466 int pci_iov_bus_range(struct pci_bus *bus); 467 extern const struct attribute_group sriov_dev_attr_group; 468 #else 469 static inline int pci_iov_init(struct pci_dev *dev) 470 { 471 return -ENODEV; 472 } 473 static inline void pci_iov_release(struct pci_dev *dev) 474 475 { 476 } 477 static inline void pci_iov_remove(struct pci_dev *dev) 478 { 479 } 480 static inline void pci_restore_iov_state(struct pci_dev *dev) 481 { 482 } 483 static inline int pci_iov_bus_range(struct pci_bus *bus) 484 { 485 return 0; 486 } 487 488 #endif /* CONFIG_PCI_IOV */ 489 490 unsigned long pci_cardbus_resource_alignment(struct resource *); 491 492 static inline resource_size_t pci_resource_alignment(struct pci_dev *dev, 493 struct resource *res) 494 { 495 #ifdef CONFIG_PCI_IOV 496 int resno = res - dev->resource; 497 498 if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END) 499 return pci_sriov_resource_alignment(dev, resno); 500 #endif 501 if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS) 502 return pci_cardbus_resource_alignment(res); 503 return resource_alignment(res); 504 } 505 506 void pci_enable_acs(struct pci_dev *dev); 507 #ifdef CONFIG_PCI_QUIRKS 508 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags); 509 int pci_dev_specific_enable_acs(struct pci_dev *dev); 510 int pci_dev_specific_disable_acs_redir(struct pci_dev *dev); 511 #else 512 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev, 513 u16 acs_flags) 514 { 515 return -ENOTTY; 516 } 517 static inline int pci_dev_specific_enable_acs(struct pci_dev *dev) 518 { 519 return -ENOTTY; 520 } 521 static inline int pci_dev_specific_disable_acs_redir(struct pci_dev *dev) 522 { 523 return -ENOTTY; 524 } 525 #endif 526 527 /* PCI error reporting and recovery */ 528 void pcie_do_recovery(struct pci_dev *dev, enum pci_channel_state state, 529 u32 service); 530 531 bool pcie_wait_for_link(struct pci_dev *pdev, bool active); 532 #ifdef CONFIG_PCIEASPM 533 void pcie_aspm_init_link_state(struct pci_dev *pdev); 534 void pcie_aspm_exit_link_state(struct pci_dev *pdev); 535 void pcie_aspm_pm_state_change(struct pci_dev *pdev); 536 void pcie_aspm_powersave_config_link(struct pci_dev *pdev); 537 #else 538 static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { } 539 static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { } 540 static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev) { } 541 static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { } 542 #endif 543 544 #ifdef CONFIG_PCIEASPM_DEBUG 545 void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev); 546 void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev); 547 #else 548 static inline void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev) { } 549 static inline void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev) { } 550 #endif 551 552 #ifdef CONFIG_PCIE_ECRC 553 void pcie_set_ecrc_checking(struct pci_dev *dev); 554 void pcie_ecrc_get_policy(char *str); 555 #else 556 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { } 557 static inline void pcie_ecrc_get_policy(char *str) { } 558 #endif 559 560 #ifdef CONFIG_PCIE_PTM 561 void pci_ptm_init(struct pci_dev *dev); 562 int pci_enable_ptm(struct pci_dev *dev, u8 *granularity); 563 #else 564 static inline void pci_ptm_init(struct pci_dev *dev) { } 565 static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity) 566 { return -EINVAL; } 567 #endif 568 569 struct pci_dev_reset_methods { 570 u16 vendor; 571 u16 device; 572 int (*reset)(struct pci_dev *dev, int probe); 573 }; 574 575 #ifdef CONFIG_PCI_QUIRKS 576 int pci_dev_specific_reset(struct pci_dev *dev, int probe); 577 #else 578 static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe) 579 { 580 return -ENOTTY; 581 } 582 #endif 583 584 #if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64) 585 int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment, 586 struct resource *res); 587 #endif 588 589 u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar); 590 int pci_rebar_get_current_size(struct pci_dev *pdev, int bar); 591 int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size); 592 static inline u64 pci_rebar_size_to_bytes(int size) 593 { 594 return 1ULL << (size + 20); 595 } 596 597 struct device_node; 598 599 #ifdef CONFIG_OF 600 int of_pci_parse_bus_range(struct device_node *node, struct resource *res); 601 int of_get_pci_domain_nr(struct device_node *node); 602 int of_pci_get_max_link_speed(struct device_node *node); 603 void pci_set_of_node(struct pci_dev *dev); 604 void pci_release_of_node(struct pci_dev *dev); 605 void pci_set_bus_of_node(struct pci_bus *bus); 606 void pci_release_bus_of_node(struct pci_bus *bus); 607 608 #else 609 static inline int 610 of_pci_parse_bus_range(struct device_node *node, struct resource *res) 611 { 612 return -EINVAL; 613 } 614 615 static inline int 616 of_get_pci_domain_nr(struct device_node *node) 617 { 618 return -1; 619 } 620 621 static inline int 622 of_pci_get_max_link_speed(struct device_node *node) 623 { 624 return -EINVAL; 625 } 626 627 static inline void pci_set_of_node(struct pci_dev *dev) { } 628 static inline void pci_release_of_node(struct pci_dev *dev) { } 629 static inline void pci_set_bus_of_node(struct pci_bus *bus) { } 630 static inline void pci_release_bus_of_node(struct pci_bus *bus) { } 631 #endif /* CONFIG_OF */ 632 633 #if defined(CONFIG_OF_ADDRESS) 634 int devm_of_pci_get_host_bridge_resources(struct device *dev, 635 unsigned char busno, unsigned char bus_max, 636 struct list_head *resources, resource_size_t *io_base); 637 #else 638 static inline int devm_of_pci_get_host_bridge_resources(struct device *dev, 639 unsigned char busno, unsigned char bus_max, 640 struct list_head *resources, resource_size_t *io_base) 641 { 642 return -EINVAL; 643 } 644 #endif 645 646 #ifdef CONFIG_PCIEAER 647 void pci_no_aer(void); 648 void pci_aer_init(struct pci_dev *dev); 649 void pci_aer_exit(struct pci_dev *dev); 650 extern const struct attribute_group aer_stats_attr_group; 651 void pci_aer_clear_fatal_status(struct pci_dev *dev); 652 void pci_aer_clear_device_status(struct pci_dev *dev); 653 #else 654 static inline void pci_no_aer(void) { } 655 static inline void pci_aer_init(struct pci_dev *d) { } 656 static inline void pci_aer_exit(struct pci_dev *d) { } 657 static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { } 658 static inline void pci_aer_clear_device_status(struct pci_dev *dev) { } 659 #endif 660 661 #ifdef CONFIG_ACPI 662 int pci_acpi_program_hp_params(struct pci_dev *dev); 663 #else 664 static inline int pci_acpi_program_hp_params(struct pci_dev *dev) 665 { 666 return -ENODEV; 667 } 668 #endif 669 670 #endif /* DRIVERS_PCI_H */ 671