1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef DRIVERS_PCI_H 3 #define DRIVERS_PCI_H 4 5 #include <linux/pci.h> 6 7 /* Number of possible devfns: 0.0 to 1f.7 inclusive */ 8 #define MAX_NR_DEVFNS 256 9 10 #define PCI_FIND_CAP_TTL 48 11 12 #define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */ 13 14 extern const unsigned char pcie_link_speed[]; 15 extern bool pci_early_dump; 16 17 bool pcie_cap_has_lnkctl(const struct pci_dev *dev); 18 bool pcie_cap_has_lnkctl2(const struct pci_dev *dev); 19 bool pcie_cap_has_rtctl(const struct pci_dev *dev); 20 21 /* Functions internal to the PCI core code */ 22 23 int pci_create_sysfs_dev_files(struct pci_dev *pdev); 24 void pci_remove_sysfs_dev_files(struct pci_dev *pdev); 25 void pci_cleanup_rom(struct pci_dev *dev); 26 #ifdef CONFIG_DMI 27 extern const struct attribute_group pci_dev_smbios_attr_group; 28 #endif 29 30 enum pci_mmap_api { 31 PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */ 32 PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */ 33 }; 34 int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai, 35 enum pci_mmap_api mmap_api); 36 37 bool pci_reset_supported(struct pci_dev *dev); 38 void pci_init_reset_methods(struct pci_dev *dev); 39 int pci_bridge_secondary_bus_reset(struct pci_dev *dev); 40 int pci_bus_error_reset(struct pci_dev *dev); 41 42 struct pci_cap_saved_data { 43 u16 cap_nr; 44 bool cap_extended; 45 unsigned int size; 46 u32 data[]; 47 }; 48 49 struct pci_cap_saved_state { 50 struct hlist_node next; 51 struct pci_cap_saved_data cap; 52 }; 53 54 void pci_allocate_cap_save_buffers(struct pci_dev *dev); 55 void pci_free_cap_save_buffers(struct pci_dev *dev); 56 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size); 57 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, 58 u16 cap, unsigned int size); 59 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap); 60 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, 61 u16 cap); 62 63 #define PCI_PM_D2_DELAY 200 /* usec; see PCIe r4.0, sec 5.9.1 */ 64 #define PCI_PM_D3HOT_WAIT 10 /* msec */ 65 #define PCI_PM_D3COLD_WAIT 100 /* msec */ 66 67 void pci_update_current_state(struct pci_dev *dev, pci_power_t state); 68 void pci_refresh_power_state(struct pci_dev *dev); 69 int pci_power_up(struct pci_dev *dev); 70 void pci_disable_enabled_device(struct pci_dev *dev); 71 int pci_finish_runtime_suspend(struct pci_dev *dev); 72 void pcie_clear_device_status(struct pci_dev *dev); 73 void pcie_clear_root_pme_status(struct pci_dev *dev); 74 bool pci_check_pme_status(struct pci_dev *dev); 75 void pci_pme_wakeup_bus(struct pci_bus *bus); 76 int __pci_pme_wakeup(struct pci_dev *dev, void *ign); 77 void pci_pme_restore(struct pci_dev *dev); 78 bool pci_dev_need_resume(struct pci_dev *dev); 79 void pci_dev_adjust_pme(struct pci_dev *dev); 80 void pci_dev_complete_resume(struct pci_dev *pci_dev); 81 void pci_config_pm_runtime_get(struct pci_dev *dev); 82 void pci_config_pm_runtime_put(struct pci_dev *dev); 83 void pci_pm_init(struct pci_dev *dev); 84 void pci_ea_init(struct pci_dev *dev); 85 void pci_msi_init(struct pci_dev *dev); 86 void pci_msix_init(struct pci_dev *dev); 87 bool pci_bridge_d3_possible(struct pci_dev *dev); 88 void pci_bridge_d3_update(struct pci_dev *dev); 89 void pci_bridge_wait_for_secondary_bus(struct pci_dev *dev); 90 void pci_bridge_reconfigure_ltr(struct pci_dev *dev); 91 92 static inline void pci_wakeup_event(struct pci_dev *dev) 93 { 94 /* Wait 100 ms before the system can be put into a sleep state. */ 95 pm_wakeup_event(&dev->dev, 100); 96 } 97 98 static inline bool pci_has_subordinate(struct pci_dev *pci_dev) 99 { 100 return !!(pci_dev->subordinate); 101 } 102 103 static inline bool pci_power_manageable(struct pci_dev *pci_dev) 104 { 105 /* 106 * Currently we allow normal PCI devices and PCI bridges transition 107 * into D3 if their bridge_d3 is set. 108 */ 109 return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3; 110 } 111 112 static inline bool pcie_downstream_port(const struct pci_dev *dev) 113 { 114 int type = pci_pcie_type(dev); 115 116 return type == PCI_EXP_TYPE_ROOT_PORT || 117 type == PCI_EXP_TYPE_DOWNSTREAM || 118 type == PCI_EXP_TYPE_PCIE_BRIDGE; 119 } 120 121 void pci_vpd_init(struct pci_dev *dev); 122 void pci_vpd_release(struct pci_dev *dev); 123 extern const struct attribute_group pci_dev_vpd_attr_group; 124 125 /* PCI Virtual Channel */ 126 int pci_save_vc_state(struct pci_dev *dev); 127 void pci_restore_vc_state(struct pci_dev *dev); 128 void pci_allocate_vc_save_buffers(struct pci_dev *dev); 129 130 /* PCI /proc functions */ 131 #ifdef CONFIG_PROC_FS 132 int pci_proc_attach_device(struct pci_dev *dev); 133 int pci_proc_detach_device(struct pci_dev *dev); 134 int pci_proc_detach_bus(struct pci_bus *bus); 135 #else 136 static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; } 137 static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; } 138 static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; } 139 #endif 140 141 /* Functions for PCI Hotplug drivers to use */ 142 int pci_hp_add_bridge(struct pci_dev *dev); 143 144 #ifdef HAVE_PCI_LEGACY 145 void pci_create_legacy_files(struct pci_bus *bus); 146 void pci_remove_legacy_files(struct pci_bus *bus); 147 #else 148 static inline void pci_create_legacy_files(struct pci_bus *bus) { return; } 149 static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; } 150 #endif 151 152 /* Lock for read/write access to pci device and bus lists */ 153 extern struct rw_semaphore pci_bus_sem; 154 extern struct mutex pci_slot_mutex; 155 156 extern raw_spinlock_t pci_lock; 157 158 extern unsigned int pci_pm_d3hot_delay; 159 160 #ifdef CONFIG_PCI_MSI 161 void pci_no_msi(void); 162 #else 163 static inline void pci_no_msi(void) { } 164 #endif 165 166 void pci_realloc_get_opt(char *); 167 168 static inline int pci_no_d1d2(struct pci_dev *dev) 169 { 170 unsigned int parent_dstates = 0; 171 172 if (dev->bus->self) 173 parent_dstates = dev->bus->self->no_d1d2; 174 return (dev->no_d1d2 || parent_dstates); 175 176 } 177 extern const struct attribute_group *pci_dev_groups[]; 178 extern const struct attribute_group *pcibus_groups[]; 179 extern const struct device_type pci_dev_type; 180 extern const struct attribute_group *pci_bus_groups[]; 181 182 extern unsigned long pci_hotplug_io_size; 183 extern unsigned long pci_hotplug_mmio_size; 184 extern unsigned long pci_hotplug_mmio_pref_size; 185 extern unsigned long pci_hotplug_bus_size; 186 187 /** 188 * pci_match_one_device - Tell if a PCI device structure has a matching 189 * PCI device id structure 190 * @id: single PCI device id structure to match 191 * @dev: the PCI device structure to match against 192 * 193 * Returns the matching pci_device_id structure or %NULL if there is no match. 194 */ 195 static inline const struct pci_device_id * 196 pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev) 197 { 198 if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) && 199 (id->device == PCI_ANY_ID || id->device == dev->device) && 200 (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) && 201 (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) && 202 !((id->class ^ dev->class) & id->class_mask)) 203 return id; 204 return NULL; 205 } 206 207 /* PCI slot sysfs helper code */ 208 #define to_pci_slot(s) container_of(s, struct pci_slot, kobj) 209 210 extern struct kset *pci_slots_kset; 211 212 struct pci_slot_attribute { 213 struct attribute attr; 214 ssize_t (*show)(struct pci_slot *, char *); 215 ssize_t (*store)(struct pci_slot *, const char *, size_t); 216 }; 217 #define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr) 218 219 enum pci_bar_type { 220 pci_bar_unknown, /* Standard PCI BAR probe */ 221 pci_bar_io, /* An I/O port BAR */ 222 pci_bar_mem32, /* A 32-bit memory BAR */ 223 pci_bar_mem64, /* A 64-bit memory BAR */ 224 }; 225 226 struct device *pci_get_host_bridge_device(struct pci_dev *dev); 227 void pci_put_host_bridge_device(struct device *dev); 228 229 int pci_configure_extended_tags(struct pci_dev *dev, void *ign); 230 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, 231 int crs_timeout); 232 bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, 233 int crs_timeout); 234 int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int crs_timeout); 235 236 int pci_setup_device(struct pci_dev *dev); 237 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, 238 struct resource *res, unsigned int reg); 239 void pci_configure_ari(struct pci_dev *dev); 240 void __pci_bus_size_bridges(struct pci_bus *bus, 241 struct list_head *realloc_head); 242 void __pci_bus_assign_resources(const struct pci_bus *bus, 243 struct list_head *realloc_head, 244 struct list_head *fail_head); 245 bool pci_bus_clip_resource(struct pci_dev *dev, int idx); 246 247 void pci_reassigndev_resource_alignment(struct pci_dev *dev); 248 void pci_disable_bridge_window(struct pci_dev *dev); 249 struct pci_bus *pci_bus_get(struct pci_bus *bus); 250 void pci_bus_put(struct pci_bus *bus); 251 252 /* PCIe link information from Link Capabilities 2 */ 253 #define PCIE_LNKCAP2_SLS2SPEED(lnkcap2) \ 254 ((lnkcap2) & PCI_EXP_LNKCAP2_SLS_64_0GB ? PCIE_SPEED_64_0GT : \ 255 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_32_0GB ? PCIE_SPEED_32_0GT : \ 256 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_16_0GB ? PCIE_SPEED_16_0GT : \ 257 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_8_0GB ? PCIE_SPEED_8_0GT : \ 258 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_5_0GB ? PCIE_SPEED_5_0GT : \ 259 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_2_5GB ? PCIE_SPEED_2_5GT : \ 260 PCI_SPEED_UNKNOWN) 261 262 /* PCIe speed to Mb/s reduced by encoding overhead */ 263 #define PCIE_SPEED2MBS_ENC(speed) \ 264 ((speed) == PCIE_SPEED_64_0GT ? 64000*128/130 : \ 265 (speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \ 266 (speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \ 267 (speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \ 268 (speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \ 269 (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \ 270 0) 271 272 const char *pci_speed_string(enum pci_bus_speed speed); 273 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev); 274 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev); 275 u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed, 276 enum pcie_link_width *width); 277 void __pcie_print_link_status(struct pci_dev *dev, bool verbose); 278 void pcie_report_downtraining(struct pci_dev *dev); 279 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status); 280 281 /* Single Root I/O Virtualization */ 282 struct pci_sriov { 283 int pos; /* Capability position */ 284 int nres; /* Number of resources */ 285 u32 cap; /* SR-IOV Capabilities */ 286 u16 ctrl; /* SR-IOV Control */ 287 u16 total_VFs; /* Total VFs associated with the PF */ 288 u16 initial_VFs; /* Initial VFs associated with the PF */ 289 u16 num_VFs; /* Number of VFs available */ 290 u16 offset; /* First VF Routing ID offset */ 291 u16 stride; /* Following VF stride */ 292 u16 vf_device; /* VF device ID */ 293 u32 pgsz; /* Page size for BAR alignment */ 294 u8 link; /* Function Dependency Link */ 295 u8 max_VF_buses; /* Max buses consumed by VFs */ 296 u16 driver_max_VFs; /* Max num VFs driver supports */ 297 struct pci_dev *dev; /* Lowest numbered PF */ 298 struct pci_dev *self; /* This PF */ 299 u32 class; /* VF device */ 300 u8 hdr_type; /* VF header type */ 301 u16 subsystem_vendor; /* VF subsystem vendor */ 302 u16 subsystem_device; /* VF subsystem device */ 303 resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */ 304 bool drivers_autoprobe; /* Auto probing of VFs by driver */ 305 }; 306 307 /** 308 * pci_dev_set_io_state - Set the new error state if possible. 309 * 310 * @dev: PCI device to set new error_state 311 * @new: the state we want dev to be in 312 * 313 * If the device is experiencing perm_failure, it has to remain in that state. 314 * Any other transition is allowed. 315 * 316 * Returns true if state has been changed to the requested state. 317 */ 318 static inline bool pci_dev_set_io_state(struct pci_dev *dev, 319 pci_channel_state_t new) 320 { 321 pci_channel_state_t old; 322 323 switch (new) { 324 case pci_channel_io_perm_failure: 325 xchg(&dev->error_state, pci_channel_io_perm_failure); 326 return true; 327 case pci_channel_io_frozen: 328 old = cmpxchg(&dev->error_state, pci_channel_io_normal, 329 pci_channel_io_frozen); 330 return old != pci_channel_io_perm_failure; 331 case pci_channel_io_normal: 332 old = cmpxchg(&dev->error_state, pci_channel_io_frozen, 333 pci_channel_io_normal); 334 return old != pci_channel_io_perm_failure; 335 default: 336 return false; 337 } 338 } 339 340 static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused) 341 { 342 pci_dev_set_io_state(dev, pci_channel_io_perm_failure); 343 344 return 0; 345 } 346 347 static inline bool pci_dev_is_disconnected(const struct pci_dev *dev) 348 { 349 return dev->error_state == pci_channel_io_perm_failure; 350 } 351 352 /* pci_dev priv_flags */ 353 #define PCI_DEV_ADDED 0 354 #define PCI_DPC_RECOVERED 1 355 #define PCI_DPC_RECOVERING 2 356 357 static inline void pci_dev_assign_added(struct pci_dev *dev, bool added) 358 { 359 assign_bit(PCI_DEV_ADDED, &dev->priv_flags, added); 360 } 361 362 static inline bool pci_dev_is_added(const struct pci_dev *dev) 363 { 364 return test_bit(PCI_DEV_ADDED, &dev->priv_flags); 365 } 366 367 #ifdef CONFIG_PCIEAER 368 #include <linux/aer.h> 369 370 #define AER_MAX_MULTI_ERR_DEVICES 5 /* Not likely to have more */ 371 372 struct aer_err_info { 373 struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES]; 374 int error_dev_num; 375 376 unsigned int id:16; 377 378 unsigned int severity:2; /* 0:NONFATAL | 1:FATAL | 2:COR */ 379 unsigned int __pad1:5; 380 unsigned int multi_error_valid:1; 381 382 unsigned int first_error:5; 383 unsigned int __pad2:2; 384 unsigned int tlp_header_valid:1; 385 386 unsigned int status; /* COR/UNCOR Error Status */ 387 unsigned int mask; /* COR/UNCOR Error Mask */ 388 struct aer_header_log_regs tlp; /* TLP Header */ 389 }; 390 391 int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info); 392 void aer_print_error(struct pci_dev *dev, struct aer_err_info *info); 393 #endif /* CONFIG_PCIEAER */ 394 395 #ifdef CONFIG_PCIEPORTBUS 396 /* Cached RCEC Endpoint Association */ 397 struct rcec_ea { 398 u8 nextbusn; 399 u8 lastbusn; 400 u32 bitmap; 401 }; 402 #endif 403 404 #ifdef CONFIG_PCIE_DPC 405 void pci_save_dpc_state(struct pci_dev *dev); 406 void pci_restore_dpc_state(struct pci_dev *dev); 407 void pci_dpc_init(struct pci_dev *pdev); 408 void dpc_process_error(struct pci_dev *pdev); 409 pci_ers_result_t dpc_reset_link(struct pci_dev *pdev); 410 bool pci_dpc_recovered(struct pci_dev *pdev); 411 #else 412 static inline void pci_save_dpc_state(struct pci_dev *dev) {} 413 static inline void pci_restore_dpc_state(struct pci_dev *dev) {} 414 static inline void pci_dpc_init(struct pci_dev *pdev) {} 415 static inline bool pci_dpc_recovered(struct pci_dev *pdev) { return false; } 416 #endif 417 418 #ifdef CONFIG_PCIEPORTBUS 419 void pci_rcec_init(struct pci_dev *dev); 420 void pci_rcec_exit(struct pci_dev *dev); 421 void pcie_link_rcec(struct pci_dev *rcec); 422 void pcie_walk_rcec(struct pci_dev *rcec, 423 int (*cb)(struct pci_dev *, void *), 424 void *userdata); 425 #else 426 static inline void pci_rcec_init(struct pci_dev *dev) {} 427 static inline void pci_rcec_exit(struct pci_dev *dev) {} 428 static inline void pcie_link_rcec(struct pci_dev *rcec) {} 429 static inline void pcie_walk_rcec(struct pci_dev *rcec, 430 int (*cb)(struct pci_dev *, void *), 431 void *userdata) {} 432 #endif 433 434 #ifdef CONFIG_PCI_ATS 435 /* Address Translation Service */ 436 void pci_ats_init(struct pci_dev *dev); 437 void pci_restore_ats_state(struct pci_dev *dev); 438 #else 439 static inline void pci_ats_init(struct pci_dev *d) { } 440 static inline void pci_restore_ats_state(struct pci_dev *dev) { } 441 #endif /* CONFIG_PCI_ATS */ 442 443 #ifdef CONFIG_PCI_PRI 444 void pci_pri_init(struct pci_dev *dev); 445 void pci_restore_pri_state(struct pci_dev *pdev); 446 #else 447 static inline void pci_pri_init(struct pci_dev *dev) { } 448 static inline void pci_restore_pri_state(struct pci_dev *pdev) { } 449 #endif 450 451 #ifdef CONFIG_PCI_PASID 452 void pci_pasid_init(struct pci_dev *dev); 453 void pci_restore_pasid_state(struct pci_dev *pdev); 454 #else 455 static inline void pci_pasid_init(struct pci_dev *dev) { } 456 static inline void pci_restore_pasid_state(struct pci_dev *pdev) { } 457 #endif 458 459 #ifdef CONFIG_PCI_IOV 460 int pci_iov_init(struct pci_dev *dev); 461 void pci_iov_release(struct pci_dev *dev); 462 void pci_iov_remove(struct pci_dev *dev); 463 void pci_iov_update_resource(struct pci_dev *dev, int resno); 464 resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno); 465 void pci_restore_iov_state(struct pci_dev *dev); 466 int pci_iov_bus_range(struct pci_bus *bus); 467 extern const struct attribute_group sriov_pf_dev_attr_group; 468 extern const struct attribute_group sriov_vf_dev_attr_group; 469 #else 470 static inline int pci_iov_init(struct pci_dev *dev) 471 { 472 return -ENODEV; 473 } 474 static inline void pci_iov_release(struct pci_dev *dev) 475 476 { 477 } 478 static inline void pci_iov_remove(struct pci_dev *dev) 479 { 480 } 481 static inline void pci_restore_iov_state(struct pci_dev *dev) 482 { 483 } 484 static inline int pci_iov_bus_range(struct pci_bus *bus) 485 { 486 return 0; 487 } 488 489 #endif /* CONFIG_PCI_IOV */ 490 491 #ifdef CONFIG_PCIE_PTM 492 void pci_ptm_init(struct pci_dev *dev); 493 void pci_save_ptm_state(struct pci_dev *dev); 494 void pci_restore_ptm_state(struct pci_dev *dev); 495 void pci_suspend_ptm(struct pci_dev *dev); 496 void pci_resume_ptm(struct pci_dev *dev); 497 #else 498 static inline void pci_ptm_init(struct pci_dev *dev) { } 499 static inline void pci_save_ptm_state(struct pci_dev *dev) { } 500 static inline void pci_restore_ptm_state(struct pci_dev *dev) { } 501 static inline void pci_suspend_ptm(struct pci_dev *dev) { } 502 static inline void pci_resume_ptm(struct pci_dev *dev) { } 503 #endif 504 505 unsigned long pci_cardbus_resource_alignment(struct resource *); 506 507 static inline resource_size_t pci_resource_alignment(struct pci_dev *dev, 508 struct resource *res) 509 { 510 #ifdef CONFIG_PCI_IOV 511 int resno = res - dev->resource; 512 513 if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END) 514 return pci_sriov_resource_alignment(dev, resno); 515 #endif 516 if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS) 517 return pci_cardbus_resource_alignment(res); 518 return resource_alignment(res); 519 } 520 521 void pci_acs_init(struct pci_dev *dev); 522 #ifdef CONFIG_PCI_QUIRKS 523 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags); 524 int pci_dev_specific_enable_acs(struct pci_dev *dev); 525 int pci_dev_specific_disable_acs_redir(struct pci_dev *dev); 526 #else 527 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev, 528 u16 acs_flags) 529 { 530 return -ENOTTY; 531 } 532 static inline int pci_dev_specific_enable_acs(struct pci_dev *dev) 533 { 534 return -ENOTTY; 535 } 536 static inline int pci_dev_specific_disable_acs_redir(struct pci_dev *dev) 537 { 538 return -ENOTTY; 539 } 540 #endif 541 542 /* PCI error reporting and recovery */ 543 pci_ers_result_t pcie_do_recovery(struct pci_dev *dev, 544 pci_channel_state_t state, 545 pci_ers_result_t (*reset_subordinates)(struct pci_dev *pdev)); 546 547 bool pcie_wait_for_link(struct pci_dev *pdev, bool active); 548 #ifdef CONFIG_PCIEASPM 549 void pcie_aspm_init_link_state(struct pci_dev *pdev); 550 void pcie_aspm_exit_link_state(struct pci_dev *pdev); 551 void pcie_aspm_powersave_config_link(struct pci_dev *pdev); 552 void pci_save_aspm_l1ss_state(struct pci_dev *dev); 553 void pci_restore_aspm_l1ss_state(struct pci_dev *dev); 554 #else 555 static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { } 556 static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { } 557 static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { } 558 static inline void pci_save_aspm_l1ss_state(struct pci_dev *dev) { } 559 static inline void pci_restore_aspm_l1ss_state(struct pci_dev *dev) { } 560 #endif 561 562 #ifdef CONFIG_PCIE_ECRC 563 void pcie_set_ecrc_checking(struct pci_dev *dev); 564 void pcie_ecrc_get_policy(char *str); 565 #else 566 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { } 567 static inline void pcie_ecrc_get_policy(char *str) { } 568 #endif 569 570 struct pci_dev_reset_methods { 571 u16 vendor; 572 u16 device; 573 int (*reset)(struct pci_dev *dev, bool probe); 574 }; 575 576 struct pci_reset_fn_method { 577 int (*reset_fn)(struct pci_dev *pdev, bool probe); 578 char *name; 579 }; 580 581 #ifdef CONFIG_PCI_QUIRKS 582 int pci_dev_specific_reset(struct pci_dev *dev, bool probe); 583 #else 584 static inline int pci_dev_specific_reset(struct pci_dev *dev, bool probe) 585 { 586 return -ENOTTY; 587 } 588 #endif 589 590 #if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64) 591 int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment, 592 struct resource *res); 593 #else 594 static inline int acpi_get_rc_resources(struct device *dev, const char *hid, 595 u16 segment, struct resource *res) 596 { 597 return -ENODEV; 598 } 599 #endif 600 601 int pci_rebar_get_current_size(struct pci_dev *pdev, int bar); 602 int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size); 603 static inline u64 pci_rebar_size_to_bytes(int size) 604 { 605 return 1ULL << (size + 20); 606 } 607 608 struct device_node; 609 610 #ifdef CONFIG_OF 611 int of_pci_parse_bus_range(struct device_node *node, struct resource *res); 612 int of_get_pci_domain_nr(struct device_node *node); 613 int of_pci_get_max_link_speed(struct device_node *node); 614 u32 of_pci_get_slot_power_limit(struct device_node *node, 615 u8 *slot_power_limit_value, 616 u8 *slot_power_limit_scale); 617 void pci_set_of_node(struct pci_dev *dev); 618 void pci_release_of_node(struct pci_dev *dev); 619 void pci_set_bus_of_node(struct pci_bus *bus); 620 void pci_release_bus_of_node(struct pci_bus *bus); 621 622 int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge); 623 624 #else 625 static inline int 626 of_pci_parse_bus_range(struct device_node *node, struct resource *res) 627 { 628 return -EINVAL; 629 } 630 631 static inline int 632 of_get_pci_domain_nr(struct device_node *node) 633 { 634 return -1; 635 } 636 637 static inline int 638 of_pci_get_max_link_speed(struct device_node *node) 639 { 640 return -EINVAL; 641 } 642 643 static inline u32 644 of_pci_get_slot_power_limit(struct device_node *node, 645 u8 *slot_power_limit_value, 646 u8 *slot_power_limit_scale) 647 { 648 if (slot_power_limit_value) 649 *slot_power_limit_value = 0; 650 if (slot_power_limit_scale) 651 *slot_power_limit_scale = 0; 652 return 0; 653 } 654 655 static inline void pci_set_of_node(struct pci_dev *dev) { } 656 static inline void pci_release_of_node(struct pci_dev *dev) { } 657 static inline void pci_set_bus_of_node(struct pci_bus *bus) { } 658 static inline void pci_release_bus_of_node(struct pci_bus *bus) { } 659 660 static inline int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge) 661 { 662 return 0; 663 } 664 665 #endif /* CONFIG_OF */ 666 667 #ifdef CONFIG_PCIEAER 668 void pci_no_aer(void); 669 void pci_aer_init(struct pci_dev *dev); 670 void pci_aer_exit(struct pci_dev *dev); 671 extern const struct attribute_group aer_stats_attr_group; 672 void pci_aer_clear_fatal_status(struct pci_dev *dev); 673 int pci_aer_clear_status(struct pci_dev *dev); 674 int pci_aer_raw_clear_status(struct pci_dev *dev); 675 #else 676 static inline void pci_no_aer(void) { } 677 static inline void pci_aer_init(struct pci_dev *d) { } 678 static inline void pci_aer_exit(struct pci_dev *d) { } 679 static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { } 680 static inline int pci_aer_clear_status(struct pci_dev *dev) { return -EINVAL; } 681 static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -EINVAL; } 682 #endif 683 684 #ifdef CONFIG_ACPI 685 int pci_acpi_program_hp_params(struct pci_dev *dev); 686 extern const struct attribute_group pci_dev_acpi_attr_group; 687 void pci_set_acpi_fwnode(struct pci_dev *dev); 688 int pci_dev_acpi_reset(struct pci_dev *dev, bool probe); 689 bool acpi_pci_power_manageable(struct pci_dev *dev); 690 bool acpi_pci_bridge_d3(struct pci_dev *dev); 691 int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state); 692 pci_power_t acpi_pci_get_power_state(struct pci_dev *dev); 693 void acpi_pci_refresh_power_state(struct pci_dev *dev); 694 int acpi_pci_wakeup(struct pci_dev *dev, bool enable); 695 bool acpi_pci_need_resume(struct pci_dev *dev); 696 pci_power_t acpi_pci_choose_state(struct pci_dev *pdev); 697 #else 698 static inline int pci_dev_acpi_reset(struct pci_dev *dev, bool probe) 699 { 700 return -ENOTTY; 701 } 702 static inline void pci_set_acpi_fwnode(struct pci_dev *dev) {} 703 static inline int pci_acpi_program_hp_params(struct pci_dev *dev) 704 { 705 return -ENODEV; 706 } 707 static inline bool acpi_pci_power_manageable(struct pci_dev *dev) 708 { 709 return false; 710 } 711 static inline bool acpi_pci_bridge_d3(struct pci_dev *dev) 712 { 713 return false; 714 } 715 static inline int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state) 716 { 717 return -ENODEV; 718 } 719 static inline pci_power_t acpi_pci_get_power_state(struct pci_dev *dev) 720 { 721 return PCI_UNKNOWN; 722 } 723 static inline void acpi_pci_refresh_power_state(struct pci_dev *dev) {} 724 static inline int acpi_pci_wakeup(struct pci_dev *dev, bool enable) 725 { 726 return -ENODEV; 727 } 728 static inline bool acpi_pci_need_resume(struct pci_dev *dev) 729 { 730 return false; 731 } 732 static inline pci_power_t acpi_pci_choose_state(struct pci_dev *pdev) 733 { 734 return PCI_POWER_ERROR; 735 } 736 #endif 737 738 #ifdef CONFIG_PCIEASPM 739 extern const struct attribute_group aspm_ctrl_attr_group; 740 #endif 741 742 extern const struct attribute_group pci_dev_reset_method_attr_group; 743 744 #ifdef CONFIG_X86_INTEL_MID 745 bool pci_use_mid_pm(void); 746 int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state); 747 pci_power_t mid_pci_get_power_state(struct pci_dev *pdev); 748 #else 749 static inline bool pci_use_mid_pm(void) 750 { 751 return false; 752 } 753 static inline int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state) 754 { 755 return -ENODEV; 756 } 757 static inline pci_power_t mid_pci_get_power_state(struct pci_dev *pdev) 758 { 759 return PCI_UNKNOWN; 760 } 761 #endif 762 763 /* 764 * Config Address for PCI Configuration Mechanism #1 765 * 766 * See PCI Local Bus Specification, Revision 3.0, 767 * Section 3.2.2.3.2, Figure 3-2, p. 50. 768 */ 769 770 #define PCI_CONF1_BUS_SHIFT 16 /* Bus number */ 771 #define PCI_CONF1_DEV_SHIFT 11 /* Device number */ 772 #define PCI_CONF1_FUNC_SHIFT 8 /* Function number */ 773 774 #define PCI_CONF1_BUS_MASK 0xff 775 #define PCI_CONF1_DEV_MASK 0x1f 776 #define PCI_CONF1_FUNC_MASK 0x7 777 #define PCI_CONF1_REG_MASK 0xfc /* Limit aligned offset to a maximum of 256B */ 778 779 #define PCI_CONF1_ENABLE BIT(31) 780 #define PCI_CONF1_BUS(x) (((x) & PCI_CONF1_BUS_MASK) << PCI_CONF1_BUS_SHIFT) 781 #define PCI_CONF1_DEV(x) (((x) & PCI_CONF1_DEV_MASK) << PCI_CONF1_DEV_SHIFT) 782 #define PCI_CONF1_FUNC(x) (((x) & PCI_CONF1_FUNC_MASK) << PCI_CONF1_FUNC_SHIFT) 783 #define PCI_CONF1_REG(x) ((x) & PCI_CONF1_REG_MASK) 784 785 #define PCI_CONF1_ADDRESS(bus, dev, func, reg) \ 786 (PCI_CONF1_ENABLE | \ 787 PCI_CONF1_BUS(bus) | \ 788 PCI_CONF1_DEV(dev) | \ 789 PCI_CONF1_FUNC(func) | \ 790 PCI_CONF1_REG(reg)) 791 792 /* 793 * Extension of PCI Config Address for accessing extended PCIe registers 794 * 795 * No standardized specification, but used on lot of non-ECAM-compliant ARM SoCs 796 * or on AMD Barcelona and new CPUs. Reserved bits [27:24] of PCI Config Address 797 * are used for specifying additional 4 high bits of PCI Express register. 798 */ 799 800 #define PCI_CONF1_EXT_REG_SHIFT 16 801 #define PCI_CONF1_EXT_REG_MASK 0xf00 802 #define PCI_CONF1_EXT_REG(x) (((x) & PCI_CONF1_EXT_REG_MASK) << PCI_CONF1_EXT_REG_SHIFT) 803 804 #define PCI_CONF1_EXT_ADDRESS(bus, dev, func, reg) \ 805 (PCI_CONF1_ADDRESS(bus, dev, func, reg) | \ 806 PCI_CONF1_EXT_REG(reg)) 807 808 #endif /* DRIVERS_PCI_H */ 809