1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef DRIVERS_PCI_H 3 #define DRIVERS_PCI_H 4 5 #include <linux/pci.h> 6 7 /* Number of possible devfns: 0.0 to 1f.7 inclusive */ 8 #define MAX_NR_DEVFNS 256 9 10 #define PCI_FIND_CAP_TTL 48 11 12 #define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */ 13 14 extern const unsigned char pcie_link_speed[]; 15 extern bool pci_early_dump; 16 17 bool pcie_cap_has_lnkctl(const struct pci_dev *dev); 18 bool pcie_cap_has_rtctl(const struct pci_dev *dev); 19 20 /* Functions internal to the PCI core code */ 21 22 int pci_create_sysfs_dev_files(struct pci_dev *pdev); 23 void pci_remove_sysfs_dev_files(struct pci_dev *pdev); 24 #if !defined(CONFIG_DMI) && !defined(CONFIG_ACPI) 25 static inline void pci_create_firmware_label_files(struct pci_dev *pdev) 26 { return; } 27 static inline void pci_remove_firmware_label_files(struct pci_dev *pdev) 28 { return; } 29 #else 30 void pci_create_firmware_label_files(struct pci_dev *pdev); 31 void pci_remove_firmware_label_files(struct pci_dev *pdev); 32 #endif 33 void pci_cleanup_rom(struct pci_dev *dev); 34 35 enum pci_mmap_api { 36 PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */ 37 PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */ 38 }; 39 int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai, 40 enum pci_mmap_api mmap_api); 41 42 int pci_probe_reset_function(struct pci_dev *dev); 43 int pci_bridge_secondary_bus_reset(struct pci_dev *dev); 44 int pci_bus_error_reset(struct pci_dev *dev); 45 46 #define PCI_PM_D2_DELAY 200 /* usec; see PCIe r4.0, sec 5.9.1 */ 47 #define PCI_PM_D3HOT_WAIT 10 /* msec */ 48 #define PCI_PM_D3COLD_WAIT 100 /* msec */ 49 50 /** 51 * struct pci_platform_pm_ops - Firmware PM callbacks 52 * 53 * @bridge_d3: Does the bridge allow entering into D3 54 * 55 * @is_manageable: returns 'true' if given device is power manageable by the 56 * platform firmware 57 * 58 * @set_state: invokes the platform firmware to set the device's power state 59 * 60 * @get_state: queries the platform firmware for a device's current power state 61 * 62 * @refresh_state: asks the platform to refresh the device's power state data 63 * 64 * @choose_state: returns PCI power state of given device preferred by the 65 * platform; to be used during system-wide transitions from a 66 * sleeping state to the working state and vice versa 67 * 68 * @set_wakeup: enables/disables wakeup capability for the device 69 * 70 * @need_resume: returns 'true' if the given device (which is currently 71 * suspended) needs to be resumed to be configured for system 72 * wakeup. 73 * 74 * If given platform is generally capable of power managing PCI devices, all of 75 * these callbacks are mandatory. 76 */ 77 struct pci_platform_pm_ops { 78 bool (*bridge_d3)(struct pci_dev *dev); 79 bool (*is_manageable)(struct pci_dev *dev); 80 int (*set_state)(struct pci_dev *dev, pci_power_t state); 81 pci_power_t (*get_state)(struct pci_dev *dev); 82 void (*refresh_state)(struct pci_dev *dev); 83 pci_power_t (*choose_state)(struct pci_dev *dev); 84 int (*set_wakeup)(struct pci_dev *dev, bool enable); 85 bool (*need_resume)(struct pci_dev *dev); 86 }; 87 88 int pci_set_platform_pm(const struct pci_platform_pm_ops *ops); 89 void pci_update_current_state(struct pci_dev *dev, pci_power_t state); 90 void pci_refresh_power_state(struct pci_dev *dev); 91 int pci_power_up(struct pci_dev *dev); 92 void pci_disable_enabled_device(struct pci_dev *dev); 93 int pci_finish_runtime_suspend(struct pci_dev *dev); 94 void pcie_clear_device_status(struct pci_dev *dev); 95 void pcie_clear_root_pme_status(struct pci_dev *dev); 96 bool pci_check_pme_status(struct pci_dev *dev); 97 void pci_pme_wakeup_bus(struct pci_bus *bus); 98 int __pci_pme_wakeup(struct pci_dev *dev, void *ign); 99 void pci_pme_restore(struct pci_dev *dev); 100 bool pci_dev_need_resume(struct pci_dev *dev); 101 void pci_dev_adjust_pme(struct pci_dev *dev); 102 void pci_dev_complete_resume(struct pci_dev *pci_dev); 103 void pci_config_pm_runtime_get(struct pci_dev *dev); 104 void pci_config_pm_runtime_put(struct pci_dev *dev); 105 void pci_pm_init(struct pci_dev *dev); 106 void pci_ea_init(struct pci_dev *dev); 107 void pci_msi_init(struct pci_dev *dev); 108 void pci_msix_init(struct pci_dev *dev); 109 void pci_allocate_cap_save_buffers(struct pci_dev *dev); 110 void pci_free_cap_save_buffers(struct pci_dev *dev); 111 bool pci_bridge_d3_possible(struct pci_dev *dev); 112 void pci_bridge_d3_update(struct pci_dev *dev); 113 void pci_bridge_wait_for_secondary_bus(struct pci_dev *dev); 114 115 static inline void pci_wakeup_event(struct pci_dev *dev) 116 { 117 /* Wait 100 ms before the system can be put into a sleep state. */ 118 pm_wakeup_event(&dev->dev, 100); 119 } 120 121 static inline bool pci_has_subordinate(struct pci_dev *pci_dev) 122 { 123 return !!(pci_dev->subordinate); 124 } 125 126 static inline bool pci_power_manageable(struct pci_dev *pci_dev) 127 { 128 /* 129 * Currently we allow normal PCI devices and PCI bridges transition 130 * into D3 if their bridge_d3 is set. 131 */ 132 return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3; 133 } 134 135 static inline bool pcie_downstream_port(const struct pci_dev *dev) 136 { 137 int type = pci_pcie_type(dev); 138 139 return type == PCI_EXP_TYPE_ROOT_PORT || 140 type == PCI_EXP_TYPE_DOWNSTREAM || 141 type == PCI_EXP_TYPE_PCIE_BRIDGE; 142 } 143 144 int pci_vpd_init(struct pci_dev *dev); 145 void pci_vpd_release(struct pci_dev *dev); 146 void pcie_vpd_create_sysfs_dev_files(struct pci_dev *dev); 147 void pcie_vpd_remove_sysfs_dev_files(struct pci_dev *dev); 148 149 /* PCI Virtual Channel */ 150 int pci_save_vc_state(struct pci_dev *dev); 151 void pci_restore_vc_state(struct pci_dev *dev); 152 void pci_allocate_vc_save_buffers(struct pci_dev *dev); 153 154 /* PCI /proc functions */ 155 #ifdef CONFIG_PROC_FS 156 int pci_proc_attach_device(struct pci_dev *dev); 157 int pci_proc_detach_device(struct pci_dev *dev); 158 int pci_proc_detach_bus(struct pci_bus *bus); 159 #else 160 static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; } 161 static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; } 162 static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; } 163 #endif 164 165 /* Functions for PCI Hotplug drivers to use */ 166 int pci_hp_add_bridge(struct pci_dev *dev); 167 168 #ifdef HAVE_PCI_LEGACY 169 void pci_create_legacy_files(struct pci_bus *bus); 170 void pci_remove_legacy_files(struct pci_bus *bus); 171 #else 172 static inline void pci_create_legacy_files(struct pci_bus *bus) { return; } 173 static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; } 174 #endif 175 176 /* Lock for read/write access to pci device and bus lists */ 177 extern struct rw_semaphore pci_bus_sem; 178 extern struct mutex pci_slot_mutex; 179 180 extern raw_spinlock_t pci_lock; 181 182 extern unsigned int pci_pm_d3hot_delay; 183 184 #ifdef CONFIG_PCI_MSI 185 void pci_no_msi(void); 186 #else 187 static inline void pci_no_msi(void) { } 188 #endif 189 190 void pci_realloc_get_opt(char *); 191 192 static inline int pci_no_d1d2(struct pci_dev *dev) 193 { 194 unsigned int parent_dstates = 0; 195 196 if (dev->bus->self) 197 parent_dstates = dev->bus->self->no_d1d2; 198 return (dev->no_d1d2 || parent_dstates); 199 200 } 201 extern const struct attribute_group *pci_dev_groups[]; 202 extern const struct attribute_group *pcibus_groups[]; 203 extern const struct device_type pci_dev_type; 204 extern const struct attribute_group *pci_bus_groups[]; 205 206 extern unsigned long pci_hotplug_io_size; 207 extern unsigned long pci_hotplug_mmio_size; 208 extern unsigned long pci_hotplug_mmio_pref_size; 209 extern unsigned long pci_hotplug_bus_size; 210 211 /** 212 * pci_match_one_device - Tell if a PCI device structure has a matching 213 * PCI device id structure 214 * @id: single PCI device id structure to match 215 * @dev: the PCI device structure to match against 216 * 217 * Returns the matching pci_device_id structure or %NULL if there is no match. 218 */ 219 static inline const struct pci_device_id * 220 pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev) 221 { 222 if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) && 223 (id->device == PCI_ANY_ID || id->device == dev->device) && 224 (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) && 225 (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) && 226 !((id->class ^ dev->class) & id->class_mask)) 227 return id; 228 return NULL; 229 } 230 231 /* PCI slot sysfs helper code */ 232 #define to_pci_slot(s) container_of(s, struct pci_slot, kobj) 233 234 extern struct kset *pci_slots_kset; 235 236 struct pci_slot_attribute { 237 struct attribute attr; 238 ssize_t (*show)(struct pci_slot *, char *); 239 ssize_t (*store)(struct pci_slot *, const char *, size_t); 240 }; 241 #define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr) 242 243 enum pci_bar_type { 244 pci_bar_unknown, /* Standard PCI BAR probe */ 245 pci_bar_io, /* An I/O port BAR */ 246 pci_bar_mem32, /* A 32-bit memory BAR */ 247 pci_bar_mem64, /* A 64-bit memory BAR */ 248 }; 249 250 struct device *pci_get_host_bridge_device(struct pci_dev *dev); 251 void pci_put_host_bridge_device(struct device *dev); 252 253 int pci_configure_extended_tags(struct pci_dev *dev, void *ign); 254 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, 255 int crs_timeout); 256 bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, 257 int crs_timeout); 258 int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int crs_timeout); 259 260 int pci_setup_device(struct pci_dev *dev); 261 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, 262 struct resource *res, unsigned int reg); 263 void pci_configure_ari(struct pci_dev *dev); 264 void __pci_bus_size_bridges(struct pci_bus *bus, 265 struct list_head *realloc_head); 266 void __pci_bus_assign_resources(const struct pci_bus *bus, 267 struct list_head *realloc_head, 268 struct list_head *fail_head); 269 bool pci_bus_clip_resource(struct pci_dev *dev, int idx); 270 271 void pci_reassigndev_resource_alignment(struct pci_dev *dev); 272 void pci_disable_bridge_window(struct pci_dev *dev); 273 struct pci_bus *pci_bus_get(struct pci_bus *bus); 274 void pci_bus_put(struct pci_bus *bus); 275 276 /* PCIe link information from Link Capabilities 2 */ 277 #define PCIE_LNKCAP2_SLS2SPEED(lnkcap2) \ 278 ((lnkcap2) & PCI_EXP_LNKCAP2_SLS_64_0GB ? PCIE_SPEED_64_0GT : \ 279 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_32_0GB ? PCIE_SPEED_32_0GT : \ 280 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_16_0GB ? PCIE_SPEED_16_0GT : \ 281 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_8_0GB ? PCIE_SPEED_8_0GT : \ 282 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_5_0GB ? PCIE_SPEED_5_0GT : \ 283 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_2_5GB ? PCIE_SPEED_2_5GT : \ 284 PCI_SPEED_UNKNOWN) 285 286 /* PCIe speed to Mb/s reduced by encoding overhead */ 287 #define PCIE_SPEED2MBS_ENC(speed) \ 288 ((speed) == PCIE_SPEED_64_0GT ? 64000*128/130 : \ 289 (speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \ 290 (speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \ 291 (speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \ 292 (speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \ 293 (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \ 294 0) 295 296 const char *pci_speed_string(enum pci_bus_speed speed); 297 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev); 298 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev); 299 u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed, 300 enum pcie_link_width *width); 301 void __pcie_print_link_status(struct pci_dev *dev, bool verbose); 302 void pcie_report_downtraining(struct pci_dev *dev); 303 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status); 304 305 /* Single Root I/O Virtualization */ 306 struct pci_sriov { 307 int pos; /* Capability position */ 308 int nres; /* Number of resources */ 309 u32 cap; /* SR-IOV Capabilities */ 310 u16 ctrl; /* SR-IOV Control */ 311 u16 total_VFs; /* Total VFs associated with the PF */ 312 u16 initial_VFs; /* Initial VFs associated with the PF */ 313 u16 num_VFs; /* Number of VFs available */ 314 u16 offset; /* First VF Routing ID offset */ 315 u16 stride; /* Following VF stride */ 316 u16 vf_device; /* VF device ID */ 317 u32 pgsz; /* Page size for BAR alignment */ 318 u8 link; /* Function Dependency Link */ 319 u8 max_VF_buses; /* Max buses consumed by VFs */ 320 u16 driver_max_VFs; /* Max num VFs driver supports */ 321 struct pci_dev *dev; /* Lowest numbered PF */ 322 struct pci_dev *self; /* This PF */ 323 u32 class; /* VF device */ 324 u8 hdr_type; /* VF header type */ 325 u16 subsystem_vendor; /* VF subsystem vendor */ 326 u16 subsystem_device; /* VF subsystem device */ 327 resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */ 328 bool drivers_autoprobe; /* Auto probing of VFs by driver */ 329 }; 330 331 /** 332 * pci_dev_set_io_state - Set the new error state if possible. 333 * 334 * @dev - pci device to set new error_state 335 * @new - the state we want dev to be in 336 * 337 * Must be called with device_lock held. 338 * 339 * Returns true if state has been changed to the requested state. 340 */ 341 static inline bool pci_dev_set_io_state(struct pci_dev *dev, 342 pci_channel_state_t new) 343 { 344 bool changed = false; 345 346 device_lock_assert(&dev->dev); 347 switch (new) { 348 case pci_channel_io_perm_failure: 349 switch (dev->error_state) { 350 case pci_channel_io_frozen: 351 case pci_channel_io_normal: 352 case pci_channel_io_perm_failure: 353 changed = true; 354 break; 355 } 356 break; 357 case pci_channel_io_frozen: 358 switch (dev->error_state) { 359 case pci_channel_io_frozen: 360 case pci_channel_io_normal: 361 changed = true; 362 break; 363 } 364 break; 365 case pci_channel_io_normal: 366 switch (dev->error_state) { 367 case pci_channel_io_frozen: 368 case pci_channel_io_normal: 369 changed = true; 370 break; 371 } 372 break; 373 } 374 if (changed) 375 dev->error_state = new; 376 return changed; 377 } 378 379 static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused) 380 { 381 device_lock(&dev->dev); 382 pci_dev_set_io_state(dev, pci_channel_io_perm_failure); 383 device_unlock(&dev->dev); 384 385 return 0; 386 } 387 388 static inline bool pci_dev_is_disconnected(const struct pci_dev *dev) 389 { 390 return dev->error_state == pci_channel_io_perm_failure; 391 } 392 393 /* pci_dev priv_flags */ 394 #define PCI_DEV_ADDED 0 395 396 static inline void pci_dev_assign_added(struct pci_dev *dev, bool added) 397 { 398 assign_bit(PCI_DEV_ADDED, &dev->priv_flags, added); 399 } 400 401 static inline bool pci_dev_is_added(const struct pci_dev *dev) 402 { 403 return test_bit(PCI_DEV_ADDED, &dev->priv_flags); 404 } 405 406 #ifdef CONFIG_PCIEAER 407 #include <linux/aer.h> 408 409 #define AER_MAX_MULTI_ERR_DEVICES 5 /* Not likely to have more */ 410 411 struct aer_err_info { 412 struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES]; 413 int error_dev_num; 414 415 unsigned int id:16; 416 417 unsigned int severity:2; /* 0:NONFATAL | 1:FATAL | 2:COR */ 418 unsigned int __pad1:5; 419 unsigned int multi_error_valid:1; 420 421 unsigned int first_error:5; 422 unsigned int __pad2:2; 423 unsigned int tlp_header_valid:1; 424 425 unsigned int status; /* COR/UNCOR Error Status */ 426 unsigned int mask; /* COR/UNCOR Error Mask */ 427 struct aer_header_log_regs tlp; /* TLP Header */ 428 }; 429 430 int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info); 431 void aer_print_error(struct pci_dev *dev, struct aer_err_info *info); 432 #endif /* CONFIG_PCIEAER */ 433 434 #ifdef CONFIG_PCIEPORTBUS 435 /* Cached RCEC Endpoint Association */ 436 struct rcec_ea { 437 u8 nextbusn; 438 u8 lastbusn; 439 u32 bitmap; 440 }; 441 #endif 442 443 #ifdef CONFIG_PCIE_DPC 444 void pci_save_dpc_state(struct pci_dev *dev); 445 void pci_restore_dpc_state(struct pci_dev *dev); 446 void pci_dpc_init(struct pci_dev *pdev); 447 void dpc_process_error(struct pci_dev *pdev); 448 pci_ers_result_t dpc_reset_link(struct pci_dev *pdev); 449 #else 450 static inline void pci_save_dpc_state(struct pci_dev *dev) {} 451 static inline void pci_restore_dpc_state(struct pci_dev *dev) {} 452 static inline void pci_dpc_init(struct pci_dev *pdev) {} 453 #endif 454 455 #ifdef CONFIG_PCIEPORTBUS 456 void pci_rcec_init(struct pci_dev *dev); 457 void pci_rcec_exit(struct pci_dev *dev); 458 void pcie_link_rcec(struct pci_dev *rcec); 459 void pcie_walk_rcec(struct pci_dev *rcec, 460 int (*cb)(struct pci_dev *, void *), 461 void *userdata); 462 #else 463 static inline void pci_rcec_init(struct pci_dev *dev) {} 464 static inline void pci_rcec_exit(struct pci_dev *dev) {} 465 static inline void pcie_link_rcec(struct pci_dev *rcec) {} 466 static inline void pcie_walk_rcec(struct pci_dev *rcec, 467 int (*cb)(struct pci_dev *, void *), 468 void *userdata) {} 469 #endif 470 471 #ifdef CONFIG_PCI_ATS 472 /* Address Translation Service */ 473 void pci_ats_init(struct pci_dev *dev); 474 void pci_restore_ats_state(struct pci_dev *dev); 475 #else 476 static inline void pci_ats_init(struct pci_dev *d) { } 477 static inline void pci_restore_ats_state(struct pci_dev *dev) { } 478 #endif /* CONFIG_PCI_ATS */ 479 480 #ifdef CONFIG_PCI_PRI 481 void pci_pri_init(struct pci_dev *dev); 482 void pci_restore_pri_state(struct pci_dev *pdev); 483 #else 484 static inline void pci_pri_init(struct pci_dev *dev) { } 485 static inline void pci_restore_pri_state(struct pci_dev *pdev) { } 486 #endif 487 488 #ifdef CONFIG_PCI_PASID 489 void pci_pasid_init(struct pci_dev *dev); 490 void pci_restore_pasid_state(struct pci_dev *pdev); 491 #else 492 static inline void pci_pasid_init(struct pci_dev *dev) { } 493 static inline void pci_restore_pasid_state(struct pci_dev *pdev) { } 494 #endif 495 496 #ifdef CONFIG_PCI_IOV 497 int pci_iov_init(struct pci_dev *dev); 498 void pci_iov_release(struct pci_dev *dev); 499 void pci_iov_remove(struct pci_dev *dev); 500 void pci_iov_update_resource(struct pci_dev *dev, int resno); 501 resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno); 502 void pci_restore_iov_state(struct pci_dev *dev); 503 int pci_iov_bus_range(struct pci_bus *bus); 504 extern const struct attribute_group sriov_dev_attr_group; 505 #else 506 static inline int pci_iov_init(struct pci_dev *dev) 507 { 508 return -ENODEV; 509 } 510 static inline void pci_iov_release(struct pci_dev *dev) 511 512 { 513 } 514 static inline void pci_iov_remove(struct pci_dev *dev) 515 { 516 } 517 static inline void pci_restore_iov_state(struct pci_dev *dev) 518 { 519 } 520 static inline int pci_iov_bus_range(struct pci_bus *bus) 521 { 522 return 0; 523 } 524 525 #endif /* CONFIG_PCI_IOV */ 526 527 #ifdef CONFIG_PCIE_PTM 528 void pci_save_ptm_state(struct pci_dev *dev); 529 void pci_restore_ptm_state(struct pci_dev *dev); 530 void pci_disable_ptm(struct pci_dev *dev); 531 #else 532 static inline void pci_save_ptm_state(struct pci_dev *dev) { } 533 static inline void pci_restore_ptm_state(struct pci_dev *dev) { } 534 static inline void pci_disable_ptm(struct pci_dev *dev) { } 535 #endif 536 537 unsigned long pci_cardbus_resource_alignment(struct resource *); 538 539 static inline resource_size_t pci_resource_alignment(struct pci_dev *dev, 540 struct resource *res) 541 { 542 #ifdef CONFIG_PCI_IOV 543 int resno = res - dev->resource; 544 545 if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END) 546 return pci_sriov_resource_alignment(dev, resno); 547 #endif 548 if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS) 549 return pci_cardbus_resource_alignment(res); 550 return resource_alignment(res); 551 } 552 553 void pci_acs_init(struct pci_dev *dev); 554 #ifdef CONFIG_PCI_QUIRKS 555 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags); 556 int pci_dev_specific_enable_acs(struct pci_dev *dev); 557 int pci_dev_specific_disable_acs_redir(struct pci_dev *dev); 558 #else 559 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev, 560 u16 acs_flags) 561 { 562 return -ENOTTY; 563 } 564 static inline int pci_dev_specific_enable_acs(struct pci_dev *dev) 565 { 566 return -ENOTTY; 567 } 568 static inline int pci_dev_specific_disable_acs_redir(struct pci_dev *dev) 569 { 570 return -ENOTTY; 571 } 572 #endif 573 574 /* PCI error reporting and recovery */ 575 pci_ers_result_t pcie_do_recovery(struct pci_dev *dev, 576 pci_channel_state_t state, 577 pci_ers_result_t (*reset_subordinates)(struct pci_dev *pdev)); 578 579 bool pcie_wait_for_link(struct pci_dev *pdev, bool active); 580 #ifdef CONFIG_PCIEASPM 581 void pcie_aspm_init_link_state(struct pci_dev *pdev); 582 void pcie_aspm_exit_link_state(struct pci_dev *pdev); 583 void pcie_aspm_pm_state_change(struct pci_dev *pdev); 584 void pcie_aspm_powersave_config_link(struct pci_dev *pdev); 585 #else 586 static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { } 587 static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { } 588 static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev) { } 589 static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { } 590 #endif 591 592 #ifdef CONFIG_PCIE_ECRC 593 void pcie_set_ecrc_checking(struct pci_dev *dev); 594 void pcie_ecrc_get_policy(char *str); 595 #else 596 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { } 597 static inline void pcie_ecrc_get_policy(char *str) { } 598 #endif 599 600 #ifdef CONFIG_PCIE_PTM 601 void pci_ptm_init(struct pci_dev *dev); 602 int pci_enable_ptm(struct pci_dev *dev, u8 *granularity); 603 #else 604 static inline void pci_ptm_init(struct pci_dev *dev) { } 605 static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity) 606 { return -EINVAL; } 607 #endif 608 609 struct pci_dev_reset_methods { 610 u16 vendor; 611 u16 device; 612 int (*reset)(struct pci_dev *dev, int probe); 613 }; 614 615 #ifdef CONFIG_PCI_QUIRKS 616 int pci_dev_specific_reset(struct pci_dev *dev, int probe); 617 #else 618 static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe) 619 { 620 return -ENOTTY; 621 } 622 #endif 623 624 #if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64) 625 int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment, 626 struct resource *res); 627 #endif 628 629 u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar); 630 int pci_rebar_get_current_size(struct pci_dev *pdev, int bar); 631 int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size); 632 static inline u64 pci_rebar_size_to_bytes(int size) 633 { 634 return 1ULL << (size + 20); 635 } 636 637 struct device_node; 638 639 #ifdef CONFIG_OF 640 int of_pci_parse_bus_range(struct device_node *node, struct resource *res); 641 int of_get_pci_domain_nr(struct device_node *node); 642 int of_pci_get_max_link_speed(struct device_node *node); 643 void pci_set_of_node(struct pci_dev *dev); 644 void pci_release_of_node(struct pci_dev *dev); 645 void pci_set_bus_of_node(struct pci_bus *bus); 646 void pci_release_bus_of_node(struct pci_bus *bus); 647 648 int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge); 649 650 #else 651 static inline int 652 of_pci_parse_bus_range(struct device_node *node, struct resource *res) 653 { 654 return -EINVAL; 655 } 656 657 static inline int 658 of_get_pci_domain_nr(struct device_node *node) 659 { 660 return -1; 661 } 662 663 static inline int 664 of_pci_get_max_link_speed(struct device_node *node) 665 { 666 return -EINVAL; 667 } 668 669 static inline void pci_set_of_node(struct pci_dev *dev) { } 670 static inline void pci_release_of_node(struct pci_dev *dev) { } 671 static inline void pci_set_bus_of_node(struct pci_bus *bus) { } 672 static inline void pci_release_bus_of_node(struct pci_bus *bus) { } 673 674 static inline int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge) 675 { 676 return 0; 677 } 678 679 #endif /* CONFIG_OF */ 680 681 #ifdef CONFIG_PCIEAER 682 void pci_no_aer(void); 683 void pci_aer_init(struct pci_dev *dev); 684 void pci_aer_exit(struct pci_dev *dev); 685 extern const struct attribute_group aer_stats_attr_group; 686 void pci_aer_clear_fatal_status(struct pci_dev *dev); 687 int pci_aer_clear_status(struct pci_dev *dev); 688 int pci_aer_raw_clear_status(struct pci_dev *dev); 689 #else 690 static inline void pci_no_aer(void) { } 691 static inline void pci_aer_init(struct pci_dev *d) { } 692 static inline void pci_aer_exit(struct pci_dev *d) { } 693 static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { } 694 static inline int pci_aer_clear_status(struct pci_dev *dev) { return -EINVAL; } 695 static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -EINVAL; } 696 #endif 697 698 #ifdef CONFIG_ACPI 699 int pci_acpi_program_hp_params(struct pci_dev *dev); 700 #else 701 static inline int pci_acpi_program_hp_params(struct pci_dev *dev) 702 { 703 return -ENODEV; 704 } 705 #endif 706 707 #ifdef CONFIG_PCIEASPM 708 extern const struct attribute_group aspm_ctrl_attr_group; 709 #endif 710 711 #endif /* DRIVERS_PCI_H */ 712