1 #ifndef DRIVERS_PCI_H 2 #define DRIVERS_PCI_H 3 4 #include <linux/workqueue.h> 5 6 #define PCI_CFG_SPACE_SIZE 256 7 #define PCI_CFG_SPACE_EXP_SIZE 4096 8 9 /* Functions internal to the PCI core code */ 10 11 extern int pci_uevent(struct device *dev, struct kobj_uevent_env *env); 12 extern int pci_create_sysfs_dev_files(struct pci_dev *pdev); 13 extern void pci_remove_sysfs_dev_files(struct pci_dev *pdev); 14 #if !defined(CONFIG_DMI) && !defined(CONFIG_ACPI) 15 static inline void pci_create_firmware_label_files(struct pci_dev *pdev) 16 { return; } 17 static inline void pci_remove_firmware_label_files(struct pci_dev *pdev) 18 { return; } 19 #else 20 extern void pci_create_firmware_label_files(struct pci_dev *pdev); 21 extern void pci_remove_firmware_label_files(struct pci_dev *pdev); 22 #endif 23 extern void pci_cleanup_rom(struct pci_dev *dev); 24 #ifdef HAVE_PCI_MMAP 25 enum pci_mmap_api { 26 PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */ 27 PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */ 28 }; 29 extern int pci_mmap_fits(struct pci_dev *pdev, int resno, 30 struct vm_area_struct *vmai, 31 enum pci_mmap_api mmap_api); 32 #endif 33 int pci_probe_reset_function(struct pci_dev *dev); 34 35 /** 36 * struct pci_platform_pm_ops - Firmware PM callbacks 37 * 38 * @is_manageable: returns 'true' if given device is power manageable by the 39 * platform firmware 40 * 41 * @set_state: invokes the platform firmware to set the device's power state 42 * 43 * @choose_state: returns PCI power state of given device preferred by the 44 * platform; to be used during system-wide transitions from a 45 * sleeping state to the working state and vice versa 46 * 47 * @can_wakeup: returns 'true' if given device is capable of waking up the 48 * system from a sleeping state 49 * 50 * @sleep_wake: enables/disables the system wake up capability of given device 51 * 52 * @run_wake: enables/disables the platform to generate run-time wake-up events 53 * for given device (the device's wake-up capability has to be 54 * enabled by @sleep_wake for this feature to work) 55 * 56 * If given platform is generally capable of power managing PCI devices, all of 57 * these callbacks are mandatory. 58 */ 59 struct pci_platform_pm_ops { 60 bool (*is_manageable)(struct pci_dev *dev); 61 int (*set_state)(struct pci_dev *dev, pci_power_t state); 62 pci_power_t (*choose_state)(struct pci_dev *dev); 63 bool (*can_wakeup)(struct pci_dev *dev); 64 int (*sleep_wake)(struct pci_dev *dev, bool enable); 65 int (*run_wake)(struct pci_dev *dev, bool enable); 66 }; 67 68 extern int pci_set_platform_pm(struct pci_platform_pm_ops *ops); 69 extern void pci_update_current_state(struct pci_dev *dev, pci_power_t state); 70 extern void pci_disable_enabled_device(struct pci_dev *dev); 71 extern int pci_finish_runtime_suspend(struct pci_dev *dev); 72 extern int __pci_pme_wakeup(struct pci_dev *dev, void *ign); 73 extern void pci_pm_init(struct pci_dev *dev); 74 extern void platform_pci_wakeup_init(struct pci_dev *dev); 75 extern void pci_allocate_cap_save_buffers(struct pci_dev *dev); 76 void pci_free_cap_save_buffers(struct pci_dev *dev); 77 78 static inline void pci_wakeup_event(struct pci_dev *dev) 79 { 80 /* Wait 100 ms before the system can be put into a sleep state. */ 81 pm_wakeup_event(&dev->dev, 100); 82 } 83 84 static inline bool pci_is_bridge(struct pci_dev *pci_dev) 85 { 86 return !!(pci_dev->subordinate); 87 } 88 89 extern int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val); 90 extern int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val); 91 extern int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val); 92 extern int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val); 93 extern int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val); 94 extern int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val); 95 96 struct pci_vpd_ops { 97 ssize_t (*read)(struct pci_dev *dev, loff_t pos, size_t count, void *buf); 98 ssize_t (*write)(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); 99 void (*release)(struct pci_dev *dev); 100 }; 101 102 struct pci_vpd { 103 unsigned int len; 104 const struct pci_vpd_ops *ops; 105 struct bin_attribute *attr; /* descriptor for sysfs VPD entry */ 106 }; 107 108 extern int pci_vpd_pci22_init(struct pci_dev *dev); 109 static inline void pci_vpd_release(struct pci_dev *dev) 110 { 111 if (dev->vpd) 112 dev->vpd->ops->release(dev); 113 } 114 115 /* PCI /proc functions */ 116 #ifdef CONFIG_PROC_FS 117 extern int pci_proc_attach_device(struct pci_dev *dev); 118 extern int pci_proc_detach_device(struct pci_dev *dev); 119 extern int pci_proc_detach_bus(struct pci_bus *bus); 120 #else 121 static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; } 122 static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; } 123 static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; } 124 #endif 125 126 /* Functions for PCI Hotplug drivers to use */ 127 extern unsigned int pci_do_scan_bus(struct pci_bus *bus); 128 129 #ifdef HAVE_PCI_LEGACY 130 extern void pci_create_legacy_files(struct pci_bus *bus); 131 extern void pci_remove_legacy_files(struct pci_bus *bus); 132 #else 133 static inline void pci_create_legacy_files(struct pci_bus *bus) { return; } 134 static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; } 135 #endif 136 137 /* Lock for read/write access to pci device and bus lists */ 138 extern struct rw_semaphore pci_bus_sem; 139 140 extern raw_spinlock_t pci_lock; 141 142 extern unsigned int pci_pm_d3_delay; 143 144 #ifdef CONFIG_PCI_MSI 145 void pci_no_msi(void); 146 extern void pci_msi_init_pci_dev(struct pci_dev *dev); 147 #else 148 static inline void pci_no_msi(void) { } 149 static inline void pci_msi_init_pci_dev(struct pci_dev *dev) { } 150 #endif 151 152 void pci_realloc_get_opt(char *); 153 154 static inline int pci_no_d1d2(struct pci_dev *dev) 155 { 156 unsigned int parent_dstates = 0; 157 158 if (dev->bus->self) 159 parent_dstates = dev->bus->self->no_d1d2; 160 return (dev->no_d1d2 || parent_dstates); 161 162 } 163 extern struct device_attribute pci_dev_attrs[]; 164 extern struct device_attribute pcibus_dev_attrs[]; 165 #ifdef CONFIG_HOTPLUG 166 extern struct bus_attribute pci_bus_attrs[]; 167 #else 168 #define pci_bus_attrs NULL 169 #endif 170 171 172 /** 173 * pci_match_one_device - Tell if a PCI device structure has a matching 174 * PCI device id structure 175 * @id: single PCI device id structure to match 176 * @dev: the PCI device structure to match against 177 * 178 * Returns the matching pci_device_id structure or %NULL if there is no match. 179 */ 180 static inline const struct pci_device_id * 181 pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev) 182 { 183 if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) && 184 (id->device == PCI_ANY_ID || id->device == dev->device) && 185 (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) && 186 (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) && 187 !((id->class ^ dev->class) & id->class_mask)) 188 return id; 189 return NULL; 190 } 191 192 /* PCI slot sysfs helper code */ 193 #define to_pci_slot(s) container_of(s, struct pci_slot, kobj) 194 195 extern struct kset *pci_slots_kset; 196 197 struct pci_slot_attribute { 198 struct attribute attr; 199 ssize_t (*show)(struct pci_slot *, char *); 200 ssize_t (*store)(struct pci_slot *, const char *, size_t); 201 }; 202 #define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr) 203 204 enum pci_bar_type { 205 pci_bar_unknown, /* Standard PCI BAR probe */ 206 pci_bar_io, /* An io port BAR */ 207 pci_bar_mem32, /* A 32-bit memory BAR */ 208 pci_bar_mem64, /* A 64-bit memory BAR */ 209 }; 210 211 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, 212 int crs_timeout); 213 extern int pci_setup_device(struct pci_dev *dev); 214 extern int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, 215 struct resource *res, unsigned int reg); 216 extern int pci_resource_bar(struct pci_dev *dev, int resno, 217 enum pci_bar_type *type); 218 extern int pci_bus_add_child(struct pci_bus *bus); 219 extern void pci_enable_ari(struct pci_dev *dev); 220 /** 221 * pci_ari_enabled - query ARI forwarding status 222 * @bus: the PCI bus 223 * 224 * Returns 1 if ARI forwarding is enabled, or 0 if not enabled; 225 */ 226 static inline int pci_ari_enabled(struct pci_bus *bus) 227 { 228 return bus->self && bus->self->ari_enabled; 229 } 230 231 void pci_reassigndev_resource_alignment(struct pci_dev *dev); 232 extern void pci_disable_bridge_window(struct pci_dev *dev); 233 234 /* Single Root I/O Virtualization */ 235 struct pci_sriov { 236 int pos; /* capability position */ 237 int nres; /* number of resources */ 238 u32 cap; /* SR-IOV Capabilities */ 239 u16 ctrl; /* SR-IOV Control */ 240 u16 total; /* total VFs associated with the PF */ 241 u16 initial; /* initial VFs associated with the PF */ 242 u16 nr_virtfn; /* number of VFs available */ 243 u16 offset; /* first VF Routing ID offset */ 244 u16 stride; /* following VF stride */ 245 u32 pgsz; /* page size for BAR alignment */ 246 u8 link; /* Function Dependency Link */ 247 struct pci_dev *dev; /* lowest numbered PF */ 248 struct pci_dev *self; /* this PF */ 249 struct mutex lock; /* lock for VF bus */ 250 struct work_struct mtask; /* VF Migration task */ 251 u8 __iomem *mstate; /* VF Migration State Array */ 252 }; 253 254 #ifdef CONFIG_PCI_ATS 255 extern void pci_restore_ats_state(struct pci_dev *dev); 256 #else 257 static inline void pci_restore_ats_state(struct pci_dev *dev) 258 { 259 } 260 #endif /* CONFIG_PCI_ATS */ 261 262 #ifdef CONFIG_PCI_IOV 263 extern int pci_iov_init(struct pci_dev *dev); 264 extern void pci_iov_release(struct pci_dev *dev); 265 extern int pci_iov_resource_bar(struct pci_dev *dev, int resno, 266 enum pci_bar_type *type); 267 extern resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, 268 int resno); 269 extern void pci_restore_iov_state(struct pci_dev *dev); 270 extern int pci_iov_bus_range(struct pci_bus *bus); 271 272 #else 273 static inline int pci_iov_init(struct pci_dev *dev) 274 { 275 return -ENODEV; 276 } 277 static inline void pci_iov_release(struct pci_dev *dev) 278 279 { 280 } 281 static inline int pci_iov_resource_bar(struct pci_dev *dev, int resno, 282 enum pci_bar_type *type) 283 { 284 return 0; 285 } 286 static inline void pci_restore_iov_state(struct pci_dev *dev) 287 { 288 } 289 static inline int pci_iov_bus_range(struct pci_bus *bus) 290 { 291 return 0; 292 } 293 294 #endif /* CONFIG_PCI_IOV */ 295 296 extern unsigned long pci_cardbus_resource_alignment(struct resource *); 297 298 static inline resource_size_t pci_resource_alignment(struct pci_dev *dev, 299 struct resource *res) 300 { 301 #ifdef CONFIG_PCI_IOV 302 int resno = res - dev->resource; 303 304 if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END) 305 return pci_sriov_resource_alignment(dev, resno); 306 #endif 307 if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS) 308 return pci_cardbus_resource_alignment(res); 309 return resource_alignment(res); 310 } 311 312 extern void pci_enable_acs(struct pci_dev *dev); 313 314 struct pci_dev_reset_methods { 315 u16 vendor; 316 u16 device; 317 int (*reset)(struct pci_dev *dev, int probe); 318 }; 319 320 #ifdef CONFIG_PCI_QUIRKS 321 extern int pci_dev_specific_reset(struct pci_dev *dev, int probe); 322 #else 323 static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe) 324 { 325 return -ENOTTY; 326 } 327 #endif 328 329 #endif /* DRIVERS_PCI_H */ 330