1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef DRIVERS_PCI_H 3 #define DRIVERS_PCI_H 4 5 #include <linux/pci.h> 6 7 /* Number of possible devfns: 0.0 to 1f.7 inclusive */ 8 #define MAX_NR_DEVFNS 256 9 10 #define PCI_FIND_CAP_TTL 48 11 12 #define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */ 13 14 extern const unsigned char pcie_link_speed[]; 15 extern bool pci_early_dump; 16 17 bool pcie_cap_has_lnkctl(const struct pci_dev *dev); 18 bool pcie_cap_has_rtctl(const struct pci_dev *dev); 19 20 /* Functions internal to the PCI core code */ 21 22 int pci_create_sysfs_dev_files(struct pci_dev *pdev); 23 void pci_remove_sysfs_dev_files(struct pci_dev *pdev); 24 #if !defined(CONFIG_DMI) && !defined(CONFIG_ACPI) 25 static inline void pci_create_firmware_label_files(struct pci_dev *pdev) 26 { return; } 27 static inline void pci_remove_firmware_label_files(struct pci_dev *pdev) 28 { return; } 29 #else 30 void pci_create_firmware_label_files(struct pci_dev *pdev); 31 void pci_remove_firmware_label_files(struct pci_dev *pdev); 32 #endif 33 void pci_cleanup_rom(struct pci_dev *dev); 34 35 enum pci_mmap_api { 36 PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */ 37 PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */ 38 }; 39 int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai, 40 enum pci_mmap_api mmap_api); 41 42 int pci_probe_reset_function(struct pci_dev *dev); 43 int pci_bridge_secondary_bus_reset(struct pci_dev *dev); 44 int pci_bus_error_reset(struct pci_dev *dev); 45 46 #define PCI_PM_D2_DELAY 200 47 #define PCI_PM_D3_WAIT 10 48 #define PCI_PM_D3COLD_WAIT 100 49 #define PCI_PM_BUS_WAIT 50 50 51 /** 52 * struct pci_platform_pm_ops - Firmware PM callbacks 53 * 54 * @bridge_d3: Does the bridge allow entering into D3 55 * 56 * @is_manageable: returns 'true' if given device is power manageable by the 57 * platform firmware 58 * 59 * @set_state: invokes the platform firmware to set the device's power state 60 * 61 * @get_state: queries the platform firmware for a device's current power state 62 * 63 * @refresh_state: asks the platform to refresh the device's power state data 64 * 65 * @choose_state: returns PCI power state of given device preferred by the 66 * platform; to be used during system-wide transitions from a 67 * sleeping state to the working state and vice versa 68 * 69 * @set_wakeup: enables/disables wakeup capability for the device 70 * 71 * @need_resume: returns 'true' if the given device (which is currently 72 * suspended) needs to be resumed to be configured for system 73 * wakeup. 74 * 75 * If given platform is generally capable of power managing PCI devices, all of 76 * these callbacks are mandatory. 77 */ 78 struct pci_platform_pm_ops { 79 bool (*bridge_d3)(struct pci_dev *dev); 80 bool (*is_manageable)(struct pci_dev *dev); 81 int (*set_state)(struct pci_dev *dev, pci_power_t state); 82 pci_power_t (*get_state)(struct pci_dev *dev); 83 void (*refresh_state)(struct pci_dev *dev); 84 pci_power_t (*choose_state)(struct pci_dev *dev); 85 int (*set_wakeup)(struct pci_dev *dev, bool enable); 86 bool (*need_resume)(struct pci_dev *dev); 87 }; 88 89 int pci_set_platform_pm(const struct pci_platform_pm_ops *ops); 90 void pci_update_current_state(struct pci_dev *dev, pci_power_t state); 91 void pci_refresh_power_state(struct pci_dev *dev); 92 int pci_power_up(struct pci_dev *dev); 93 void pci_disable_enabled_device(struct pci_dev *dev); 94 int pci_finish_runtime_suspend(struct pci_dev *dev); 95 void pcie_clear_device_status(struct pci_dev *dev); 96 void pcie_clear_root_pme_status(struct pci_dev *dev); 97 bool pci_check_pme_status(struct pci_dev *dev); 98 void pci_pme_wakeup_bus(struct pci_bus *bus); 99 int __pci_pme_wakeup(struct pci_dev *dev, void *ign); 100 void pci_pme_restore(struct pci_dev *dev); 101 bool pci_dev_need_resume(struct pci_dev *dev); 102 void pci_dev_adjust_pme(struct pci_dev *dev); 103 void pci_dev_complete_resume(struct pci_dev *pci_dev); 104 void pci_config_pm_runtime_get(struct pci_dev *dev); 105 void pci_config_pm_runtime_put(struct pci_dev *dev); 106 void pci_pm_init(struct pci_dev *dev); 107 void pci_ea_init(struct pci_dev *dev); 108 void pci_allocate_cap_save_buffers(struct pci_dev *dev); 109 void pci_free_cap_save_buffers(struct pci_dev *dev); 110 bool pci_bridge_d3_possible(struct pci_dev *dev); 111 void pci_bridge_d3_update(struct pci_dev *dev); 112 void pci_bridge_wait_for_secondary_bus(struct pci_dev *dev); 113 114 static inline void pci_wakeup_event(struct pci_dev *dev) 115 { 116 /* Wait 100 ms before the system can be put into a sleep state. */ 117 pm_wakeup_event(&dev->dev, 100); 118 } 119 120 static inline bool pci_has_subordinate(struct pci_dev *pci_dev) 121 { 122 return !!(pci_dev->subordinate); 123 } 124 125 static inline bool pci_power_manageable(struct pci_dev *pci_dev) 126 { 127 /* 128 * Currently we allow normal PCI devices and PCI bridges transition 129 * into D3 if their bridge_d3 is set. 130 */ 131 return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3; 132 } 133 134 static inline bool pcie_downstream_port(const struct pci_dev *dev) 135 { 136 int type = pci_pcie_type(dev); 137 138 return type == PCI_EXP_TYPE_ROOT_PORT || 139 type == PCI_EXP_TYPE_DOWNSTREAM || 140 type == PCI_EXP_TYPE_PCIE_BRIDGE; 141 } 142 143 int pci_vpd_init(struct pci_dev *dev); 144 void pci_vpd_release(struct pci_dev *dev); 145 void pcie_vpd_create_sysfs_dev_files(struct pci_dev *dev); 146 void pcie_vpd_remove_sysfs_dev_files(struct pci_dev *dev); 147 148 /* PCI Virtual Channel */ 149 int pci_save_vc_state(struct pci_dev *dev); 150 void pci_restore_vc_state(struct pci_dev *dev); 151 void pci_allocate_vc_save_buffers(struct pci_dev *dev); 152 153 /* PCI /proc functions */ 154 #ifdef CONFIG_PROC_FS 155 int pci_proc_attach_device(struct pci_dev *dev); 156 int pci_proc_detach_device(struct pci_dev *dev); 157 int pci_proc_detach_bus(struct pci_bus *bus); 158 #else 159 static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; } 160 static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; } 161 static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; } 162 #endif 163 164 /* Functions for PCI Hotplug drivers to use */ 165 int pci_hp_add_bridge(struct pci_dev *dev); 166 167 #ifdef HAVE_PCI_LEGACY 168 void pci_create_legacy_files(struct pci_bus *bus); 169 void pci_remove_legacy_files(struct pci_bus *bus); 170 #else 171 static inline void pci_create_legacy_files(struct pci_bus *bus) { return; } 172 static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; } 173 #endif 174 175 /* Lock for read/write access to pci device and bus lists */ 176 extern struct rw_semaphore pci_bus_sem; 177 extern struct mutex pci_slot_mutex; 178 179 extern raw_spinlock_t pci_lock; 180 181 extern unsigned int pci_pm_d3_delay; 182 183 #ifdef CONFIG_PCI_MSI 184 void pci_no_msi(void); 185 #else 186 static inline void pci_no_msi(void) { } 187 #endif 188 189 static inline void pci_msi_set_enable(struct pci_dev *dev, int enable) 190 { 191 u16 control; 192 193 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); 194 control &= ~PCI_MSI_FLAGS_ENABLE; 195 if (enable) 196 control |= PCI_MSI_FLAGS_ENABLE; 197 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); 198 } 199 200 static inline void pci_msix_clear_and_set_ctrl(struct pci_dev *dev, u16 clear, u16 set) 201 { 202 u16 ctrl; 203 204 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl); 205 ctrl &= ~clear; 206 ctrl |= set; 207 pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, ctrl); 208 } 209 210 void pci_realloc_get_opt(char *); 211 212 static inline int pci_no_d1d2(struct pci_dev *dev) 213 { 214 unsigned int parent_dstates = 0; 215 216 if (dev->bus->self) 217 parent_dstates = dev->bus->self->no_d1d2; 218 return (dev->no_d1d2 || parent_dstates); 219 220 } 221 extern const struct attribute_group *pci_dev_groups[]; 222 extern const struct attribute_group *pcibus_groups[]; 223 extern const struct device_type pci_dev_type; 224 extern const struct attribute_group *pci_bus_groups[]; 225 226 extern unsigned long pci_hotplug_io_size; 227 extern unsigned long pci_hotplug_mmio_size; 228 extern unsigned long pci_hotplug_mmio_pref_size; 229 extern unsigned long pci_hotplug_bus_size; 230 231 /** 232 * pci_match_one_device - Tell if a PCI device structure has a matching 233 * PCI device id structure 234 * @id: single PCI device id structure to match 235 * @dev: the PCI device structure to match against 236 * 237 * Returns the matching pci_device_id structure or %NULL if there is no match. 238 */ 239 static inline const struct pci_device_id * 240 pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev) 241 { 242 if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) && 243 (id->device == PCI_ANY_ID || id->device == dev->device) && 244 (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) && 245 (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) && 246 !((id->class ^ dev->class) & id->class_mask)) 247 return id; 248 return NULL; 249 } 250 251 /* PCI slot sysfs helper code */ 252 #define to_pci_slot(s) container_of(s, struct pci_slot, kobj) 253 254 extern struct kset *pci_slots_kset; 255 256 struct pci_slot_attribute { 257 struct attribute attr; 258 ssize_t (*show)(struct pci_slot *, char *); 259 ssize_t (*store)(struct pci_slot *, const char *, size_t); 260 }; 261 #define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr) 262 263 enum pci_bar_type { 264 pci_bar_unknown, /* Standard PCI BAR probe */ 265 pci_bar_io, /* An I/O port BAR */ 266 pci_bar_mem32, /* A 32-bit memory BAR */ 267 pci_bar_mem64, /* A 64-bit memory BAR */ 268 }; 269 270 struct device *pci_get_host_bridge_device(struct pci_dev *dev); 271 void pci_put_host_bridge_device(struct device *dev); 272 273 int pci_configure_extended_tags(struct pci_dev *dev, void *ign); 274 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, 275 int crs_timeout); 276 bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, 277 int crs_timeout); 278 int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int crs_timeout); 279 280 int pci_setup_device(struct pci_dev *dev); 281 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, 282 struct resource *res, unsigned int reg); 283 void pci_configure_ari(struct pci_dev *dev); 284 void __pci_bus_size_bridges(struct pci_bus *bus, 285 struct list_head *realloc_head); 286 void __pci_bus_assign_resources(const struct pci_bus *bus, 287 struct list_head *realloc_head, 288 struct list_head *fail_head); 289 bool pci_bus_clip_resource(struct pci_dev *dev, int idx); 290 291 void pci_reassigndev_resource_alignment(struct pci_dev *dev); 292 void pci_disable_bridge_window(struct pci_dev *dev); 293 struct pci_bus *pci_bus_get(struct pci_bus *bus); 294 void pci_bus_put(struct pci_bus *bus); 295 296 /* PCIe link information from Link Capabilities 2 */ 297 #define PCIE_LNKCAP2_SLS2SPEED(lnkcap2) \ 298 ((lnkcap2) & PCI_EXP_LNKCAP2_SLS_32_0GB ? PCIE_SPEED_32_0GT : \ 299 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_16_0GB ? PCIE_SPEED_16_0GT : \ 300 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_8_0GB ? PCIE_SPEED_8_0GT : \ 301 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_5_0GB ? PCIE_SPEED_5_0GT : \ 302 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_2_5GB ? PCIE_SPEED_2_5GT : \ 303 PCI_SPEED_UNKNOWN) 304 305 /* PCIe speed to Mb/s reduced by encoding overhead */ 306 #define PCIE_SPEED2MBS_ENC(speed) \ 307 ((speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \ 308 (speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \ 309 (speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \ 310 (speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \ 311 (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \ 312 0) 313 314 const char *pci_speed_string(enum pci_bus_speed speed); 315 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev); 316 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev); 317 u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed, 318 enum pcie_link_width *width); 319 void __pcie_print_link_status(struct pci_dev *dev, bool verbose); 320 void pcie_report_downtraining(struct pci_dev *dev); 321 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status); 322 323 /* Single Root I/O Virtualization */ 324 struct pci_sriov { 325 int pos; /* Capability position */ 326 int nres; /* Number of resources */ 327 u32 cap; /* SR-IOV Capabilities */ 328 u16 ctrl; /* SR-IOV Control */ 329 u16 total_VFs; /* Total VFs associated with the PF */ 330 u16 initial_VFs; /* Initial VFs associated with the PF */ 331 u16 num_VFs; /* Number of VFs available */ 332 u16 offset; /* First VF Routing ID offset */ 333 u16 stride; /* Following VF stride */ 334 u16 vf_device; /* VF device ID */ 335 u32 pgsz; /* Page size for BAR alignment */ 336 u8 link; /* Function Dependency Link */ 337 u8 max_VF_buses; /* Max buses consumed by VFs */ 338 u16 driver_max_VFs; /* Max num VFs driver supports */ 339 struct pci_dev *dev; /* Lowest numbered PF */ 340 struct pci_dev *self; /* This PF */ 341 u32 class; /* VF device */ 342 u8 hdr_type; /* VF header type */ 343 u16 subsystem_vendor; /* VF subsystem vendor */ 344 u16 subsystem_device; /* VF subsystem device */ 345 resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */ 346 bool drivers_autoprobe; /* Auto probing of VFs by driver */ 347 }; 348 349 /** 350 * pci_dev_set_io_state - Set the new error state if possible. 351 * 352 * @dev - pci device to set new error_state 353 * @new - the state we want dev to be in 354 * 355 * Must be called with device_lock held. 356 * 357 * Returns true if state has been changed to the requested state. 358 */ 359 static inline bool pci_dev_set_io_state(struct pci_dev *dev, 360 pci_channel_state_t new) 361 { 362 bool changed = false; 363 364 device_lock_assert(&dev->dev); 365 switch (new) { 366 case pci_channel_io_perm_failure: 367 switch (dev->error_state) { 368 case pci_channel_io_frozen: 369 case pci_channel_io_normal: 370 case pci_channel_io_perm_failure: 371 changed = true; 372 break; 373 } 374 break; 375 case pci_channel_io_frozen: 376 switch (dev->error_state) { 377 case pci_channel_io_frozen: 378 case pci_channel_io_normal: 379 changed = true; 380 break; 381 } 382 break; 383 case pci_channel_io_normal: 384 switch (dev->error_state) { 385 case pci_channel_io_frozen: 386 case pci_channel_io_normal: 387 changed = true; 388 break; 389 } 390 break; 391 } 392 if (changed) 393 dev->error_state = new; 394 return changed; 395 } 396 397 static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused) 398 { 399 device_lock(&dev->dev); 400 pci_dev_set_io_state(dev, pci_channel_io_perm_failure); 401 device_unlock(&dev->dev); 402 403 return 0; 404 } 405 406 static inline bool pci_dev_is_disconnected(const struct pci_dev *dev) 407 { 408 return dev->error_state == pci_channel_io_perm_failure; 409 } 410 411 /* pci_dev priv_flags */ 412 #define PCI_DEV_ADDED 0 413 414 static inline void pci_dev_assign_added(struct pci_dev *dev, bool added) 415 { 416 assign_bit(PCI_DEV_ADDED, &dev->priv_flags, added); 417 } 418 419 static inline bool pci_dev_is_added(const struct pci_dev *dev) 420 { 421 return test_bit(PCI_DEV_ADDED, &dev->priv_flags); 422 } 423 424 #ifdef CONFIG_PCIEAER 425 #include <linux/aer.h> 426 427 #define AER_MAX_MULTI_ERR_DEVICES 5 /* Not likely to have more */ 428 429 struct aer_err_info { 430 struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES]; 431 int error_dev_num; 432 433 unsigned int id:16; 434 435 unsigned int severity:2; /* 0:NONFATAL | 1:FATAL | 2:COR */ 436 unsigned int __pad1:5; 437 unsigned int multi_error_valid:1; 438 439 unsigned int first_error:5; 440 unsigned int __pad2:2; 441 unsigned int tlp_header_valid:1; 442 443 unsigned int status; /* COR/UNCOR Error Status */ 444 unsigned int mask; /* COR/UNCOR Error Mask */ 445 struct aer_header_log_regs tlp; /* TLP Header */ 446 }; 447 448 int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info); 449 void aer_print_error(struct pci_dev *dev, struct aer_err_info *info); 450 #endif /* CONFIG_PCIEAER */ 451 452 #ifdef CONFIG_PCIE_DPC 453 void pci_save_dpc_state(struct pci_dev *dev); 454 void pci_restore_dpc_state(struct pci_dev *dev); 455 void pci_dpc_init(struct pci_dev *pdev); 456 void dpc_process_error(struct pci_dev *pdev); 457 pci_ers_result_t dpc_reset_link(struct pci_dev *pdev); 458 #else 459 static inline void pci_save_dpc_state(struct pci_dev *dev) {} 460 static inline void pci_restore_dpc_state(struct pci_dev *dev) {} 461 static inline void pci_dpc_init(struct pci_dev *pdev) {} 462 #endif 463 464 #ifdef CONFIG_PCI_ATS 465 /* Address Translation Service */ 466 void pci_ats_init(struct pci_dev *dev); 467 void pci_restore_ats_state(struct pci_dev *dev); 468 #else 469 static inline void pci_ats_init(struct pci_dev *d) { } 470 static inline void pci_restore_ats_state(struct pci_dev *dev) { } 471 #endif /* CONFIG_PCI_ATS */ 472 473 #ifdef CONFIG_PCI_PRI 474 void pci_pri_init(struct pci_dev *dev); 475 void pci_restore_pri_state(struct pci_dev *pdev); 476 #else 477 static inline void pci_pri_init(struct pci_dev *dev) { } 478 static inline void pci_restore_pri_state(struct pci_dev *pdev) { } 479 #endif 480 481 #ifdef CONFIG_PCI_PASID 482 void pci_pasid_init(struct pci_dev *dev); 483 void pci_restore_pasid_state(struct pci_dev *pdev); 484 #else 485 static inline void pci_pasid_init(struct pci_dev *dev) { } 486 static inline void pci_restore_pasid_state(struct pci_dev *pdev) { } 487 #endif 488 489 #ifdef CONFIG_PCI_IOV 490 int pci_iov_init(struct pci_dev *dev); 491 void pci_iov_release(struct pci_dev *dev); 492 void pci_iov_remove(struct pci_dev *dev); 493 void pci_iov_update_resource(struct pci_dev *dev, int resno); 494 resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno); 495 void pci_restore_iov_state(struct pci_dev *dev); 496 int pci_iov_bus_range(struct pci_bus *bus); 497 extern const struct attribute_group sriov_dev_attr_group; 498 #else 499 static inline int pci_iov_init(struct pci_dev *dev) 500 { 501 return -ENODEV; 502 } 503 static inline void pci_iov_release(struct pci_dev *dev) 504 505 { 506 } 507 static inline void pci_iov_remove(struct pci_dev *dev) 508 { 509 } 510 static inline void pci_restore_iov_state(struct pci_dev *dev) 511 { 512 } 513 static inline int pci_iov_bus_range(struct pci_bus *bus) 514 { 515 return 0; 516 } 517 518 #endif /* CONFIG_PCI_IOV */ 519 520 unsigned long pci_cardbus_resource_alignment(struct resource *); 521 522 static inline resource_size_t pci_resource_alignment(struct pci_dev *dev, 523 struct resource *res) 524 { 525 #ifdef CONFIG_PCI_IOV 526 int resno = res - dev->resource; 527 528 if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END) 529 return pci_sriov_resource_alignment(dev, resno); 530 #endif 531 if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS) 532 return pci_cardbus_resource_alignment(res); 533 return resource_alignment(res); 534 } 535 536 void pci_acs_init(struct pci_dev *dev); 537 #ifdef CONFIG_PCI_QUIRKS 538 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags); 539 int pci_dev_specific_enable_acs(struct pci_dev *dev); 540 int pci_dev_specific_disable_acs_redir(struct pci_dev *dev); 541 #else 542 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev, 543 u16 acs_flags) 544 { 545 return -ENOTTY; 546 } 547 static inline int pci_dev_specific_enable_acs(struct pci_dev *dev) 548 { 549 return -ENOTTY; 550 } 551 static inline int pci_dev_specific_disable_acs_redir(struct pci_dev *dev) 552 { 553 return -ENOTTY; 554 } 555 #endif 556 557 /* PCI error reporting and recovery */ 558 pci_ers_result_t pcie_do_recovery(struct pci_dev *dev, 559 pci_channel_state_t state, 560 pci_ers_result_t (*reset_link)(struct pci_dev *pdev)); 561 562 bool pcie_wait_for_link(struct pci_dev *pdev, bool active); 563 #ifdef CONFIG_PCIEASPM 564 void pcie_aspm_init_link_state(struct pci_dev *pdev); 565 void pcie_aspm_exit_link_state(struct pci_dev *pdev); 566 void pcie_aspm_pm_state_change(struct pci_dev *pdev); 567 void pcie_aspm_powersave_config_link(struct pci_dev *pdev); 568 #else 569 static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { } 570 static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { } 571 static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev) { } 572 static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { } 573 #endif 574 575 #ifdef CONFIG_PCIE_ECRC 576 void pcie_set_ecrc_checking(struct pci_dev *dev); 577 void pcie_ecrc_get_policy(char *str); 578 #else 579 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { } 580 static inline void pcie_ecrc_get_policy(char *str) { } 581 #endif 582 583 #ifdef CONFIG_PCIE_PTM 584 void pci_ptm_init(struct pci_dev *dev); 585 int pci_enable_ptm(struct pci_dev *dev, u8 *granularity); 586 #else 587 static inline void pci_ptm_init(struct pci_dev *dev) { } 588 static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity) 589 { return -EINVAL; } 590 #endif 591 592 struct pci_dev_reset_methods { 593 u16 vendor; 594 u16 device; 595 int (*reset)(struct pci_dev *dev, int probe); 596 }; 597 598 #ifdef CONFIG_PCI_QUIRKS 599 int pci_dev_specific_reset(struct pci_dev *dev, int probe); 600 #else 601 static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe) 602 { 603 return -ENOTTY; 604 } 605 #endif 606 607 #if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64) 608 int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment, 609 struct resource *res); 610 #endif 611 612 u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar); 613 int pci_rebar_get_current_size(struct pci_dev *pdev, int bar); 614 int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size); 615 static inline u64 pci_rebar_size_to_bytes(int size) 616 { 617 return 1ULL << (size + 20); 618 } 619 620 struct device_node; 621 622 #ifdef CONFIG_OF 623 int of_pci_parse_bus_range(struct device_node *node, struct resource *res); 624 int of_get_pci_domain_nr(struct device_node *node); 625 int of_pci_get_max_link_speed(struct device_node *node); 626 void pci_set_of_node(struct pci_dev *dev); 627 void pci_release_of_node(struct pci_dev *dev); 628 void pci_set_bus_of_node(struct pci_bus *bus); 629 void pci_release_bus_of_node(struct pci_bus *bus); 630 631 int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge); 632 633 #else 634 static inline int 635 of_pci_parse_bus_range(struct device_node *node, struct resource *res) 636 { 637 return -EINVAL; 638 } 639 640 static inline int 641 of_get_pci_domain_nr(struct device_node *node) 642 { 643 return -1; 644 } 645 646 static inline int 647 of_pci_get_max_link_speed(struct device_node *node) 648 { 649 return -EINVAL; 650 } 651 652 static inline void pci_set_of_node(struct pci_dev *dev) { } 653 static inline void pci_release_of_node(struct pci_dev *dev) { } 654 static inline void pci_set_bus_of_node(struct pci_bus *bus) { } 655 static inline void pci_release_bus_of_node(struct pci_bus *bus) { } 656 657 static inline int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge) 658 { 659 return 0; 660 } 661 662 #endif /* CONFIG_OF */ 663 664 #ifdef CONFIG_PCIEAER 665 void pci_no_aer(void); 666 void pci_aer_init(struct pci_dev *dev); 667 void pci_aer_exit(struct pci_dev *dev); 668 extern const struct attribute_group aer_stats_attr_group; 669 void pci_aer_clear_fatal_status(struct pci_dev *dev); 670 int pci_aer_clear_status(struct pci_dev *dev); 671 int pci_aer_raw_clear_status(struct pci_dev *dev); 672 #else 673 static inline void pci_no_aer(void) { } 674 static inline void pci_aer_init(struct pci_dev *d) { } 675 static inline void pci_aer_exit(struct pci_dev *d) { } 676 static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { } 677 static inline int pci_aer_clear_status(struct pci_dev *dev) { return -EINVAL; } 678 static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -EINVAL; } 679 #endif 680 681 #ifdef CONFIG_ACPI 682 int pci_acpi_program_hp_params(struct pci_dev *dev); 683 #else 684 static inline int pci_acpi_program_hp_params(struct pci_dev *dev) 685 { 686 return -ENODEV; 687 } 688 #endif 689 690 #ifdef CONFIG_PCIEASPM 691 extern const struct attribute_group aspm_ctrl_attr_group; 692 #endif 693 694 #endif /* DRIVERS_PCI_H */ 695