1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef DRIVERS_PCI_H 3 #define DRIVERS_PCI_H 4 5 #define PCI_FIND_CAP_TTL 48 6 7 #define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */ 8 9 extern const unsigned char pcie_link_speed[]; 10 extern bool pci_early_dump; 11 12 bool pcie_cap_has_lnkctl(const struct pci_dev *dev); 13 14 /* Functions internal to the PCI core code */ 15 16 int pci_create_sysfs_dev_files(struct pci_dev *pdev); 17 void pci_remove_sysfs_dev_files(struct pci_dev *pdev); 18 #if !defined(CONFIG_DMI) && !defined(CONFIG_ACPI) 19 static inline void pci_create_firmware_label_files(struct pci_dev *pdev) 20 { return; } 21 static inline void pci_remove_firmware_label_files(struct pci_dev *pdev) 22 { return; } 23 #else 24 void pci_create_firmware_label_files(struct pci_dev *pdev); 25 void pci_remove_firmware_label_files(struct pci_dev *pdev); 26 #endif 27 void pci_cleanup_rom(struct pci_dev *dev); 28 29 enum pci_mmap_api { 30 PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */ 31 PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */ 32 }; 33 int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai, 34 enum pci_mmap_api mmap_api); 35 36 int pci_probe_reset_function(struct pci_dev *dev); 37 int pci_bridge_secondary_bus_reset(struct pci_dev *dev); 38 39 /** 40 * struct pci_platform_pm_ops - Firmware PM callbacks 41 * 42 * @is_manageable: returns 'true' if given device is power manageable by the 43 * platform firmware 44 * 45 * @set_state: invokes the platform firmware to set the device's power state 46 * 47 * @get_state: queries the platform firmware for a device's current power state 48 * 49 * @choose_state: returns PCI power state of given device preferred by the 50 * platform; to be used during system-wide transitions from a 51 * sleeping state to the working state and vice versa 52 * 53 * @set_wakeup: enables/disables wakeup capability for the device 54 * 55 * @need_resume: returns 'true' if the given device (which is currently 56 * suspended) needs to be resumed to be configured for system 57 * wakeup. 58 * 59 * If given platform is generally capable of power managing PCI devices, all of 60 * these callbacks are mandatory. 61 */ 62 struct pci_platform_pm_ops { 63 bool (*is_manageable)(struct pci_dev *dev); 64 int (*set_state)(struct pci_dev *dev, pci_power_t state); 65 pci_power_t (*get_state)(struct pci_dev *dev); 66 pci_power_t (*choose_state)(struct pci_dev *dev); 67 int (*set_wakeup)(struct pci_dev *dev, bool enable); 68 bool (*need_resume)(struct pci_dev *dev); 69 }; 70 71 int pci_set_platform_pm(const struct pci_platform_pm_ops *ops); 72 void pci_update_current_state(struct pci_dev *dev, pci_power_t state); 73 void pci_power_up(struct pci_dev *dev); 74 void pci_disable_enabled_device(struct pci_dev *dev); 75 int pci_finish_runtime_suspend(struct pci_dev *dev); 76 void pcie_clear_root_pme_status(struct pci_dev *dev); 77 int __pci_pme_wakeup(struct pci_dev *dev, void *ign); 78 void pci_pme_restore(struct pci_dev *dev); 79 bool pci_dev_keep_suspended(struct pci_dev *dev); 80 void pci_dev_complete_resume(struct pci_dev *pci_dev); 81 void pci_config_pm_runtime_get(struct pci_dev *dev); 82 void pci_config_pm_runtime_put(struct pci_dev *dev); 83 void pci_pm_init(struct pci_dev *dev); 84 void pci_ea_init(struct pci_dev *dev); 85 void pci_allocate_cap_save_buffers(struct pci_dev *dev); 86 void pci_free_cap_save_buffers(struct pci_dev *dev); 87 bool pci_bridge_d3_possible(struct pci_dev *dev); 88 void pci_bridge_d3_update(struct pci_dev *dev); 89 90 static inline void pci_wakeup_event(struct pci_dev *dev) 91 { 92 /* Wait 100 ms before the system can be put into a sleep state. */ 93 pm_wakeup_event(&dev->dev, 100); 94 } 95 96 static inline bool pci_has_subordinate(struct pci_dev *pci_dev) 97 { 98 return !!(pci_dev->subordinate); 99 } 100 101 static inline bool pci_power_manageable(struct pci_dev *pci_dev) 102 { 103 /* 104 * Currently we allow normal PCI devices and PCI bridges transition 105 * into D3 if their bridge_d3 is set. 106 */ 107 return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3; 108 } 109 110 int pci_vpd_init(struct pci_dev *dev); 111 void pci_vpd_release(struct pci_dev *dev); 112 void pcie_vpd_create_sysfs_dev_files(struct pci_dev *dev); 113 void pcie_vpd_remove_sysfs_dev_files(struct pci_dev *dev); 114 115 /* PCI /proc functions */ 116 #ifdef CONFIG_PROC_FS 117 int pci_proc_attach_device(struct pci_dev *dev); 118 int pci_proc_detach_device(struct pci_dev *dev); 119 int pci_proc_detach_bus(struct pci_bus *bus); 120 #else 121 static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; } 122 static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; } 123 static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; } 124 #endif 125 126 /* Functions for PCI Hotplug drivers to use */ 127 int pci_hp_add_bridge(struct pci_dev *dev); 128 129 #ifdef HAVE_PCI_LEGACY 130 void pci_create_legacy_files(struct pci_bus *bus); 131 void pci_remove_legacy_files(struct pci_bus *bus); 132 #else 133 static inline void pci_create_legacy_files(struct pci_bus *bus) { return; } 134 static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; } 135 #endif 136 137 /* Lock for read/write access to pci device and bus lists */ 138 extern struct rw_semaphore pci_bus_sem; 139 140 extern raw_spinlock_t pci_lock; 141 142 extern unsigned int pci_pm_d3_delay; 143 144 #ifdef CONFIG_PCI_MSI 145 void pci_no_msi(void); 146 #else 147 static inline void pci_no_msi(void) { } 148 #endif 149 150 static inline void pci_msi_set_enable(struct pci_dev *dev, int enable) 151 { 152 u16 control; 153 154 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); 155 control &= ~PCI_MSI_FLAGS_ENABLE; 156 if (enable) 157 control |= PCI_MSI_FLAGS_ENABLE; 158 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); 159 } 160 161 static inline void pci_msix_clear_and_set_ctrl(struct pci_dev *dev, u16 clear, u16 set) 162 { 163 u16 ctrl; 164 165 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl); 166 ctrl &= ~clear; 167 ctrl |= set; 168 pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, ctrl); 169 } 170 171 void pci_realloc_get_opt(char *); 172 173 static inline int pci_no_d1d2(struct pci_dev *dev) 174 { 175 unsigned int parent_dstates = 0; 176 177 if (dev->bus->self) 178 parent_dstates = dev->bus->self->no_d1d2; 179 return (dev->no_d1d2 || parent_dstates); 180 181 } 182 extern const struct attribute_group *pci_dev_groups[]; 183 extern const struct attribute_group *pcibus_groups[]; 184 extern const struct device_type pci_dev_type; 185 extern const struct attribute_group *pci_bus_groups[]; 186 187 188 /** 189 * pci_match_one_device - Tell if a PCI device structure has a matching 190 * PCI device id structure 191 * @id: single PCI device id structure to match 192 * @dev: the PCI device structure to match against 193 * 194 * Returns the matching pci_device_id structure or %NULL if there is no match. 195 */ 196 static inline const struct pci_device_id * 197 pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev) 198 { 199 if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) && 200 (id->device == PCI_ANY_ID || id->device == dev->device) && 201 (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) && 202 (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) && 203 !((id->class ^ dev->class) & id->class_mask)) 204 return id; 205 return NULL; 206 } 207 208 /* PCI slot sysfs helper code */ 209 #define to_pci_slot(s) container_of(s, struct pci_slot, kobj) 210 211 extern struct kset *pci_slots_kset; 212 213 struct pci_slot_attribute { 214 struct attribute attr; 215 ssize_t (*show)(struct pci_slot *, char *); 216 ssize_t (*store)(struct pci_slot *, const char *, size_t); 217 }; 218 #define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr) 219 220 enum pci_bar_type { 221 pci_bar_unknown, /* Standard PCI BAR probe */ 222 pci_bar_io, /* An I/O port BAR */ 223 pci_bar_mem32, /* A 32-bit memory BAR */ 224 pci_bar_mem64, /* A 64-bit memory BAR */ 225 }; 226 227 int pci_configure_extended_tags(struct pci_dev *dev, void *ign); 228 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, 229 int crs_timeout); 230 bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, 231 int crs_timeout); 232 int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int crs_timeout); 233 234 int pci_setup_device(struct pci_dev *dev); 235 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, 236 struct resource *res, unsigned int reg); 237 void pci_configure_ari(struct pci_dev *dev); 238 void __pci_bus_size_bridges(struct pci_bus *bus, 239 struct list_head *realloc_head); 240 void __pci_bus_assign_resources(const struct pci_bus *bus, 241 struct list_head *realloc_head, 242 struct list_head *fail_head); 243 bool pci_bus_clip_resource(struct pci_dev *dev, int idx); 244 245 void pci_reassigndev_resource_alignment(struct pci_dev *dev); 246 void pci_disable_bridge_window(struct pci_dev *dev); 247 248 /* PCIe link information */ 249 #define PCIE_SPEED2STR(speed) \ 250 ((speed) == PCIE_SPEED_16_0GT ? "16 GT/s" : \ 251 (speed) == PCIE_SPEED_8_0GT ? "8 GT/s" : \ 252 (speed) == PCIE_SPEED_5_0GT ? "5 GT/s" : \ 253 (speed) == PCIE_SPEED_2_5GT ? "2.5 GT/s" : \ 254 "Unknown speed") 255 256 /* PCIe speed to Mb/s reduced by encoding overhead */ 257 #define PCIE_SPEED2MBS_ENC(speed) \ 258 ((speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \ 259 (speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \ 260 (speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \ 261 (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \ 262 0) 263 264 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev); 265 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev); 266 u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed, 267 enum pcie_link_width *width); 268 void __pcie_print_link_status(struct pci_dev *dev, bool verbose); 269 270 /* Single Root I/O Virtualization */ 271 struct pci_sriov { 272 int pos; /* Capability position */ 273 int nres; /* Number of resources */ 274 u32 cap; /* SR-IOV Capabilities */ 275 u16 ctrl; /* SR-IOV Control */ 276 u16 total_VFs; /* Total VFs associated with the PF */ 277 u16 initial_VFs; /* Initial VFs associated with the PF */ 278 u16 num_VFs; /* Number of VFs available */ 279 u16 offset; /* First VF Routing ID offset */ 280 u16 stride; /* Following VF stride */ 281 u16 vf_device; /* VF device ID */ 282 u32 pgsz; /* Page size for BAR alignment */ 283 u8 link; /* Function Dependency Link */ 284 u8 max_VF_buses; /* Max buses consumed by VFs */ 285 u16 driver_max_VFs; /* Max num VFs driver supports */ 286 struct pci_dev *dev; /* Lowest numbered PF */ 287 struct pci_dev *self; /* This PF */ 288 u32 class; /* VF device */ 289 u8 hdr_type; /* VF header type */ 290 u16 subsystem_vendor; /* VF subsystem vendor */ 291 u16 subsystem_device; /* VF subsystem device */ 292 resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */ 293 bool drivers_autoprobe; /* Auto probing of VFs by driver */ 294 }; 295 296 /* pci_dev priv_flags */ 297 #define PCI_DEV_DISCONNECTED 0 298 #define PCI_DEV_ADDED 1 299 300 static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused) 301 { 302 set_bit(PCI_DEV_DISCONNECTED, &dev->priv_flags); 303 return 0; 304 } 305 306 static inline bool pci_dev_is_disconnected(const struct pci_dev *dev) 307 { 308 return test_bit(PCI_DEV_DISCONNECTED, &dev->priv_flags); 309 } 310 311 static inline void pci_dev_assign_added(struct pci_dev *dev, bool added) 312 { 313 assign_bit(PCI_DEV_ADDED, &dev->priv_flags, added); 314 } 315 316 static inline bool pci_dev_is_added(const struct pci_dev *dev) 317 { 318 return test_bit(PCI_DEV_ADDED, &dev->priv_flags); 319 } 320 321 #ifdef CONFIG_PCIEAER 322 #include <linux/aer.h> 323 324 #define AER_MAX_MULTI_ERR_DEVICES 5 /* Not likely to have more */ 325 326 struct aer_err_info { 327 struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES]; 328 int error_dev_num; 329 330 unsigned int id:16; 331 332 unsigned int severity:2; /* 0:NONFATAL | 1:FATAL | 2:COR */ 333 unsigned int __pad1:5; 334 unsigned int multi_error_valid:1; 335 336 unsigned int first_error:5; 337 unsigned int __pad2:2; 338 unsigned int tlp_header_valid:1; 339 340 unsigned int status; /* COR/UNCOR Error Status */ 341 unsigned int mask; /* COR/UNCOR Error Mask */ 342 struct aer_header_log_regs tlp; /* TLP Header */ 343 }; 344 345 int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info); 346 void aer_print_error(struct pci_dev *dev, struct aer_err_info *info); 347 #endif /* CONFIG_PCIEAER */ 348 349 #ifdef CONFIG_PCI_ATS 350 void pci_restore_ats_state(struct pci_dev *dev); 351 #else 352 static inline void pci_restore_ats_state(struct pci_dev *dev) 353 { 354 } 355 #endif /* CONFIG_PCI_ATS */ 356 357 #ifdef CONFIG_PCI_IOV 358 int pci_iov_init(struct pci_dev *dev); 359 void pci_iov_release(struct pci_dev *dev); 360 void pci_iov_remove(struct pci_dev *dev); 361 void pci_iov_update_resource(struct pci_dev *dev, int resno); 362 resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno); 363 void pci_restore_iov_state(struct pci_dev *dev); 364 int pci_iov_bus_range(struct pci_bus *bus); 365 366 #else 367 static inline int pci_iov_init(struct pci_dev *dev) 368 { 369 return -ENODEV; 370 } 371 static inline void pci_iov_release(struct pci_dev *dev) 372 373 { 374 } 375 static inline void pci_iov_remove(struct pci_dev *dev) 376 { 377 } 378 static inline void pci_restore_iov_state(struct pci_dev *dev) 379 { 380 } 381 static inline int pci_iov_bus_range(struct pci_bus *bus) 382 { 383 return 0; 384 } 385 386 #endif /* CONFIG_PCI_IOV */ 387 388 unsigned long pci_cardbus_resource_alignment(struct resource *); 389 390 static inline resource_size_t pci_resource_alignment(struct pci_dev *dev, 391 struct resource *res) 392 { 393 #ifdef CONFIG_PCI_IOV 394 int resno = res - dev->resource; 395 396 if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END) 397 return pci_sriov_resource_alignment(dev, resno); 398 #endif 399 if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS) 400 return pci_cardbus_resource_alignment(res); 401 return resource_alignment(res); 402 } 403 404 void pci_enable_acs(struct pci_dev *dev); 405 #ifdef CONFIG_PCI_QUIRKS 406 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags); 407 int pci_dev_specific_enable_acs(struct pci_dev *dev); 408 int pci_dev_specific_disable_acs_redir(struct pci_dev *dev); 409 #else 410 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev, 411 u16 acs_flags) 412 { 413 return -ENOTTY; 414 } 415 static inline int pci_dev_specific_enable_acs(struct pci_dev *dev) 416 { 417 return -ENOTTY; 418 } 419 static inline int pci_dev_specific_disable_acs_redir(struct pci_dev *dev) 420 { 421 return -ENOTTY; 422 } 423 #endif 424 425 /* PCI error reporting and recovery */ 426 void pcie_do_fatal_recovery(struct pci_dev *dev, u32 service); 427 void pcie_do_nonfatal_recovery(struct pci_dev *dev); 428 429 bool pcie_wait_for_link(struct pci_dev *pdev, bool active); 430 #ifdef CONFIG_PCIEASPM 431 void pcie_aspm_init_link_state(struct pci_dev *pdev); 432 void pcie_aspm_exit_link_state(struct pci_dev *pdev); 433 void pcie_aspm_pm_state_change(struct pci_dev *pdev); 434 void pcie_aspm_powersave_config_link(struct pci_dev *pdev); 435 #else 436 static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { } 437 static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { } 438 static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev) { } 439 static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { } 440 #endif 441 442 #ifdef CONFIG_PCIEASPM_DEBUG 443 void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev); 444 void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev); 445 #else 446 static inline void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev) { } 447 static inline void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev) { } 448 #endif 449 450 #ifdef CONFIG_PCIE_PTM 451 void pci_ptm_init(struct pci_dev *dev); 452 #else 453 static inline void pci_ptm_init(struct pci_dev *dev) { } 454 #endif 455 456 struct pci_dev_reset_methods { 457 u16 vendor; 458 u16 device; 459 int (*reset)(struct pci_dev *dev, int probe); 460 }; 461 462 #ifdef CONFIG_PCI_QUIRKS 463 int pci_dev_specific_reset(struct pci_dev *dev, int probe); 464 #else 465 static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe) 466 { 467 return -ENOTTY; 468 } 469 #endif 470 471 #if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64) 472 int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment, 473 struct resource *res); 474 #endif 475 476 u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar); 477 int pci_rebar_get_current_size(struct pci_dev *pdev, int bar); 478 int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size); 479 static inline u64 pci_rebar_size_to_bytes(int size) 480 { 481 return 1ULL << (size + 20); 482 } 483 484 struct device_node; 485 486 #ifdef CONFIG_OF 487 int of_pci_parse_bus_range(struct device_node *node, struct resource *res); 488 int of_get_pci_domain_nr(struct device_node *node); 489 int of_pci_get_max_link_speed(struct device_node *node); 490 491 #else 492 static inline int 493 of_pci_parse_bus_range(struct device_node *node, struct resource *res) 494 { 495 return -EINVAL; 496 } 497 498 static inline int 499 of_get_pci_domain_nr(struct device_node *node) 500 { 501 return -1; 502 } 503 504 static inline int 505 of_pci_get_max_link_speed(struct device_node *node) 506 { 507 return -EINVAL; 508 } 509 #endif /* CONFIG_OF */ 510 511 #if defined(CONFIG_OF_ADDRESS) 512 int devm_of_pci_get_host_bridge_resources(struct device *dev, 513 unsigned char busno, unsigned char bus_max, 514 struct list_head *resources, resource_size_t *io_base); 515 #else 516 static inline int devm_of_pci_get_host_bridge_resources(struct device *dev, 517 unsigned char busno, unsigned char bus_max, 518 struct list_head *resources, resource_size_t *io_base) 519 { 520 return -EINVAL; 521 } 522 #endif 523 524 #ifdef CONFIG_PCIEAER 525 void pci_no_aer(void); 526 void pci_aer_init(struct pci_dev *dev); 527 void pci_aer_exit(struct pci_dev *dev); 528 extern const struct attribute_group aer_stats_attr_group; 529 void pci_aer_clear_fatal_status(struct pci_dev *dev); 530 void pci_aer_clear_device_status(struct pci_dev *dev); 531 #else 532 static inline void pci_no_aer(void) { } 533 static inline int pci_aer_init(struct pci_dev *d) { return -ENODEV; } 534 static inline void pci_aer_exit(struct pci_dev *d) { } 535 static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { } 536 static inline void pci_aer_clear_device_status(struct pci_dev *dev) { } 537 #endif 538 539 #endif /* DRIVERS_PCI_H */ 540