1 /* 2 * PCI Bus Services, see include/linux/pci.h for further explanation. 3 * 4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter, 5 * David Mosberger-Tang 6 * 7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz> 8 */ 9 10 #include <linux/kernel.h> 11 #include <linux/delay.h> 12 #include <linux/init.h> 13 #include <linux/of.h> 14 #include <linux/of_pci.h> 15 #include <linux/pci.h> 16 #include <linux/pm.h> 17 #include <linux/slab.h> 18 #include <linux/module.h> 19 #include <linux/spinlock.h> 20 #include <linux/string.h> 21 #include <linux/log2.h> 22 #include <linux/pci-aspm.h> 23 #include <linux/pm_wakeup.h> 24 #include <linux/interrupt.h> 25 #include <linux/device.h> 26 #include <linux/pm_runtime.h> 27 #include <linux/pci_hotplug.h> 28 #include <asm/setup.h> 29 #include <linux/aer.h> 30 #include "pci.h" 31 32 const char *pci_power_names[] = { 33 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown", 34 }; 35 EXPORT_SYMBOL_GPL(pci_power_names); 36 37 int isa_dma_bridge_buggy; 38 EXPORT_SYMBOL(isa_dma_bridge_buggy); 39 40 int pci_pci_problems; 41 EXPORT_SYMBOL(pci_pci_problems); 42 43 unsigned int pci_pm_d3_delay; 44 45 static void pci_pme_list_scan(struct work_struct *work); 46 47 static LIST_HEAD(pci_pme_list); 48 static DEFINE_MUTEX(pci_pme_list_mutex); 49 static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan); 50 51 struct pci_pme_device { 52 struct list_head list; 53 struct pci_dev *dev; 54 }; 55 56 #define PME_TIMEOUT 1000 /* How long between PME checks */ 57 58 static void pci_dev_d3_sleep(struct pci_dev *dev) 59 { 60 unsigned int delay = dev->d3_delay; 61 62 if (delay < pci_pm_d3_delay) 63 delay = pci_pm_d3_delay; 64 65 msleep(delay); 66 } 67 68 #ifdef CONFIG_PCI_DOMAINS 69 int pci_domains_supported = 1; 70 #endif 71 72 #define DEFAULT_CARDBUS_IO_SIZE (256) 73 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024) 74 /* pci=cbmemsize=nnM,cbiosize=nn can override this */ 75 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE; 76 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE; 77 78 #define DEFAULT_HOTPLUG_IO_SIZE (256) 79 #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024) 80 /* pci=hpmemsize=nnM,hpiosize=nn can override this */ 81 unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE; 82 unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE; 83 84 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_DEFAULT; 85 86 /* 87 * The default CLS is used if arch didn't set CLS explicitly and not 88 * all pci devices agree on the same value. Arch can override either 89 * the dfl or actual value as it sees fit. Don't forget this is 90 * measured in 32-bit words, not bytes. 91 */ 92 u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2; 93 u8 pci_cache_line_size; 94 95 /* 96 * If we set up a device for bus mastering, we need to check the latency 97 * timer as certain BIOSes forget to set it properly. 98 */ 99 unsigned int pcibios_max_latency = 255; 100 101 /* If set, the PCIe ARI capability will not be used. */ 102 static bool pcie_ari_disabled; 103 104 /** 105 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children 106 * @bus: pointer to PCI bus structure to search 107 * 108 * Given a PCI bus, returns the highest PCI bus number present in the set 109 * including the given PCI bus and its list of child PCI buses. 110 */ 111 unsigned char pci_bus_max_busnr(struct pci_bus *bus) 112 { 113 struct pci_bus *tmp; 114 unsigned char max, n; 115 116 max = bus->busn_res.end; 117 list_for_each_entry(tmp, &bus->children, node) { 118 n = pci_bus_max_busnr(tmp); 119 if (n > max) 120 max = n; 121 } 122 return max; 123 } 124 EXPORT_SYMBOL_GPL(pci_bus_max_busnr); 125 126 #ifdef CONFIG_HAS_IOMEM 127 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar) 128 { 129 struct resource *res = &pdev->resource[bar]; 130 131 /* 132 * Make sure the BAR is actually a memory resource, not an IO resource 133 */ 134 if (res->flags & IORESOURCE_UNSET || !(res->flags & IORESOURCE_MEM)) { 135 dev_warn(&pdev->dev, "can't ioremap BAR %d: %pR\n", bar, res); 136 return NULL; 137 } 138 return ioremap_nocache(res->start, resource_size(res)); 139 } 140 EXPORT_SYMBOL_GPL(pci_ioremap_bar); 141 142 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar) 143 { 144 /* 145 * Make sure the BAR is actually a memory resource, not an IO resource 146 */ 147 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { 148 WARN_ON(1); 149 return NULL; 150 } 151 return ioremap_wc(pci_resource_start(pdev, bar), 152 pci_resource_len(pdev, bar)); 153 } 154 EXPORT_SYMBOL_GPL(pci_ioremap_wc_bar); 155 #endif 156 157 158 static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn, 159 u8 pos, int cap, int *ttl) 160 { 161 u8 id; 162 u16 ent; 163 164 pci_bus_read_config_byte(bus, devfn, pos, &pos); 165 166 while ((*ttl)--) { 167 if (pos < 0x40) 168 break; 169 pos &= ~3; 170 pci_bus_read_config_word(bus, devfn, pos, &ent); 171 172 id = ent & 0xff; 173 if (id == 0xff) 174 break; 175 if (id == cap) 176 return pos; 177 pos = (ent >> 8); 178 } 179 return 0; 180 } 181 182 static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn, 183 u8 pos, int cap) 184 { 185 int ttl = PCI_FIND_CAP_TTL; 186 187 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl); 188 } 189 190 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap) 191 { 192 return __pci_find_next_cap(dev->bus, dev->devfn, 193 pos + PCI_CAP_LIST_NEXT, cap); 194 } 195 EXPORT_SYMBOL_GPL(pci_find_next_capability); 196 197 static int __pci_bus_find_cap_start(struct pci_bus *bus, 198 unsigned int devfn, u8 hdr_type) 199 { 200 u16 status; 201 202 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status); 203 if (!(status & PCI_STATUS_CAP_LIST)) 204 return 0; 205 206 switch (hdr_type) { 207 case PCI_HEADER_TYPE_NORMAL: 208 case PCI_HEADER_TYPE_BRIDGE: 209 return PCI_CAPABILITY_LIST; 210 case PCI_HEADER_TYPE_CARDBUS: 211 return PCI_CB_CAPABILITY_LIST; 212 } 213 214 return 0; 215 } 216 217 /** 218 * pci_find_capability - query for devices' capabilities 219 * @dev: PCI device to query 220 * @cap: capability code 221 * 222 * Tell if a device supports a given PCI capability. 223 * Returns the address of the requested capability structure within the 224 * device's PCI configuration space or 0 in case the device does not 225 * support it. Possible values for @cap: 226 * 227 * %PCI_CAP_ID_PM Power Management 228 * %PCI_CAP_ID_AGP Accelerated Graphics Port 229 * %PCI_CAP_ID_VPD Vital Product Data 230 * %PCI_CAP_ID_SLOTID Slot Identification 231 * %PCI_CAP_ID_MSI Message Signalled Interrupts 232 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap 233 * %PCI_CAP_ID_PCIX PCI-X 234 * %PCI_CAP_ID_EXP PCI Express 235 */ 236 int pci_find_capability(struct pci_dev *dev, int cap) 237 { 238 int pos; 239 240 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); 241 if (pos) 242 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap); 243 244 return pos; 245 } 246 EXPORT_SYMBOL(pci_find_capability); 247 248 /** 249 * pci_bus_find_capability - query for devices' capabilities 250 * @bus: the PCI bus to query 251 * @devfn: PCI device to query 252 * @cap: capability code 253 * 254 * Like pci_find_capability() but works for pci devices that do not have a 255 * pci_dev structure set up yet. 256 * 257 * Returns the address of the requested capability structure within the 258 * device's PCI configuration space or 0 in case the device does not 259 * support it. 260 */ 261 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap) 262 { 263 int pos; 264 u8 hdr_type; 265 266 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type); 267 268 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f); 269 if (pos) 270 pos = __pci_find_next_cap(bus, devfn, pos, cap); 271 272 return pos; 273 } 274 EXPORT_SYMBOL(pci_bus_find_capability); 275 276 /** 277 * pci_find_next_ext_capability - Find an extended capability 278 * @dev: PCI device to query 279 * @start: address at which to start looking (0 to start at beginning of list) 280 * @cap: capability code 281 * 282 * Returns the address of the next matching extended capability structure 283 * within the device's PCI configuration space or 0 if the device does 284 * not support it. Some capabilities can occur several times, e.g., the 285 * vendor-specific capability, and this provides a way to find them all. 286 */ 287 int pci_find_next_ext_capability(struct pci_dev *dev, int start, int cap) 288 { 289 u32 header; 290 int ttl; 291 int pos = PCI_CFG_SPACE_SIZE; 292 293 /* minimum 8 bytes per capability */ 294 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; 295 296 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE) 297 return 0; 298 299 if (start) 300 pos = start; 301 302 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) 303 return 0; 304 305 /* 306 * If we have no capabilities, this is indicated by cap ID, 307 * cap version and next pointer all being 0. 308 */ 309 if (header == 0) 310 return 0; 311 312 while (ttl-- > 0) { 313 if (PCI_EXT_CAP_ID(header) == cap && pos != start) 314 return pos; 315 316 pos = PCI_EXT_CAP_NEXT(header); 317 if (pos < PCI_CFG_SPACE_SIZE) 318 break; 319 320 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) 321 break; 322 } 323 324 return 0; 325 } 326 EXPORT_SYMBOL_GPL(pci_find_next_ext_capability); 327 328 /** 329 * pci_find_ext_capability - Find an extended capability 330 * @dev: PCI device to query 331 * @cap: capability code 332 * 333 * Returns the address of the requested extended capability structure 334 * within the device's PCI configuration space or 0 if the device does 335 * not support it. Possible values for @cap: 336 * 337 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting 338 * %PCI_EXT_CAP_ID_VC Virtual Channel 339 * %PCI_EXT_CAP_ID_DSN Device Serial Number 340 * %PCI_EXT_CAP_ID_PWR Power Budgeting 341 */ 342 int pci_find_ext_capability(struct pci_dev *dev, int cap) 343 { 344 return pci_find_next_ext_capability(dev, 0, cap); 345 } 346 EXPORT_SYMBOL_GPL(pci_find_ext_capability); 347 348 static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap) 349 { 350 int rc, ttl = PCI_FIND_CAP_TTL; 351 u8 cap, mask; 352 353 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST) 354 mask = HT_3BIT_CAP_MASK; 355 else 356 mask = HT_5BIT_CAP_MASK; 357 358 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos, 359 PCI_CAP_ID_HT, &ttl); 360 while (pos) { 361 rc = pci_read_config_byte(dev, pos + 3, &cap); 362 if (rc != PCIBIOS_SUCCESSFUL) 363 return 0; 364 365 if ((cap & mask) == ht_cap) 366 return pos; 367 368 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, 369 pos + PCI_CAP_LIST_NEXT, 370 PCI_CAP_ID_HT, &ttl); 371 } 372 373 return 0; 374 } 375 /** 376 * pci_find_next_ht_capability - query a device's Hypertransport capabilities 377 * @dev: PCI device to query 378 * @pos: Position from which to continue searching 379 * @ht_cap: Hypertransport capability code 380 * 381 * To be used in conjunction with pci_find_ht_capability() to search for 382 * all capabilities matching @ht_cap. @pos should always be a value returned 383 * from pci_find_ht_capability(). 384 * 385 * NB. To be 100% safe against broken PCI devices, the caller should take 386 * steps to avoid an infinite loop. 387 */ 388 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap) 389 { 390 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap); 391 } 392 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability); 393 394 /** 395 * pci_find_ht_capability - query a device's Hypertransport capabilities 396 * @dev: PCI device to query 397 * @ht_cap: Hypertransport capability code 398 * 399 * Tell if a device supports a given Hypertransport capability. 400 * Returns an address within the device's PCI configuration space 401 * or 0 in case the device does not support the request capability. 402 * The address points to the PCI capability, of type PCI_CAP_ID_HT, 403 * which has a Hypertransport capability matching @ht_cap. 404 */ 405 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap) 406 { 407 int pos; 408 409 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); 410 if (pos) 411 pos = __pci_find_next_ht_cap(dev, pos, ht_cap); 412 413 return pos; 414 } 415 EXPORT_SYMBOL_GPL(pci_find_ht_capability); 416 417 /** 418 * pci_find_parent_resource - return resource region of parent bus of given region 419 * @dev: PCI device structure contains resources to be searched 420 * @res: child resource record for which parent is sought 421 * 422 * For given resource region of given device, return the resource 423 * region of parent bus the given region is contained in. 424 */ 425 struct resource *pci_find_parent_resource(const struct pci_dev *dev, 426 struct resource *res) 427 { 428 const struct pci_bus *bus = dev->bus; 429 struct resource *r; 430 int i; 431 432 pci_bus_for_each_resource(bus, r, i) { 433 if (!r) 434 continue; 435 if (res->start && resource_contains(r, res)) { 436 437 /* 438 * If the window is prefetchable but the BAR is 439 * not, the allocator made a mistake. 440 */ 441 if (r->flags & IORESOURCE_PREFETCH && 442 !(res->flags & IORESOURCE_PREFETCH)) 443 return NULL; 444 445 /* 446 * If we're below a transparent bridge, there may 447 * be both a positively-decoded aperture and a 448 * subtractively-decoded region that contain the BAR. 449 * We want the positively-decoded one, so this depends 450 * on pci_bus_for_each_resource() giving us those 451 * first. 452 */ 453 return r; 454 } 455 } 456 return NULL; 457 } 458 EXPORT_SYMBOL(pci_find_parent_resource); 459 460 /** 461 * pci_find_pcie_root_port - return PCIe Root Port 462 * @dev: PCI device to query 463 * 464 * Traverse up the parent chain and return the PCIe Root Port PCI Device 465 * for a given PCI Device. 466 */ 467 struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev) 468 { 469 struct pci_dev *bridge, *highest_pcie_bridge = NULL; 470 471 bridge = pci_upstream_bridge(dev); 472 while (bridge && pci_is_pcie(bridge)) { 473 highest_pcie_bridge = bridge; 474 bridge = pci_upstream_bridge(bridge); 475 } 476 477 if (pci_pcie_type(highest_pcie_bridge) != PCI_EXP_TYPE_ROOT_PORT) 478 return NULL; 479 480 return highest_pcie_bridge; 481 } 482 EXPORT_SYMBOL(pci_find_pcie_root_port); 483 484 /** 485 * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos 486 * @dev: the PCI device to operate on 487 * @pos: config space offset of status word 488 * @mask: mask of bit(s) to care about in status word 489 * 490 * Return 1 when mask bit(s) in status word clear, 0 otherwise. 491 */ 492 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask) 493 { 494 int i; 495 496 /* Wait for Transaction Pending bit clean */ 497 for (i = 0; i < 4; i++) { 498 u16 status; 499 if (i) 500 msleep((1 << (i - 1)) * 100); 501 502 pci_read_config_word(dev, pos, &status); 503 if (!(status & mask)) 504 return 1; 505 } 506 507 return 0; 508 } 509 510 /** 511 * pci_restore_bars - restore a device's BAR values (e.g. after wake-up) 512 * @dev: PCI device to have its BARs restored 513 * 514 * Restore the BAR values for a given device, so as to make it 515 * accessible by its driver. 516 */ 517 static void pci_restore_bars(struct pci_dev *dev) 518 { 519 int i; 520 521 /* Per SR-IOV spec 3.4.1.11, VF BARs are RO zero */ 522 if (dev->is_virtfn) 523 return; 524 525 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) 526 pci_update_resource(dev, i); 527 } 528 529 static const struct pci_platform_pm_ops *pci_platform_pm; 530 531 int pci_set_platform_pm(const struct pci_platform_pm_ops *ops) 532 { 533 if (!ops->is_manageable || !ops->set_state || !ops->choose_state 534 || !ops->sleep_wake) 535 return -EINVAL; 536 pci_platform_pm = ops; 537 return 0; 538 } 539 540 static inline bool platform_pci_power_manageable(struct pci_dev *dev) 541 { 542 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false; 543 } 544 545 static inline int platform_pci_set_power_state(struct pci_dev *dev, 546 pci_power_t t) 547 { 548 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS; 549 } 550 551 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev) 552 { 553 return pci_platform_pm ? 554 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR; 555 } 556 557 static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable) 558 { 559 return pci_platform_pm ? 560 pci_platform_pm->sleep_wake(dev, enable) : -ENODEV; 561 } 562 563 static inline int platform_pci_run_wake(struct pci_dev *dev, bool enable) 564 { 565 return pci_platform_pm ? 566 pci_platform_pm->run_wake(dev, enable) : -ENODEV; 567 } 568 569 static inline bool platform_pci_need_resume(struct pci_dev *dev) 570 { 571 return pci_platform_pm ? pci_platform_pm->need_resume(dev) : false; 572 } 573 574 /** 575 * pci_raw_set_power_state - Use PCI PM registers to set the power state of 576 * given PCI device 577 * @dev: PCI device to handle. 578 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into. 579 * 580 * RETURN VALUE: 581 * -EINVAL if the requested state is invalid. 582 * -EIO if device does not support PCI PM or its PM capabilities register has a 583 * wrong version, or device doesn't support the requested state. 584 * 0 if device already is in the requested state. 585 * 0 if device's power state has been successfully changed. 586 */ 587 static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state) 588 { 589 u16 pmcsr; 590 bool need_restore = false; 591 592 /* Check if we're already there */ 593 if (dev->current_state == state) 594 return 0; 595 596 if (!dev->pm_cap) 597 return -EIO; 598 599 if (state < PCI_D0 || state > PCI_D3hot) 600 return -EINVAL; 601 602 /* Validate current state: 603 * Can enter D0 from any state, but if we can only go deeper 604 * to sleep if we're already in a low power state 605 */ 606 if (state != PCI_D0 && dev->current_state <= PCI_D3cold 607 && dev->current_state > state) { 608 dev_err(&dev->dev, "invalid power transition (from state %d to %d)\n", 609 dev->current_state, state); 610 return -EINVAL; 611 } 612 613 /* check if this device supports the desired state */ 614 if ((state == PCI_D1 && !dev->d1_support) 615 || (state == PCI_D2 && !dev->d2_support)) 616 return -EIO; 617 618 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); 619 620 /* If we're (effectively) in D3, force entire word to 0. 621 * This doesn't affect PME_Status, disables PME_En, and 622 * sets PowerState to 0. 623 */ 624 switch (dev->current_state) { 625 case PCI_D0: 626 case PCI_D1: 627 case PCI_D2: 628 pmcsr &= ~PCI_PM_CTRL_STATE_MASK; 629 pmcsr |= state; 630 break; 631 case PCI_D3hot: 632 case PCI_D3cold: 633 case PCI_UNKNOWN: /* Boot-up */ 634 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot 635 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET)) 636 need_restore = true; 637 /* Fall-through: force to D0 */ 638 default: 639 pmcsr = 0; 640 break; 641 } 642 643 /* enter specified state */ 644 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); 645 646 /* Mandatory power management transition delays */ 647 /* see PCI PM 1.1 5.6.1 table 18 */ 648 if (state == PCI_D3hot || dev->current_state == PCI_D3hot) 649 pci_dev_d3_sleep(dev); 650 else if (state == PCI_D2 || dev->current_state == PCI_D2) 651 udelay(PCI_PM_D2_DELAY); 652 653 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); 654 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); 655 if (dev->current_state != state && printk_ratelimit()) 656 dev_info(&dev->dev, "Refused to change power state, currently in D%d\n", 657 dev->current_state); 658 659 /* 660 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT 661 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning 662 * from D3hot to D0 _may_ perform an internal reset, thereby 663 * going to "D0 Uninitialized" rather than "D0 Initialized". 664 * For example, at least some versions of the 3c905B and the 665 * 3c556B exhibit this behaviour. 666 * 667 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave 668 * devices in a D3hot state at boot. Consequently, we need to 669 * restore at least the BARs so that the device will be 670 * accessible to its driver. 671 */ 672 if (need_restore) 673 pci_restore_bars(dev); 674 675 if (dev->bus->self) 676 pcie_aspm_pm_state_change(dev->bus->self); 677 678 return 0; 679 } 680 681 /** 682 * pci_update_current_state - Read PCI power state of given device from its 683 * PCI PM registers and cache it 684 * @dev: PCI device to handle. 685 * @state: State to cache in case the device doesn't have the PM capability 686 */ 687 void pci_update_current_state(struct pci_dev *dev, pci_power_t state) 688 { 689 if (dev->pm_cap) { 690 u16 pmcsr; 691 692 /* 693 * Configuration space is not accessible for device in 694 * D3cold, so just keep or set D3cold for safety 695 */ 696 if (dev->current_state == PCI_D3cold) 697 return; 698 if (state == PCI_D3cold) { 699 dev->current_state = PCI_D3cold; 700 return; 701 } 702 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); 703 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); 704 } else { 705 dev->current_state = state; 706 } 707 } 708 709 /** 710 * pci_power_up - Put the given device into D0 forcibly 711 * @dev: PCI device to power up 712 */ 713 void pci_power_up(struct pci_dev *dev) 714 { 715 if (platform_pci_power_manageable(dev)) 716 platform_pci_set_power_state(dev, PCI_D0); 717 718 pci_raw_set_power_state(dev, PCI_D0); 719 pci_update_current_state(dev, PCI_D0); 720 } 721 722 /** 723 * pci_platform_power_transition - Use platform to change device power state 724 * @dev: PCI device to handle. 725 * @state: State to put the device into. 726 */ 727 static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state) 728 { 729 int error; 730 731 if (platform_pci_power_manageable(dev)) { 732 error = platform_pci_set_power_state(dev, state); 733 if (!error) 734 pci_update_current_state(dev, state); 735 } else 736 error = -ENODEV; 737 738 if (error && !dev->pm_cap) /* Fall back to PCI_D0 */ 739 dev->current_state = PCI_D0; 740 741 return error; 742 } 743 744 /** 745 * pci_wakeup - Wake up a PCI device 746 * @pci_dev: Device to handle. 747 * @ign: ignored parameter 748 */ 749 static int pci_wakeup(struct pci_dev *pci_dev, void *ign) 750 { 751 pci_wakeup_event(pci_dev); 752 pm_request_resume(&pci_dev->dev); 753 return 0; 754 } 755 756 /** 757 * pci_wakeup_bus - Walk given bus and wake up devices on it 758 * @bus: Top bus of the subtree to walk. 759 */ 760 static void pci_wakeup_bus(struct pci_bus *bus) 761 { 762 if (bus) 763 pci_walk_bus(bus, pci_wakeup, NULL); 764 } 765 766 /** 767 * __pci_start_power_transition - Start power transition of a PCI device 768 * @dev: PCI device to handle. 769 * @state: State to put the device into. 770 */ 771 static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state) 772 { 773 if (state == PCI_D0) { 774 pci_platform_power_transition(dev, PCI_D0); 775 /* 776 * Mandatory power management transition delays, see 777 * PCI Express Base Specification Revision 2.0 Section 778 * 6.6.1: Conventional Reset. Do not delay for 779 * devices powered on/off by corresponding bridge, 780 * because have already delayed for the bridge. 781 */ 782 if (dev->runtime_d3cold) { 783 msleep(dev->d3cold_delay); 784 /* 785 * When powering on a bridge from D3cold, the 786 * whole hierarchy may be powered on into 787 * D0uninitialized state, resume them to give 788 * them a chance to suspend again 789 */ 790 pci_wakeup_bus(dev->subordinate); 791 } 792 } 793 } 794 795 /** 796 * __pci_dev_set_current_state - Set current state of a PCI device 797 * @dev: Device to handle 798 * @data: pointer to state to be set 799 */ 800 static int __pci_dev_set_current_state(struct pci_dev *dev, void *data) 801 { 802 pci_power_t state = *(pci_power_t *)data; 803 804 dev->current_state = state; 805 return 0; 806 } 807 808 /** 809 * __pci_bus_set_current_state - Walk given bus and set current state of devices 810 * @bus: Top bus of the subtree to walk. 811 * @state: state to be set 812 */ 813 static void __pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state) 814 { 815 if (bus) 816 pci_walk_bus(bus, __pci_dev_set_current_state, &state); 817 } 818 819 /** 820 * __pci_complete_power_transition - Complete power transition of a PCI device 821 * @dev: PCI device to handle. 822 * @state: State to put the device into. 823 * 824 * This function should not be called directly by device drivers. 825 */ 826 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state) 827 { 828 int ret; 829 830 if (state <= PCI_D0) 831 return -EINVAL; 832 ret = pci_platform_power_transition(dev, state); 833 /* Power off the bridge may power off the whole hierarchy */ 834 if (!ret && state == PCI_D3cold) 835 __pci_bus_set_current_state(dev->subordinate, PCI_D3cold); 836 return ret; 837 } 838 EXPORT_SYMBOL_GPL(__pci_complete_power_transition); 839 840 /** 841 * pci_set_power_state - Set the power state of a PCI device 842 * @dev: PCI device to handle. 843 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into. 844 * 845 * Transition a device to a new power state, using the platform firmware and/or 846 * the device's PCI PM registers. 847 * 848 * RETURN VALUE: 849 * -EINVAL if the requested state is invalid. 850 * -EIO if device does not support PCI PM or its PM capabilities register has a 851 * wrong version, or device doesn't support the requested state. 852 * 0 if device already is in the requested state. 853 * 0 if device's power state has been successfully changed. 854 */ 855 int pci_set_power_state(struct pci_dev *dev, pci_power_t state) 856 { 857 int error; 858 859 /* bound the state we're entering */ 860 if (state > PCI_D3cold) 861 state = PCI_D3cold; 862 else if (state < PCI_D0) 863 state = PCI_D0; 864 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev)) 865 /* 866 * If the device or the parent bridge do not support PCI PM, 867 * ignore the request if we're doing anything other than putting 868 * it into D0 (which would only happen on boot). 869 */ 870 return 0; 871 872 /* Check if we're already there */ 873 if (dev->current_state == state) 874 return 0; 875 876 __pci_start_power_transition(dev, state); 877 878 /* This device is quirked not to be put into D3, so 879 don't put it in D3 */ 880 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3)) 881 return 0; 882 883 /* 884 * To put device in D3cold, we put device into D3hot in native 885 * way, then put device into D3cold with platform ops 886 */ 887 error = pci_raw_set_power_state(dev, state > PCI_D3hot ? 888 PCI_D3hot : state); 889 890 if (!__pci_complete_power_transition(dev, state)) 891 error = 0; 892 893 return error; 894 } 895 EXPORT_SYMBOL(pci_set_power_state); 896 897 /** 898 * pci_choose_state - Choose the power state of a PCI device 899 * @dev: PCI device to be suspended 900 * @state: target sleep state for the whole system. This is the value 901 * that is passed to suspend() function. 902 * 903 * Returns PCI power state suitable for given device and given system 904 * message. 905 */ 906 907 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state) 908 { 909 pci_power_t ret; 910 911 if (!dev->pm_cap) 912 return PCI_D0; 913 914 ret = platform_pci_choose_state(dev); 915 if (ret != PCI_POWER_ERROR) 916 return ret; 917 918 switch (state.event) { 919 case PM_EVENT_ON: 920 return PCI_D0; 921 case PM_EVENT_FREEZE: 922 case PM_EVENT_PRETHAW: 923 /* REVISIT both freeze and pre-thaw "should" use D0 */ 924 case PM_EVENT_SUSPEND: 925 case PM_EVENT_HIBERNATE: 926 return PCI_D3hot; 927 default: 928 dev_info(&dev->dev, "unrecognized suspend event %d\n", 929 state.event); 930 BUG(); 931 } 932 return PCI_D0; 933 } 934 EXPORT_SYMBOL(pci_choose_state); 935 936 #define PCI_EXP_SAVE_REGS 7 937 938 static struct pci_cap_saved_state *_pci_find_saved_cap(struct pci_dev *pci_dev, 939 u16 cap, bool extended) 940 { 941 struct pci_cap_saved_state *tmp; 942 943 hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) { 944 if (tmp->cap.cap_extended == extended && tmp->cap.cap_nr == cap) 945 return tmp; 946 } 947 return NULL; 948 } 949 950 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap) 951 { 952 return _pci_find_saved_cap(dev, cap, false); 953 } 954 955 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, u16 cap) 956 { 957 return _pci_find_saved_cap(dev, cap, true); 958 } 959 960 static int pci_save_pcie_state(struct pci_dev *dev) 961 { 962 int i = 0; 963 struct pci_cap_saved_state *save_state; 964 u16 *cap; 965 966 if (!pci_is_pcie(dev)) 967 return 0; 968 969 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); 970 if (!save_state) { 971 dev_err(&dev->dev, "buffer not found in %s\n", __func__); 972 return -ENOMEM; 973 } 974 975 cap = (u16 *)&save_state->cap.data[0]; 976 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]); 977 pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]); 978 pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]); 979 pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]); 980 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]); 981 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]); 982 pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]); 983 984 return 0; 985 } 986 987 static void pci_restore_pcie_state(struct pci_dev *dev) 988 { 989 int i = 0; 990 struct pci_cap_saved_state *save_state; 991 u16 *cap; 992 993 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); 994 if (!save_state) 995 return; 996 997 cap = (u16 *)&save_state->cap.data[0]; 998 pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]); 999 pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]); 1000 pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]); 1001 pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]); 1002 pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]); 1003 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]); 1004 pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]); 1005 } 1006 1007 1008 static int pci_save_pcix_state(struct pci_dev *dev) 1009 { 1010 int pos; 1011 struct pci_cap_saved_state *save_state; 1012 1013 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); 1014 if (!pos) 1015 return 0; 1016 1017 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); 1018 if (!save_state) { 1019 dev_err(&dev->dev, "buffer not found in %s\n", __func__); 1020 return -ENOMEM; 1021 } 1022 1023 pci_read_config_word(dev, pos + PCI_X_CMD, 1024 (u16 *)save_state->cap.data); 1025 1026 return 0; 1027 } 1028 1029 static void pci_restore_pcix_state(struct pci_dev *dev) 1030 { 1031 int i = 0, pos; 1032 struct pci_cap_saved_state *save_state; 1033 u16 *cap; 1034 1035 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); 1036 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); 1037 if (!save_state || !pos) 1038 return; 1039 cap = (u16 *)&save_state->cap.data[0]; 1040 1041 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]); 1042 } 1043 1044 1045 /** 1046 * pci_save_state - save the PCI configuration space of a device before suspending 1047 * @dev: - PCI device that we're dealing with 1048 */ 1049 int pci_save_state(struct pci_dev *dev) 1050 { 1051 int i; 1052 /* XXX: 100% dword access ok here? */ 1053 for (i = 0; i < 16; i++) 1054 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]); 1055 dev->state_saved = true; 1056 1057 i = pci_save_pcie_state(dev); 1058 if (i != 0) 1059 return i; 1060 1061 i = pci_save_pcix_state(dev); 1062 if (i != 0) 1063 return i; 1064 1065 return pci_save_vc_state(dev); 1066 } 1067 EXPORT_SYMBOL(pci_save_state); 1068 1069 static void pci_restore_config_dword(struct pci_dev *pdev, int offset, 1070 u32 saved_val, int retry) 1071 { 1072 u32 val; 1073 1074 pci_read_config_dword(pdev, offset, &val); 1075 if (val == saved_val) 1076 return; 1077 1078 for (;;) { 1079 dev_dbg(&pdev->dev, "restoring config space at offset %#x (was %#x, writing %#x)\n", 1080 offset, val, saved_val); 1081 pci_write_config_dword(pdev, offset, saved_val); 1082 if (retry-- <= 0) 1083 return; 1084 1085 pci_read_config_dword(pdev, offset, &val); 1086 if (val == saved_val) 1087 return; 1088 1089 mdelay(1); 1090 } 1091 } 1092 1093 static void pci_restore_config_space_range(struct pci_dev *pdev, 1094 int start, int end, int retry) 1095 { 1096 int index; 1097 1098 for (index = end; index >= start; index--) 1099 pci_restore_config_dword(pdev, 4 * index, 1100 pdev->saved_config_space[index], 1101 retry); 1102 } 1103 1104 static void pci_restore_config_space(struct pci_dev *pdev) 1105 { 1106 if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) { 1107 pci_restore_config_space_range(pdev, 10, 15, 0); 1108 /* Restore BARs before the command register. */ 1109 pci_restore_config_space_range(pdev, 4, 9, 10); 1110 pci_restore_config_space_range(pdev, 0, 3, 0); 1111 } else { 1112 pci_restore_config_space_range(pdev, 0, 15, 0); 1113 } 1114 } 1115 1116 /** 1117 * pci_restore_state - Restore the saved state of a PCI device 1118 * @dev: - PCI device that we're dealing with 1119 */ 1120 void pci_restore_state(struct pci_dev *dev) 1121 { 1122 if (!dev->state_saved) 1123 return; 1124 1125 /* PCI Express register must be restored first */ 1126 pci_restore_pcie_state(dev); 1127 pci_restore_ats_state(dev); 1128 pci_restore_vc_state(dev); 1129 1130 pci_cleanup_aer_error_status_regs(dev); 1131 1132 pci_restore_config_space(dev); 1133 1134 pci_restore_pcix_state(dev); 1135 pci_restore_msi_state(dev); 1136 1137 /* Restore ACS and IOV configuration state */ 1138 pci_enable_acs(dev); 1139 pci_restore_iov_state(dev); 1140 1141 dev->state_saved = false; 1142 } 1143 EXPORT_SYMBOL(pci_restore_state); 1144 1145 struct pci_saved_state { 1146 u32 config_space[16]; 1147 struct pci_cap_saved_data cap[0]; 1148 }; 1149 1150 /** 1151 * pci_store_saved_state - Allocate and return an opaque struct containing 1152 * the device saved state. 1153 * @dev: PCI device that we're dealing with 1154 * 1155 * Return NULL if no state or error. 1156 */ 1157 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev) 1158 { 1159 struct pci_saved_state *state; 1160 struct pci_cap_saved_state *tmp; 1161 struct pci_cap_saved_data *cap; 1162 size_t size; 1163 1164 if (!dev->state_saved) 1165 return NULL; 1166 1167 size = sizeof(*state) + sizeof(struct pci_cap_saved_data); 1168 1169 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) 1170 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size; 1171 1172 state = kzalloc(size, GFP_KERNEL); 1173 if (!state) 1174 return NULL; 1175 1176 memcpy(state->config_space, dev->saved_config_space, 1177 sizeof(state->config_space)); 1178 1179 cap = state->cap; 1180 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) { 1181 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size; 1182 memcpy(cap, &tmp->cap, len); 1183 cap = (struct pci_cap_saved_data *)((u8 *)cap + len); 1184 } 1185 /* Empty cap_save terminates list */ 1186 1187 return state; 1188 } 1189 EXPORT_SYMBOL_GPL(pci_store_saved_state); 1190 1191 /** 1192 * pci_load_saved_state - Reload the provided save state into struct pci_dev. 1193 * @dev: PCI device that we're dealing with 1194 * @state: Saved state returned from pci_store_saved_state() 1195 */ 1196 int pci_load_saved_state(struct pci_dev *dev, 1197 struct pci_saved_state *state) 1198 { 1199 struct pci_cap_saved_data *cap; 1200 1201 dev->state_saved = false; 1202 1203 if (!state) 1204 return 0; 1205 1206 memcpy(dev->saved_config_space, state->config_space, 1207 sizeof(state->config_space)); 1208 1209 cap = state->cap; 1210 while (cap->size) { 1211 struct pci_cap_saved_state *tmp; 1212 1213 tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended); 1214 if (!tmp || tmp->cap.size != cap->size) 1215 return -EINVAL; 1216 1217 memcpy(tmp->cap.data, cap->data, tmp->cap.size); 1218 cap = (struct pci_cap_saved_data *)((u8 *)cap + 1219 sizeof(struct pci_cap_saved_data) + cap->size); 1220 } 1221 1222 dev->state_saved = true; 1223 return 0; 1224 } 1225 EXPORT_SYMBOL_GPL(pci_load_saved_state); 1226 1227 /** 1228 * pci_load_and_free_saved_state - Reload the save state pointed to by state, 1229 * and free the memory allocated for it. 1230 * @dev: PCI device that we're dealing with 1231 * @state: Pointer to saved state returned from pci_store_saved_state() 1232 */ 1233 int pci_load_and_free_saved_state(struct pci_dev *dev, 1234 struct pci_saved_state **state) 1235 { 1236 int ret = pci_load_saved_state(dev, *state); 1237 kfree(*state); 1238 *state = NULL; 1239 return ret; 1240 } 1241 EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state); 1242 1243 int __weak pcibios_enable_device(struct pci_dev *dev, int bars) 1244 { 1245 return pci_enable_resources(dev, bars); 1246 } 1247 1248 static int do_pci_enable_device(struct pci_dev *dev, int bars) 1249 { 1250 int err; 1251 struct pci_dev *bridge; 1252 u16 cmd; 1253 u8 pin; 1254 1255 err = pci_set_power_state(dev, PCI_D0); 1256 if (err < 0 && err != -EIO) 1257 return err; 1258 1259 bridge = pci_upstream_bridge(dev); 1260 if (bridge) 1261 pcie_aspm_powersave_config_link(bridge); 1262 1263 err = pcibios_enable_device(dev, bars); 1264 if (err < 0) 1265 return err; 1266 pci_fixup_device(pci_fixup_enable, dev); 1267 1268 if (dev->msi_enabled || dev->msix_enabled) 1269 return 0; 1270 1271 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); 1272 if (pin) { 1273 pci_read_config_word(dev, PCI_COMMAND, &cmd); 1274 if (cmd & PCI_COMMAND_INTX_DISABLE) 1275 pci_write_config_word(dev, PCI_COMMAND, 1276 cmd & ~PCI_COMMAND_INTX_DISABLE); 1277 } 1278 1279 return 0; 1280 } 1281 1282 /** 1283 * pci_reenable_device - Resume abandoned device 1284 * @dev: PCI device to be resumed 1285 * 1286 * Note this function is a backend of pci_default_resume and is not supposed 1287 * to be called by normal code, write proper resume handler and use it instead. 1288 */ 1289 int pci_reenable_device(struct pci_dev *dev) 1290 { 1291 if (pci_is_enabled(dev)) 1292 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1); 1293 return 0; 1294 } 1295 EXPORT_SYMBOL(pci_reenable_device); 1296 1297 static void pci_enable_bridge(struct pci_dev *dev) 1298 { 1299 struct pci_dev *bridge; 1300 int retval; 1301 1302 bridge = pci_upstream_bridge(dev); 1303 if (bridge) 1304 pci_enable_bridge(bridge); 1305 1306 if (pci_is_enabled(dev)) { 1307 if (!dev->is_busmaster) 1308 pci_set_master(dev); 1309 return; 1310 } 1311 1312 retval = pci_enable_device(dev); 1313 if (retval) 1314 dev_err(&dev->dev, "Error enabling bridge (%d), continuing\n", 1315 retval); 1316 pci_set_master(dev); 1317 } 1318 1319 static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags) 1320 { 1321 struct pci_dev *bridge; 1322 int err; 1323 int i, bars = 0; 1324 1325 /* 1326 * Power state could be unknown at this point, either due to a fresh 1327 * boot or a device removal call. So get the current power state 1328 * so that things like MSI message writing will behave as expected 1329 * (e.g. if the device really is in D0 at enable time). 1330 */ 1331 if (dev->pm_cap) { 1332 u16 pmcsr; 1333 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); 1334 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); 1335 } 1336 1337 if (atomic_inc_return(&dev->enable_cnt) > 1) 1338 return 0; /* already enabled */ 1339 1340 bridge = pci_upstream_bridge(dev); 1341 if (bridge) 1342 pci_enable_bridge(bridge); 1343 1344 /* only skip sriov related */ 1345 for (i = 0; i <= PCI_ROM_RESOURCE; i++) 1346 if (dev->resource[i].flags & flags) 1347 bars |= (1 << i); 1348 for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++) 1349 if (dev->resource[i].flags & flags) 1350 bars |= (1 << i); 1351 1352 err = do_pci_enable_device(dev, bars); 1353 if (err < 0) 1354 atomic_dec(&dev->enable_cnt); 1355 return err; 1356 } 1357 1358 /** 1359 * pci_enable_device_io - Initialize a device for use with IO space 1360 * @dev: PCI device to be initialized 1361 * 1362 * Initialize device before it's used by a driver. Ask low-level code 1363 * to enable I/O resources. Wake up the device if it was suspended. 1364 * Beware, this function can fail. 1365 */ 1366 int pci_enable_device_io(struct pci_dev *dev) 1367 { 1368 return pci_enable_device_flags(dev, IORESOURCE_IO); 1369 } 1370 EXPORT_SYMBOL(pci_enable_device_io); 1371 1372 /** 1373 * pci_enable_device_mem - Initialize a device for use with Memory space 1374 * @dev: PCI device to be initialized 1375 * 1376 * Initialize device before it's used by a driver. Ask low-level code 1377 * to enable Memory resources. Wake up the device if it was suspended. 1378 * Beware, this function can fail. 1379 */ 1380 int pci_enable_device_mem(struct pci_dev *dev) 1381 { 1382 return pci_enable_device_flags(dev, IORESOURCE_MEM); 1383 } 1384 EXPORT_SYMBOL(pci_enable_device_mem); 1385 1386 /** 1387 * pci_enable_device - Initialize device before it's used by a driver. 1388 * @dev: PCI device to be initialized 1389 * 1390 * Initialize device before it's used by a driver. Ask low-level code 1391 * to enable I/O and memory. Wake up the device if it was suspended. 1392 * Beware, this function can fail. 1393 * 1394 * Note we don't actually enable the device many times if we call 1395 * this function repeatedly (we just increment the count). 1396 */ 1397 int pci_enable_device(struct pci_dev *dev) 1398 { 1399 return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO); 1400 } 1401 EXPORT_SYMBOL(pci_enable_device); 1402 1403 /* 1404 * Managed PCI resources. This manages device on/off, intx/msi/msix 1405 * on/off and BAR regions. pci_dev itself records msi/msix status, so 1406 * there's no need to track it separately. pci_devres is initialized 1407 * when a device is enabled using managed PCI device enable interface. 1408 */ 1409 struct pci_devres { 1410 unsigned int enabled:1; 1411 unsigned int pinned:1; 1412 unsigned int orig_intx:1; 1413 unsigned int restore_intx:1; 1414 u32 region_mask; 1415 }; 1416 1417 static void pcim_release(struct device *gendev, void *res) 1418 { 1419 struct pci_dev *dev = to_pci_dev(gendev); 1420 struct pci_devres *this = res; 1421 int i; 1422 1423 if (dev->msi_enabled) 1424 pci_disable_msi(dev); 1425 if (dev->msix_enabled) 1426 pci_disable_msix(dev); 1427 1428 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) 1429 if (this->region_mask & (1 << i)) 1430 pci_release_region(dev, i); 1431 1432 if (this->restore_intx) 1433 pci_intx(dev, this->orig_intx); 1434 1435 if (this->enabled && !this->pinned) 1436 pci_disable_device(dev); 1437 } 1438 1439 static struct pci_devres *get_pci_dr(struct pci_dev *pdev) 1440 { 1441 struct pci_devres *dr, *new_dr; 1442 1443 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL); 1444 if (dr) 1445 return dr; 1446 1447 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL); 1448 if (!new_dr) 1449 return NULL; 1450 return devres_get(&pdev->dev, new_dr, NULL, NULL); 1451 } 1452 1453 static struct pci_devres *find_pci_dr(struct pci_dev *pdev) 1454 { 1455 if (pci_is_managed(pdev)) 1456 return devres_find(&pdev->dev, pcim_release, NULL, NULL); 1457 return NULL; 1458 } 1459 1460 /** 1461 * pcim_enable_device - Managed pci_enable_device() 1462 * @pdev: PCI device to be initialized 1463 * 1464 * Managed pci_enable_device(). 1465 */ 1466 int pcim_enable_device(struct pci_dev *pdev) 1467 { 1468 struct pci_devres *dr; 1469 int rc; 1470 1471 dr = get_pci_dr(pdev); 1472 if (unlikely(!dr)) 1473 return -ENOMEM; 1474 if (dr->enabled) 1475 return 0; 1476 1477 rc = pci_enable_device(pdev); 1478 if (!rc) { 1479 pdev->is_managed = 1; 1480 dr->enabled = 1; 1481 } 1482 return rc; 1483 } 1484 EXPORT_SYMBOL(pcim_enable_device); 1485 1486 /** 1487 * pcim_pin_device - Pin managed PCI device 1488 * @pdev: PCI device to pin 1489 * 1490 * Pin managed PCI device @pdev. Pinned device won't be disabled on 1491 * driver detach. @pdev must have been enabled with 1492 * pcim_enable_device(). 1493 */ 1494 void pcim_pin_device(struct pci_dev *pdev) 1495 { 1496 struct pci_devres *dr; 1497 1498 dr = find_pci_dr(pdev); 1499 WARN_ON(!dr || !dr->enabled); 1500 if (dr) 1501 dr->pinned = 1; 1502 } 1503 EXPORT_SYMBOL(pcim_pin_device); 1504 1505 /* 1506 * pcibios_add_device - provide arch specific hooks when adding device dev 1507 * @dev: the PCI device being added 1508 * 1509 * Permits the platform to provide architecture specific functionality when 1510 * devices are added. This is the default implementation. Architecture 1511 * implementations can override this. 1512 */ 1513 int __weak pcibios_add_device(struct pci_dev *dev) 1514 { 1515 return 0; 1516 } 1517 1518 /** 1519 * pcibios_release_device - provide arch specific hooks when releasing device dev 1520 * @dev: the PCI device being released 1521 * 1522 * Permits the platform to provide architecture specific functionality when 1523 * devices are released. This is the default implementation. Architecture 1524 * implementations can override this. 1525 */ 1526 void __weak pcibios_release_device(struct pci_dev *dev) {} 1527 1528 /** 1529 * pcibios_disable_device - disable arch specific PCI resources for device dev 1530 * @dev: the PCI device to disable 1531 * 1532 * Disables architecture specific PCI resources for the device. This 1533 * is the default implementation. Architecture implementations can 1534 * override this. 1535 */ 1536 void __weak pcibios_disable_device(struct pci_dev *dev) {} 1537 1538 /** 1539 * pcibios_penalize_isa_irq - penalize an ISA IRQ 1540 * @irq: ISA IRQ to penalize 1541 * @active: IRQ active or not 1542 * 1543 * Permits the platform to provide architecture-specific functionality when 1544 * penalizing ISA IRQs. This is the default implementation. Architecture 1545 * implementations can override this. 1546 */ 1547 void __weak pcibios_penalize_isa_irq(int irq, int active) {} 1548 1549 static void do_pci_disable_device(struct pci_dev *dev) 1550 { 1551 u16 pci_command; 1552 1553 pci_read_config_word(dev, PCI_COMMAND, &pci_command); 1554 if (pci_command & PCI_COMMAND_MASTER) { 1555 pci_command &= ~PCI_COMMAND_MASTER; 1556 pci_write_config_word(dev, PCI_COMMAND, pci_command); 1557 } 1558 1559 pcibios_disable_device(dev); 1560 } 1561 1562 /** 1563 * pci_disable_enabled_device - Disable device without updating enable_cnt 1564 * @dev: PCI device to disable 1565 * 1566 * NOTE: This function is a backend of PCI power management routines and is 1567 * not supposed to be called drivers. 1568 */ 1569 void pci_disable_enabled_device(struct pci_dev *dev) 1570 { 1571 if (pci_is_enabled(dev)) 1572 do_pci_disable_device(dev); 1573 } 1574 1575 /** 1576 * pci_disable_device - Disable PCI device after use 1577 * @dev: PCI device to be disabled 1578 * 1579 * Signal to the system that the PCI device is not in use by the system 1580 * anymore. This only involves disabling PCI bus-mastering, if active. 1581 * 1582 * Note we don't actually disable the device until all callers of 1583 * pci_enable_device() have called pci_disable_device(). 1584 */ 1585 void pci_disable_device(struct pci_dev *dev) 1586 { 1587 struct pci_devres *dr; 1588 1589 dr = find_pci_dr(dev); 1590 if (dr) 1591 dr->enabled = 0; 1592 1593 dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0, 1594 "disabling already-disabled device"); 1595 1596 if (atomic_dec_return(&dev->enable_cnt) != 0) 1597 return; 1598 1599 do_pci_disable_device(dev); 1600 1601 dev->is_busmaster = 0; 1602 } 1603 EXPORT_SYMBOL(pci_disable_device); 1604 1605 /** 1606 * pcibios_set_pcie_reset_state - set reset state for device dev 1607 * @dev: the PCIe device reset 1608 * @state: Reset state to enter into 1609 * 1610 * 1611 * Sets the PCIe reset state for the device. This is the default 1612 * implementation. Architecture implementations can override this. 1613 */ 1614 int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev, 1615 enum pcie_reset_state state) 1616 { 1617 return -EINVAL; 1618 } 1619 1620 /** 1621 * pci_set_pcie_reset_state - set reset state for device dev 1622 * @dev: the PCIe device reset 1623 * @state: Reset state to enter into 1624 * 1625 * 1626 * Sets the PCI reset state for the device. 1627 */ 1628 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state) 1629 { 1630 return pcibios_set_pcie_reset_state(dev, state); 1631 } 1632 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state); 1633 1634 /** 1635 * pci_check_pme_status - Check if given device has generated PME. 1636 * @dev: Device to check. 1637 * 1638 * Check the PME status of the device and if set, clear it and clear PME enable 1639 * (if set). Return 'true' if PME status and PME enable were both set or 1640 * 'false' otherwise. 1641 */ 1642 bool pci_check_pme_status(struct pci_dev *dev) 1643 { 1644 int pmcsr_pos; 1645 u16 pmcsr; 1646 bool ret = false; 1647 1648 if (!dev->pm_cap) 1649 return false; 1650 1651 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL; 1652 pci_read_config_word(dev, pmcsr_pos, &pmcsr); 1653 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS)) 1654 return false; 1655 1656 /* Clear PME status. */ 1657 pmcsr |= PCI_PM_CTRL_PME_STATUS; 1658 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) { 1659 /* Disable PME to avoid interrupt flood. */ 1660 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE; 1661 ret = true; 1662 } 1663 1664 pci_write_config_word(dev, pmcsr_pos, pmcsr); 1665 1666 return ret; 1667 } 1668 1669 /** 1670 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set. 1671 * @dev: Device to handle. 1672 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag. 1673 * 1674 * Check if @dev has generated PME and queue a resume request for it in that 1675 * case. 1676 */ 1677 static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset) 1678 { 1679 if (pme_poll_reset && dev->pme_poll) 1680 dev->pme_poll = false; 1681 1682 if (pci_check_pme_status(dev)) { 1683 pci_wakeup_event(dev); 1684 pm_request_resume(&dev->dev); 1685 } 1686 return 0; 1687 } 1688 1689 /** 1690 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary. 1691 * @bus: Top bus of the subtree to walk. 1692 */ 1693 void pci_pme_wakeup_bus(struct pci_bus *bus) 1694 { 1695 if (bus) 1696 pci_walk_bus(bus, pci_pme_wakeup, (void *)true); 1697 } 1698 1699 1700 /** 1701 * pci_pme_capable - check the capability of PCI device to generate PME# 1702 * @dev: PCI device to handle. 1703 * @state: PCI state from which device will issue PME#. 1704 */ 1705 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state) 1706 { 1707 if (!dev->pm_cap) 1708 return false; 1709 1710 return !!(dev->pme_support & (1 << state)); 1711 } 1712 EXPORT_SYMBOL(pci_pme_capable); 1713 1714 static void pci_pme_list_scan(struct work_struct *work) 1715 { 1716 struct pci_pme_device *pme_dev, *n; 1717 1718 mutex_lock(&pci_pme_list_mutex); 1719 list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) { 1720 if (pme_dev->dev->pme_poll) { 1721 struct pci_dev *bridge; 1722 1723 bridge = pme_dev->dev->bus->self; 1724 /* 1725 * If bridge is in low power state, the 1726 * configuration space of subordinate devices 1727 * may be not accessible 1728 */ 1729 if (bridge && bridge->current_state != PCI_D0) 1730 continue; 1731 pci_pme_wakeup(pme_dev->dev, NULL); 1732 } else { 1733 list_del(&pme_dev->list); 1734 kfree(pme_dev); 1735 } 1736 } 1737 if (!list_empty(&pci_pme_list)) 1738 schedule_delayed_work(&pci_pme_work, 1739 msecs_to_jiffies(PME_TIMEOUT)); 1740 mutex_unlock(&pci_pme_list_mutex); 1741 } 1742 1743 static void __pci_pme_active(struct pci_dev *dev, bool enable) 1744 { 1745 u16 pmcsr; 1746 1747 if (!dev->pme_support) 1748 return; 1749 1750 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); 1751 /* Clear PME_Status by writing 1 to it and enable PME# */ 1752 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE; 1753 if (!enable) 1754 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE; 1755 1756 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); 1757 } 1758 1759 /** 1760 * pci_pme_active - enable or disable PCI device's PME# function 1761 * @dev: PCI device to handle. 1762 * @enable: 'true' to enable PME# generation; 'false' to disable it. 1763 * 1764 * The caller must verify that the device is capable of generating PME# before 1765 * calling this function with @enable equal to 'true'. 1766 */ 1767 void pci_pme_active(struct pci_dev *dev, bool enable) 1768 { 1769 __pci_pme_active(dev, enable); 1770 1771 /* 1772 * PCI (as opposed to PCIe) PME requires that the device have 1773 * its PME# line hooked up correctly. Not all hardware vendors 1774 * do this, so the PME never gets delivered and the device 1775 * remains asleep. The easiest way around this is to 1776 * periodically walk the list of suspended devices and check 1777 * whether any have their PME flag set. The assumption is that 1778 * we'll wake up often enough anyway that this won't be a huge 1779 * hit, and the power savings from the devices will still be a 1780 * win. 1781 * 1782 * Although PCIe uses in-band PME message instead of PME# line 1783 * to report PME, PME does not work for some PCIe devices in 1784 * reality. For example, there are devices that set their PME 1785 * status bits, but don't really bother to send a PME message; 1786 * there are PCI Express Root Ports that don't bother to 1787 * trigger interrupts when they receive PME messages from the 1788 * devices below. So PME poll is used for PCIe devices too. 1789 */ 1790 1791 if (dev->pme_poll) { 1792 struct pci_pme_device *pme_dev; 1793 if (enable) { 1794 pme_dev = kmalloc(sizeof(struct pci_pme_device), 1795 GFP_KERNEL); 1796 if (!pme_dev) { 1797 dev_warn(&dev->dev, "can't enable PME#\n"); 1798 return; 1799 } 1800 pme_dev->dev = dev; 1801 mutex_lock(&pci_pme_list_mutex); 1802 list_add(&pme_dev->list, &pci_pme_list); 1803 if (list_is_singular(&pci_pme_list)) 1804 schedule_delayed_work(&pci_pme_work, 1805 msecs_to_jiffies(PME_TIMEOUT)); 1806 mutex_unlock(&pci_pme_list_mutex); 1807 } else { 1808 mutex_lock(&pci_pme_list_mutex); 1809 list_for_each_entry(pme_dev, &pci_pme_list, list) { 1810 if (pme_dev->dev == dev) { 1811 list_del(&pme_dev->list); 1812 kfree(pme_dev); 1813 break; 1814 } 1815 } 1816 mutex_unlock(&pci_pme_list_mutex); 1817 } 1818 } 1819 1820 dev_dbg(&dev->dev, "PME# %s\n", enable ? "enabled" : "disabled"); 1821 } 1822 EXPORT_SYMBOL(pci_pme_active); 1823 1824 /** 1825 * __pci_enable_wake - enable PCI device as wakeup event source 1826 * @dev: PCI device affected 1827 * @state: PCI state from which device will issue wakeup events 1828 * @runtime: True if the events are to be generated at run time 1829 * @enable: True to enable event generation; false to disable 1830 * 1831 * This enables the device as a wakeup event source, or disables it. 1832 * When such events involves platform-specific hooks, those hooks are 1833 * called automatically by this routine. 1834 * 1835 * Devices with legacy power management (no standard PCI PM capabilities) 1836 * always require such platform hooks. 1837 * 1838 * RETURN VALUE: 1839 * 0 is returned on success 1840 * -EINVAL is returned if device is not supposed to wake up the system 1841 * Error code depending on the platform is returned if both the platform and 1842 * the native mechanism fail to enable the generation of wake-up events 1843 */ 1844 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, 1845 bool runtime, bool enable) 1846 { 1847 int ret = 0; 1848 1849 if (enable && !runtime && !device_may_wakeup(&dev->dev)) 1850 return -EINVAL; 1851 1852 /* Don't do the same thing twice in a row for one device. */ 1853 if (!!enable == !!dev->wakeup_prepared) 1854 return 0; 1855 1856 /* 1857 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don 1858 * Anderson we should be doing PME# wake enable followed by ACPI wake 1859 * enable. To disable wake-up we call the platform first, for symmetry. 1860 */ 1861 1862 if (enable) { 1863 int error; 1864 1865 if (pci_pme_capable(dev, state)) 1866 pci_pme_active(dev, true); 1867 else 1868 ret = 1; 1869 error = runtime ? platform_pci_run_wake(dev, true) : 1870 platform_pci_sleep_wake(dev, true); 1871 if (ret) 1872 ret = error; 1873 if (!ret) 1874 dev->wakeup_prepared = true; 1875 } else { 1876 if (runtime) 1877 platform_pci_run_wake(dev, false); 1878 else 1879 platform_pci_sleep_wake(dev, false); 1880 pci_pme_active(dev, false); 1881 dev->wakeup_prepared = false; 1882 } 1883 1884 return ret; 1885 } 1886 EXPORT_SYMBOL(__pci_enable_wake); 1887 1888 /** 1889 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold 1890 * @dev: PCI device to prepare 1891 * @enable: True to enable wake-up event generation; false to disable 1892 * 1893 * Many drivers want the device to wake up the system from D3_hot or D3_cold 1894 * and this function allows them to set that up cleanly - pci_enable_wake() 1895 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI 1896 * ordering constraints. 1897 * 1898 * This function only returns error code if the device is not capable of 1899 * generating PME# from both D3_hot and D3_cold, and the platform is unable to 1900 * enable wake-up power for it. 1901 */ 1902 int pci_wake_from_d3(struct pci_dev *dev, bool enable) 1903 { 1904 return pci_pme_capable(dev, PCI_D3cold) ? 1905 pci_enable_wake(dev, PCI_D3cold, enable) : 1906 pci_enable_wake(dev, PCI_D3hot, enable); 1907 } 1908 EXPORT_SYMBOL(pci_wake_from_d3); 1909 1910 /** 1911 * pci_target_state - find an appropriate low power state for a given PCI dev 1912 * @dev: PCI device 1913 * 1914 * Use underlying platform code to find a supported low power state for @dev. 1915 * If the platform can't manage @dev, return the deepest state from which it 1916 * can generate wake events, based on any available PME info. 1917 */ 1918 static pci_power_t pci_target_state(struct pci_dev *dev) 1919 { 1920 pci_power_t target_state = PCI_D3hot; 1921 1922 if (platform_pci_power_manageable(dev)) { 1923 /* 1924 * Call the platform to choose the target state of the device 1925 * and enable wake-up from this state if supported. 1926 */ 1927 pci_power_t state = platform_pci_choose_state(dev); 1928 1929 switch (state) { 1930 case PCI_POWER_ERROR: 1931 case PCI_UNKNOWN: 1932 break; 1933 case PCI_D1: 1934 case PCI_D2: 1935 if (pci_no_d1d2(dev)) 1936 break; 1937 default: 1938 target_state = state; 1939 } 1940 } else if (!dev->pm_cap) { 1941 target_state = PCI_D0; 1942 } else if (device_may_wakeup(&dev->dev)) { 1943 /* 1944 * Find the deepest state from which the device can generate 1945 * wake-up events, make it the target state and enable device 1946 * to generate PME#. 1947 */ 1948 if (dev->pme_support) { 1949 while (target_state 1950 && !(dev->pme_support & (1 << target_state))) 1951 target_state--; 1952 } 1953 } 1954 1955 return target_state; 1956 } 1957 1958 /** 1959 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state 1960 * @dev: Device to handle. 1961 * 1962 * Choose the power state appropriate for the device depending on whether 1963 * it can wake up the system and/or is power manageable by the platform 1964 * (PCI_D3hot is the default) and put the device into that state. 1965 */ 1966 int pci_prepare_to_sleep(struct pci_dev *dev) 1967 { 1968 pci_power_t target_state = pci_target_state(dev); 1969 int error; 1970 1971 if (target_state == PCI_POWER_ERROR) 1972 return -EIO; 1973 1974 pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev)); 1975 1976 error = pci_set_power_state(dev, target_state); 1977 1978 if (error) 1979 pci_enable_wake(dev, target_state, false); 1980 1981 return error; 1982 } 1983 EXPORT_SYMBOL(pci_prepare_to_sleep); 1984 1985 /** 1986 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state 1987 * @dev: Device to handle. 1988 * 1989 * Disable device's system wake-up capability and put it into D0. 1990 */ 1991 int pci_back_from_sleep(struct pci_dev *dev) 1992 { 1993 pci_enable_wake(dev, PCI_D0, false); 1994 return pci_set_power_state(dev, PCI_D0); 1995 } 1996 EXPORT_SYMBOL(pci_back_from_sleep); 1997 1998 /** 1999 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend. 2000 * @dev: PCI device being suspended. 2001 * 2002 * Prepare @dev to generate wake-up events at run time and put it into a low 2003 * power state. 2004 */ 2005 int pci_finish_runtime_suspend(struct pci_dev *dev) 2006 { 2007 pci_power_t target_state = pci_target_state(dev); 2008 int error; 2009 2010 if (target_state == PCI_POWER_ERROR) 2011 return -EIO; 2012 2013 dev->runtime_d3cold = target_state == PCI_D3cold; 2014 2015 __pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev)); 2016 2017 error = pci_set_power_state(dev, target_state); 2018 2019 if (error) { 2020 __pci_enable_wake(dev, target_state, true, false); 2021 dev->runtime_d3cold = false; 2022 } 2023 2024 return error; 2025 } 2026 2027 /** 2028 * pci_dev_run_wake - Check if device can generate run-time wake-up events. 2029 * @dev: Device to check. 2030 * 2031 * Return true if the device itself is capable of generating wake-up events 2032 * (through the platform or using the native PCIe PME) or if the device supports 2033 * PME and one of its upstream bridges can generate wake-up events. 2034 */ 2035 bool pci_dev_run_wake(struct pci_dev *dev) 2036 { 2037 struct pci_bus *bus = dev->bus; 2038 2039 if (device_run_wake(&dev->dev)) 2040 return true; 2041 2042 if (!dev->pme_support) 2043 return false; 2044 2045 while (bus->parent) { 2046 struct pci_dev *bridge = bus->self; 2047 2048 if (device_run_wake(&bridge->dev)) 2049 return true; 2050 2051 bus = bus->parent; 2052 } 2053 2054 /* We have reached the root bus. */ 2055 if (bus->bridge) 2056 return device_run_wake(bus->bridge); 2057 2058 return false; 2059 } 2060 EXPORT_SYMBOL_GPL(pci_dev_run_wake); 2061 2062 /** 2063 * pci_dev_keep_suspended - Check if the device can stay in the suspended state. 2064 * @pci_dev: Device to check. 2065 * 2066 * Return 'true' if the device is runtime-suspended, it doesn't have to be 2067 * reconfigured due to wakeup settings difference between system and runtime 2068 * suspend and the current power state of it is suitable for the upcoming 2069 * (system) transition. 2070 * 2071 * If the device is not configured for system wakeup, disable PME for it before 2072 * returning 'true' to prevent it from waking up the system unnecessarily. 2073 */ 2074 bool pci_dev_keep_suspended(struct pci_dev *pci_dev) 2075 { 2076 struct device *dev = &pci_dev->dev; 2077 2078 if (!pm_runtime_suspended(dev) 2079 || pci_target_state(pci_dev) != pci_dev->current_state 2080 || platform_pci_need_resume(pci_dev)) 2081 return false; 2082 2083 /* 2084 * At this point the device is good to go unless it's been configured 2085 * to generate PME at the runtime suspend time, but it is not supposed 2086 * to wake up the system. In that case, simply disable PME for it 2087 * (it will have to be re-enabled on exit from system resume). 2088 * 2089 * If the device's power state is D3cold and the platform check above 2090 * hasn't triggered, the device's configuration is suitable and we don't 2091 * need to manipulate it at all. 2092 */ 2093 spin_lock_irq(&dev->power.lock); 2094 2095 if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold && 2096 !device_may_wakeup(dev)) 2097 __pci_pme_active(pci_dev, false); 2098 2099 spin_unlock_irq(&dev->power.lock); 2100 return true; 2101 } 2102 2103 /** 2104 * pci_dev_complete_resume - Finalize resume from system sleep for a device. 2105 * @pci_dev: Device to handle. 2106 * 2107 * If the device is runtime suspended and wakeup-capable, enable PME for it as 2108 * it might have been disabled during the prepare phase of system suspend if 2109 * the device was not configured for system wakeup. 2110 */ 2111 void pci_dev_complete_resume(struct pci_dev *pci_dev) 2112 { 2113 struct device *dev = &pci_dev->dev; 2114 2115 if (!pci_dev_run_wake(pci_dev)) 2116 return; 2117 2118 spin_lock_irq(&dev->power.lock); 2119 2120 if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold) 2121 __pci_pme_active(pci_dev, true); 2122 2123 spin_unlock_irq(&dev->power.lock); 2124 } 2125 2126 void pci_config_pm_runtime_get(struct pci_dev *pdev) 2127 { 2128 struct device *dev = &pdev->dev; 2129 struct device *parent = dev->parent; 2130 2131 if (parent) 2132 pm_runtime_get_sync(parent); 2133 pm_runtime_get_noresume(dev); 2134 /* 2135 * pdev->current_state is set to PCI_D3cold during suspending, 2136 * so wait until suspending completes 2137 */ 2138 pm_runtime_barrier(dev); 2139 /* 2140 * Only need to resume devices in D3cold, because config 2141 * registers are still accessible for devices suspended but 2142 * not in D3cold. 2143 */ 2144 if (pdev->current_state == PCI_D3cold) 2145 pm_runtime_resume(dev); 2146 } 2147 2148 void pci_config_pm_runtime_put(struct pci_dev *pdev) 2149 { 2150 struct device *dev = &pdev->dev; 2151 struct device *parent = dev->parent; 2152 2153 pm_runtime_put(dev); 2154 if (parent) 2155 pm_runtime_put_sync(parent); 2156 } 2157 2158 /** 2159 * pci_pm_init - Initialize PM functions of given PCI device 2160 * @dev: PCI device to handle. 2161 */ 2162 void pci_pm_init(struct pci_dev *dev) 2163 { 2164 int pm; 2165 u16 pmc; 2166 2167 pm_runtime_forbid(&dev->dev); 2168 pm_runtime_set_active(&dev->dev); 2169 pm_runtime_enable(&dev->dev); 2170 device_enable_async_suspend(&dev->dev); 2171 dev->wakeup_prepared = false; 2172 2173 dev->pm_cap = 0; 2174 dev->pme_support = 0; 2175 2176 /* find PCI PM capability in list */ 2177 pm = pci_find_capability(dev, PCI_CAP_ID_PM); 2178 if (!pm) 2179 return; 2180 /* Check device's ability to generate PME# */ 2181 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc); 2182 2183 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) { 2184 dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n", 2185 pmc & PCI_PM_CAP_VER_MASK); 2186 return; 2187 } 2188 2189 dev->pm_cap = pm; 2190 dev->d3_delay = PCI_PM_D3_WAIT; 2191 dev->d3cold_delay = PCI_PM_D3COLD_WAIT; 2192 dev->d3cold_allowed = true; 2193 2194 dev->d1_support = false; 2195 dev->d2_support = false; 2196 if (!pci_no_d1d2(dev)) { 2197 if (pmc & PCI_PM_CAP_D1) 2198 dev->d1_support = true; 2199 if (pmc & PCI_PM_CAP_D2) 2200 dev->d2_support = true; 2201 2202 if (dev->d1_support || dev->d2_support) 2203 dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n", 2204 dev->d1_support ? " D1" : "", 2205 dev->d2_support ? " D2" : ""); 2206 } 2207 2208 pmc &= PCI_PM_CAP_PME_MASK; 2209 if (pmc) { 2210 dev_printk(KERN_DEBUG, &dev->dev, 2211 "PME# supported from%s%s%s%s%s\n", 2212 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "", 2213 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "", 2214 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "", 2215 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "", 2216 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : ""); 2217 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT; 2218 dev->pme_poll = true; 2219 /* 2220 * Make device's PM flags reflect the wake-up capability, but 2221 * let the user space enable it to wake up the system as needed. 2222 */ 2223 device_set_wakeup_capable(&dev->dev, true); 2224 /* Disable the PME# generation functionality */ 2225 pci_pme_active(dev, false); 2226 } 2227 } 2228 2229 static unsigned long pci_ea_flags(struct pci_dev *dev, u8 prop) 2230 { 2231 unsigned long flags = IORESOURCE_PCI_FIXED; 2232 2233 switch (prop) { 2234 case PCI_EA_P_MEM: 2235 case PCI_EA_P_VF_MEM: 2236 flags |= IORESOURCE_MEM; 2237 break; 2238 case PCI_EA_P_MEM_PREFETCH: 2239 case PCI_EA_P_VF_MEM_PREFETCH: 2240 flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH; 2241 break; 2242 case PCI_EA_P_IO: 2243 flags |= IORESOURCE_IO; 2244 break; 2245 default: 2246 return 0; 2247 } 2248 2249 return flags; 2250 } 2251 2252 static struct resource *pci_ea_get_resource(struct pci_dev *dev, u8 bei, 2253 u8 prop) 2254 { 2255 if (bei <= PCI_EA_BEI_BAR5 && prop <= PCI_EA_P_IO) 2256 return &dev->resource[bei]; 2257 #ifdef CONFIG_PCI_IOV 2258 else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5 && 2259 (prop == PCI_EA_P_VF_MEM || prop == PCI_EA_P_VF_MEM_PREFETCH)) 2260 return &dev->resource[PCI_IOV_RESOURCES + 2261 bei - PCI_EA_BEI_VF_BAR0]; 2262 #endif 2263 else if (bei == PCI_EA_BEI_ROM) 2264 return &dev->resource[PCI_ROM_RESOURCE]; 2265 else 2266 return NULL; 2267 } 2268 2269 /* Read an Enhanced Allocation (EA) entry */ 2270 static int pci_ea_read(struct pci_dev *dev, int offset) 2271 { 2272 struct resource *res; 2273 int ent_size, ent_offset = offset; 2274 resource_size_t start, end; 2275 unsigned long flags; 2276 u32 dw0, bei, base, max_offset; 2277 u8 prop; 2278 bool support_64 = (sizeof(resource_size_t) >= 8); 2279 2280 pci_read_config_dword(dev, ent_offset, &dw0); 2281 ent_offset += 4; 2282 2283 /* Entry size field indicates DWORDs after 1st */ 2284 ent_size = ((dw0 & PCI_EA_ES) + 1) << 2; 2285 2286 if (!(dw0 & PCI_EA_ENABLE)) /* Entry not enabled */ 2287 goto out; 2288 2289 bei = (dw0 & PCI_EA_BEI) >> 4; 2290 prop = (dw0 & PCI_EA_PP) >> 8; 2291 2292 /* 2293 * If the Property is in the reserved range, try the Secondary 2294 * Property instead. 2295 */ 2296 if (prop > PCI_EA_P_BRIDGE_IO && prop < PCI_EA_P_MEM_RESERVED) 2297 prop = (dw0 & PCI_EA_SP) >> 16; 2298 if (prop > PCI_EA_P_BRIDGE_IO) 2299 goto out; 2300 2301 res = pci_ea_get_resource(dev, bei, prop); 2302 if (!res) { 2303 dev_err(&dev->dev, "Unsupported EA entry BEI: %u\n", bei); 2304 goto out; 2305 } 2306 2307 flags = pci_ea_flags(dev, prop); 2308 if (!flags) { 2309 dev_err(&dev->dev, "Unsupported EA properties: %#x\n", prop); 2310 goto out; 2311 } 2312 2313 /* Read Base */ 2314 pci_read_config_dword(dev, ent_offset, &base); 2315 start = (base & PCI_EA_FIELD_MASK); 2316 ent_offset += 4; 2317 2318 /* Read MaxOffset */ 2319 pci_read_config_dword(dev, ent_offset, &max_offset); 2320 ent_offset += 4; 2321 2322 /* Read Base MSBs (if 64-bit entry) */ 2323 if (base & PCI_EA_IS_64) { 2324 u32 base_upper; 2325 2326 pci_read_config_dword(dev, ent_offset, &base_upper); 2327 ent_offset += 4; 2328 2329 flags |= IORESOURCE_MEM_64; 2330 2331 /* entry starts above 32-bit boundary, can't use */ 2332 if (!support_64 && base_upper) 2333 goto out; 2334 2335 if (support_64) 2336 start |= ((u64)base_upper << 32); 2337 } 2338 2339 end = start + (max_offset | 0x03); 2340 2341 /* Read MaxOffset MSBs (if 64-bit entry) */ 2342 if (max_offset & PCI_EA_IS_64) { 2343 u32 max_offset_upper; 2344 2345 pci_read_config_dword(dev, ent_offset, &max_offset_upper); 2346 ent_offset += 4; 2347 2348 flags |= IORESOURCE_MEM_64; 2349 2350 /* entry too big, can't use */ 2351 if (!support_64 && max_offset_upper) 2352 goto out; 2353 2354 if (support_64) 2355 end += ((u64)max_offset_upper << 32); 2356 } 2357 2358 if (end < start) { 2359 dev_err(&dev->dev, "EA Entry crosses address boundary\n"); 2360 goto out; 2361 } 2362 2363 if (ent_size != ent_offset - offset) { 2364 dev_err(&dev->dev, 2365 "EA Entry Size (%d) does not match length read (%d)\n", 2366 ent_size, ent_offset - offset); 2367 goto out; 2368 } 2369 2370 res->name = pci_name(dev); 2371 res->start = start; 2372 res->end = end; 2373 res->flags = flags; 2374 2375 if (bei <= PCI_EA_BEI_BAR5) 2376 dev_printk(KERN_DEBUG, &dev->dev, "BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n", 2377 bei, res, prop); 2378 else if (bei == PCI_EA_BEI_ROM) 2379 dev_printk(KERN_DEBUG, &dev->dev, "ROM: %pR (from Enhanced Allocation, properties %#02x)\n", 2380 res, prop); 2381 else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5) 2382 dev_printk(KERN_DEBUG, &dev->dev, "VF BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n", 2383 bei - PCI_EA_BEI_VF_BAR0, res, prop); 2384 else 2385 dev_printk(KERN_DEBUG, &dev->dev, "BEI %d res: %pR (from Enhanced Allocation, properties %#02x)\n", 2386 bei, res, prop); 2387 2388 out: 2389 return offset + ent_size; 2390 } 2391 2392 /* Enhanced Allocation Initalization */ 2393 void pci_ea_init(struct pci_dev *dev) 2394 { 2395 int ea; 2396 u8 num_ent; 2397 int offset; 2398 int i; 2399 2400 /* find PCI EA capability in list */ 2401 ea = pci_find_capability(dev, PCI_CAP_ID_EA); 2402 if (!ea) 2403 return; 2404 2405 /* determine the number of entries */ 2406 pci_bus_read_config_byte(dev->bus, dev->devfn, ea + PCI_EA_NUM_ENT, 2407 &num_ent); 2408 num_ent &= PCI_EA_NUM_ENT_MASK; 2409 2410 offset = ea + PCI_EA_FIRST_ENT; 2411 2412 /* Skip DWORD 2 for type 1 functions */ 2413 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) 2414 offset += 4; 2415 2416 /* parse each EA entry */ 2417 for (i = 0; i < num_ent; ++i) 2418 offset = pci_ea_read(dev, offset); 2419 } 2420 2421 static void pci_add_saved_cap(struct pci_dev *pci_dev, 2422 struct pci_cap_saved_state *new_cap) 2423 { 2424 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space); 2425 } 2426 2427 /** 2428 * _pci_add_cap_save_buffer - allocate buffer for saving given 2429 * capability registers 2430 * @dev: the PCI device 2431 * @cap: the capability to allocate the buffer for 2432 * @extended: Standard or Extended capability ID 2433 * @size: requested size of the buffer 2434 */ 2435 static int _pci_add_cap_save_buffer(struct pci_dev *dev, u16 cap, 2436 bool extended, unsigned int size) 2437 { 2438 int pos; 2439 struct pci_cap_saved_state *save_state; 2440 2441 if (extended) 2442 pos = pci_find_ext_capability(dev, cap); 2443 else 2444 pos = pci_find_capability(dev, cap); 2445 2446 if (!pos) 2447 return 0; 2448 2449 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL); 2450 if (!save_state) 2451 return -ENOMEM; 2452 2453 save_state->cap.cap_nr = cap; 2454 save_state->cap.cap_extended = extended; 2455 save_state->cap.size = size; 2456 pci_add_saved_cap(dev, save_state); 2457 2458 return 0; 2459 } 2460 2461 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size) 2462 { 2463 return _pci_add_cap_save_buffer(dev, cap, false, size); 2464 } 2465 2466 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, u16 cap, unsigned int size) 2467 { 2468 return _pci_add_cap_save_buffer(dev, cap, true, size); 2469 } 2470 2471 /** 2472 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities 2473 * @dev: the PCI device 2474 */ 2475 void pci_allocate_cap_save_buffers(struct pci_dev *dev) 2476 { 2477 int error; 2478 2479 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP, 2480 PCI_EXP_SAVE_REGS * sizeof(u16)); 2481 if (error) 2482 dev_err(&dev->dev, 2483 "unable to preallocate PCI Express save buffer\n"); 2484 2485 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16)); 2486 if (error) 2487 dev_err(&dev->dev, 2488 "unable to preallocate PCI-X save buffer\n"); 2489 2490 pci_allocate_vc_save_buffers(dev); 2491 } 2492 2493 void pci_free_cap_save_buffers(struct pci_dev *dev) 2494 { 2495 struct pci_cap_saved_state *tmp; 2496 struct hlist_node *n; 2497 2498 hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next) 2499 kfree(tmp); 2500 } 2501 2502 /** 2503 * pci_configure_ari - enable or disable ARI forwarding 2504 * @dev: the PCI device 2505 * 2506 * If @dev and its upstream bridge both support ARI, enable ARI in the 2507 * bridge. Otherwise, disable ARI in the bridge. 2508 */ 2509 void pci_configure_ari(struct pci_dev *dev) 2510 { 2511 u32 cap; 2512 struct pci_dev *bridge; 2513 2514 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn) 2515 return; 2516 2517 bridge = dev->bus->self; 2518 if (!bridge) 2519 return; 2520 2521 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap); 2522 if (!(cap & PCI_EXP_DEVCAP2_ARI)) 2523 return; 2524 2525 if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) { 2526 pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2, 2527 PCI_EXP_DEVCTL2_ARI); 2528 bridge->ari_enabled = 1; 2529 } else { 2530 pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2, 2531 PCI_EXP_DEVCTL2_ARI); 2532 bridge->ari_enabled = 0; 2533 } 2534 } 2535 2536 static int pci_acs_enable; 2537 2538 /** 2539 * pci_request_acs - ask for ACS to be enabled if supported 2540 */ 2541 void pci_request_acs(void) 2542 { 2543 pci_acs_enable = 1; 2544 } 2545 2546 /** 2547 * pci_std_enable_acs - enable ACS on devices using standard ACS capabilites 2548 * @dev: the PCI device 2549 */ 2550 static int pci_std_enable_acs(struct pci_dev *dev) 2551 { 2552 int pos; 2553 u16 cap; 2554 u16 ctrl; 2555 2556 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS); 2557 if (!pos) 2558 return -ENODEV; 2559 2560 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap); 2561 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl); 2562 2563 /* Source Validation */ 2564 ctrl |= (cap & PCI_ACS_SV); 2565 2566 /* P2P Request Redirect */ 2567 ctrl |= (cap & PCI_ACS_RR); 2568 2569 /* P2P Completion Redirect */ 2570 ctrl |= (cap & PCI_ACS_CR); 2571 2572 /* Upstream Forwarding */ 2573 ctrl |= (cap & PCI_ACS_UF); 2574 2575 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl); 2576 2577 return 0; 2578 } 2579 2580 /** 2581 * pci_enable_acs - enable ACS if hardware support it 2582 * @dev: the PCI device 2583 */ 2584 void pci_enable_acs(struct pci_dev *dev) 2585 { 2586 if (!pci_acs_enable) 2587 return; 2588 2589 if (!pci_std_enable_acs(dev)) 2590 return; 2591 2592 pci_dev_specific_enable_acs(dev); 2593 } 2594 2595 static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags) 2596 { 2597 int pos; 2598 u16 cap, ctrl; 2599 2600 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ACS); 2601 if (!pos) 2602 return false; 2603 2604 /* 2605 * Except for egress control, capabilities are either required 2606 * or only required if controllable. Features missing from the 2607 * capability field can therefore be assumed as hard-wired enabled. 2608 */ 2609 pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap); 2610 acs_flags &= (cap | PCI_ACS_EC); 2611 2612 pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl); 2613 return (ctrl & acs_flags) == acs_flags; 2614 } 2615 2616 /** 2617 * pci_acs_enabled - test ACS against required flags for a given device 2618 * @pdev: device to test 2619 * @acs_flags: required PCI ACS flags 2620 * 2621 * Return true if the device supports the provided flags. Automatically 2622 * filters out flags that are not implemented on multifunction devices. 2623 * 2624 * Note that this interface checks the effective ACS capabilities of the 2625 * device rather than the actual capabilities. For instance, most single 2626 * function endpoints are not required to support ACS because they have no 2627 * opportunity for peer-to-peer access. We therefore return 'true' 2628 * regardless of whether the device exposes an ACS capability. This makes 2629 * it much easier for callers of this function to ignore the actual type 2630 * or topology of the device when testing ACS support. 2631 */ 2632 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags) 2633 { 2634 int ret; 2635 2636 ret = pci_dev_specific_acs_enabled(pdev, acs_flags); 2637 if (ret >= 0) 2638 return ret > 0; 2639 2640 /* 2641 * Conventional PCI and PCI-X devices never support ACS, either 2642 * effectively or actually. The shared bus topology implies that 2643 * any device on the bus can receive or snoop DMA. 2644 */ 2645 if (!pci_is_pcie(pdev)) 2646 return false; 2647 2648 switch (pci_pcie_type(pdev)) { 2649 /* 2650 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec, 2651 * but since their primary interface is PCI/X, we conservatively 2652 * handle them as we would a non-PCIe device. 2653 */ 2654 case PCI_EXP_TYPE_PCIE_BRIDGE: 2655 /* 2656 * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never 2657 * applicable... must never implement an ACS Extended Capability...". 2658 * This seems arbitrary, but we take a conservative interpretation 2659 * of this statement. 2660 */ 2661 case PCI_EXP_TYPE_PCI_BRIDGE: 2662 case PCI_EXP_TYPE_RC_EC: 2663 return false; 2664 /* 2665 * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should 2666 * implement ACS in order to indicate their peer-to-peer capabilities, 2667 * regardless of whether they are single- or multi-function devices. 2668 */ 2669 case PCI_EXP_TYPE_DOWNSTREAM: 2670 case PCI_EXP_TYPE_ROOT_PORT: 2671 return pci_acs_flags_enabled(pdev, acs_flags); 2672 /* 2673 * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be 2674 * implemented by the remaining PCIe types to indicate peer-to-peer 2675 * capabilities, but only when they are part of a multifunction 2676 * device. The footnote for section 6.12 indicates the specific 2677 * PCIe types included here. 2678 */ 2679 case PCI_EXP_TYPE_ENDPOINT: 2680 case PCI_EXP_TYPE_UPSTREAM: 2681 case PCI_EXP_TYPE_LEG_END: 2682 case PCI_EXP_TYPE_RC_END: 2683 if (!pdev->multifunction) 2684 break; 2685 2686 return pci_acs_flags_enabled(pdev, acs_flags); 2687 } 2688 2689 /* 2690 * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable 2691 * to single function devices with the exception of downstream ports. 2692 */ 2693 return true; 2694 } 2695 2696 /** 2697 * pci_acs_path_enable - test ACS flags from start to end in a hierarchy 2698 * @start: starting downstream device 2699 * @end: ending upstream device or NULL to search to the root bus 2700 * @acs_flags: required flags 2701 * 2702 * Walk up a device tree from start to end testing PCI ACS support. If 2703 * any step along the way does not support the required flags, return false. 2704 */ 2705 bool pci_acs_path_enabled(struct pci_dev *start, 2706 struct pci_dev *end, u16 acs_flags) 2707 { 2708 struct pci_dev *pdev, *parent = start; 2709 2710 do { 2711 pdev = parent; 2712 2713 if (!pci_acs_enabled(pdev, acs_flags)) 2714 return false; 2715 2716 if (pci_is_root_bus(pdev->bus)) 2717 return (end == NULL); 2718 2719 parent = pdev->bus->self; 2720 } while (pdev != end); 2721 2722 return true; 2723 } 2724 2725 /** 2726 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge 2727 * @dev: the PCI device 2728 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD) 2729 * 2730 * Perform INTx swizzling for a device behind one level of bridge. This is 2731 * required by section 9.1 of the PCI-to-PCI bridge specification for devices 2732 * behind bridges on add-in cards. For devices with ARI enabled, the slot 2733 * number is always 0 (see the Implementation Note in section 2.2.8.1 of 2734 * the PCI Express Base Specification, Revision 2.1) 2735 */ 2736 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin) 2737 { 2738 int slot; 2739 2740 if (pci_ari_enabled(dev->bus)) 2741 slot = 0; 2742 else 2743 slot = PCI_SLOT(dev->devfn); 2744 2745 return (((pin - 1) + slot) % 4) + 1; 2746 } 2747 2748 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge) 2749 { 2750 u8 pin; 2751 2752 pin = dev->pin; 2753 if (!pin) 2754 return -1; 2755 2756 while (!pci_is_root_bus(dev->bus)) { 2757 pin = pci_swizzle_interrupt_pin(dev, pin); 2758 dev = dev->bus->self; 2759 } 2760 *bridge = dev; 2761 return pin; 2762 } 2763 2764 /** 2765 * pci_common_swizzle - swizzle INTx all the way to root bridge 2766 * @dev: the PCI device 2767 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD) 2768 * 2769 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI 2770 * bridges all the way up to a PCI root bus. 2771 */ 2772 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp) 2773 { 2774 u8 pin = *pinp; 2775 2776 while (!pci_is_root_bus(dev->bus)) { 2777 pin = pci_swizzle_interrupt_pin(dev, pin); 2778 dev = dev->bus->self; 2779 } 2780 *pinp = pin; 2781 return PCI_SLOT(dev->devfn); 2782 } 2783 EXPORT_SYMBOL_GPL(pci_common_swizzle); 2784 2785 /** 2786 * pci_release_region - Release a PCI bar 2787 * @pdev: PCI device whose resources were previously reserved by pci_request_region 2788 * @bar: BAR to release 2789 * 2790 * Releases the PCI I/O and memory resources previously reserved by a 2791 * successful call to pci_request_region. Call this function only 2792 * after all use of the PCI regions has ceased. 2793 */ 2794 void pci_release_region(struct pci_dev *pdev, int bar) 2795 { 2796 struct pci_devres *dr; 2797 2798 if (pci_resource_len(pdev, bar) == 0) 2799 return; 2800 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) 2801 release_region(pci_resource_start(pdev, bar), 2802 pci_resource_len(pdev, bar)); 2803 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) 2804 release_mem_region(pci_resource_start(pdev, bar), 2805 pci_resource_len(pdev, bar)); 2806 2807 dr = find_pci_dr(pdev); 2808 if (dr) 2809 dr->region_mask &= ~(1 << bar); 2810 } 2811 EXPORT_SYMBOL(pci_release_region); 2812 2813 /** 2814 * __pci_request_region - Reserved PCI I/O and memory resource 2815 * @pdev: PCI device whose resources are to be reserved 2816 * @bar: BAR to be reserved 2817 * @res_name: Name to be associated with resource. 2818 * @exclusive: whether the region access is exclusive or not 2819 * 2820 * Mark the PCI region associated with PCI device @pdev BR @bar as 2821 * being reserved by owner @res_name. Do not access any 2822 * address inside the PCI regions unless this call returns 2823 * successfully. 2824 * 2825 * If @exclusive is set, then the region is marked so that userspace 2826 * is explicitly not allowed to map the resource via /dev/mem or 2827 * sysfs MMIO access. 2828 * 2829 * Returns 0 on success, or %EBUSY on error. A warning 2830 * message is also printed on failure. 2831 */ 2832 static int __pci_request_region(struct pci_dev *pdev, int bar, 2833 const char *res_name, int exclusive) 2834 { 2835 struct pci_devres *dr; 2836 2837 if (pci_resource_len(pdev, bar) == 0) 2838 return 0; 2839 2840 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) { 2841 if (!request_region(pci_resource_start(pdev, bar), 2842 pci_resource_len(pdev, bar), res_name)) 2843 goto err_out; 2844 } else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) { 2845 if (!__request_mem_region(pci_resource_start(pdev, bar), 2846 pci_resource_len(pdev, bar), res_name, 2847 exclusive)) 2848 goto err_out; 2849 } 2850 2851 dr = find_pci_dr(pdev); 2852 if (dr) 2853 dr->region_mask |= 1 << bar; 2854 2855 return 0; 2856 2857 err_out: 2858 dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar, 2859 &pdev->resource[bar]); 2860 return -EBUSY; 2861 } 2862 2863 /** 2864 * pci_request_region - Reserve PCI I/O and memory resource 2865 * @pdev: PCI device whose resources are to be reserved 2866 * @bar: BAR to be reserved 2867 * @res_name: Name to be associated with resource 2868 * 2869 * Mark the PCI region associated with PCI device @pdev BAR @bar as 2870 * being reserved by owner @res_name. Do not access any 2871 * address inside the PCI regions unless this call returns 2872 * successfully. 2873 * 2874 * Returns 0 on success, or %EBUSY on error. A warning 2875 * message is also printed on failure. 2876 */ 2877 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) 2878 { 2879 return __pci_request_region(pdev, bar, res_name, 0); 2880 } 2881 EXPORT_SYMBOL(pci_request_region); 2882 2883 /** 2884 * pci_request_region_exclusive - Reserved PCI I/O and memory resource 2885 * @pdev: PCI device whose resources are to be reserved 2886 * @bar: BAR to be reserved 2887 * @res_name: Name to be associated with resource. 2888 * 2889 * Mark the PCI region associated with PCI device @pdev BR @bar as 2890 * being reserved by owner @res_name. Do not access any 2891 * address inside the PCI regions unless this call returns 2892 * successfully. 2893 * 2894 * Returns 0 on success, or %EBUSY on error. A warning 2895 * message is also printed on failure. 2896 * 2897 * The key difference that _exclusive makes it that userspace is 2898 * explicitly not allowed to map the resource via /dev/mem or 2899 * sysfs. 2900 */ 2901 int pci_request_region_exclusive(struct pci_dev *pdev, int bar, 2902 const char *res_name) 2903 { 2904 return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE); 2905 } 2906 EXPORT_SYMBOL(pci_request_region_exclusive); 2907 2908 /** 2909 * pci_release_selected_regions - Release selected PCI I/O and memory resources 2910 * @pdev: PCI device whose resources were previously reserved 2911 * @bars: Bitmask of BARs to be released 2912 * 2913 * Release selected PCI I/O and memory resources previously reserved. 2914 * Call this function only after all use of the PCI regions has ceased. 2915 */ 2916 void pci_release_selected_regions(struct pci_dev *pdev, int bars) 2917 { 2918 int i; 2919 2920 for (i = 0; i < 6; i++) 2921 if (bars & (1 << i)) 2922 pci_release_region(pdev, i); 2923 } 2924 EXPORT_SYMBOL(pci_release_selected_regions); 2925 2926 static int __pci_request_selected_regions(struct pci_dev *pdev, int bars, 2927 const char *res_name, int excl) 2928 { 2929 int i; 2930 2931 for (i = 0; i < 6; i++) 2932 if (bars & (1 << i)) 2933 if (__pci_request_region(pdev, i, res_name, excl)) 2934 goto err_out; 2935 return 0; 2936 2937 err_out: 2938 while (--i >= 0) 2939 if (bars & (1 << i)) 2940 pci_release_region(pdev, i); 2941 2942 return -EBUSY; 2943 } 2944 2945 2946 /** 2947 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources 2948 * @pdev: PCI device whose resources are to be reserved 2949 * @bars: Bitmask of BARs to be requested 2950 * @res_name: Name to be associated with resource 2951 */ 2952 int pci_request_selected_regions(struct pci_dev *pdev, int bars, 2953 const char *res_name) 2954 { 2955 return __pci_request_selected_regions(pdev, bars, res_name, 0); 2956 } 2957 EXPORT_SYMBOL(pci_request_selected_regions); 2958 2959 int pci_request_selected_regions_exclusive(struct pci_dev *pdev, int bars, 2960 const char *res_name) 2961 { 2962 return __pci_request_selected_regions(pdev, bars, res_name, 2963 IORESOURCE_EXCLUSIVE); 2964 } 2965 EXPORT_SYMBOL(pci_request_selected_regions_exclusive); 2966 2967 /** 2968 * pci_release_regions - Release reserved PCI I/O and memory resources 2969 * @pdev: PCI device whose resources were previously reserved by pci_request_regions 2970 * 2971 * Releases all PCI I/O and memory resources previously reserved by a 2972 * successful call to pci_request_regions. Call this function only 2973 * after all use of the PCI regions has ceased. 2974 */ 2975 2976 void pci_release_regions(struct pci_dev *pdev) 2977 { 2978 pci_release_selected_regions(pdev, (1 << 6) - 1); 2979 } 2980 EXPORT_SYMBOL(pci_release_regions); 2981 2982 /** 2983 * pci_request_regions - Reserved PCI I/O and memory resources 2984 * @pdev: PCI device whose resources are to be reserved 2985 * @res_name: Name to be associated with resource. 2986 * 2987 * Mark all PCI regions associated with PCI device @pdev as 2988 * being reserved by owner @res_name. Do not access any 2989 * address inside the PCI regions unless this call returns 2990 * successfully. 2991 * 2992 * Returns 0 on success, or %EBUSY on error. A warning 2993 * message is also printed on failure. 2994 */ 2995 int pci_request_regions(struct pci_dev *pdev, const char *res_name) 2996 { 2997 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name); 2998 } 2999 EXPORT_SYMBOL(pci_request_regions); 3000 3001 /** 3002 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources 3003 * @pdev: PCI device whose resources are to be reserved 3004 * @res_name: Name to be associated with resource. 3005 * 3006 * Mark all PCI regions associated with PCI device @pdev as 3007 * being reserved by owner @res_name. Do not access any 3008 * address inside the PCI regions unless this call returns 3009 * successfully. 3010 * 3011 * pci_request_regions_exclusive() will mark the region so that 3012 * /dev/mem and the sysfs MMIO access will not be allowed. 3013 * 3014 * Returns 0 on success, or %EBUSY on error. A warning 3015 * message is also printed on failure. 3016 */ 3017 int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name) 3018 { 3019 return pci_request_selected_regions_exclusive(pdev, 3020 ((1 << 6) - 1), res_name); 3021 } 3022 EXPORT_SYMBOL(pci_request_regions_exclusive); 3023 3024 /** 3025 * pci_remap_iospace - Remap the memory mapped I/O space 3026 * @res: Resource describing the I/O space 3027 * @phys_addr: physical address of range to be mapped 3028 * 3029 * Remap the memory mapped I/O space described by the @res 3030 * and the CPU physical address @phys_addr into virtual address space. 3031 * Only architectures that have memory mapped IO functions defined 3032 * (and the PCI_IOBASE value defined) should call this function. 3033 */ 3034 int __weak pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr) 3035 { 3036 #if defined(PCI_IOBASE) && defined(CONFIG_MMU) 3037 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start; 3038 3039 if (!(res->flags & IORESOURCE_IO)) 3040 return -EINVAL; 3041 3042 if (res->end > IO_SPACE_LIMIT) 3043 return -EINVAL; 3044 3045 return ioremap_page_range(vaddr, vaddr + resource_size(res), phys_addr, 3046 pgprot_device(PAGE_KERNEL)); 3047 #else 3048 /* this architecture does not have memory mapped I/O space, 3049 so this function should never be called */ 3050 WARN_ONCE(1, "This architecture does not support memory mapped I/O\n"); 3051 return -ENODEV; 3052 #endif 3053 } 3054 3055 static void __pci_set_master(struct pci_dev *dev, bool enable) 3056 { 3057 u16 old_cmd, cmd; 3058 3059 pci_read_config_word(dev, PCI_COMMAND, &old_cmd); 3060 if (enable) 3061 cmd = old_cmd | PCI_COMMAND_MASTER; 3062 else 3063 cmd = old_cmd & ~PCI_COMMAND_MASTER; 3064 if (cmd != old_cmd) { 3065 dev_dbg(&dev->dev, "%s bus mastering\n", 3066 enable ? "enabling" : "disabling"); 3067 pci_write_config_word(dev, PCI_COMMAND, cmd); 3068 } 3069 dev->is_busmaster = enable; 3070 } 3071 3072 /** 3073 * pcibios_setup - process "pci=" kernel boot arguments 3074 * @str: string used to pass in "pci=" kernel boot arguments 3075 * 3076 * Process kernel boot arguments. This is the default implementation. 3077 * Architecture specific implementations can override this as necessary. 3078 */ 3079 char * __weak __init pcibios_setup(char *str) 3080 { 3081 return str; 3082 } 3083 3084 /** 3085 * pcibios_set_master - enable PCI bus-mastering for device dev 3086 * @dev: the PCI device to enable 3087 * 3088 * Enables PCI bus-mastering for the device. This is the default 3089 * implementation. Architecture specific implementations can override 3090 * this if necessary. 3091 */ 3092 void __weak pcibios_set_master(struct pci_dev *dev) 3093 { 3094 u8 lat; 3095 3096 /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */ 3097 if (pci_is_pcie(dev)) 3098 return; 3099 3100 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat); 3101 if (lat < 16) 3102 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency; 3103 else if (lat > pcibios_max_latency) 3104 lat = pcibios_max_latency; 3105 else 3106 return; 3107 3108 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat); 3109 } 3110 3111 /** 3112 * pci_set_master - enables bus-mastering for device dev 3113 * @dev: the PCI device to enable 3114 * 3115 * Enables bus-mastering on the device and calls pcibios_set_master() 3116 * to do the needed arch specific settings. 3117 */ 3118 void pci_set_master(struct pci_dev *dev) 3119 { 3120 __pci_set_master(dev, true); 3121 pcibios_set_master(dev); 3122 } 3123 EXPORT_SYMBOL(pci_set_master); 3124 3125 /** 3126 * pci_clear_master - disables bus-mastering for device dev 3127 * @dev: the PCI device to disable 3128 */ 3129 void pci_clear_master(struct pci_dev *dev) 3130 { 3131 __pci_set_master(dev, false); 3132 } 3133 EXPORT_SYMBOL(pci_clear_master); 3134 3135 /** 3136 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed 3137 * @dev: the PCI device for which MWI is to be enabled 3138 * 3139 * Helper function for pci_set_mwi. 3140 * Originally copied from drivers/net/acenic.c. 3141 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. 3142 * 3143 * RETURNS: An appropriate -ERRNO error value on error, or zero for success. 3144 */ 3145 int pci_set_cacheline_size(struct pci_dev *dev) 3146 { 3147 u8 cacheline_size; 3148 3149 if (!pci_cache_line_size) 3150 return -EINVAL; 3151 3152 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be 3153 equal to or multiple of the right value. */ 3154 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); 3155 if (cacheline_size >= pci_cache_line_size && 3156 (cacheline_size % pci_cache_line_size) == 0) 3157 return 0; 3158 3159 /* Write the correct value. */ 3160 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size); 3161 /* Read it back. */ 3162 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); 3163 if (cacheline_size == pci_cache_line_size) 3164 return 0; 3165 3166 dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not supported\n", 3167 pci_cache_line_size << 2); 3168 3169 return -EINVAL; 3170 } 3171 EXPORT_SYMBOL_GPL(pci_set_cacheline_size); 3172 3173 /** 3174 * pci_set_mwi - enables memory-write-invalidate PCI transaction 3175 * @dev: the PCI device for which MWI is enabled 3176 * 3177 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. 3178 * 3179 * RETURNS: An appropriate -ERRNO error value on error, or zero for success. 3180 */ 3181 int pci_set_mwi(struct pci_dev *dev) 3182 { 3183 #ifdef PCI_DISABLE_MWI 3184 return 0; 3185 #else 3186 int rc; 3187 u16 cmd; 3188 3189 rc = pci_set_cacheline_size(dev); 3190 if (rc) 3191 return rc; 3192 3193 pci_read_config_word(dev, PCI_COMMAND, &cmd); 3194 if (!(cmd & PCI_COMMAND_INVALIDATE)) { 3195 dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n"); 3196 cmd |= PCI_COMMAND_INVALIDATE; 3197 pci_write_config_word(dev, PCI_COMMAND, cmd); 3198 } 3199 return 0; 3200 #endif 3201 } 3202 EXPORT_SYMBOL(pci_set_mwi); 3203 3204 /** 3205 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction 3206 * @dev: the PCI device for which MWI is enabled 3207 * 3208 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. 3209 * Callers are not required to check the return value. 3210 * 3211 * RETURNS: An appropriate -ERRNO error value on error, or zero for success. 3212 */ 3213 int pci_try_set_mwi(struct pci_dev *dev) 3214 { 3215 #ifdef PCI_DISABLE_MWI 3216 return 0; 3217 #else 3218 return pci_set_mwi(dev); 3219 #endif 3220 } 3221 EXPORT_SYMBOL(pci_try_set_mwi); 3222 3223 /** 3224 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev 3225 * @dev: the PCI device to disable 3226 * 3227 * Disables PCI Memory-Write-Invalidate transaction on the device 3228 */ 3229 void pci_clear_mwi(struct pci_dev *dev) 3230 { 3231 #ifndef PCI_DISABLE_MWI 3232 u16 cmd; 3233 3234 pci_read_config_word(dev, PCI_COMMAND, &cmd); 3235 if (cmd & PCI_COMMAND_INVALIDATE) { 3236 cmd &= ~PCI_COMMAND_INVALIDATE; 3237 pci_write_config_word(dev, PCI_COMMAND, cmd); 3238 } 3239 #endif 3240 } 3241 EXPORT_SYMBOL(pci_clear_mwi); 3242 3243 /** 3244 * pci_intx - enables/disables PCI INTx for device dev 3245 * @pdev: the PCI device to operate on 3246 * @enable: boolean: whether to enable or disable PCI INTx 3247 * 3248 * Enables/disables PCI INTx for device dev 3249 */ 3250 void pci_intx(struct pci_dev *pdev, int enable) 3251 { 3252 u16 pci_command, new; 3253 3254 pci_read_config_word(pdev, PCI_COMMAND, &pci_command); 3255 3256 if (enable) 3257 new = pci_command & ~PCI_COMMAND_INTX_DISABLE; 3258 else 3259 new = pci_command | PCI_COMMAND_INTX_DISABLE; 3260 3261 if (new != pci_command) { 3262 struct pci_devres *dr; 3263 3264 pci_write_config_word(pdev, PCI_COMMAND, new); 3265 3266 dr = find_pci_dr(pdev); 3267 if (dr && !dr->restore_intx) { 3268 dr->restore_intx = 1; 3269 dr->orig_intx = !enable; 3270 } 3271 } 3272 } 3273 EXPORT_SYMBOL_GPL(pci_intx); 3274 3275 /** 3276 * pci_intx_mask_supported - probe for INTx masking support 3277 * @dev: the PCI device to operate on 3278 * 3279 * Check if the device dev support INTx masking via the config space 3280 * command word. 3281 */ 3282 bool pci_intx_mask_supported(struct pci_dev *dev) 3283 { 3284 bool mask_supported = false; 3285 u16 orig, new; 3286 3287 if (dev->broken_intx_masking) 3288 return false; 3289 3290 pci_cfg_access_lock(dev); 3291 3292 pci_read_config_word(dev, PCI_COMMAND, &orig); 3293 pci_write_config_word(dev, PCI_COMMAND, 3294 orig ^ PCI_COMMAND_INTX_DISABLE); 3295 pci_read_config_word(dev, PCI_COMMAND, &new); 3296 3297 /* 3298 * There's no way to protect against hardware bugs or detect them 3299 * reliably, but as long as we know what the value should be, let's 3300 * go ahead and check it. 3301 */ 3302 if ((new ^ orig) & ~PCI_COMMAND_INTX_DISABLE) { 3303 dev_err(&dev->dev, "Command register changed from 0x%x to 0x%x: driver or hardware bug?\n", 3304 orig, new); 3305 } else if ((new ^ orig) & PCI_COMMAND_INTX_DISABLE) { 3306 mask_supported = true; 3307 pci_write_config_word(dev, PCI_COMMAND, orig); 3308 } 3309 3310 pci_cfg_access_unlock(dev); 3311 return mask_supported; 3312 } 3313 EXPORT_SYMBOL_GPL(pci_intx_mask_supported); 3314 3315 static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask) 3316 { 3317 struct pci_bus *bus = dev->bus; 3318 bool mask_updated = true; 3319 u32 cmd_status_dword; 3320 u16 origcmd, newcmd; 3321 unsigned long flags; 3322 bool irq_pending; 3323 3324 /* 3325 * We do a single dword read to retrieve both command and status. 3326 * Document assumptions that make this possible. 3327 */ 3328 BUILD_BUG_ON(PCI_COMMAND % 4); 3329 BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS); 3330 3331 raw_spin_lock_irqsave(&pci_lock, flags); 3332 3333 bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword); 3334 3335 irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT; 3336 3337 /* 3338 * Check interrupt status register to see whether our device 3339 * triggered the interrupt (when masking) or the next IRQ is 3340 * already pending (when unmasking). 3341 */ 3342 if (mask != irq_pending) { 3343 mask_updated = false; 3344 goto done; 3345 } 3346 3347 origcmd = cmd_status_dword; 3348 newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE; 3349 if (mask) 3350 newcmd |= PCI_COMMAND_INTX_DISABLE; 3351 if (newcmd != origcmd) 3352 bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd); 3353 3354 done: 3355 raw_spin_unlock_irqrestore(&pci_lock, flags); 3356 3357 return mask_updated; 3358 } 3359 3360 /** 3361 * pci_check_and_mask_intx - mask INTx on pending interrupt 3362 * @dev: the PCI device to operate on 3363 * 3364 * Check if the device dev has its INTx line asserted, mask it and 3365 * return true in that case. False is returned if not interrupt was 3366 * pending. 3367 */ 3368 bool pci_check_and_mask_intx(struct pci_dev *dev) 3369 { 3370 return pci_check_and_set_intx_mask(dev, true); 3371 } 3372 EXPORT_SYMBOL_GPL(pci_check_and_mask_intx); 3373 3374 /** 3375 * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending 3376 * @dev: the PCI device to operate on 3377 * 3378 * Check if the device dev has its INTx line asserted, unmask it if not 3379 * and return true. False is returned and the mask remains active if 3380 * there was still an interrupt pending. 3381 */ 3382 bool pci_check_and_unmask_intx(struct pci_dev *dev) 3383 { 3384 return pci_check_and_set_intx_mask(dev, false); 3385 } 3386 EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx); 3387 3388 /** 3389 * pci_wait_for_pending_transaction - waits for pending transaction 3390 * @dev: the PCI device to operate on 3391 * 3392 * Return 0 if transaction is pending 1 otherwise. 3393 */ 3394 int pci_wait_for_pending_transaction(struct pci_dev *dev) 3395 { 3396 if (!pci_is_pcie(dev)) 3397 return 1; 3398 3399 return pci_wait_for_pending(dev, pci_pcie_cap(dev) + PCI_EXP_DEVSTA, 3400 PCI_EXP_DEVSTA_TRPND); 3401 } 3402 EXPORT_SYMBOL(pci_wait_for_pending_transaction); 3403 3404 /* 3405 * We should only need to wait 100ms after FLR, but some devices take longer. 3406 * Wait for up to 1000ms for config space to return something other than -1. 3407 * Intel IGD requires this when an LCD panel is attached. We read the 2nd 3408 * dword because VFs don't implement the 1st dword. 3409 */ 3410 static void pci_flr_wait(struct pci_dev *dev) 3411 { 3412 int i = 0; 3413 u32 id; 3414 3415 do { 3416 msleep(100); 3417 pci_read_config_dword(dev, PCI_COMMAND, &id); 3418 } while (i++ < 10 && id == ~0); 3419 3420 if (id == ~0) 3421 dev_warn(&dev->dev, "Failed to return from FLR\n"); 3422 else if (i > 1) 3423 dev_info(&dev->dev, "Required additional %dms to return from FLR\n", 3424 (i - 1) * 100); 3425 } 3426 3427 static int pcie_flr(struct pci_dev *dev, int probe) 3428 { 3429 u32 cap; 3430 3431 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap); 3432 if (!(cap & PCI_EXP_DEVCAP_FLR)) 3433 return -ENOTTY; 3434 3435 if (probe) 3436 return 0; 3437 3438 if (!pci_wait_for_pending_transaction(dev)) 3439 dev_err(&dev->dev, "timed out waiting for pending transaction; performing function level reset anyway\n"); 3440 3441 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR); 3442 pci_flr_wait(dev); 3443 return 0; 3444 } 3445 3446 static int pci_af_flr(struct pci_dev *dev, int probe) 3447 { 3448 int pos; 3449 u8 cap; 3450 3451 pos = pci_find_capability(dev, PCI_CAP_ID_AF); 3452 if (!pos) 3453 return -ENOTTY; 3454 3455 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap); 3456 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR)) 3457 return -ENOTTY; 3458 3459 if (probe) 3460 return 0; 3461 3462 /* 3463 * Wait for Transaction Pending bit to clear. A word-aligned test 3464 * is used, so we use the conrol offset rather than status and shift 3465 * the test bit to match. 3466 */ 3467 if (!pci_wait_for_pending(dev, pos + PCI_AF_CTRL, 3468 PCI_AF_STATUS_TP << 8)) 3469 dev_err(&dev->dev, "timed out waiting for pending transaction; performing AF function level reset anyway\n"); 3470 3471 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR); 3472 pci_flr_wait(dev); 3473 return 0; 3474 } 3475 3476 /** 3477 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0. 3478 * @dev: Device to reset. 3479 * @probe: If set, only check if the device can be reset this way. 3480 * 3481 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is 3482 * unset, it will be reinitialized internally when going from PCI_D3hot to 3483 * PCI_D0. If that's the case and the device is not in a low-power state 3484 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset. 3485 * 3486 * NOTE: This causes the caller to sleep for twice the device power transition 3487 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms 3488 * by default (i.e. unless the @dev's d3_delay field has a different value). 3489 * Moreover, only devices in D0 can be reset by this function. 3490 */ 3491 static int pci_pm_reset(struct pci_dev *dev, int probe) 3492 { 3493 u16 csr; 3494 3495 if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET) 3496 return -ENOTTY; 3497 3498 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr); 3499 if (csr & PCI_PM_CTRL_NO_SOFT_RESET) 3500 return -ENOTTY; 3501 3502 if (probe) 3503 return 0; 3504 3505 if (dev->current_state != PCI_D0) 3506 return -EINVAL; 3507 3508 csr &= ~PCI_PM_CTRL_STATE_MASK; 3509 csr |= PCI_D3hot; 3510 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); 3511 pci_dev_d3_sleep(dev); 3512 3513 csr &= ~PCI_PM_CTRL_STATE_MASK; 3514 csr |= PCI_D0; 3515 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); 3516 pci_dev_d3_sleep(dev); 3517 3518 return 0; 3519 } 3520 3521 void pci_reset_secondary_bus(struct pci_dev *dev) 3522 { 3523 u16 ctrl; 3524 3525 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl); 3526 ctrl |= PCI_BRIDGE_CTL_BUS_RESET; 3527 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl); 3528 /* 3529 * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double 3530 * this to 2ms to ensure that we meet the minimum requirement. 3531 */ 3532 msleep(2); 3533 3534 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET; 3535 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl); 3536 3537 /* 3538 * Trhfa for conventional PCI is 2^25 clock cycles. 3539 * Assuming a minimum 33MHz clock this results in a 1s 3540 * delay before we can consider subordinate devices to 3541 * be re-initialized. PCIe has some ways to shorten this, 3542 * but we don't make use of them yet. 3543 */ 3544 ssleep(1); 3545 } 3546 3547 void __weak pcibios_reset_secondary_bus(struct pci_dev *dev) 3548 { 3549 pci_reset_secondary_bus(dev); 3550 } 3551 3552 /** 3553 * pci_reset_bridge_secondary_bus - Reset the secondary bus on a PCI bridge. 3554 * @dev: Bridge device 3555 * 3556 * Use the bridge control register to assert reset on the secondary bus. 3557 * Devices on the secondary bus are left in power-on state. 3558 */ 3559 void pci_reset_bridge_secondary_bus(struct pci_dev *dev) 3560 { 3561 pcibios_reset_secondary_bus(dev); 3562 } 3563 EXPORT_SYMBOL_GPL(pci_reset_bridge_secondary_bus); 3564 3565 static int pci_parent_bus_reset(struct pci_dev *dev, int probe) 3566 { 3567 struct pci_dev *pdev; 3568 3569 if (pci_is_root_bus(dev->bus) || dev->subordinate || 3570 !dev->bus->self || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET) 3571 return -ENOTTY; 3572 3573 list_for_each_entry(pdev, &dev->bus->devices, bus_list) 3574 if (pdev != dev) 3575 return -ENOTTY; 3576 3577 if (probe) 3578 return 0; 3579 3580 pci_reset_bridge_secondary_bus(dev->bus->self); 3581 3582 return 0; 3583 } 3584 3585 static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, int probe) 3586 { 3587 int rc = -ENOTTY; 3588 3589 if (!hotplug || !try_module_get(hotplug->ops->owner)) 3590 return rc; 3591 3592 if (hotplug->ops->reset_slot) 3593 rc = hotplug->ops->reset_slot(hotplug, probe); 3594 3595 module_put(hotplug->ops->owner); 3596 3597 return rc; 3598 } 3599 3600 static int pci_dev_reset_slot_function(struct pci_dev *dev, int probe) 3601 { 3602 struct pci_dev *pdev; 3603 3604 if (dev->subordinate || !dev->slot || 3605 dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET) 3606 return -ENOTTY; 3607 3608 list_for_each_entry(pdev, &dev->bus->devices, bus_list) 3609 if (pdev != dev && pdev->slot == dev->slot) 3610 return -ENOTTY; 3611 3612 return pci_reset_hotplug_slot(dev->slot->hotplug, probe); 3613 } 3614 3615 static int __pci_dev_reset(struct pci_dev *dev, int probe) 3616 { 3617 int rc; 3618 3619 might_sleep(); 3620 3621 rc = pci_dev_specific_reset(dev, probe); 3622 if (rc != -ENOTTY) 3623 goto done; 3624 3625 rc = pcie_flr(dev, probe); 3626 if (rc != -ENOTTY) 3627 goto done; 3628 3629 rc = pci_af_flr(dev, probe); 3630 if (rc != -ENOTTY) 3631 goto done; 3632 3633 rc = pci_pm_reset(dev, probe); 3634 if (rc != -ENOTTY) 3635 goto done; 3636 3637 rc = pci_dev_reset_slot_function(dev, probe); 3638 if (rc != -ENOTTY) 3639 goto done; 3640 3641 rc = pci_parent_bus_reset(dev, probe); 3642 done: 3643 return rc; 3644 } 3645 3646 static void pci_dev_lock(struct pci_dev *dev) 3647 { 3648 pci_cfg_access_lock(dev); 3649 /* block PM suspend, driver probe, etc. */ 3650 device_lock(&dev->dev); 3651 } 3652 3653 /* Return 1 on successful lock, 0 on contention */ 3654 static int pci_dev_trylock(struct pci_dev *dev) 3655 { 3656 if (pci_cfg_access_trylock(dev)) { 3657 if (device_trylock(&dev->dev)) 3658 return 1; 3659 pci_cfg_access_unlock(dev); 3660 } 3661 3662 return 0; 3663 } 3664 3665 static void pci_dev_unlock(struct pci_dev *dev) 3666 { 3667 device_unlock(&dev->dev); 3668 pci_cfg_access_unlock(dev); 3669 } 3670 3671 /** 3672 * pci_reset_notify - notify device driver of reset 3673 * @dev: device to be notified of reset 3674 * @prepare: 'true' if device is about to be reset; 'false' if reset attempt 3675 * completed 3676 * 3677 * Must be called prior to device access being disabled and after device 3678 * access is restored. 3679 */ 3680 static void pci_reset_notify(struct pci_dev *dev, bool prepare) 3681 { 3682 const struct pci_error_handlers *err_handler = 3683 dev->driver ? dev->driver->err_handler : NULL; 3684 if (err_handler && err_handler->reset_notify) 3685 err_handler->reset_notify(dev, prepare); 3686 } 3687 3688 static void pci_dev_save_and_disable(struct pci_dev *dev) 3689 { 3690 pci_reset_notify(dev, true); 3691 3692 /* 3693 * Wake-up device prior to save. PM registers default to D0 after 3694 * reset and a simple register restore doesn't reliably return 3695 * to a non-D0 state anyway. 3696 */ 3697 pci_set_power_state(dev, PCI_D0); 3698 3699 pci_save_state(dev); 3700 /* 3701 * Disable the device by clearing the Command register, except for 3702 * INTx-disable which is set. This not only disables MMIO and I/O port 3703 * BARs, but also prevents the device from being Bus Master, preventing 3704 * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3 3705 * compliant devices, INTx-disable prevents legacy interrupts. 3706 */ 3707 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE); 3708 } 3709 3710 static void pci_dev_restore(struct pci_dev *dev) 3711 { 3712 pci_restore_state(dev); 3713 pci_reset_notify(dev, false); 3714 } 3715 3716 static int pci_dev_reset(struct pci_dev *dev, int probe) 3717 { 3718 int rc; 3719 3720 if (!probe) 3721 pci_dev_lock(dev); 3722 3723 rc = __pci_dev_reset(dev, probe); 3724 3725 if (!probe) 3726 pci_dev_unlock(dev); 3727 3728 return rc; 3729 } 3730 3731 /** 3732 * __pci_reset_function - reset a PCI device function 3733 * @dev: PCI device to reset 3734 * 3735 * Some devices allow an individual function to be reset without affecting 3736 * other functions in the same device. The PCI device must be responsive 3737 * to PCI config space in order to use this function. 3738 * 3739 * The device function is presumed to be unused when this function is called. 3740 * Resetting the device will make the contents of PCI configuration space 3741 * random, so any caller of this must be prepared to reinitialise the 3742 * device including MSI, bus mastering, BARs, decoding IO and memory spaces, 3743 * etc. 3744 * 3745 * Returns 0 if the device function was successfully reset or negative if the 3746 * device doesn't support resetting a single function. 3747 */ 3748 int __pci_reset_function(struct pci_dev *dev) 3749 { 3750 return pci_dev_reset(dev, 0); 3751 } 3752 EXPORT_SYMBOL_GPL(__pci_reset_function); 3753 3754 /** 3755 * __pci_reset_function_locked - reset a PCI device function while holding 3756 * the @dev mutex lock. 3757 * @dev: PCI device to reset 3758 * 3759 * Some devices allow an individual function to be reset without affecting 3760 * other functions in the same device. The PCI device must be responsive 3761 * to PCI config space in order to use this function. 3762 * 3763 * The device function is presumed to be unused and the caller is holding 3764 * the device mutex lock when this function is called. 3765 * Resetting the device will make the contents of PCI configuration space 3766 * random, so any caller of this must be prepared to reinitialise the 3767 * device including MSI, bus mastering, BARs, decoding IO and memory spaces, 3768 * etc. 3769 * 3770 * Returns 0 if the device function was successfully reset or negative if the 3771 * device doesn't support resetting a single function. 3772 */ 3773 int __pci_reset_function_locked(struct pci_dev *dev) 3774 { 3775 return __pci_dev_reset(dev, 0); 3776 } 3777 EXPORT_SYMBOL_GPL(__pci_reset_function_locked); 3778 3779 /** 3780 * pci_probe_reset_function - check whether the device can be safely reset 3781 * @dev: PCI device to reset 3782 * 3783 * Some devices allow an individual function to be reset without affecting 3784 * other functions in the same device. The PCI device must be responsive 3785 * to PCI config space in order to use this function. 3786 * 3787 * Returns 0 if the device function can be reset or negative if the 3788 * device doesn't support resetting a single function. 3789 */ 3790 int pci_probe_reset_function(struct pci_dev *dev) 3791 { 3792 return pci_dev_reset(dev, 1); 3793 } 3794 3795 /** 3796 * pci_reset_function - quiesce and reset a PCI device function 3797 * @dev: PCI device to reset 3798 * 3799 * Some devices allow an individual function to be reset without affecting 3800 * other functions in the same device. The PCI device must be responsive 3801 * to PCI config space in order to use this function. 3802 * 3803 * This function does not just reset the PCI portion of a device, but 3804 * clears all the state associated with the device. This function differs 3805 * from __pci_reset_function in that it saves and restores device state 3806 * over the reset. 3807 * 3808 * Returns 0 if the device function was successfully reset or negative if the 3809 * device doesn't support resetting a single function. 3810 */ 3811 int pci_reset_function(struct pci_dev *dev) 3812 { 3813 int rc; 3814 3815 rc = pci_dev_reset(dev, 1); 3816 if (rc) 3817 return rc; 3818 3819 pci_dev_save_and_disable(dev); 3820 3821 rc = pci_dev_reset(dev, 0); 3822 3823 pci_dev_restore(dev); 3824 3825 return rc; 3826 } 3827 EXPORT_SYMBOL_GPL(pci_reset_function); 3828 3829 /** 3830 * pci_try_reset_function - quiesce and reset a PCI device function 3831 * @dev: PCI device to reset 3832 * 3833 * Same as above, except return -EAGAIN if unable to lock device. 3834 */ 3835 int pci_try_reset_function(struct pci_dev *dev) 3836 { 3837 int rc; 3838 3839 rc = pci_dev_reset(dev, 1); 3840 if (rc) 3841 return rc; 3842 3843 pci_dev_save_and_disable(dev); 3844 3845 if (pci_dev_trylock(dev)) { 3846 rc = __pci_dev_reset(dev, 0); 3847 pci_dev_unlock(dev); 3848 } else 3849 rc = -EAGAIN; 3850 3851 pci_dev_restore(dev); 3852 3853 return rc; 3854 } 3855 EXPORT_SYMBOL_GPL(pci_try_reset_function); 3856 3857 /* Do any devices on or below this bus prevent a bus reset? */ 3858 static bool pci_bus_resetable(struct pci_bus *bus) 3859 { 3860 struct pci_dev *dev; 3861 3862 list_for_each_entry(dev, &bus->devices, bus_list) { 3863 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET || 3864 (dev->subordinate && !pci_bus_resetable(dev->subordinate))) 3865 return false; 3866 } 3867 3868 return true; 3869 } 3870 3871 /* Lock devices from the top of the tree down */ 3872 static void pci_bus_lock(struct pci_bus *bus) 3873 { 3874 struct pci_dev *dev; 3875 3876 list_for_each_entry(dev, &bus->devices, bus_list) { 3877 pci_dev_lock(dev); 3878 if (dev->subordinate) 3879 pci_bus_lock(dev->subordinate); 3880 } 3881 } 3882 3883 /* Unlock devices from the bottom of the tree up */ 3884 static void pci_bus_unlock(struct pci_bus *bus) 3885 { 3886 struct pci_dev *dev; 3887 3888 list_for_each_entry(dev, &bus->devices, bus_list) { 3889 if (dev->subordinate) 3890 pci_bus_unlock(dev->subordinate); 3891 pci_dev_unlock(dev); 3892 } 3893 } 3894 3895 /* Return 1 on successful lock, 0 on contention */ 3896 static int pci_bus_trylock(struct pci_bus *bus) 3897 { 3898 struct pci_dev *dev; 3899 3900 list_for_each_entry(dev, &bus->devices, bus_list) { 3901 if (!pci_dev_trylock(dev)) 3902 goto unlock; 3903 if (dev->subordinate) { 3904 if (!pci_bus_trylock(dev->subordinate)) { 3905 pci_dev_unlock(dev); 3906 goto unlock; 3907 } 3908 } 3909 } 3910 return 1; 3911 3912 unlock: 3913 list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) { 3914 if (dev->subordinate) 3915 pci_bus_unlock(dev->subordinate); 3916 pci_dev_unlock(dev); 3917 } 3918 return 0; 3919 } 3920 3921 /* Do any devices on or below this slot prevent a bus reset? */ 3922 static bool pci_slot_resetable(struct pci_slot *slot) 3923 { 3924 struct pci_dev *dev; 3925 3926 list_for_each_entry(dev, &slot->bus->devices, bus_list) { 3927 if (!dev->slot || dev->slot != slot) 3928 continue; 3929 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET || 3930 (dev->subordinate && !pci_bus_resetable(dev->subordinate))) 3931 return false; 3932 } 3933 3934 return true; 3935 } 3936 3937 /* Lock devices from the top of the tree down */ 3938 static void pci_slot_lock(struct pci_slot *slot) 3939 { 3940 struct pci_dev *dev; 3941 3942 list_for_each_entry(dev, &slot->bus->devices, bus_list) { 3943 if (!dev->slot || dev->slot != slot) 3944 continue; 3945 pci_dev_lock(dev); 3946 if (dev->subordinate) 3947 pci_bus_lock(dev->subordinate); 3948 } 3949 } 3950 3951 /* Unlock devices from the bottom of the tree up */ 3952 static void pci_slot_unlock(struct pci_slot *slot) 3953 { 3954 struct pci_dev *dev; 3955 3956 list_for_each_entry(dev, &slot->bus->devices, bus_list) { 3957 if (!dev->slot || dev->slot != slot) 3958 continue; 3959 if (dev->subordinate) 3960 pci_bus_unlock(dev->subordinate); 3961 pci_dev_unlock(dev); 3962 } 3963 } 3964 3965 /* Return 1 on successful lock, 0 on contention */ 3966 static int pci_slot_trylock(struct pci_slot *slot) 3967 { 3968 struct pci_dev *dev; 3969 3970 list_for_each_entry(dev, &slot->bus->devices, bus_list) { 3971 if (!dev->slot || dev->slot != slot) 3972 continue; 3973 if (!pci_dev_trylock(dev)) 3974 goto unlock; 3975 if (dev->subordinate) { 3976 if (!pci_bus_trylock(dev->subordinate)) { 3977 pci_dev_unlock(dev); 3978 goto unlock; 3979 } 3980 } 3981 } 3982 return 1; 3983 3984 unlock: 3985 list_for_each_entry_continue_reverse(dev, 3986 &slot->bus->devices, bus_list) { 3987 if (!dev->slot || dev->slot != slot) 3988 continue; 3989 if (dev->subordinate) 3990 pci_bus_unlock(dev->subordinate); 3991 pci_dev_unlock(dev); 3992 } 3993 return 0; 3994 } 3995 3996 /* Save and disable devices from the top of the tree down */ 3997 static void pci_bus_save_and_disable(struct pci_bus *bus) 3998 { 3999 struct pci_dev *dev; 4000 4001 list_for_each_entry(dev, &bus->devices, bus_list) { 4002 pci_dev_save_and_disable(dev); 4003 if (dev->subordinate) 4004 pci_bus_save_and_disable(dev->subordinate); 4005 } 4006 } 4007 4008 /* 4009 * Restore devices from top of the tree down - parent bridges need to be 4010 * restored before we can get to subordinate devices. 4011 */ 4012 static void pci_bus_restore(struct pci_bus *bus) 4013 { 4014 struct pci_dev *dev; 4015 4016 list_for_each_entry(dev, &bus->devices, bus_list) { 4017 pci_dev_restore(dev); 4018 if (dev->subordinate) 4019 pci_bus_restore(dev->subordinate); 4020 } 4021 } 4022 4023 /* Save and disable devices from the top of the tree down */ 4024 static void pci_slot_save_and_disable(struct pci_slot *slot) 4025 { 4026 struct pci_dev *dev; 4027 4028 list_for_each_entry(dev, &slot->bus->devices, bus_list) { 4029 if (!dev->slot || dev->slot != slot) 4030 continue; 4031 pci_dev_save_and_disable(dev); 4032 if (dev->subordinate) 4033 pci_bus_save_and_disable(dev->subordinate); 4034 } 4035 } 4036 4037 /* 4038 * Restore devices from top of the tree down - parent bridges need to be 4039 * restored before we can get to subordinate devices. 4040 */ 4041 static void pci_slot_restore(struct pci_slot *slot) 4042 { 4043 struct pci_dev *dev; 4044 4045 list_for_each_entry(dev, &slot->bus->devices, bus_list) { 4046 if (!dev->slot || dev->slot != slot) 4047 continue; 4048 pci_dev_restore(dev); 4049 if (dev->subordinate) 4050 pci_bus_restore(dev->subordinate); 4051 } 4052 } 4053 4054 static int pci_slot_reset(struct pci_slot *slot, int probe) 4055 { 4056 int rc; 4057 4058 if (!slot || !pci_slot_resetable(slot)) 4059 return -ENOTTY; 4060 4061 if (!probe) 4062 pci_slot_lock(slot); 4063 4064 might_sleep(); 4065 4066 rc = pci_reset_hotplug_slot(slot->hotplug, probe); 4067 4068 if (!probe) 4069 pci_slot_unlock(slot); 4070 4071 return rc; 4072 } 4073 4074 /** 4075 * pci_probe_reset_slot - probe whether a PCI slot can be reset 4076 * @slot: PCI slot to probe 4077 * 4078 * Return 0 if slot can be reset, negative if a slot reset is not supported. 4079 */ 4080 int pci_probe_reset_slot(struct pci_slot *slot) 4081 { 4082 return pci_slot_reset(slot, 1); 4083 } 4084 EXPORT_SYMBOL_GPL(pci_probe_reset_slot); 4085 4086 /** 4087 * pci_reset_slot - reset a PCI slot 4088 * @slot: PCI slot to reset 4089 * 4090 * A PCI bus may host multiple slots, each slot may support a reset mechanism 4091 * independent of other slots. For instance, some slots may support slot power 4092 * control. In the case of a 1:1 bus to slot architecture, this function may 4093 * wrap the bus reset to avoid spurious slot related events such as hotplug. 4094 * Generally a slot reset should be attempted before a bus reset. All of the 4095 * function of the slot and any subordinate buses behind the slot are reset 4096 * through this function. PCI config space of all devices in the slot and 4097 * behind the slot is saved before and restored after reset. 4098 * 4099 * Return 0 on success, non-zero on error. 4100 */ 4101 int pci_reset_slot(struct pci_slot *slot) 4102 { 4103 int rc; 4104 4105 rc = pci_slot_reset(slot, 1); 4106 if (rc) 4107 return rc; 4108 4109 pci_slot_save_and_disable(slot); 4110 4111 rc = pci_slot_reset(slot, 0); 4112 4113 pci_slot_restore(slot); 4114 4115 return rc; 4116 } 4117 EXPORT_SYMBOL_GPL(pci_reset_slot); 4118 4119 /** 4120 * pci_try_reset_slot - Try to reset a PCI slot 4121 * @slot: PCI slot to reset 4122 * 4123 * Same as above except return -EAGAIN if the slot cannot be locked 4124 */ 4125 int pci_try_reset_slot(struct pci_slot *slot) 4126 { 4127 int rc; 4128 4129 rc = pci_slot_reset(slot, 1); 4130 if (rc) 4131 return rc; 4132 4133 pci_slot_save_and_disable(slot); 4134 4135 if (pci_slot_trylock(slot)) { 4136 might_sleep(); 4137 rc = pci_reset_hotplug_slot(slot->hotplug, 0); 4138 pci_slot_unlock(slot); 4139 } else 4140 rc = -EAGAIN; 4141 4142 pci_slot_restore(slot); 4143 4144 return rc; 4145 } 4146 EXPORT_SYMBOL_GPL(pci_try_reset_slot); 4147 4148 static int pci_bus_reset(struct pci_bus *bus, int probe) 4149 { 4150 if (!bus->self || !pci_bus_resetable(bus)) 4151 return -ENOTTY; 4152 4153 if (probe) 4154 return 0; 4155 4156 pci_bus_lock(bus); 4157 4158 might_sleep(); 4159 4160 pci_reset_bridge_secondary_bus(bus->self); 4161 4162 pci_bus_unlock(bus); 4163 4164 return 0; 4165 } 4166 4167 /** 4168 * pci_probe_reset_bus - probe whether a PCI bus can be reset 4169 * @bus: PCI bus to probe 4170 * 4171 * Return 0 if bus can be reset, negative if a bus reset is not supported. 4172 */ 4173 int pci_probe_reset_bus(struct pci_bus *bus) 4174 { 4175 return pci_bus_reset(bus, 1); 4176 } 4177 EXPORT_SYMBOL_GPL(pci_probe_reset_bus); 4178 4179 /** 4180 * pci_reset_bus - reset a PCI bus 4181 * @bus: top level PCI bus to reset 4182 * 4183 * Do a bus reset on the given bus and any subordinate buses, saving 4184 * and restoring state of all devices. 4185 * 4186 * Return 0 on success, non-zero on error. 4187 */ 4188 int pci_reset_bus(struct pci_bus *bus) 4189 { 4190 int rc; 4191 4192 rc = pci_bus_reset(bus, 1); 4193 if (rc) 4194 return rc; 4195 4196 pci_bus_save_and_disable(bus); 4197 4198 rc = pci_bus_reset(bus, 0); 4199 4200 pci_bus_restore(bus); 4201 4202 return rc; 4203 } 4204 EXPORT_SYMBOL_GPL(pci_reset_bus); 4205 4206 /** 4207 * pci_try_reset_bus - Try to reset a PCI bus 4208 * @bus: top level PCI bus to reset 4209 * 4210 * Same as above except return -EAGAIN if the bus cannot be locked 4211 */ 4212 int pci_try_reset_bus(struct pci_bus *bus) 4213 { 4214 int rc; 4215 4216 rc = pci_bus_reset(bus, 1); 4217 if (rc) 4218 return rc; 4219 4220 pci_bus_save_and_disable(bus); 4221 4222 if (pci_bus_trylock(bus)) { 4223 might_sleep(); 4224 pci_reset_bridge_secondary_bus(bus->self); 4225 pci_bus_unlock(bus); 4226 } else 4227 rc = -EAGAIN; 4228 4229 pci_bus_restore(bus); 4230 4231 return rc; 4232 } 4233 EXPORT_SYMBOL_GPL(pci_try_reset_bus); 4234 4235 /** 4236 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count 4237 * @dev: PCI device to query 4238 * 4239 * Returns mmrbc: maximum designed memory read count in bytes 4240 * or appropriate error value. 4241 */ 4242 int pcix_get_max_mmrbc(struct pci_dev *dev) 4243 { 4244 int cap; 4245 u32 stat; 4246 4247 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); 4248 if (!cap) 4249 return -EINVAL; 4250 4251 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat)) 4252 return -EINVAL; 4253 4254 return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21); 4255 } 4256 EXPORT_SYMBOL(pcix_get_max_mmrbc); 4257 4258 /** 4259 * pcix_get_mmrbc - get PCI-X maximum memory read byte count 4260 * @dev: PCI device to query 4261 * 4262 * Returns mmrbc: maximum memory read count in bytes 4263 * or appropriate error value. 4264 */ 4265 int pcix_get_mmrbc(struct pci_dev *dev) 4266 { 4267 int cap; 4268 u16 cmd; 4269 4270 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); 4271 if (!cap) 4272 return -EINVAL; 4273 4274 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd)) 4275 return -EINVAL; 4276 4277 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2); 4278 } 4279 EXPORT_SYMBOL(pcix_get_mmrbc); 4280 4281 /** 4282 * pcix_set_mmrbc - set PCI-X maximum memory read byte count 4283 * @dev: PCI device to query 4284 * @mmrbc: maximum memory read count in bytes 4285 * valid values are 512, 1024, 2048, 4096 4286 * 4287 * If possible sets maximum memory read byte count, some bridges have erratas 4288 * that prevent this. 4289 */ 4290 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc) 4291 { 4292 int cap; 4293 u32 stat, v, o; 4294 u16 cmd; 4295 4296 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc)) 4297 return -EINVAL; 4298 4299 v = ffs(mmrbc) - 10; 4300 4301 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); 4302 if (!cap) 4303 return -EINVAL; 4304 4305 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat)) 4306 return -EINVAL; 4307 4308 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21) 4309 return -E2BIG; 4310 4311 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd)) 4312 return -EINVAL; 4313 4314 o = (cmd & PCI_X_CMD_MAX_READ) >> 2; 4315 if (o != v) { 4316 if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC)) 4317 return -EIO; 4318 4319 cmd &= ~PCI_X_CMD_MAX_READ; 4320 cmd |= v << 2; 4321 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd)) 4322 return -EIO; 4323 } 4324 return 0; 4325 } 4326 EXPORT_SYMBOL(pcix_set_mmrbc); 4327 4328 /** 4329 * pcie_get_readrq - get PCI Express read request size 4330 * @dev: PCI device to query 4331 * 4332 * Returns maximum memory read request in bytes 4333 * or appropriate error value. 4334 */ 4335 int pcie_get_readrq(struct pci_dev *dev) 4336 { 4337 u16 ctl; 4338 4339 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl); 4340 4341 return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12); 4342 } 4343 EXPORT_SYMBOL(pcie_get_readrq); 4344 4345 /** 4346 * pcie_set_readrq - set PCI Express maximum memory read request 4347 * @dev: PCI device to query 4348 * @rq: maximum memory read count in bytes 4349 * valid values are 128, 256, 512, 1024, 2048, 4096 4350 * 4351 * If possible sets maximum memory read request in bytes 4352 */ 4353 int pcie_set_readrq(struct pci_dev *dev, int rq) 4354 { 4355 u16 v; 4356 4357 if (rq < 128 || rq > 4096 || !is_power_of_2(rq)) 4358 return -EINVAL; 4359 4360 /* 4361 * If using the "performance" PCIe config, we clamp the 4362 * read rq size to the max packet size to prevent the 4363 * host bridge generating requests larger than we can 4364 * cope with 4365 */ 4366 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) { 4367 int mps = pcie_get_mps(dev); 4368 4369 if (mps < rq) 4370 rq = mps; 4371 } 4372 4373 v = (ffs(rq) - 8) << 12; 4374 4375 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL, 4376 PCI_EXP_DEVCTL_READRQ, v); 4377 } 4378 EXPORT_SYMBOL(pcie_set_readrq); 4379 4380 /** 4381 * pcie_get_mps - get PCI Express maximum payload size 4382 * @dev: PCI device to query 4383 * 4384 * Returns maximum payload size in bytes 4385 */ 4386 int pcie_get_mps(struct pci_dev *dev) 4387 { 4388 u16 ctl; 4389 4390 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl); 4391 4392 return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5); 4393 } 4394 EXPORT_SYMBOL(pcie_get_mps); 4395 4396 /** 4397 * pcie_set_mps - set PCI Express maximum payload size 4398 * @dev: PCI device to query 4399 * @mps: maximum payload size in bytes 4400 * valid values are 128, 256, 512, 1024, 2048, 4096 4401 * 4402 * If possible sets maximum payload size 4403 */ 4404 int pcie_set_mps(struct pci_dev *dev, int mps) 4405 { 4406 u16 v; 4407 4408 if (mps < 128 || mps > 4096 || !is_power_of_2(mps)) 4409 return -EINVAL; 4410 4411 v = ffs(mps) - 8; 4412 if (v > dev->pcie_mpss) 4413 return -EINVAL; 4414 v <<= 5; 4415 4416 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL, 4417 PCI_EXP_DEVCTL_PAYLOAD, v); 4418 } 4419 EXPORT_SYMBOL(pcie_set_mps); 4420 4421 /** 4422 * pcie_get_minimum_link - determine minimum link settings of a PCI device 4423 * @dev: PCI device to query 4424 * @speed: storage for minimum speed 4425 * @width: storage for minimum width 4426 * 4427 * This function will walk up the PCI device chain and determine the minimum 4428 * link width and speed of the device. 4429 */ 4430 int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed, 4431 enum pcie_link_width *width) 4432 { 4433 int ret; 4434 4435 *speed = PCI_SPEED_UNKNOWN; 4436 *width = PCIE_LNK_WIDTH_UNKNOWN; 4437 4438 while (dev) { 4439 u16 lnksta; 4440 enum pci_bus_speed next_speed; 4441 enum pcie_link_width next_width; 4442 4443 ret = pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta); 4444 if (ret) 4445 return ret; 4446 4447 next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS]; 4448 next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >> 4449 PCI_EXP_LNKSTA_NLW_SHIFT; 4450 4451 if (next_speed < *speed) 4452 *speed = next_speed; 4453 4454 if (next_width < *width) 4455 *width = next_width; 4456 4457 dev = dev->bus->self; 4458 } 4459 4460 return 0; 4461 } 4462 EXPORT_SYMBOL(pcie_get_minimum_link); 4463 4464 /** 4465 * pci_select_bars - Make BAR mask from the type of resource 4466 * @dev: the PCI device for which BAR mask is made 4467 * @flags: resource type mask to be selected 4468 * 4469 * This helper routine makes bar mask from the type of resource. 4470 */ 4471 int pci_select_bars(struct pci_dev *dev, unsigned long flags) 4472 { 4473 int i, bars = 0; 4474 for (i = 0; i < PCI_NUM_RESOURCES; i++) 4475 if (pci_resource_flags(dev, i) & flags) 4476 bars |= (1 << i); 4477 return bars; 4478 } 4479 EXPORT_SYMBOL(pci_select_bars); 4480 4481 /** 4482 * pci_resource_bar - get position of the BAR associated with a resource 4483 * @dev: the PCI device 4484 * @resno: the resource number 4485 * @type: the BAR type to be filled in 4486 * 4487 * Returns BAR position in config space, or 0 if the BAR is invalid. 4488 */ 4489 int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type) 4490 { 4491 int reg; 4492 4493 if (resno < PCI_ROM_RESOURCE) { 4494 *type = pci_bar_unknown; 4495 return PCI_BASE_ADDRESS_0 + 4 * resno; 4496 } else if (resno == PCI_ROM_RESOURCE) { 4497 *type = pci_bar_mem32; 4498 return dev->rom_base_reg; 4499 } else if (resno < PCI_BRIDGE_RESOURCES) { 4500 /* device specific resource */ 4501 *type = pci_bar_unknown; 4502 reg = pci_iov_resource_bar(dev, resno); 4503 if (reg) 4504 return reg; 4505 } 4506 4507 dev_err(&dev->dev, "BAR %d: invalid resource\n", resno); 4508 return 0; 4509 } 4510 4511 /* Some architectures require additional programming to enable VGA */ 4512 static arch_set_vga_state_t arch_set_vga_state; 4513 4514 void __init pci_register_set_vga_state(arch_set_vga_state_t func) 4515 { 4516 arch_set_vga_state = func; /* NULL disables */ 4517 } 4518 4519 static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode, 4520 unsigned int command_bits, u32 flags) 4521 { 4522 if (arch_set_vga_state) 4523 return arch_set_vga_state(dev, decode, command_bits, 4524 flags); 4525 return 0; 4526 } 4527 4528 /** 4529 * pci_set_vga_state - set VGA decode state on device and parents if requested 4530 * @dev: the PCI device 4531 * @decode: true = enable decoding, false = disable decoding 4532 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY 4533 * @flags: traverse ancestors and change bridges 4534 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE 4535 */ 4536 int pci_set_vga_state(struct pci_dev *dev, bool decode, 4537 unsigned int command_bits, u32 flags) 4538 { 4539 struct pci_bus *bus; 4540 struct pci_dev *bridge; 4541 u16 cmd; 4542 int rc; 4543 4544 WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) && (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY))); 4545 4546 /* ARCH specific VGA enables */ 4547 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags); 4548 if (rc) 4549 return rc; 4550 4551 if (flags & PCI_VGA_STATE_CHANGE_DECODES) { 4552 pci_read_config_word(dev, PCI_COMMAND, &cmd); 4553 if (decode == true) 4554 cmd |= command_bits; 4555 else 4556 cmd &= ~command_bits; 4557 pci_write_config_word(dev, PCI_COMMAND, cmd); 4558 } 4559 4560 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE)) 4561 return 0; 4562 4563 bus = dev->bus; 4564 while (bus) { 4565 bridge = bus->self; 4566 if (bridge) { 4567 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL, 4568 &cmd); 4569 if (decode == true) 4570 cmd |= PCI_BRIDGE_CTL_VGA; 4571 else 4572 cmd &= ~PCI_BRIDGE_CTL_VGA; 4573 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, 4574 cmd); 4575 } 4576 bus = bus->parent; 4577 } 4578 return 0; 4579 } 4580 4581 bool pci_device_is_present(struct pci_dev *pdev) 4582 { 4583 u32 v; 4584 4585 return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0); 4586 } 4587 EXPORT_SYMBOL_GPL(pci_device_is_present); 4588 4589 void pci_ignore_hotplug(struct pci_dev *dev) 4590 { 4591 struct pci_dev *bridge = dev->bus->self; 4592 4593 dev->ignore_hotplug = 1; 4594 /* Propagate the "ignore hotplug" setting to the parent bridge. */ 4595 if (bridge) 4596 bridge->ignore_hotplug = 1; 4597 } 4598 EXPORT_SYMBOL_GPL(pci_ignore_hotplug); 4599 4600 #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE 4601 static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0}; 4602 static DEFINE_SPINLOCK(resource_alignment_lock); 4603 4604 /** 4605 * pci_specified_resource_alignment - get resource alignment specified by user. 4606 * @dev: the PCI device to get 4607 * 4608 * RETURNS: Resource alignment if it is specified. 4609 * Zero if it is not specified. 4610 */ 4611 static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev) 4612 { 4613 int seg, bus, slot, func, align_order, count; 4614 resource_size_t align = 0; 4615 char *p; 4616 4617 spin_lock(&resource_alignment_lock); 4618 p = resource_alignment_param; 4619 while (*p) { 4620 count = 0; 4621 if (sscanf(p, "%d%n", &align_order, &count) == 1 && 4622 p[count] == '@') { 4623 p += count + 1; 4624 } else { 4625 align_order = -1; 4626 } 4627 if (sscanf(p, "%x:%x:%x.%x%n", 4628 &seg, &bus, &slot, &func, &count) != 4) { 4629 seg = 0; 4630 if (sscanf(p, "%x:%x.%x%n", 4631 &bus, &slot, &func, &count) != 3) { 4632 /* Invalid format */ 4633 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n", 4634 p); 4635 break; 4636 } 4637 } 4638 p += count; 4639 if (seg == pci_domain_nr(dev->bus) && 4640 bus == dev->bus->number && 4641 slot == PCI_SLOT(dev->devfn) && 4642 func == PCI_FUNC(dev->devfn)) { 4643 if (align_order == -1) 4644 align = PAGE_SIZE; 4645 else 4646 align = 1 << align_order; 4647 /* Found */ 4648 break; 4649 } 4650 if (*p != ';' && *p != ',') { 4651 /* End of param or invalid format */ 4652 break; 4653 } 4654 p++; 4655 } 4656 spin_unlock(&resource_alignment_lock); 4657 return align; 4658 } 4659 4660 /* 4661 * This function disables memory decoding and releases memory resources 4662 * of the device specified by kernel's boot parameter 'pci=resource_alignment='. 4663 * It also rounds up size to specified alignment. 4664 * Later on, the kernel will assign page-aligned memory resource back 4665 * to the device. 4666 */ 4667 void pci_reassigndev_resource_alignment(struct pci_dev *dev) 4668 { 4669 int i; 4670 struct resource *r; 4671 resource_size_t align, size; 4672 u16 command; 4673 4674 /* check if specified PCI is target device to reassign */ 4675 align = pci_specified_resource_alignment(dev); 4676 if (!align) 4677 return; 4678 4679 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL && 4680 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) { 4681 dev_warn(&dev->dev, 4682 "Can't reassign resources to host bridge.\n"); 4683 return; 4684 } 4685 4686 dev_info(&dev->dev, 4687 "Disabling memory decoding and releasing memory resources.\n"); 4688 pci_read_config_word(dev, PCI_COMMAND, &command); 4689 command &= ~PCI_COMMAND_MEMORY; 4690 pci_write_config_word(dev, PCI_COMMAND, command); 4691 4692 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) { 4693 r = &dev->resource[i]; 4694 if (!(r->flags & IORESOURCE_MEM)) 4695 continue; 4696 size = resource_size(r); 4697 if (size < align) { 4698 size = align; 4699 dev_info(&dev->dev, 4700 "Rounding up size of resource #%d to %#llx.\n", 4701 i, (unsigned long long)size); 4702 } 4703 r->flags |= IORESOURCE_UNSET; 4704 r->end = size - 1; 4705 r->start = 0; 4706 } 4707 /* Need to disable bridge's resource window, 4708 * to enable the kernel to reassign new resource 4709 * window later on. 4710 */ 4711 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE && 4712 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { 4713 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) { 4714 r = &dev->resource[i]; 4715 if (!(r->flags & IORESOURCE_MEM)) 4716 continue; 4717 r->flags |= IORESOURCE_UNSET; 4718 r->end = resource_size(r) - 1; 4719 r->start = 0; 4720 } 4721 pci_disable_bridge_window(dev); 4722 } 4723 } 4724 4725 static ssize_t pci_set_resource_alignment_param(const char *buf, size_t count) 4726 { 4727 if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1) 4728 count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1; 4729 spin_lock(&resource_alignment_lock); 4730 strncpy(resource_alignment_param, buf, count); 4731 resource_alignment_param[count] = '\0'; 4732 spin_unlock(&resource_alignment_lock); 4733 return count; 4734 } 4735 4736 static ssize_t pci_get_resource_alignment_param(char *buf, size_t size) 4737 { 4738 size_t count; 4739 spin_lock(&resource_alignment_lock); 4740 count = snprintf(buf, size, "%s", resource_alignment_param); 4741 spin_unlock(&resource_alignment_lock); 4742 return count; 4743 } 4744 4745 static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf) 4746 { 4747 return pci_get_resource_alignment_param(buf, PAGE_SIZE); 4748 } 4749 4750 static ssize_t pci_resource_alignment_store(struct bus_type *bus, 4751 const char *buf, size_t count) 4752 { 4753 return pci_set_resource_alignment_param(buf, count); 4754 } 4755 4756 BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show, 4757 pci_resource_alignment_store); 4758 4759 static int __init pci_resource_alignment_sysfs_init(void) 4760 { 4761 return bus_create_file(&pci_bus_type, 4762 &bus_attr_resource_alignment); 4763 } 4764 late_initcall(pci_resource_alignment_sysfs_init); 4765 4766 static void pci_no_domains(void) 4767 { 4768 #ifdef CONFIG_PCI_DOMAINS 4769 pci_domains_supported = 0; 4770 #endif 4771 } 4772 4773 #ifdef CONFIG_PCI_DOMAINS 4774 static atomic_t __domain_nr = ATOMIC_INIT(-1); 4775 4776 int pci_get_new_domain_nr(void) 4777 { 4778 return atomic_inc_return(&__domain_nr); 4779 } 4780 4781 #ifdef CONFIG_PCI_DOMAINS_GENERIC 4782 void pci_bus_assign_domain_nr(struct pci_bus *bus, struct device *parent) 4783 { 4784 static int use_dt_domains = -1; 4785 int domain = -1; 4786 4787 if (parent) 4788 domain = of_get_pci_domain_nr(parent->of_node); 4789 /* 4790 * Check DT domain and use_dt_domains values. 4791 * 4792 * If DT domain property is valid (domain >= 0) and 4793 * use_dt_domains != 0, the DT assignment is valid since this means 4794 * we have not previously allocated a domain number by using 4795 * pci_get_new_domain_nr(); we should also update use_dt_domains to 4796 * 1, to indicate that we have just assigned a domain number from 4797 * DT. 4798 * 4799 * If DT domain property value is not valid (ie domain < 0), and we 4800 * have not previously assigned a domain number from DT 4801 * (use_dt_domains != 1) we should assign a domain number by 4802 * using the: 4803 * 4804 * pci_get_new_domain_nr() 4805 * 4806 * API and update the use_dt_domains value to keep track of method we 4807 * are using to assign domain numbers (use_dt_domains = 0). 4808 * 4809 * All other combinations imply we have a platform that is trying 4810 * to mix domain numbers obtained from DT and pci_get_new_domain_nr(), 4811 * which is a recipe for domain mishandling and it is prevented by 4812 * invalidating the domain value (domain = -1) and printing a 4813 * corresponding error. 4814 */ 4815 if (domain >= 0 && use_dt_domains) { 4816 use_dt_domains = 1; 4817 } else if (domain < 0 && use_dt_domains != 1) { 4818 use_dt_domains = 0; 4819 domain = pci_get_new_domain_nr(); 4820 } else { 4821 dev_err(parent, "Node %s has inconsistent \"linux,pci-domain\" property in DT\n", 4822 parent->of_node->full_name); 4823 domain = -1; 4824 } 4825 4826 bus->domain_nr = domain; 4827 } 4828 #endif 4829 #endif 4830 4831 /** 4832 * pci_ext_cfg_avail - can we access extended PCI config space? 4833 * 4834 * Returns 1 if we can access PCI extended config space (offsets 4835 * greater than 0xff). This is the default implementation. Architecture 4836 * implementations can override this. 4837 */ 4838 int __weak pci_ext_cfg_avail(void) 4839 { 4840 return 1; 4841 } 4842 4843 void __weak pci_fixup_cardbus(struct pci_bus *bus) 4844 { 4845 } 4846 EXPORT_SYMBOL(pci_fixup_cardbus); 4847 4848 static int __init pci_setup(char *str) 4849 { 4850 while (str) { 4851 char *k = strchr(str, ','); 4852 if (k) 4853 *k++ = 0; 4854 if (*str && (str = pcibios_setup(str)) && *str) { 4855 if (!strcmp(str, "nomsi")) { 4856 pci_no_msi(); 4857 } else if (!strcmp(str, "noaer")) { 4858 pci_no_aer(); 4859 } else if (!strncmp(str, "realloc=", 8)) { 4860 pci_realloc_get_opt(str + 8); 4861 } else if (!strncmp(str, "realloc", 7)) { 4862 pci_realloc_get_opt("on"); 4863 } else if (!strcmp(str, "nodomains")) { 4864 pci_no_domains(); 4865 } else if (!strncmp(str, "noari", 5)) { 4866 pcie_ari_disabled = true; 4867 } else if (!strncmp(str, "cbiosize=", 9)) { 4868 pci_cardbus_io_size = memparse(str + 9, &str); 4869 } else if (!strncmp(str, "cbmemsize=", 10)) { 4870 pci_cardbus_mem_size = memparse(str + 10, &str); 4871 } else if (!strncmp(str, "resource_alignment=", 19)) { 4872 pci_set_resource_alignment_param(str + 19, 4873 strlen(str + 19)); 4874 } else if (!strncmp(str, "ecrc=", 5)) { 4875 pcie_ecrc_get_policy(str + 5); 4876 } else if (!strncmp(str, "hpiosize=", 9)) { 4877 pci_hotplug_io_size = memparse(str + 9, &str); 4878 } else if (!strncmp(str, "hpmemsize=", 10)) { 4879 pci_hotplug_mem_size = memparse(str + 10, &str); 4880 } else if (!strncmp(str, "pcie_bus_tune_off", 17)) { 4881 pcie_bus_config = PCIE_BUS_TUNE_OFF; 4882 } else if (!strncmp(str, "pcie_bus_safe", 13)) { 4883 pcie_bus_config = PCIE_BUS_SAFE; 4884 } else if (!strncmp(str, "pcie_bus_perf", 13)) { 4885 pcie_bus_config = PCIE_BUS_PERFORMANCE; 4886 } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) { 4887 pcie_bus_config = PCIE_BUS_PEER2PEER; 4888 } else if (!strncmp(str, "pcie_scan_all", 13)) { 4889 pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS); 4890 } else { 4891 printk(KERN_ERR "PCI: Unknown option `%s'\n", 4892 str); 4893 } 4894 } 4895 str = k; 4896 } 4897 return 0; 4898 } 4899 early_param("pci", pci_setup); 4900