1 /* 2 * PCI Bus Services, see include/linux/pci.h for further explanation. 3 * 4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter, 5 * David Mosberger-Tang 6 * 7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz> 8 */ 9 10 #include <linux/kernel.h> 11 #include <linux/delay.h> 12 #include <linux/init.h> 13 #include <linux/pci.h> 14 #include <linux/pm.h> 15 #include <linux/slab.h> 16 #include <linux/module.h> 17 #include <linux/spinlock.h> 18 #include <linux/string.h> 19 #include <linux/log2.h> 20 #include <linux/pci-aspm.h> 21 #include <linux/pm_wakeup.h> 22 #include <linux/interrupt.h> 23 #include <linux/device.h> 24 #include <linux/pm_runtime.h> 25 #include <linux/pci_hotplug.h> 26 #include <asm-generic/pci-bridge.h> 27 #include <asm/setup.h> 28 #include "pci.h" 29 30 const char *pci_power_names[] = { 31 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown", 32 }; 33 EXPORT_SYMBOL_GPL(pci_power_names); 34 35 int isa_dma_bridge_buggy; 36 EXPORT_SYMBOL(isa_dma_bridge_buggy); 37 38 int pci_pci_problems; 39 EXPORT_SYMBOL(pci_pci_problems); 40 41 unsigned int pci_pm_d3_delay; 42 43 static void pci_pme_list_scan(struct work_struct *work); 44 45 static LIST_HEAD(pci_pme_list); 46 static DEFINE_MUTEX(pci_pme_list_mutex); 47 static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan); 48 49 struct pci_pme_device { 50 struct list_head list; 51 struct pci_dev *dev; 52 }; 53 54 #define PME_TIMEOUT 1000 /* How long between PME checks */ 55 56 static void pci_dev_d3_sleep(struct pci_dev *dev) 57 { 58 unsigned int delay = dev->d3_delay; 59 60 if (delay < pci_pm_d3_delay) 61 delay = pci_pm_d3_delay; 62 63 msleep(delay); 64 } 65 66 #ifdef CONFIG_PCI_DOMAINS 67 int pci_domains_supported = 1; 68 #endif 69 70 #define DEFAULT_CARDBUS_IO_SIZE (256) 71 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024) 72 /* pci=cbmemsize=nnM,cbiosize=nn can override this */ 73 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE; 74 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE; 75 76 #define DEFAULT_HOTPLUG_IO_SIZE (256) 77 #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024) 78 /* pci=hpmemsize=nnM,hpiosize=nn can override this */ 79 unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE; 80 unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE; 81 82 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_TUNE_OFF; 83 84 /* 85 * The default CLS is used if arch didn't set CLS explicitly and not 86 * all pci devices agree on the same value. Arch can override either 87 * the dfl or actual value as it sees fit. Don't forget this is 88 * measured in 32-bit words, not bytes. 89 */ 90 u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2; 91 u8 pci_cache_line_size; 92 93 /* 94 * If we set up a device for bus mastering, we need to check the latency 95 * timer as certain BIOSes forget to set it properly. 96 */ 97 unsigned int pcibios_max_latency = 255; 98 99 /* If set, the PCIe ARI capability will not be used. */ 100 static bool pcie_ari_disabled; 101 102 /** 103 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children 104 * @bus: pointer to PCI bus structure to search 105 * 106 * Given a PCI bus, returns the highest PCI bus number present in the set 107 * including the given PCI bus and its list of child PCI buses. 108 */ 109 unsigned char pci_bus_max_busnr(struct pci_bus* bus) 110 { 111 struct list_head *tmp; 112 unsigned char max, n; 113 114 max = bus->busn_res.end; 115 list_for_each(tmp, &bus->children) { 116 n = pci_bus_max_busnr(pci_bus_b(tmp)); 117 if(n > max) 118 max = n; 119 } 120 return max; 121 } 122 EXPORT_SYMBOL_GPL(pci_bus_max_busnr); 123 124 #ifdef CONFIG_HAS_IOMEM 125 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar) 126 { 127 /* 128 * Make sure the BAR is actually a memory resource, not an IO resource 129 */ 130 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { 131 WARN_ON(1); 132 return NULL; 133 } 134 return ioremap_nocache(pci_resource_start(pdev, bar), 135 pci_resource_len(pdev, bar)); 136 } 137 EXPORT_SYMBOL_GPL(pci_ioremap_bar); 138 #endif 139 140 #define PCI_FIND_CAP_TTL 48 141 142 static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn, 143 u8 pos, int cap, int *ttl) 144 { 145 u8 id; 146 147 while ((*ttl)--) { 148 pci_bus_read_config_byte(bus, devfn, pos, &pos); 149 if (pos < 0x40) 150 break; 151 pos &= ~3; 152 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID, 153 &id); 154 if (id == 0xff) 155 break; 156 if (id == cap) 157 return pos; 158 pos += PCI_CAP_LIST_NEXT; 159 } 160 return 0; 161 } 162 163 static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn, 164 u8 pos, int cap) 165 { 166 int ttl = PCI_FIND_CAP_TTL; 167 168 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl); 169 } 170 171 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap) 172 { 173 return __pci_find_next_cap(dev->bus, dev->devfn, 174 pos + PCI_CAP_LIST_NEXT, cap); 175 } 176 EXPORT_SYMBOL_GPL(pci_find_next_capability); 177 178 static int __pci_bus_find_cap_start(struct pci_bus *bus, 179 unsigned int devfn, u8 hdr_type) 180 { 181 u16 status; 182 183 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status); 184 if (!(status & PCI_STATUS_CAP_LIST)) 185 return 0; 186 187 switch (hdr_type) { 188 case PCI_HEADER_TYPE_NORMAL: 189 case PCI_HEADER_TYPE_BRIDGE: 190 return PCI_CAPABILITY_LIST; 191 case PCI_HEADER_TYPE_CARDBUS: 192 return PCI_CB_CAPABILITY_LIST; 193 default: 194 return 0; 195 } 196 197 return 0; 198 } 199 200 /** 201 * pci_find_capability - query for devices' capabilities 202 * @dev: PCI device to query 203 * @cap: capability code 204 * 205 * Tell if a device supports a given PCI capability. 206 * Returns the address of the requested capability structure within the 207 * device's PCI configuration space or 0 in case the device does not 208 * support it. Possible values for @cap: 209 * 210 * %PCI_CAP_ID_PM Power Management 211 * %PCI_CAP_ID_AGP Accelerated Graphics Port 212 * %PCI_CAP_ID_VPD Vital Product Data 213 * %PCI_CAP_ID_SLOTID Slot Identification 214 * %PCI_CAP_ID_MSI Message Signalled Interrupts 215 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap 216 * %PCI_CAP_ID_PCIX PCI-X 217 * %PCI_CAP_ID_EXP PCI Express 218 */ 219 int pci_find_capability(struct pci_dev *dev, int cap) 220 { 221 int pos; 222 223 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); 224 if (pos) 225 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap); 226 227 return pos; 228 } 229 230 /** 231 * pci_bus_find_capability - query for devices' capabilities 232 * @bus: the PCI bus to query 233 * @devfn: PCI device to query 234 * @cap: capability code 235 * 236 * Like pci_find_capability() but works for pci devices that do not have a 237 * pci_dev structure set up yet. 238 * 239 * Returns the address of the requested capability structure within the 240 * device's PCI configuration space or 0 in case the device does not 241 * support it. 242 */ 243 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap) 244 { 245 int pos; 246 u8 hdr_type; 247 248 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type); 249 250 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f); 251 if (pos) 252 pos = __pci_find_next_cap(bus, devfn, pos, cap); 253 254 return pos; 255 } 256 257 /** 258 * pci_find_next_ext_capability - Find an extended capability 259 * @dev: PCI device to query 260 * @start: address at which to start looking (0 to start at beginning of list) 261 * @cap: capability code 262 * 263 * Returns the address of the next matching extended capability structure 264 * within the device's PCI configuration space or 0 if the device does 265 * not support it. Some capabilities can occur several times, e.g., the 266 * vendor-specific capability, and this provides a way to find them all. 267 */ 268 int pci_find_next_ext_capability(struct pci_dev *dev, int start, int cap) 269 { 270 u32 header; 271 int ttl; 272 int pos = PCI_CFG_SPACE_SIZE; 273 274 /* minimum 8 bytes per capability */ 275 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; 276 277 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE) 278 return 0; 279 280 if (start) 281 pos = start; 282 283 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) 284 return 0; 285 286 /* 287 * If we have no capabilities, this is indicated by cap ID, 288 * cap version and next pointer all being 0. 289 */ 290 if (header == 0) 291 return 0; 292 293 while (ttl-- > 0) { 294 if (PCI_EXT_CAP_ID(header) == cap && pos != start) 295 return pos; 296 297 pos = PCI_EXT_CAP_NEXT(header); 298 if (pos < PCI_CFG_SPACE_SIZE) 299 break; 300 301 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) 302 break; 303 } 304 305 return 0; 306 } 307 EXPORT_SYMBOL_GPL(pci_find_next_ext_capability); 308 309 /** 310 * pci_find_ext_capability - Find an extended capability 311 * @dev: PCI device to query 312 * @cap: capability code 313 * 314 * Returns the address of the requested extended capability structure 315 * within the device's PCI configuration space or 0 if the device does 316 * not support it. Possible values for @cap: 317 * 318 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting 319 * %PCI_EXT_CAP_ID_VC Virtual Channel 320 * %PCI_EXT_CAP_ID_DSN Device Serial Number 321 * %PCI_EXT_CAP_ID_PWR Power Budgeting 322 */ 323 int pci_find_ext_capability(struct pci_dev *dev, int cap) 324 { 325 return pci_find_next_ext_capability(dev, 0, cap); 326 } 327 EXPORT_SYMBOL_GPL(pci_find_ext_capability); 328 329 static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap) 330 { 331 int rc, ttl = PCI_FIND_CAP_TTL; 332 u8 cap, mask; 333 334 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST) 335 mask = HT_3BIT_CAP_MASK; 336 else 337 mask = HT_5BIT_CAP_MASK; 338 339 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos, 340 PCI_CAP_ID_HT, &ttl); 341 while (pos) { 342 rc = pci_read_config_byte(dev, pos + 3, &cap); 343 if (rc != PCIBIOS_SUCCESSFUL) 344 return 0; 345 346 if ((cap & mask) == ht_cap) 347 return pos; 348 349 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, 350 pos + PCI_CAP_LIST_NEXT, 351 PCI_CAP_ID_HT, &ttl); 352 } 353 354 return 0; 355 } 356 /** 357 * pci_find_next_ht_capability - query a device's Hypertransport capabilities 358 * @dev: PCI device to query 359 * @pos: Position from which to continue searching 360 * @ht_cap: Hypertransport capability code 361 * 362 * To be used in conjunction with pci_find_ht_capability() to search for 363 * all capabilities matching @ht_cap. @pos should always be a value returned 364 * from pci_find_ht_capability(). 365 * 366 * NB. To be 100% safe against broken PCI devices, the caller should take 367 * steps to avoid an infinite loop. 368 */ 369 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap) 370 { 371 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap); 372 } 373 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability); 374 375 /** 376 * pci_find_ht_capability - query a device's Hypertransport capabilities 377 * @dev: PCI device to query 378 * @ht_cap: Hypertransport capability code 379 * 380 * Tell if a device supports a given Hypertransport capability. 381 * Returns an address within the device's PCI configuration space 382 * or 0 in case the device does not support the request capability. 383 * The address points to the PCI capability, of type PCI_CAP_ID_HT, 384 * which has a Hypertransport capability matching @ht_cap. 385 */ 386 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap) 387 { 388 int pos; 389 390 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); 391 if (pos) 392 pos = __pci_find_next_ht_cap(dev, pos, ht_cap); 393 394 return pos; 395 } 396 EXPORT_SYMBOL_GPL(pci_find_ht_capability); 397 398 /** 399 * pci_find_parent_resource - return resource region of parent bus of given region 400 * @dev: PCI device structure contains resources to be searched 401 * @res: child resource record for which parent is sought 402 * 403 * For given resource region of given device, return the resource 404 * region of parent bus the given region is contained in or where 405 * it should be allocated from. 406 */ 407 struct resource * 408 pci_find_parent_resource(const struct pci_dev *dev, struct resource *res) 409 { 410 const struct pci_bus *bus = dev->bus; 411 int i; 412 struct resource *best = NULL, *r; 413 414 pci_bus_for_each_resource(bus, r, i) { 415 if (!r) 416 continue; 417 if (res->start && !(res->start >= r->start && res->end <= r->end)) 418 continue; /* Not contained */ 419 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM)) 420 continue; /* Wrong type */ 421 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH)) 422 return r; /* Exact match */ 423 /* We can't insert a non-prefetch resource inside a prefetchable parent .. */ 424 if (r->flags & IORESOURCE_PREFETCH) 425 continue; 426 /* .. but we can put a prefetchable resource inside a non-prefetchable one */ 427 if (!best) 428 best = r; 429 } 430 return best; 431 } 432 433 /** 434 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up) 435 * @dev: PCI device to have its BARs restored 436 * 437 * Restore the BAR values for a given device, so as to make it 438 * accessible by its driver. 439 */ 440 static void 441 pci_restore_bars(struct pci_dev *dev) 442 { 443 int i; 444 445 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) 446 pci_update_resource(dev, i); 447 } 448 449 static struct pci_platform_pm_ops *pci_platform_pm; 450 451 int pci_set_platform_pm(struct pci_platform_pm_ops *ops) 452 { 453 if (!ops->is_manageable || !ops->set_state || !ops->choose_state 454 || !ops->sleep_wake) 455 return -EINVAL; 456 pci_platform_pm = ops; 457 return 0; 458 } 459 460 static inline bool platform_pci_power_manageable(struct pci_dev *dev) 461 { 462 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false; 463 } 464 465 static inline int platform_pci_set_power_state(struct pci_dev *dev, 466 pci_power_t t) 467 { 468 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS; 469 } 470 471 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev) 472 { 473 return pci_platform_pm ? 474 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR; 475 } 476 477 static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable) 478 { 479 return pci_platform_pm ? 480 pci_platform_pm->sleep_wake(dev, enable) : -ENODEV; 481 } 482 483 static inline int platform_pci_run_wake(struct pci_dev *dev, bool enable) 484 { 485 return pci_platform_pm ? 486 pci_platform_pm->run_wake(dev, enable) : -ENODEV; 487 } 488 489 /** 490 * pci_raw_set_power_state - Use PCI PM registers to set the power state of 491 * given PCI device 492 * @dev: PCI device to handle. 493 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into. 494 * 495 * RETURN VALUE: 496 * -EINVAL if the requested state is invalid. 497 * -EIO if device does not support PCI PM or its PM capabilities register has a 498 * wrong version, or device doesn't support the requested state. 499 * 0 if device already is in the requested state. 500 * 0 if device's power state has been successfully changed. 501 */ 502 static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state) 503 { 504 u16 pmcsr; 505 bool need_restore = false; 506 507 /* Check if we're already there */ 508 if (dev->current_state == state) 509 return 0; 510 511 if (!dev->pm_cap) 512 return -EIO; 513 514 if (state < PCI_D0 || state > PCI_D3hot) 515 return -EINVAL; 516 517 /* Validate current state: 518 * Can enter D0 from any state, but if we can only go deeper 519 * to sleep if we're already in a low power state 520 */ 521 if (state != PCI_D0 && dev->current_state <= PCI_D3cold 522 && dev->current_state > state) { 523 dev_err(&dev->dev, "invalid power transition " 524 "(from state %d to %d)\n", dev->current_state, state); 525 return -EINVAL; 526 } 527 528 /* check if this device supports the desired state */ 529 if ((state == PCI_D1 && !dev->d1_support) 530 || (state == PCI_D2 && !dev->d2_support)) 531 return -EIO; 532 533 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); 534 535 /* If we're (effectively) in D3, force entire word to 0. 536 * This doesn't affect PME_Status, disables PME_En, and 537 * sets PowerState to 0. 538 */ 539 switch (dev->current_state) { 540 case PCI_D0: 541 case PCI_D1: 542 case PCI_D2: 543 pmcsr &= ~PCI_PM_CTRL_STATE_MASK; 544 pmcsr |= state; 545 break; 546 case PCI_D3hot: 547 case PCI_D3cold: 548 case PCI_UNKNOWN: /* Boot-up */ 549 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot 550 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET)) 551 need_restore = true; 552 /* Fall-through: force to D0 */ 553 default: 554 pmcsr = 0; 555 break; 556 } 557 558 /* enter specified state */ 559 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); 560 561 /* Mandatory power management transition delays */ 562 /* see PCI PM 1.1 5.6.1 table 18 */ 563 if (state == PCI_D3hot || dev->current_state == PCI_D3hot) 564 pci_dev_d3_sleep(dev); 565 else if (state == PCI_D2 || dev->current_state == PCI_D2) 566 udelay(PCI_PM_D2_DELAY); 567 568 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); 569 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); 570 if (dev->current_state != state && printk_ratelimit()) 571 dev_info(&dev->dev, "Refused to change power state, " 572 "currently in D%d\n", dev->current_state); 573 574 /* 575 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT 576 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning 577 * from D3hot to D0 _may_ perform an internal reset, thereby 578 * going to "D0 Uninitialized" rather than "D0 Initialized". 579 * For example, at least some versions of the 3c905B and the 580 * 3c556B exhibit this behaviour. 581 * 582 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave 583 * devices in a D3hot state at boot. Consequently, we need to 584 * restore at least the BARs so that the device will be 585 * accessible to its driver. 586 */ 587 if (need_restore) 588 pci_restore_bars(dev); 589 590 if (dev->bus->self) 591 pcie_aspm_pm_state_change(dev->bus->self); 592 593 return 0; 594 } 595 596 /** 597 * pci_update_current_state - Read PCI power state of given device from its 598 * PCI PM registers and cache it 599 * @dev: PCI device to handle. 600 * @state: State to cache in case the device doesn't have the PM capability 601 */ 602 void pci_update_current_state(struct pci_dev *dev, pci_power_t state) 603 { 604 if (dev->pm_cap) { 605 u16 pmcsr; 606 607 /* 608 * Configuration space is not accessible for device in 609 * D3cold, so just keep or set D3cold for safety 610 */ 611 if (dev->current_state == PCI_D3cold) 612 return; 613 if (state == PCI_D3cold) { 614 dev->current_state = PCI_D3cold; 615 return; 616 } 617 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); 618 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); 619 } else { 620 dev->current_state = state; 621 } 622 } 623 624 /** 625 * pci_power_up - Put the given device into D0 forcibly 626 * @dev: PCI device to power up 627 */ 628 void pci_power_up(struct pci_dev *dev) 629 { 630 if (platform_pci_power_manageable(dev)) 631 platform_pci_set_power_state(dev, PCI_D0); 632 633 pci_raw_set_power_state(dev, PCI_D0); 634 pci_update_current_state(dev, PCI_D0); 635 } 636 637 /** 638 * pci_platform_power_transition - Use platform to change device power state 639 * @dev: PCI device to handle. 640 * @state: State to put the device into. 641 */ 642 static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state) 643 { 644 int error; 645 646 if (platform_pci_power_manageable(dev)) { 647 error = platform_pci_set_power_state(dev, state); 648 if (!error) 649 pci_update_current_state(dev, state); 650 } else 651 error = -ENODEV; 652 653 if (error && !dev->pm_cap) /* Fall back to PCI_D0 */ 654 dev->current_state = PCI_D0; 655 656 return error; 657 } 658 659 /** 660 * __pci_start_power_transition - Start power transition of a PCI device 661 * @dev: PCI device to handle. 662 * @state: State to put the device into. 663 */ 664 static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state) 665 { 666 if (state == PCI_D0) { 667 pci_platform_power_transition(dev, PCI_D0); 668 /* 669 * Mandatory power management transition delays, see 670 * PCI Express Base Specification Revision 2.0 Section 671 * 6.6.1: Conventional Reset. Do not delay for 672 * devices powered on/off by corresponding bridge, 673 * because have already delayed for the bridge. 674 */ 675 if (dev->runtime_d3cold) { 676 msleep(dev->d3cold_delay); 677 /* 678 * When powering on a bridge from D3cold, the 679 * whole hierarchy may be powered on into 680 * D0uninitialized state, resume them to give 681 * them a chance to suspend again 682 */ 683 pci_wakeup_bus(dev->subordinate); 684 } 685 } 686 } 687 688 /** 689 * __pci_dev_set_current_state - Set current state of a PCI device 690 * @dev: Device to handle 691 * @data: pointer to state to be set 692 */ 693 static int __pci_dev_set_current_state(struct pci_dev *dev, void *data) 694 { 695 pci_power_t state = *(pci_power_t *)data; 696 697 dev->current_state = state; 698 return 0; 699 } 700 701 /** 702 * __pci_bus_set_current_state - Walk given bus and set current state of devices 703 * @bus: Top bus of the subtree to walk. 704 * @state: state to be set 705 */ 706 static void __pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state) 707 { 708 if (bus) 709 pci_walk_bus(bus, __pci_dev_set_current_state, &state); 710 } 711 712 /** 713 * __pci_complete_power_transition - Complete power transition of a PCI device 714 * @dev: PCI device to handle. 715 * @state: State to put the device into. 716 * 717 * This function should not be called directly by device drivers. 718 */ 719 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state) 720 { 721 int ret; 722 723 if (state <= PCI_D0) 724 return -EINVAL; 725 ret = pci_platform_power_transition(dev, state); 726 /* Power off the bridge may power off the whole hierarchy */ 727 if (!ret && state == PCI_D3cold) 728 __pci_bus_set_current_state(dev->subordinate, PCI_D3cold); 729 return ret; 730 } 731 EXPORT_SYMBOL_GPL(__pci_complete_power_transition); 732 733 /** 734 * pci_set_power_state - Set the power state of a PCI device 735 * @dev: PCI device to handle. 736 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into. 737 * 738 * Transition a device to a new power state, using the platform firmware and/or 739 * the device's PCI PM registers. 740 * 741 * RETURN VALUE: 742 * -EINVAL if the requested state is invalid. 743 * -EIO if device does not support PCI PM or its PM capabilities register has a 744 * wrong version, or device doesn't support the requested state. 745 * 0 if device already is in the requested state. 746 * 0 if device's power state has been successfully changed. 747 */ 748 int pci_set_power_state(struct pci_dev *dev, pci_power_t state) 749 { 750 int error; 751 752 /* bound the state we're entering */ 753 if (state > PCI_D3cold) 754 state = PCI_D3cold; 755 else if (state < PCI_D0) 756 state = PCI_D0; 757 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev)) 758 /* 759 * If the device or the parent bridge do not support PCI PM, 760 * ignore the request if we're doing anything other than putting 761 * it into D0 (which would only happen on boot). 762 */ 763 return 0; 764 765 /* Check if we're already there */ 766 if (dev->current_state == state) 767 return 0; 768 769 __pci_start_power_transition(dev, state); 770 771 /* This device is quirked not to be put into D3, so 772 don't put it in D3 */ 773 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3)) 774 return 0; 775 776 /* 777 * To put device in D3cold, we put device into D3hot in native 778 * way, then put device into D3cold with platform ops 779 */ 780 error = pci_raw_set_power_state(dev, state > PCI_D3hot ? 781 PCI_D3hot : state); 782 783 if (!__pci_complete_power_transition(dev, state)) 784 error = 0; 785 /* 786 * When aspm_policy is "powersave" this call ensures 787 * that ASPM is configured. 788 */ 789 if (!error && dev->bus->self) 790 pcie_aspm_powersave_config_link(dev->bus->self); 791 792 return error; 793 } 794 795 /** 796 * pci_choose_state - Choose the power state of a PCI device 797 * @dev: PCI device to be suspended 798 * @state: target sleep state for the whole system. This is the value 799 * that is passed to suspend() function. 800 * 801 * Returns PCI power state suitable for given device and given system 802 * message. 803 */ 804 805 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state) 806 { 807 pci_power_t ret; 808 809 if (!dev->pm_cap) 810 return PCI_D0; 811 812 ret = platform_pci_choose_state(dev); 813 if (ret != PCI_POWER_ERROR) 814 return ret; 815 816 switch (state.event) { 817 case PM_EVENT_ON: 818 return PCI_D0; 819 case PM_EVENT_FREEZE: 820 case PM_EVENT_PRETHAW: 821 /* REVISIT both freeze and pre-thaw "should" use D0 */ 822 case PM_EVENT_SUSPEND: 823 case PM_EVENT_HIBERNATE: 824 return PCI_D3hot; 825 default: 826 dev_info(&dev->dev, "unrecognized suspend event %d\n", 827 state.event); 828 BUG(); 829 } 830 return PCI_D0; 831 } 832 833 EXPORT_SYMBOL(pci_choose_state); 834 835 #define PCI_EXP_SAVE_REGS 7 836 837 838 static struct pci_cap_saved_state *pci_find_saved_cap( 839 struct pci_dev *pci_dev, char cap) 840 { 841 struct pci_cap_saved_state *tmp; 842 843 hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) { 844 if (tmp->cap.cap_nr == cap) 845 return tmp; 846 } 847 return NULL; 848 } 849 850 static int pci_save_pcie_state(struct pci_dev *dev) 851 { 852 int i = 0; 853 struct pci_cap_saved_state *save_state; 854 u16 *cap; 855 856 if (!pci_is_pcie(dev)) 857 return 0; 858 859 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); 860 if (!save_state) { 861 dev_err(&dev->dev, "buffer not found in %s\n", __func__); 862 return -ENOMEM; 863 } 864 865 cap = (u16 *)&save_state->cap.data[0]; 866 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]); 867 pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]); 868 pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]); 869 pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]); 870 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]); 871 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]); 872 pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]); 873 874 return 0; 875 } 876 877 static void pci_restore_pcie_state(struct pci_dev *dev) 878 { 879 int i = 0; 880 struct pci_cap_saved_state *save_state; 881 u16 *cap; 882 883 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); 884 if (!save_state) 885 return; 886 887 cap = (u16 *)&save_state->cap.data[0]; 888 pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]); 889 pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]); 890 pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]); 891 pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]); 892 pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]); 893 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]); 894 pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]); 895 } 896 897 898 static int pci_save_pcix_state(struct pci_dev *dev) 899 { 900 int pos; 901 struct pci_cap_saved_state *save_state; 902 903 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); 904 if (pos <= 0) 905 return 0; 906 907 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); 908 if (!save_state) { 909 dev_err(&dev->dev, "buffer not found in %s\n", __func__); 910 return -ENOMEM; 911 } 912 913 pci_read_config_word(dev, pos + PCI_X_CMD, 914 (u16 *)save_state->cap.data); 915 916 return 0; 917 } 918 919 static void pci_restore_pcix_state(struct pci_dev *dev) 920 { 921 int i = 0, pos; 922 struct pci_cap_saved_state *save_state; 923 u16 *cap; 924 925 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); 926 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); 927 if (!save_state || pos <= 0) 928 return; 929 cap = (u16 *)&save_state->cap.data[0]; 930 931 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]); 932 } 933 934 935 /** 936 * pci_save_state - save the PCI configuration space of a device before suspending 937 * @dev: - PCI device that we're dealing with 938 */ 939 int 940 pci_save_state(struct pci_dev *dev) 941 { 942 int i; 943 /* XXX: 100% dword access ok here? */ 944 for (i = 0; i < 16; i++) 945 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]); 946 dev->state_saved = true; 947 if ((i = pci_save_pcie_state(dev)) != 0) 948 return i; 949 if ((i = pci_save_pcix_state(dev)) != 0) 950 return i; 951 return 0; 952 } 953 954 static void pci_restore_config_dword(struct pci_dev *pdev, int offset, 955 u32 saved_val, int retry) 956 { 957 u32 val; 958 959 pci_read_config_dword(pdev, offset, &val); 960 if (val == saved_val) 961 return; 962 963 for (;;) { 964 dev_dbg(&pdev->dev, "restoring config space at offset " 965 "%#x (was %#x, writing %#x)\n", offset, val, saved_val); 966 pci_write_config_dword(pdev, offset, saved_val); 967 if (retry-- <= 0) 968 return; 969 970 pci_read_config_dword(pdev, offset, &val); 971 if (val == saved_val) 972 return; 973 974 mdelay(1); 975 } 976 } 977 978 static void pci_restore_config_space_range(struct pci_dev *pdev, 979 int start, int end, int retry) 980 { 981 int index; 982 983 for (index = end; index >= start; index--) 984 pci_restore_config_dword(pdev, 4 * index, 985 pdev->saved_config_space[index], 986 retry); 987 } 988 989 static void pci_restore_config_space(struct pci_dev *pdev) 990 { 991 if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) { 992 pci_restore_config_space_range(pdev, 10, 15, 0); 993 /* Restore BARs before the command register. */ 994 pci_restore_config_space_range(pdev, 4, 9, 10); 995 pci_restore_config_space_range(pdev, 0, 3, 0); 996 } else { 997 pci_restore_config_space_range(pdev, 0, 15, 0); 998 } 999 } 1000 1001 /** 1002 * pci_restore_state - Restore the saved state of a PCI device 1003 * @dev: - PCI device that we're dealing with 1004 */ 1005 void pci_restore_state(struct pci_dev *dev) 1006 { 1007 if (!dev->state_saved) 1008 return; 1009 1010 /* PCI Express register must be restored first */ 1011 pci_restore_pcie_state(dev); 1012 pci_restore_ats_state(dev); 1013 1014 pci_restore_config_space(dev); 1015 1016 pci_restore_pcix_state(dev); 1017 pci_restore_msi_state(dev); 1018 pci_restore_iov_state(dev); 1019 1020 dev->state_saved = false; 1021 } 1022 1023 struct pci_saved_state { 1024 u32 config_space[16]; 1025 struct pci_cap_saved_data cap[0]; 1026 }; 1027 1028 /** 1029 * pci_store_saved_state - Allocate and return an opaque struct containing 1030 * the device saved state. 1031 * @dev: PCI device that we're dealing with 1032 * 1033 * Rerturn NULL if no state or error. 1034 */ 1035 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev) 1036 { 1037 struct pci_saved_state *state; 1038 struct pci_cap_saved_state *tmp; 1039 struct pci_cap_saved_data *cap; 1040 size_t size; 1041 1042 if (!dev->state_saved) 1043 return NULL; 1044 1045 size = sizeof(*state) + sizeof(struct pci_cap_saved_data); 1046 1047 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) 1048 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size; 1049 1050 state = kzalloc(size, GFP_KERNEL); 1051 if (!state) 1052 return NULL; 1053 1054 memcpy(state->config_space, dev->saved_config_space, 1055 sizeof(state->config_space)); 1056 1057 cap = state->cap; 1058 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) { 1059 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size; 1060 memcpy(cap, &tmp->cap, len); 1061 cap = (struct pci_cap_saved_data *)((u8 *)cap + len); 1062 } 1063 /* Empty cap_save terminates list */ 1064 1065 return state; 1066 } 1067 EXPORT_SYMBOL_GPL(pci_store_saved_state); 1068 1069 /** 1070 * pci_load_saved_state - Reload the provided save state into struct pci_dev. 1071 * @dev: PCI device that we're dealing with 1072 * @state: Saved state returned from pci_store_saved_state() 1073 */ 1074 int pci_load_saved_state(struct pci_dev *dev, struct pci_saved_state *state) 1075 { 1076 struct pci_cap_saved_data *cap; 1077 1078 dev->state_saved = false; 1079 1080 if (!state) 1081 return 0; 1082 1083 memcpy(dev->saved_config_space, state->config_space, 1084 sizeof(state->config_space)); 1085 1086 cap = state->cap; 1087 while (cap->size) { 1088 struct pci_cap_saved_state *tmp; 1089 1090 tmp = pci_find_saved_cap(dev, cap->cap_nr); 1091 if (!tmp || tmp->cap.size != cap->size) 1092 return -EINVAL; 1093 1094 memcpy(tmp->cap.data, cap->data, tmp->cap.size); 1095 cap = (struct pci_cap_saved_data *)((u8 *)cap + 1096 sizeof(struct pci_cap_saved_data) + cap->size); 1097 } 1098 1099 dev->state_saved = true; 1100 return 0; 1101 } 1102 EXPORT_SYMBOL_GPL(pci_load_saved_state); 1103 1104 /** 1105 * pci_load_and_free_saved_state - Reload the save state pointed to by state, 1106 * and free the memory allocated for it. 1107 * @dev: PCI device that we're dealing with 1108 * @state: Pointer to saved state returned from pci_store_saved_state() 1109 */ 1110 int pci_load_and_free_saved_state(struct pci_dev *dev, 1111 struct pci_saved_state **state) 1112 { 1113 int ret = pci_load_saved_state(dev, *state); 1114 kfree(*state); 1115 *state = NULL; 1116 return ret; 1117 } 1118 EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state); 1119 1120 static int do_pci_enable_device(struct pci_dev *dev, int bars) 1121 { 1122 int err; 1123 1124 err = pci_set_power_state(dev, PCI_D0); 1125 if (err < 0 && err != -EIO) 1126 return err; 1127 err = pcibios_enable_device(dev, bars); 1128 if (err < 0) 1129 return err; 1130 pci_fixup_device(pci_fixup_enable, dev); 1131 1132 return 0; 1133 } 1134 1135 /** 1136 * pci_reenable_device - Resume abandoned device 1137 * @dev: PCI device to be resumed 1138 * 1139 * Note this function is a backend of pci_default_resume and is not supposed 1140 * to be called by normal code, write proper resume handler and use it instead. 1141 */ 1142 int pci_reenable_device(struct pci_dev *dev) 1143 { 1144 if (pci_is_enabled(dev)) 1145 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1); 1146 return 0; 1147 } 1148 1149 static void pci_enable_bridge(struct pci_dev *dev) 1150 { 1151 int retval; 1152 1153 if (!dev) 1154 return; 1155 1156 pci_enable_bridge(dev->bus->self); 1157 1158 if (pci_is_enabled(dev)) { 1159 if (!dev->is_busmaster) { 1160 dev_warn(&dev->dev, "driver skip pci_set_master, fix it!\n"); 1161 pci_set_master(dev); 1162 } 1163 return; 1164 } 1165 1166 retval = pci_enable_device(dev); 1167 if (retval) 1168 dev_err(&dev->dev, "Error enabling bridge (%d), continuing\n", 1169 retval); 1170 pci_set_master(dev); 1171 } 1172 1173 static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags) 1174 { 1175 int err; 1176 int i, bars = 0; 1177 1178 /* 1179 * Power state could be unknown at this point, either due to a fresh 1180 * boot or a device removal call. So get the current power state 1181 * so that things like MSI message writing will behave as expected 1182 * (e.g. if the device really is in D0 at enable time). 1183 */ 1184 if (dev->pm_cap) { 1185 u16 pmcsr; 1186 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); 1187 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); 1188 } 1189 1190 if (atomic_inc_return(&dev->enable_cnt) > 1) 1191 return 0; /* already enabled */ 1192 1193 pci_enable_bridge(dev->bus->self); 1194 1195 /* only skip sriov related */ 1196 for (i = 0; i <= PCI_ROM_RESOURCE; i++) 1197 if (dev->resource[i].flags & flags) 1198 bars |= (1 << i); 1199 for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++) 1200 if (dev->resource[i].flags & flags) 1201 bars |= (1 << i); 1202 1203 err = do_pci_enable_device(dev, bars); 1204 if (err < 0) 1205 atomic_dec(&dev->enable_cnt); 1206 return err; 1207 } 1208 1209 /** 1210 * pci_enable_device_io - Initialize a device for use with IO space 1211 * @dev: PCI device to be initialized 1212 * 1213 * Initialize device before it's used by a driver. Ask low-level code 1214 * to enable I/O resources. Wake up the device if it was suspended. 1215 * Beware, this function can fail. 1216 */ 1217 int pci_enable_device_io(struct pci_dev *dev) 1218 { 1219 return pci_enable_device_flags(dev, IORESOURCE_IO); 1220 } 1221 1222 /** 1223 * pci_enable_device_mem - Initialize a device for use with Memory space 1224 * @dev: PCI device to be initialized 1225 * 1226 * Initialize device before it's used by a driver. Ask low-level code 1227 * to enable Memory resources. Wake up the device if it was suspended. 1228 * Beware, this function can fail. 1229 */ 1230 int pci_enable_device_mem(struct pci_dev *dev) 1231 { 1232 return pci_enable_device_flags(dev, IORESOURCE_MEM); 1233 } 1234 1235 /** 1236 * pci_enable_device - Initialize device before it's used by a driver. 1237 * @dev: PCI device to be initialized 1238 * 1239 * Initialize device before it's used by a driver. Ask low-level code 1240 * to enable I/O and memory. Wake up the device if it was suspended. 1241 * Beware, this function can fail. 1242 * 1243 * Note we don't actually enable the device many times if we call 1244 * this function repeatedly (we just increment the count). 1245 */ 1246 int pci_enable_device(struct pci_dev *dev) 1247 { 1248 return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO); 1249 } 1250 1251 /* 1252 * Managed PCI resources. This manages device on/off, intx/msi/msix 1253 * on/off and BAR regions. pci_dev itself records msi/msix status, so 1254 * there's no need to track it separately. pci_devres is initialized 1255 * when a device is enabled using managed PCI device enable interface. 1256 */ 1257 struct pci_devres { 1258 unsigned int enabled:1; 1259 unsigned int pinned:1; 1260 unsigned int orig_intx:1; 1261 unsigned int restore_intx:1; 1262 u32 region_mask; 1263 }; 1264 1265 static void pcim_release(struct device *gendev, void *res) 1266 { 1267 struct pci_dev *dev = container_of(gendev, struct pci_dev, dev); 1268 struct pci_devres *this = res; 1269 int i; 1270 1271 if (dev->msi_enabled) 1272 pci_disable_msi(dev); 1273 if (dev->msix_enabled) 1274 pci_disable_msix(dev); 1275 1276 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) 1277 if (this->region_mask & (1 << i)) 1278 pci_release_region(dev, i); 1279 1280 if (this->restore_intx) 1281 pci_intx(dev, this->orig_intx); 1282 1283 if (this->enabled && !this->pinned) 1284 pci_disable_device(dev); 1285 } 1286 1287 static struct pci_devres * get_pci_dr(struct pci_dev *pdev) 1288 { 1289 struct pci_devres *dr, *new_dr; 1290 1291 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL); 1292 if (dr) 1293 return dr; 1294 1295 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL); 1296 if (!new_dr) 1297 return NULL; 1298 return devres_get(&pdev->dev, new_dr, NULL, NULL); 1299 } 1300 1301 static struct pci_devres * find_pci_dr(struct pci_dev *pdev) 1302 { 1303 if (pci_is_managed(pdev)) 1304 return devres_find(&pdev->dev, pcim_release, NULL, NULL); 1305 return NULL; 1306 } 1307 1308 /** 1309 * pcim_enable_device - Managed pci_enable_device() 1310 * @pdev: PCI device to be initialized 1311 * 1312 * Managed pci_enable_device(). 1313 */ 1314 int pcim_enable_device(struct pci_dev *pdev) 1315 { 1316 struct pci_devres *dr; 1317 int rc; 1318 1319 dr = get_pci_dr(pdev); 1320 if (unlikely(!dr)) 1321 return -ENOMEM; 1322 if (dr->enabled) 1323 return 0; 1324 1325 rc = pci_enable_device(pdev); 1326 if (!rc) { 1327 pdev->is_managed = 1; 1328 dr->enabled = 1; 1329 } 1330 return rc; 1331 } 1332 1333 /** 1334 * pcim_pin_device - Pin managed PCI device 1335 * @pdev: PCI device to pin 1336 * 1337 * Pin managed PCI device @pdev. Pinned device won't be disabled on 1338 * driver detach. @pdev must have been enabled with 1339 * pcim_enable_device(). 1340 */ 1341 void pcim_pin_device(struct pci_dev *pdev) 1342 { 1343 struct pci_devres *dr; 1344 1345 dr = find_pci_dr(pdev); 1346 WARN_ON(!dr || !dr->enabled); 1347 if (dr) 1348 dr->pinned = 1; 1349 } 1350 1351 /* 1352 * pcibios_add_device - provide arch specific hooks when adding device dev 1353 * @dev: the PCI device being added 1354 * 1355 * Permits the platform to provide architecture specific functionality when 1356 * devices are added. This is the default implementation. Architecture 1357 * implementations can override this. 1358 */ 1359 int __weak pcibios_add_device (struct pci_dev *dev) 1360 { 1361 return 0; 1362 } 1363 1364 /** 1365 * pcibios_release_device - provide arch specific hooks when releasing device dev 1366 * @dev: the PCI device being released 1367 * 1368 * Permits the platform to provide architecture specific functionality when 1369 * devices are released. This is the default implementation. Architecture 1370 * implementations can override this. 1371 */ 1372 void __weak pcibios_release_device(struct pci_dev *dev) {} 1373 1374 /** 1375 * pcibios_disable_device - disable arch specific PCI resources for device dev 1376 * @dev: the PCI device to disable 1377 * 1378 * Disables architecture specific PCI resources for the device. This 1379 * is the default implementation. Architecture implementations can 1380 * override this. 1381 */ 1382 void __weak pcibios_disable_device (struct pci_dev *dev) {} 1383 1384 static void do_pci_disable_device(struct pci_dev *dev) 1385 { 1386 u16 pci_command; 1387 1388 pci_read_config_word(dev, PCI_COMMAND, &pci_command); 1389 if (pci_command & PCI_COMMAND_MASTER) { 1390 pci_command &= ~PCI_COMMAND_MASTER; 1391 pci_write_config_word(dev, PCI_COMMAND, pci_command); 1392 } 1393 1394 pcibios_disable_device(dev); 1395 } 1396 1397 /** 1398 * pci_disable_enabled_device - Disable device without updating enable_cnt 1399 * @dev: PCI device to disable 1400 * 1401 * NOTE: This function is a backend of PCI power management routines and is 1402 * not supposed to be called drivers. 1403 */ 1404 void pci_disable_enabled_device(struct pci_dev *dev) 1405 { 1406 if (pci_is_enabled(dev)) 1407 do_pci_disable_device(dev); 1408 } 1409 1410 /** 1411 * pci_disable_device - Disable PCI device after use 1412 * @dev: PCI device to be disabled 1413 * 1414 * Signal to the system that the PCI device is not in use by the system 1415 * anymore. This only involves disabling PCI bus-mastering, if active. 1416 * 1417 * Note we don't actually disable the device until all callers of 1418 * pci_enable_device() have called pci_disable_device(). 1419 */ 1420 void 1421 pci_disable_device(struct pci_dev *dev) 1422 { 1423 struct pci_devres *dr; 1424 1425 dr = find_pci_dr(dev); 1426 if (dr) 1427 dr->enabled = 0; 1428 1429 dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0, 1430 "disabling already-disabled device"); 1431 1432 if (atomic_dec_return(&dev->enable_cnt) != 0) 1433 return; 1434 1435 do_pci_disable_device(dev); 1436 1437 dev->is_busmaster = 0; 1438 } 1439 1440 /** 1441 * pcibios_set_pcie_reset_state - set reset state for device dev 1442 * @dev: the PCIe device reset 1443 * @state: Reset state to enter into 1444 * 1445 * 1446 * Sets the PCIe reset state for the device. This is the default 1447 * implementation. Architecture implementations can override this. 1448 */ 1449 int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev, 1450 enum pcie_reset_state state) 1451 { 1452 return -EINVAL; 1453 } 1454 1455 /** 1456 * pci_set_pcie_reset_state - set reset state for device dev 1457 * @dev: the PCIe device reset 1458 * @state: Reset state to enter into 1459 * 1460 * 1461 * Sets the PCI reset state for the device. 1462 */ 1463 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state) 1464 { 1465 return pcibios_set_pcie_reset_state(dev, state); 1466 } 1467 1468 /** 1469 * pci_check_pme_status - Check if given device has generated PME. 1470 * @dev: Device to check. 1471 * 1472 * Check the PME status of the device and if set, clear it and clear PME enable 1473 * (if set). Return 'true' if PME status and PME enable were both set or 1474 * 'false' otherwise. 1475 */ 1476 bool pci_check_pme_status(struct pci_dev *dev) 1477 { 1478 int pmcsr_pos; 1479 u16 pmcsr; 1480 bool ret = false; 1481 1482 if (!dev->pm_cap) 1483 return false; 1484 1485 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL; 1486 pci_read_config_word(dev, pmcsr_pos, &pmcsr); 1487 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS)) 1488 return false; 1489 1490 /* Clear PME status. */ 1491 pmcsr |= PCI_PM_CTRL_PME_STATUS; 1492 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) { 1493 /* Disable PME to avoid interrupt flood. */ 1494 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE; 1495 ret = true; 1496 } 1497 1498 pci_write_config_word(dev, pmcsr_pos, pmcsr); 1499 1500 return ret; 1501 } 1502 1503 /** 1504 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set. 1505 * @dev: Device to handle. 1506 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag. 1507 * 1508 * Check if @dev has generated PME and queue a resume request for it in that 1509 * case. 1510 */ 1511 static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset) 1512 { 1513 if (pme_poll_reset && dev->pme_poll) 1514 dev->pme_poll = false; 1515 1516 if (pci_check_pme_status(dev)) { 1517 pci_wakeup_event(dev); 1518 pm_request_resume(&dev->dev); 1519 } 1520 return 0; 1521 } 1522 1523 /** 1524 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary. 1525 * @bus: Top bus of the subtree to walk. 1526 */ 1527 void pci_pme_wakeup_bus(struct pci_bus *bus) 1528 { 1529 if (bus) 1530 pci_walk_bus(bus, pci_pme_wakeup, (void *)true); 1531 } 1532 1533 /** 1534 * pci_wakeup - Wake up a PCI device 1535 * @pci_dev: Device to handle. 1536 * @ign: ignored parameter 1537 */ 1538 static int pci_wakeup(struct pci_dev *pci_dev, void *ign) 1539 { 1540 pci_wakeup_event(pci_dev); 1541 pm_request_resume(&pci_dev->dev); 1542 return 0; 1543 } 1544 1545 /** 1546 * pci_wakeup_bus - Walk given bus and wake up devices on it 1547 * @bus: Top bus of the subtree to walk. 1548 */ 1549 void pci_wakeup_bus(struct pci_bus *bus) 1550 { 1551 if (bus) 1552 pci_walk_bus(bus, pci_wakeup, NULL); 1553 } 1554 1555 /** 1556 * pci_pme_capable - check the capability of PCI device to generate PME# 1557 * @dev: PCI device to handle. 1558 * @state: PCI state from which device will issue PME#. 1559 */ 1560 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state) 1561 { 1562 if (!dev->pm_cap) 1563 return false; 1564 1565 return !!(dev->pme_support & (1 << state)); 1566 } 1567 1568 static void pci_pme_list_scan(struct work_struct *work) 1569 { 1570 struct pci_pme_device *pme_dev, *n; 1571 1572 mutex_lock(&pci_pme_list_mutex); 1573 if (!list_empty(&pci_pme_list)) { 1574 list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) { 1575 if (pme_dev->dev->pme_poll) { 1576 struct pci_dev *bridge; 1577 1578 bridge = pme_dev->dev->bus->self; 1579 /* 1580 * If bridge is in low power state, the 1581 * configuration space of subordinate devices 1582 * may be not accessible 1583 */ 1584 if (bridge && bridge->current_state != PCI_D0) 1585 continue; 1586 pci_pme_wakeup(pme_dev->dev, NULL); 1587 } else { 1588 list_del(&pme_dev->list); 1589 kfree(pme_dev); 1590 } 1591 } 1592 if (!list_empty(&pci_pme_list)) 1593 schedule_delayed_work(&pci_pme_work, 1594 msecs_to_jiffies(PME_TIMEOUT)); 1595 } 1596 mutex_unlock(&pci_pme_list_mutex); 1597 } 1598 1599 /** 1600 * pci_pme_active - enable or disable PCI device's PME# function 1601 * @dev: PCI device to handle. 1602 * @enable: 'true' to enable PME# generation; 'false' to disable it. 1603 * 1604 * The caller must verify that the device is capable of generating PME# before 1605 * calling this function with @enable equal to 'true'. 1606 */ 1607 void pci_pme_active(struct pci_dev *dev, bool enable) 1608 { 1609 u16 pmcsr; 1610 1611 if (!dev->pme_support) 1612 return; 1613 1614 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); 1615 /* Clear PME_Status by writing 1 to it and enable PME# */ 1616 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE; 1617 if (!enable) 1618 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE; 1619 1620 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); 1621 1622 /* 1623 * PCI (as opposed to PCIe) PME requires that the device have 1624 * its PME# line hooked up correctly. Not all hardware vendors 1625 * do this, so the PME never gets delivered and the device 1626 * remains asleep. The easiest way around this is to 1627 * periodically walk the list of suspended devices and check 1628 * whether any have their PME flag set. The assumption is that 1629 * we'll wake up often enough anyway that this won't be a huge 1630 * hit, and the power savings from the devices will still be a 1631 * win. 1632 * 1633 * Although PCIe uses in-band PME message instead of PME# line 1634 * to report PME, PME does not work for some PCIe devices in 1635 * reality. For example, there are devices that set their PME 1636 * status bits, but don't really bother to send a PME message; 1637 * there are PCI Express Root Ports that don't bother to 1638 * trigger interrupts when they receive PME messages from the 1639 * devices below. So PME poll is used for PCIe devices too. 1640 */ 1641 1642 if (dev->pme_poll) { 1643 struct pci_pme_device *pme_dev; 1644 if (enable) { 1645 pme_dev = kmalloc(sizeof(struct pci_pme_device), 1646 GFP_KERNEL); 1647 if (!pme_dev) 1648 goto out; 1649 pme_dev->dev = dev; 1650 mutex_lock(&pci_pme_list_mutex); 1651 list_add(&pme_dev->list, &pci_pme_list); 1652 if (list_is_singular(&pci_pme_list)) 1653 schedule_delayed_work(&pci_pme_work, 1654 msecs_to_jiffies(PME_TIMEOUT)); 1655 mutex_unlock(&pci_pme_list_mutex); 1656 } else { 1657 mutex_lock(&pci_pme_list_mutex); 1658 list_for_each_entry(pme_dev, &pci_pme_list, list) { 1659 if (pme_dev->dev == dev) { 1660 list_del(&pme_dev->list); 1661 kfree(pme_dev); 1662 break; 1663 } 1664 } 1665 mutex_unlock(&pci_pme_list_mutex); 1666 } 1667 } 1668 1669 out: 1670 dev_dbg(&dev->dev, "PME# %s\n", enable ? "enabled" : "disabled"); 1671 } 1672 1673 /** 1674 * __pci_enable_wake - enable PCI device as wakeup event source 1675 * @dev: PCI device affected 1676 * @state: PCI state from which device will issue wakeup events 1677 * @runtime: True if the events are to be generated at run time 1678 * @enable: True to enable event generation; false to disable 1679 * 1680 * This enables the device as a wakeup event source, or disables it. 1681 * When such events involves platform-specific hooks, those hooks are 1682 * called automatically by this routine. 1683 * 1684 * Devices with legacy power management (no standard PCI PM capabilities) 1685 * always require such platform hooks. 1686 * 1687 * RETURN VALUE: 1688 * 0 is returned on success 1689 * -EINVAL is returned if device is not supposed to wake up the system 1690 * Error code depending on the platform is returned if both the platform and 1691 * the native mechanism fail to enable the generation of wake-up events 1692 */ 1693 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, 1694 bool runtime, bool enable) 1695 { 1696 int ret = 0; 1697 1698 if (enable && !runtime && !device_may_wakeup(&dev->dev)) 1699 return -EINVAL; 1700 1701 /* Don't do the same thing twice in a row for one device. */ 1702 if (!!enable == !!dev->wakeup_prepared) 1703 return 0; 1704 1705 /* 1706 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don 1707 * Anderson we should be doing PME# wake enable followed by ACPI wake 1708 * enable. To disable wake-up we call the platform first, for symmetry. 1709 */ 1710 1711 if (enable) { 1712 int error; 1713 1714 if (pci_pme_capable(dev, state)) 1715 pci_pme_active(dev, true); 1716 else 1717 ret = 1; 1718 error = runtime ? platform_pci_run_wake(dev, true) : 1719 platform_pci_sleep_wake(dev, true); 1720 if (ret) 1721 ret = error; 1722 if (!ret) 1723 dev->wakeup_prepared = true; 1724 } else { 1725 if (runtime) 1726 platform_pci_run_wake(dev, false); 1727 else 1728 platform_pci_sleep_wake(dev, false); 1729 pci_pme_active(dev, false); 1730 dev->wakeup_prepared = false; 1731 } 1732 1733 return ret; 1734 } 1735 EXPORT_SYMBOL(__pci_enable_wake); 1736 1737 /** 1738 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold 1739 * @dev: PCI device to prepare 1740 * @enable: True to enable wake-up event generation; false to disable 1741 * 1742 * Many drivers want the device to wake up the system from D3_hot or D3_cold 1743 * and this function allows them to set that up cleanly - pci_enable_wake() 1744 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI 1745 * ordering constraints. 1746 * 1747 * This function only returns error code if the device is not capable of 1748 * generating PME# from both D3_hot and D3_cold, and the platform is unable to 1749 * enable wake-up power for it. 1750 */ 1751 int pci_wake_from_d3(struct pci_dev *dev, bool enable) 1752 { 1753 return pci_pme_capable(dev, PCI_D3cold) ? 1754 pci_enable_wake(dev, PCI_D3cold, enable) : 1755 pci_enable_wake(dev, PCI_D3hot, enable); 1756 } 1757 1758 /** 1759 * pci_target_state - find an appropriate low power state for a given PCI dev 1760 * @dev: PCI device 1761 * 1762 * Use underlying platform code to find a supported low power state for @dev. 1763 * If the platform can't manage @dev, return the deepest state from which it 1764 * can generate wake events, based on any available PME info. 1765 */ 1766 pci_power_t pci_target_state(struct pci_dev *dev) 1767 { 1768 pci_power_t target_state = PCI_D3hot; 1769 1770 if (platform_pci_power_manageable(dev)) { 1771 /* 1772 * Call the platform to choose the target state of the device 1773 * and enable wake-up from this state if supported. 1774 */ 1775 pci_power_t state = platform_pci_choose_state(dev); 1776 1777 switch (state) { 1778 case PCI_POWER_ERROR: 1779 case PCI_UNKNOWN: 1780 break; 1781 case PCI_D1: 1782 case PCI_D2: 1783 if (pci_no_d1d2(dev)) 1784 break; 1785 default: 1786 target_state = state; 1787 } 1788 } else if (!dev->pm_cap) { 1789 target_state = PCI_D0; 1790 } else if (device_may_wakeup(&dev->dev)) { 1791 /* 1792 * Find the deepest state from which the device can generate 1793 * wake-up events, make it the target state and enable device 1794 * to generate PME#. 1795 */ 1796 if (dev->pme_support) { 1797 while (target_state 1798 && !(dev->pme_support & (1 << target_state))) 1799 target_state--; 1800 } 1801 } 1802 1803 return target_state; 1804 } 1805 1806 /** 1807 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state 1808 * @dev: Device to handle. 1809 * 1810 * Choose the power state appropriate for the device depending on whether 1811 * it can wake up the system and/or is power manageable by the platform 1812 * (PCI_D3hot is the default) and put the device into that state. 1813 */ 1814 int pci_prepare_to_sleep(struct pci_dev *dev) 1815 { 1816 pci_power_t target_state = pci_target_state(dev); 1817 int error; 1818 1819 if (target_state == PCI_POWER_ERROR) 1820 return -EIO; 1821 1822 /* D3cold during system suspend/hibernate is not supported */ 1823 if (target_state > PCI_D3hot) 1824 target_state = PCI_D3hot; 1825 1826 pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev)); 1827 1828 error = pci_set_power_state(dev, target_state); 1829 1830 if (error) 1831 pci_enable_wake(dev, target_state, false); 1832 1833 return error; 1834 } 1835 1836 /** 1837 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state 1838 * @dev: Device to handle. 1839 * 1840 * Disable device's system wake-up capability and put it into D0. 1841 */ 1842 int pci_back_from_sleep(struct pci_dev *dev) 1843 { 1844 pci_enable_wake(dev, PCI_D0, false); 1845 return pci_set_power_state(dev, PCI_D0); 1846 } 1847 1848 /** 1849 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend. 1850 * @dev: PCI device being suspended. 1851 * 1852 * Prepare @dev to generate wake-up events at run time and put it into a low 1853 * power state. 1854 */ 1855 int pci_finish_runtime_suspend(struct pci_dev *dev) 1856 { 1857 pci_power_t target_state = pci_target_state(dev); 1858 int error; 1859 1860 if (target_state == PCI_POWER_ERROR) 1861 return -EIO; 1862 1863 dev->runtime_d3cold = target_state == PCI_D3cold; 1864 1865 __pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev)); 1866 1867 error = pci_set_power_state(dev, target_state); 1868 1869 if (error) { 1870 __pci_enable_wake(dev, target_state, true, false); 1871 dev->runtime_d3cold = false; 1872 } 1873 1874 return error; 1875 } 1876 1877 /** 1878 * pci_dev_run_wake - Check if device can generate run-time wake-up events. 1879 * @dev: Device to check. 1880 * 1881 * Return true if the device itself is cabable of generating wake-up events 1882 * (through the platform or using the native PCIe PME) or if the device supports 1883 * PME and one of its upstream bridges can generate wake-up events. 1884 */ 1885 bool pci_dev_run_wake(struct pci_dev *dev) 1886 { 1887 struct pci_bus *bus = dev->bus; 1888 1889 if (device_run_wake(&dev->dev)) 1890 return true; 1891 1892 if (!dev->pme_support) 1893 return false; 1894 1895 while (bus->parent) { 1896 struct pci_dev *bridge = bus->self; 1897 1898 if (device_run_wake(&bridge->dev)) 1899 return true; 1900 1901 bus = bus->parent; 1902 } 1903 1904 /* We have reached the root bus. */ 1905 if (bus->bridge) 1906 return device_run_wake(bus->bridge); 1907 1908 return false; 1909 } 1910 EXPORT_SYMBOL_GPL(pci_dev_run_wake); 1911 1912 void pci_config_pm_runtime_get(struct pci_dev *pdev) 1913 { 1914 struct device *dev = &pdev->dev; 1915 struct device *parent = dev->parent; 1916 1917 if (parent) 1918 pm_runtime_get_sync(parent); 1919 pm_runtime_get_noresume(dev); 1920 /* 1921 * pdev->current_state is set to PCI_D3cold during suspending, 1922 * so wait until suspending completes 1923 */ 1924 pm_runtime_barrier(dev); 1925 /* 1926 * Only need to resume devices in D3cold, because config 1927 * registers are still accessible for devices suspended but 1928 * not in D3cold. 1929 */ 1930 if (pdev->current_state == PCI_D3cold) 1931 pm_runtime_resume(dev); 1932 } 1933 1934 void pci_config_pm_runtime_put(struct pci_dev *pdev) 1935 { 1936 struct device *dev = &pdev->dev; 1937 struct device *parent = dev->parent; 1938 1939 pm_runtime_put(dev); 1940 if (parent) 1941 pm_runtime_put_sync(parent); 1942 } 1943 1944 /** 1945 * pci_pm_init - Initialize PM functions of given PCI device 1946 * @dev: PCI device to handle. 1947 */ 1948 void pci_pm_init(struct pci_dev *dev) 1949 { 1950 int pm; 1951 u16 pmc; 1952 1953 pm_runtime_forbid(&dev->dev); 1954 pm_runtime_set_active(&dev->dev); 1955 pm_runtime_enable(&dev->dev); 1956 device_enable_async_suspend(&dev->dev); 1957 dev->wakeup_prepared = false; 1958 1959 dev->pm_cap = 0; 1960 dev->pme_support = 0; 1961 1962 /* find PCI PM capability in list */ 1963 pm = pci_find_capability(dev, PCI_CAP_ID_PM); 1964 if (!pm) 1965 return; 1966 /* Check device's ability to generate PME# */ 1967 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc); 1968 1969 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) { 1970 dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n", 1971 pmc & PCI_PM_CAP_VER_MASK); 1972 return; 1973 } 1974 1975 dev->pm_cap = pm; 1976 dev->d3_delay = PCI_PM_D3_WAIT; 1977 dev->d3cold_delay = PCI_PM_D3COLD_WAIT; 1978 dev->d3cold_allowed = true; 1979 1980 dev->d1_support = false; 1981 dev->d2_support = false; 1982 if (!pci_no_d1d2(dev)) { 1983 if (pmc & PCI_PM_CAP_D1) 1984 dev->d1_support = true; 1985 if (pmc & PCI_PM_CAP_D2) 1986 dev->d2_support = true; 1987 1988 if (dev->d1_support || dev->d2_support) 1989 dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n", 1990 dev->d1_support ? " D1" : "", 1991 dev->d2_support ? " D2" : ""); 1992 } 1993 1994 pmc &= PCI_PM_CAP_PME_MASK; 1995 if (pmc) { 1996 dev_printk(KERN_DEBUG, &dev->dev, 1997 "PME# supported from%s%s%s%s%s\n", 1998 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "", 1999 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "", 2000 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "", 2001 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "", 2002 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : ""); 2003 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT; 2004 dev->pme_poll = true; 2005 /* 2006 * Make device's PM flags reflect the wake-up capability, but 2007 * let the user space enable it to wake up the system as needed. 2008 */ 2009 device_set_wakeup_capable(&dev->dev, true); 2010 /* Disable the PME# generation functionality */ 2011 pci_pme_active(dev, false); 2012 } 2013 } 2014 2015 static void pci_add_saved_cap(struct pci_dev *pci_dev, 2016 struct pci_cap_saved_state *new_cap) 2017 { 2018 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space); 2019 } 2020 2021 /** 2022 * pci_add_cap_save_buffer - allocate buffer for saving given capability registers 2023 * @dev: the PCI device 2024 * @cap: the capability to allocate the buffer for 2025 * @size: requested size of the buffer 2026 */ 2027 static int pci_add_cap_save_buffer( 2028 struct pci_dev *dev, char cap, unsigned int size) 2029 { 2030 int pos; 2031 struct pci_cap_saved_state *save_state; 2032 2033 pos = pci_find_capability(dev, cap); 2034 if (pos <= 0) 2035 return 0; 2036 2037 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL); 2038 if (!save_state) 2039 return -ENOMEM; 2040 2041 save_state->cap.cap_nr = cap; 2042 save_state->cap.size = size; 2043 pci_add_saved_cap(dev, save_state); 2044 2045 return 0; 2046 } 2047 2048 /** 2049 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities 2050 * @dev: the PCI device 2051 */ 2052 void pci_allocate_cap_save_buffers(struct pci_dev *dev) 2053 { 2054 int error; 2055 2056 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP, 2057 PCI_EXP_SAVE_REGS * sizeof(u16)); 2058 if (error) 2059 dev_err(&dev->dev, 2060 "unable to preallocate PCI Express save buffer\n"); 2061 2062 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16)); 2063 if (error) 2064 dev_err(&dev->dev, 2065 "unable to preallocate PCI-X save buffer\n"); 2066 } 2067 2068 void pci_free_cap_save_buffers(struct pci_dev *dev) 2069 { 2070 struct pci_cap_saved_state *tmp; 2071 struct hlist_node *n; 2072 2073 hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next) 2074 kfree(tmp); 2075 } 2076 2077 /** 2078 * pci_configure_ari - enable or disable ARI forwarding 2079 * @dev: the PCI device 2080 * 2081 * If @dev and its upstream bridge both support ARI, enable ARI in the 2082 * bridge. Otherwise, disable ARI in the bridge. 2083 */ 2084 void pci_configure_ari(struct pci_dev *dev) 2085 { 2086 u32 cap; 2087 struct pci_dev *bridge; 2088 2089 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn) 2090 return; 2091 2092 bridge = dev->bus->self; 2093 if (!bridge) 2094 return; 2095 2096 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap); 2097 if (!(cap & PCI_EXP_DEVCAP2_ARI)) 2098 return; 2099 2100 if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) { 2101 pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2, 2102 PCI_EXP_DEVCTL2_ARI); 2103 bridge->ari_enabled = 1; 2104 } else { 2105 pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2, 2106 PCI_EXP_DEVCTL2_ARI); 2107 bridge->ari_enabled = 0; 2108 } 2109 } 2110 2111 /** 2112 * pci_enable_ido - enable ID-based Ordering on a device 2113 * @dev: the PCI device 2114 * @type: which types of IDO to enable 2115 * 2116 * Enable ID-based ordering on @dev. @type can contain the bits 2117 * %PCI_EXP_IDO_REQUEST and/or %PCI_EXP_IDO_COMPLETION to indicate 2118 * which types of transactions are allowed to be re-ordered. 2119 */ 2120 void pci_enable_ido(struct pci_dev *dev, unsigned long type) 2121 { 2122 u16 ctrl = 0; 2123 2124 if (type & PCI_EXP_IDO_REQUEST) 2125 ctrl |= PCI_EXP_DEVCTL2_IDO_REQ_EN; 2126 if (type & PCI_EXP_IDO_COMPLETION) 2127 ctrl |= PCI_EXP_DEVCTL2_IDO_CMP_EN; 2128 if (ctrl) 2129 pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, ctrl); 2130 } 2131 EXPORT_SYMBOL(pci_enable_ido); 2132 2133 /** 2134 * pci_disable_ido - disable ID-based ordering on a device 2135 * @dev: the PCI device 2136 * @type: which types of IDO to disable 2137 */ 2138 void pci_disable_ido(struct pci_dev *dev, unsigned long type) 2139 { 2140 u16 ctrl = 0; 2141 2142 if (type & PCI_EXP_IDO_REQUEST) 2143 ctrl |= PCI_EXP_DEVCTL2_IDO_REQ_EN; 2144 if (type & PCI_EXP_IDO_COMPLETION) 2145 ctrl |= PCI_EXP_DEVCTL2_IDO_CMP_EN; 2146 if (ctrl) 2147 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2, ctrl); 2148 } 2149 EXPORT_SYMBOL(pci_disable_ido); 2150 2151 /** 2152 * pci_enable_obff - enable optimized buffer flush/fill 2153 * @dev: PCI device 2154 * @type: type of signaling to use 2155 * 2156 * Try to enable @type OBFF signaling on @dev. It will try using WAKE# 2157 * signaling if possible, falling back to message signaling only if 2158 * WAKE# isn't supported. @type should indicate whether the PCIe link 2159 * be brought out of L0s or L1 to send the message. It should be either 2160 * %PCI_EXP_OBFF_SIGNAL_ALWAYS or %PCI_OBFF_SIGNAL_L0. 2161 * 2162 * If your device can benefit from receiving all messages, even at the 2163 * power cost of bringing the link back up from a low power state, use 2164 * %PCI_EXP_OBFF_SIGNAL_ALWAYS. Otherwise, use %PCI_OBFF_SIGNAL_L0 (the 2165 * preferred type). 2166 * 2167 * RETURNS: 2168 * Zero on success, appropriate error number on failure. 2169 */ 2170 int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type type) 2171 { 2172 u32 cap; 2173 u16 ctrl; 2174 int ret; 2175 2176 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap); 2177 if (!(cap & PCI_EXP_DEVCAP2_OBFF_MASK)) 2178 return -ENOTSUPP; /* no OBFF support at all */ 2179 2180 /* Make sure the topology supports OBFF as well */ 2181 if (dev->bus->self) { 2182 ret = pci_enable_obff(dev->bus->self, type); 2183 if (ret) 2184 return ret; 2185 } 2186 2187 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &ctrl); 2188 if (cap & PCI_EXP_DEVCAP2_OBFF_WAKE) 2189 ctrl |= PCI_EXP_DEVCTL2_OBFF_WAKE_EN; 2190 else { 2191 switch (type) { 2192 case PCI_EXP_OBFF_SIGNAL_L0: 2193 if (!(ctrl & PCI_EXP_DEVCTL2_OBFF_WAKE_EN)) 2194 ctrl |= PCI_EXP_DEVCTL2_OBFF_MSGA_EN; 2195 break; 2196 case PCI_EXP_OBFF_SIGNAL_ALWAYS: 2197 ctrl &= ~PCI_EXP_DEVCTL2_OBFF_WAKE_EN; 2198 ctrl |= PCI_EXP_DEVCTL2_OBFF_MSGB_EN; 2199 break; 2200 default: 2201 WARN(1, "bad OBFF signal type\n"); 2202 return -ENOTSUPP; 2203 } 2204 } 2205 pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, ctrl); 2206 2207 return 0; 2208 } 2209 EXPORT_SYMBOL(pci_enable_obff); 2210 2211 /** 2212 * pci_disable_obff - disable optimized buffer flush/fill 2213 * @dev: PCI device 2214 * 2215 * Disable OBFF on @dev. 2216 */ 2217 void pci_disable_obff(struct pci_dev *dev) 2218 { 2219 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2, 2220 PCI_EXP_DEVCTL2_OBFF_WAKE_EN); 2221 } 2222 EXPORT_SYMBOL(pci_disable_obff); 2223 2224 /** 2225 * pci_ltr_supported - check whether a device supports LTR 2226 * @dev: PCI device 2227 * 2228 * RETURNS: 2229 * True if @dev supports latency tolerance reporting, false otherwise. 2230 */ 2231 static bool pci_ltr_supported(struct pci_dev *dev) 2232 { 2233 u32 cap; 2234 2235 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap); 2236 2237 return cap & PCI_EXP_DEVCAP2_LTR; 2238 } 2239 2240 /** 2241 * pci_enable_ltr - enable latency tolerance reporting 2242 * @dev: PCI device 2243 * 2244 * Enable LTR on @dev if possible, which means enabling it first on 2245 * upstream ports. 2246 * 2247 * RETURNS: 2248 * Zero on success, errno on failure. 2249 */ 2250 int pci_enable_ltr(struct pci_dev *dev) 2251 { 2252 int ret; 2253 2254 /* Only primary function can enable/disable LTR */ 2255 if (PCI_FUNC(dev->devfn) != 0) 2256 return -EINVAL; 2257 2258 if (!pci_ltr_supported(dev)) 2259 return -ENOTSUPP; 2260 2261 /* Enable upstream ports first */ 2262 if (dev->bus->self) { 2263 ret = pci_enable_ltr(dev->bus->self); 2264 if (ret) 2265 return ret; 2266 } 2267 2268 return pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, 2269 PCI_EXP_DEVCTL2_LTR_EN); 2270 } 2271 EXPORT_SYMBOL(pci_enable_ltr); 2272 2273 /** 2274 * pci_disable_ltr - disable latency tolerance reporting 2275 * @dev: PCI device 2276 */ 2277 void pci_disable_ltr(struct pci_dev *dev) 2278 { 2279 /* Only primary function can enable/disable LTR */ 2280 if (PCI_FUNC(dev->devfn) != 0) 2281 return; 2282 2283 if (!pci_ltr_supported(dev)) 2284 return; 2285 2286 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2, 2287 PCI_EXP_DEVCTL2_LTR_EN); 2288 } 2289 EXPORT_SYMBOL(pci_disable_ltr); 2290 2291 static int __pci_ltr_scale(int *val) 2292 { 2293 int scale = 0; 2294 2295 while (*val > 1023) { 2296 *val = (*val + 31) / 32; 2297 scale++; 2298 } 2299 return scale; 2300 } 2301 2302 /** 2303 * pci_set_ltr - set LTR latency values 2304 * @dev: PCI device 2305 * @snoop_lat_ns: snoop latency in nanoseconds 2306 * @nosnoop_lat_ns: nosnoop latency in nanoseconds 2307 * 2308 * Figure out the scale and set the LTR values accordingly. 2309 */ 2310 int pci_set_ltr(struct pci_dev *dev, int snoop_lat_ns, int nosnoop_lat_ns) 2311 { 2312 int pos, ret, snoop_scale, nosnoop_scale; 2313 u16 val; 2314 2315 if (!pci_ltr_supported(dev)) 2316 return -ENOTSUPP; 2317 2318 snoop_scale = __pci_ltr_scale(&snoop_lat_ns); 2319 nosnoop_scale = __pci_ltr_scale(&nosnoop_lat_ns); 2320 2321 if (snoop_lat_ns > PCI_LTR_VALUE_MASK || 2322 nosnoop_lat_ns > PCI_LTR_VALUE_MASK) 2323 return -EINVAL; 2324 2325 if ((snoop_scale > (PCI_LTR_SCALE_MASK >> PCI_LTR_SCALE_SHIFT)) || 2326 (nosnoop_scale > (PCI_LTR_SCALE_MASK >> PCI_LTR_SCALE_SHIFT))) 2327 return -EINVAL; 2328 2329 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR); 2330 if (!pos) 2331 return -ENOTSUPP; 2332 2333 val = (snoop_scale << PCI_LTR_SCALE_SHIFT) | snoop_lat_ns; 2334 ret = pci_write_config_word(dev, pos + PCI_LTR_MAX_SNOOP_LAT, val); 2335 if (ret != 4) 2336 return -EIO; 2337 2338 val = (nosnoop_scale << PCI_LTR_SCALE_SHIFT) | nosnoop_lat_ns; 2339 ret = pci_write_config_word(dev, pos + PCI_LTR_MAX_NOSNOOP_LAT, val); 2340 if (ret != 4) 2341 return -EIO; 2342 2343 return 0; 2344 } 2345 EXPORT_SYMBOL(pci_set_ltr); 2346 2347 static int pci_acs_enable; 2348 2349 /** 2350 * pci_request_acs - ask for ACS to be enabled if supported 2351 */ 2352 void pci_request_acs(void) 2353 { 2354 pci_acs_enable = 1; 2355 } 2356 2357 /** 2358 * pci_enable_acs - enable ACS if hardware support it 2359 * @dev: the PCI device 2360 */ 2361 void pci_enable_acs(struct pci_dev *dev) 2362 { 2363 int pos; 2364 u16 cap; 2365 u16 ctrl; 2366 2367 if (!pci_acs_enable) 2368 return; 2369 2370 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS); 2371 if (!pos) 2372 return; 2373 2374 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap); 2375 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl); 2376 2377 /* Source Validation */ 2378 ctrl |= (cap & PCI_ACS_SV); 2379 2380 /* P2P Request Redirect */ 2381 ctrl |= (cap & PCI_ACS_RR); 2382 2383 /* P2P Completion Redirect */ 2384 ctrl |= (cap & PCI_ACS_CR); 2385 2386 /* Upstream Forwarding */ 2387 ctrl |= (cap & PCI_ACS_UF); 2388 2389 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl); 2390 } 2391 2392 static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags) 2393 { 2394 int pos; 2395 u16 cap, ctrl; 2396 2397 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ACS); 2398 if (!pos) 2399 return false; 2400 2401 /* 2402 * Except for egress control, capabilities are either required 2403 * or only required if controllable. Features missing from the 2404 * capability field can therefore be assumed as hard-wired enabled. 2405 */ 2406 pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap); 2407 acs_flags &= (cap | PCI_ACS_EC); 2408 2409 pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl); 2410 return (ctrl & acs_flags) == acs_flags; 2411 } 2412 2413 /** 2414 * pci_acs_enabled - test ACS against required flags for a given device 2415 * @pdev: device to test 2416 * @acs_flags: required PCI ACS flags 2417 * 2418 * Return true if the device supports the provided flags. Automatically 2419 * filters out flags that are not implemented on multifunction devices. 2420 * 2421 * Note that this interface checks the effective ACS capabilities of the 2422 * device rather than the actual capabilities. For instance, most single 2423 * function endpoints are not required to support ACS because they have no 2424 * opportunity for peer-to-peer access. We therefore return 'true' 2425 * regardless of whether the device exposes an ACS capability. This makes 2426 * it much easier for callers of this function to ignore the actual type 2427 * or topology of the device when testing ACS support. 2428 */ 2429 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags) 2430 { 2431 int ret; 2432 2433 ret = pci_dev_specific_acs_enabled(pdev, acs_flags); 2434 if (ret >= 0) 2435 return ret > 0; 2436 2437 /* 2438 * Conventional PCI and PCI-X devices never support ACS, either 2439 * effectively or actually. The shared bus topology implies that 2440 * any device on the bus can receive or snoop DMA. 2441 */ 2442 if (!pci_is_pcie(pdev)) 2443 return false; 2444 2445 switch (pci_pcie_type(pdev)) { 2446 /* 2447 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec, 2448 * but since their primary inteface is PCI/X, we conservatively 2449 * handle them as we would a non-PCIe device. 2450 */ 2451 case PCI_EXP_TYPE_PCIE_BRIDGE: 2452 /* 2453 * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never 2454 * applicable... must never implement an ACS Extended Capability...". 2455 * This seems arbitrary, but we take a conservative interpretation 2456 * of this statement. 2457 */ 2458 case PCI_EXP_TYPE_PCI_BRIDGE: 2459 case PCI_EXP_TYPE_RC_EC: 2460 return false; 2461 /* 2462 * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should 2463 * implement ACS in order to indicate their peer-to-peer capabilities, 2464 * regardless of whether they are single- or multi-function devices. 2465 */ 2466 case PCI_EXP_TYPE_DOWNSTREAM: 2467 case PCI_EXP_TYPE_ROOT_PORT: 2468 return pci_acs_flags_enabled(pdev, acs_flags); 2469 /* 2470 * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be 2471 * implemented by the remaining PCIe types to indicate peer-to-peer 2472 * capabilities, but only when they are part of a multifunciton 2473 * device. The footnote for section 6.12 indicates the specific 2474 * PCIe types included here. 2475 */ 2476 case PCI_EXP_TYPE_ENDPOINT: 2477 case PCI_EXP_TYPE_UPSTREAM: 2478 case PCI_EXP_TYPE_LEG_END: 2479 case PCI_EXP_TYPE_RC_END: 2480 if (!pdev->multifunction) 2481 break; 2482 2483 return pci_acs_flags_enabled(pdev, acs_flags); 2484 } 2485 2486 /* 2487 * PCIe 3.0, 6.12.1.3 specifies no ACS capabilties are applicable 2488 * to single function devices with the exception of downstream ports. 2489 */ 2490 return true; 2491 } 2492 2493 /** 2494 * pci_acs_path_enable - test ACS flags from start to end in a hierarchy 2495 * @start: starting downstream device 2496 * @end: ending upstream device or NULL to search to the root bus 2497 * @acs_flags: required flags 2498 * 2499 * Walk up a device tree from start to end testing PCI ACS support. If 2500 * any step along the way does not support the required flags, return false. 2501 */ 2502 bool pci_acs_path_enabled(struct pci_dev *start, 2503 struct pci_dev *end, u16 acs_flags) 2504 { 2505 struct pci_dev *pdev, *parent = start; 2506 2507 do { 2508 pdev = parent; 2509 2510 if (!pci_acs_enabled(pdev, acs_flags)) 2511 return false; 2512 2513 if (pci_is_root_bus(pdev->bus)) 2514 return (end == NULL); 2515 2516 parent = pdev->bus->self; 2517 } while (pdev != end); 2518 2519 return true; 2520 } 2521 2522 /** 2523 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge 2524 * @dev: the PCI device 2525 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD) 2526 * 2527 * Perform INTx swizzling for a device behind one level of bridge. This is 2528 * required by section 9.1 of the PCI-to-PCI bridge specification for devices 2529 * behind bridges on add-in cards. For devices with ARI enabled, the slot 2530 * number is always 0 (see the Implementation Note in section 2.2.8.1 of 2531 * the PCI Express Base Specification, Revision 2.1) 2532 */ 2533 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin) 2534 { 2535 int slot; 2536 2537 if (pci_ari_enabled(dev->bus)) 2538 slot = 0; 2539 else 2540 slot = PCI_SLOT(dev->devfn); 2541 2542 return (((pin - 1) + slot) % 4) + 1; 2543 } 2544 2545 int 2546 pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge) 2547 { 2548 u8 pin; 2549 2550 pin = dev->pin; 2551 if (!pin) 2552 return -1; 2553 2554 while (!pci_is_root_bus(dev->bus)) { 2555 pin = pci_swizzle_interrupt_pin(dev, pin); 2556 dev = dev->bus->self; 2557 } 2558 *bridge = dev; 2559 return pin; 2560 } 2561 2562 /** 2563 * pci_common_swizzle - swizzle INTx all the way to root bridge 2564 * @dev: the PCI device 2565 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD) 2566 * 2567 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI 2568 * bridges all the way up to a PCI root bus. 2569 */ 2570 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp) 2571 { 2572 u8 pin = *pinp; 2573 2574 while (!pci_is_root_bus(dev->bus)) { 2575 pin = pci_swizzle_interrupt_pin(dev, pin); 2576 dev = dev->bus->self; 2577 } 2578 *pinp = pin; 2579 return PCI_SLOT(dev->devfn); 2580 } 2581 2582 /** 2583 * pci_release_region - Release a PCI bar 2584 * @pdev: PCI device whose resources were previously reserved by pci_request_region 2585 * @bar: BAR to release 2586 * 2587 * Releases the PCI I/O and memory resources previously reserved by a 2588 * successful call to pci_request_region. Call this function only 2589 * after all use of the PCI regions has ceased. 2590 */ 2591 void pci_release_region(struct pci_dev *pdev, int bar) 2592 { 2593 struct pci_devres *dr; 2594 2595 if (pci_resource_len(pdev, bar) == 0) 2596 return; 2597 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) 2598 release_region(pci_resource_start(pdev, bar), 2599 pci_resource_len(pdev, bar)); 2600 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) 2601 release_mem_region(pci_resource_start(pdev, bar), 2602 pci_resource_len(pdev, bar)); 2603 2604 dr = find_pci_dr(pdev); 2605 if (dr) 2606 dr->region_mask &= ~(1 << bar); 2607 } 2608 2609 /** 2610 * __pci_request_region - Reserved PCI I/O and memory resource 2611 * @pdev: PCI device whose resources are to be reserved 2612 * @bar: BAR to be reserved 2613 * @res_name: Name to be associated with resource. 2614 * @exclusive: whether the region access is exclusive or not 2615 * 2616 * Mark the PCI region associated with PCI device @pdev BR @bar as 2617 * being reserved by owner @res_name. Do not access any 2618 * address inside the PCI regions unless this call returns 2619 * successfully. 2620 * 2621 * If @exclusive is set, then the region is marked so that userspace 2622 * is explicitly not allowed to map the resource via /dev/mem or 2623 * sysfs MMIO access. 2624 * 2625 * Returns 0 on success, or %EBUSY on error. A warning 2626 * message is also printed on failure. 2627 */ 2628 static int __pci_request_region(struct pci_dev *pdev, int bar, const char *res_name, 2629 int exclusive) 2630 { 2631 struct pci_devres *dr; 2632 2633 if (pci_resource_len(pdev, bar) == 0) 2634 return 0; 2635 2636 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) { 2637 if (!request_region(pci_resource_start(pdev, bar), 2638 pci_resource_len(pdev, bar), res_name)) 2639 goto err_out; 2640 } 2641 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) { 2642 if (!__request_mem_region(pci_resource_start(pdev, bar), 2643 pci_resource_len(pdev, bar), res_name, 2644 exclusive)) 2645 goto err_out; 2646 } 2647 2648 dr = find_pci_dr(pdev); 2649 if (dr) 2650 dr->region_mask |= 1 << bar; 2651 2652 return 0; 2653 2654 err_out: 2655 dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar, 2656 &pdev->resource[bar]); 2657 return -EBUSY; 2658 } 2659 2660 /** 2661 * pci_request_region - Reserve PCI I/O and memory resource 2662 * @pdev: PCI device whose resources are to be reserved 2663 * @bar: BAR to be reserved 2664 * @res_name: Name to be associated with resource 2665 * 2666 * Mark the PCI region associated with PCI device @pdev BAR @bar as 2667 * being reserved by owner @res_name. Do not access any 2668 * address inside the PCI regions unless this call returns 2669 * successfully. 2670 * 2671 * Returns 0 on success, or %EBUSY on error. A warning 2672 * message is also printed on failure. 2673 */ 2674 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) 2675 { 2676 return __pci_request_region(pdev, bar, res_name, 0); 2677 } 2678 2679 /** 2680 * pci_request_region_exclusive - Reserved PCI I/O and memory resource 2681 * @pdev: PCI device whose resources are to be reserved 2682 * @bar: BAR to be reserved 2683 * @res_name: Name to be associated with resource. 2684 * 2685 * Mark the PCI region associated with PCI device @pdev BR @bar as 2686 * being reserved by owner @res_name. Do not access any 2687 * address inside the PCI regions unless this call returns 2688 * successfully. 2689 * 2690 * Returns 0 on success, or %EBUSY on error. A warning 2691 * message is also printed on failure. 2692 * 2693 * The key difference that _exclusive makes it that userspace is 2694 * explicitly not allowed to map the resource via /dev/mem or 2695 * sysfs. 2696 */ 2697 int pci_request_region_exclusive(struct pci_dev *pdev, int bar, const char *res_name) 2698 { 2699 return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE); 2700 } 2701 /** 2702 * pci_release_selected_regions - Release selected PCI I/O and memory resources 2703 * @pdev: PCI device whose resources were previously reserved 2704 * @bars: Bitmask of BARs to be released 2705 * 2706 * Release selected PCI I/O and memory resources previously reserved. 2707 * Call this function only after all use of the PCI regions has ceased. 2708 */ 2709 void pci_release_selected_regions(struct pci_dev *pdev, int bars) 2710 { 2711 int i; 2712 2713 for (i = 0; i < 6; i++) 2714 if (bars & (1 << i)) 2715 pci_release_region(pdev, i); 2716 } 2717 2718 static int __pci_request_selected_regions(struct pci_dev *pdev, int bars, 2719 const char *res_name, int excl) 2720 { 2721 int i; 2722 2723 for (i = 0; i < 6; i++) 2724 if (bars & (1 << i)) 2725 if (__pci_request_region(pdev, i, res_name, excl)) 2726 goto err_out; 2727 return 0; 2728 2729 err_out: 2730 while(--i >= 0) 2731 if (bars & (1 << i)) 2732 pci_release_region(pdev, i); 2733 2734 return -EBUSY; 2735 } 2736 2737 2738 /** 2739 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources 2740 * @pdev: PCI device whose resources are to be reserved 2741 * @bars: Bitmask of BARs to be requested 2742 * @res_name: Name to be associated with resource 2743 */ 2744 int pci_request_selected_regions(struct pci_dev *pdev, int bars, 2745 const char *res_name) 2746 { 2747 return __pci_request_selected_regions(pdev, bars, res_name, 0); 2748 } 2749 2750 int pci_request_selected_regions_exclusive(struct pci_dev *pdev, 2751 int bars, const char *res_name) 2752 { 2753 return __pci_request_selected_regions(pdev, bars, res_name, 2754 IORESOURCE_EXCLUSIVE); 2755 } 2756 2757 /** 2758 * pci_release_regions - Release reserved PCI I/O and memory resources 2759 * @pdev: PCI device whose resources were previously reserved by pci_request_regions 2760 * 2761 * Releases all PCI I/O and memory resources previously reserved by a 2762 * successful call to pci_request_regions. Call this function only 2763 * after all use of the PCI regions has ceased. 2764 */ 2765 2766 void pci_release_regions(struct pci_dev *pdev) 2767 { 2768 pci_release_selected_regions(pdev, (1 << 6) - 1); 2769 } 2770 2771 /** 2772 * pci_request_regions - Reserved PCI I/O and memory resources 2773 * @pdev: PCI device whose resources are to be reserved 2774 * @res_name: Name to be associated with resource. 2775 * 2776 * Mark all PCI regions associated with PCI device @pdev as 2777 * being reserved by owner @res_name. Do not access any 2778 * address inside the PCI regions unless this call returns 2779 * successfully. 2780 * 2781 * Returns 0 on success, or %EBUSY on error. A warning 2782 * message is also printed on failure. 2783 */ 2784 int pci_request_regions(struct pci_dev *pdev, const char *res_name) 2785 { 2786 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name); 2787 } 2788 2789 /** 2790 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources 2791 * @pdev: PCI device whose resources are to be reserved 2792 * @res_name: Name to be associated with resource. 2793 * 2794 * Mark all PCI regions associated with PCI device @pdev as 2795 * being reserved by owner @res_name. Do not access any 2796 * address inside the PCI regions unless this call returns 2797 * successfully. 2798 * 2799 * pci_request_regions_exclusive() will mark the region so that 2800 * /dev/mem and the sysfs MMIO access will not be allowed. 2801 * 2802 * Returns 0 on success, or %EBUSY on error. A warning 2803 * message is also printed on failure. 2804 */ 2805 int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name) 2806 { 2807 return pci_request_selected_regions_exclusive(pdev, 2808 ((1 << 6) - 1), res_name); 2809 } 2810 2811 static void __pci_set_master(struct pci_dev *dev, bool enable) 2812 { 2813 u16 old_cmd, cmd; 2814 2815 pci_read_config_word(dev, PCI_COMMAND, &old_cmd); 2816 if (enable) 2817 cmd = old_cmd | PCI_COMMAND_MASTER; 2818 else 2819 cmd = old_cmd & ~PCI_COMMAND_MASTER; 2820 if (cmd != old_cmd) { 2821 dev_dbg(&dev->dev, "%s bus mastering\n", 2822 enable ? "enabling" : "disabling"); 2823 pci_write_config_word(dev, PCI_COMMAND, cmd); 2824 } 2825 dev->is_busmaster = enable; 2826 } 2827 2828 /** 2829 * pcibios_setup - process "pci=" kernel boot arguments 2830 * @str: string used to pass in "pci=" kernel boot arguments 2831 * 2832 * Process kernel boot arguments. This is the default implementation. 2833 * Architecture specific implementations can override this as necessary. 2834 */ 2835 char * __weak __init pcibios_setup(char *str) 2836 { 2837 return str; 2838 } 2839 2840 /** 2841 * pcibios_set_master - enable PCI bus-mastering for device dev 2842 * @dev: the PCI device to enable 2843 * 2844 * Enables PCI bus-mastering for the device. This is the default 2845 * implementation. Architecture specific implementations can override 2846 * this if necessary. 2847 */ 2848 void __weak pcibios_set_master(struct pci_dev *dev) 2849 { 2850 u8 lat; 2851 2852 /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */ 2853 if (pci_is_pcie(dev)) 2854 return; 2855 2856 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat); 2857 if (lat < 16) 2858 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency; 2859 else if (lat > pcibios_max_latency) 2860 lat = pcibios_max_latency; 2861 else 2862 return; 2863 dev_printk(KERN_DEBUG, &dev->dev, "setting latency timer to %d\n", lat); 2864 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat); 2865 } 2866 2867 /** 2868 * pci_set_master - enables bus-mastering for device dev 2869 * @dev: the PCI device to enable 2870 * 2871 * Enables bus-mastering on the device and calls pcibios_set_master() 2872 * to do the needed arch specific settings. 2873 */ 2874 void pci_set_master(struct pci_dev *dev) 2875 { 2876 __pci_set_master(dev, true); 2877 pcibios_set_master(dev); 2878 } 2879 2880 /** 2881 * pci_clear_master - disables bus-mastering for device dev 2882 * @dev: the PCI device to disable 2883 */ 2884 void pci_clear_master(struct pci_dev *dev) 2885 { 2886 __pci_set_master(dev, false); 2887 } 2888 2889 /** 2890 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed 2891 * @dev: the PCI device for which MWI is to be enabled 2892 * 2893 * Helper function for pci_set_mwi. 2894 * Originally copied from drivers/net/acenic.c. 2895 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. 2896 * 2897 * RETURNS: An appropriate -ERRNO error value on error, or zero for success. 2898 */ 2899 int pci_set_cacheline_size(struct pci_dev *dev) 2900 { 2901 u8 cacheline_size; 2902 2903 if (!pci_cache_line_size) 2904 return -EINVAL; 2905 2906 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be 2907 equal to or multiple of the right value. */ 2908 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); 2909 if (cacheline_size >= pci_cache_line_size && 2910 (cacheline_size % pci_cache_line_size) == 0) 2911 return 0; 2912 2913 /* Write the correct value. */ 2914 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size); 2915 /* Read it back. */ 2916 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); 2917 if (cacheline_size == pci_cache_line_size) 2918 return 0; 2919 2920 dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not " 2921 "supported\n", pci_cache_line_size << 2); 2922 2923 return -EINVAL; 2924 } 2925 EXPORT_SYMBOL_GPL(pci_set_cacheline_size); 2926 2927 #ifdef PCI_DISABLE_MWI 2928 int pci_set_mwi(struct pci_dev *dev) 2929 { 2930 return 0; 2931 } 2932 2933 int pci_try_set_mwi(struct pci_dev *dev) 2934 { 2935 return 0; 2936 } 2937 2938 void pci_clear_mwi(struct pci_dev *dev) 2939 { 2940 } 2941 2942 #else 2943 2944 /** 2945 * pci_set_mwi - enables memory-write-invalidate PCI transaction 2946 * @dev: the PCI device for which MWI is enabled 2947 * 2948 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. 2949 * 2950 * RETURNS: An appropriate -ERRNO error value on error, or zero for success. 2951 */ 2952 int 2953 pci_set_mwi(struct pci_dev *dev) 2954 { 2955 int rc; 2956 u16 cmd; 2957 2958 rc = pci_set_cacheline_size(dev); 2959 if (rc) 2960 return rc; 2961 2962 pci_read_config_word(dev, PCI_COMMAND, &cmd); 2963 if (! (cmd & PCI_COMMAND_INVALIDATE)) { 2964 dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n"); 2965 cmd |= PCI_COMMAND_INVALIDATE; 2966 pci_write_config_word(dev, PCI_COMMAND, cmd); 2967 } 2968 2969 return 0; 2970 } 2971 2972 /** 2973 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction 2974 * @dev: the PCI device for which MWI is enabled 2975 * 2976 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. 2977 * Callers are not required to check the return value. 2978 * 2979 * RETURNS: An appropriate -ERRNO error value on error, or zero for success. 2980 */ 2981 int pci_try_set_mwi(struct pci_dev *dev) 2982 { 2983 int rc = pci_set_mwi(dev); 2984 return rc; 2985 } 2986 2987 /** 2988 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev 2989 * @dev: the PCI device to disable 2990 * 2991 * Disables PCI Memory-Write-Invalidate transaction on the device 2992 */ 2993 void 2994 pci_clear_mwi(struct pci_dev *dev) 2995 { 2996 u16 cmd; 2997 2998 pci_read_config_word(dev, PCI_COMMAND, &cmd); 2999 if (cmd & PCI_COMMAND_INVALIDATE) { 3000 cmd &= ~PCI_COMMAND_INVALIDATE; 3001 pci_write_config_word(dev, PCI_COMMAND, cmd); 3002 } 3003 } 3004 #endif /* ! PCI_DISABLE_MWI */ 3005 3006 /** 3007 * pci_intx - enables/disables PCI INTx for device dev 3008 * @pdev: the PCI device to operate on 3009 * @enable: boolean: whether to enable or disable PCI INTx 3010 * 3011 * Enables/disables PCI INTx for device dev 3012 */ 3013 void 3014 pci_intx(struct pci_dev *pdev, int enable) 3015 { 3016 u16 pci_command, new; 3017 3018 pci_read_config_word(pdev, PCI_COMMAND, &pci_command); 3019 3020 if (enable) { 3021 new = pci_command & ~PCI_COMMAND_INTX_DISABLE; 3022 } else { 3023 new = pci_command | PCI_COMMAND_INTX_DISABLE; 3024 } 3025 3026 if (new != pci_command) { 3027 struct pci_devres *dr; 3028 3029 pci_write_config_word(pdev, PCI_COMMAND, new); 3030 3031 dr = find_pci_dr(pdev); 3032 if (dr && !dr->restore_intx) { 3033 dr->restore_intx = 1; 3034 dr->orig_intx = !enable; 3035 } 3036 } 3037 } 3038 3039 /** 3040 * pci_intx_mask_supported - probe for INTx masking support 3041 * @dev: the PCI device to operate on 3042 * 3043 * Check if the device dev support INTx masking via the config space 3044 * command word. 3045 */ 3046 bool pci_intx_mask_supported(struct pci_dev *dev) 3047 { 3048 bool mask_supported = false; 3049 u16 orig, new; 3050 3051 if (dev->broken_intx_masking) 3052 return false; 3053 3054 pci_cfg_access_lock(dev); 3055 3056 pci_read_config_word(dev, PCI_COMMAND, &orig); 3057 pci_write_config_word(dev, PCI_COMMAND, 3058 orig ^ PCI_COMMAND_INTX_DISABLE); 3059 pci_read_config_word(dev, PCI_COMMAND, &new); 3060 3061 /* 3062 * There's no way to protect against hardware bugs or detect them 3063 * reliably, but as long as we know what the value should be, let's 3064 * go ahead and check it. 3065 */ 3066 if ((new ^ orig) & ~PCI_COMMAND_INTX_DISABLE) { 3067 dev_err(&dev->dev, "Command register changed from " 3068 "0x%x to 0x%x: driver or hardware bug?\n", orig, new); 3069 } else if ((new ^ orig) & PCI_COMMAND_INTX_DISABLE) { 3070 mask_supported = true; 3071 pci_write_config_word(dev, PCI_COMMAND, orig); 3072 } 3073 3074 pci_cfg_access_unlock(dev); 3075 return mask_supported; 3076 } 3077 EXPORT_SYMBOL_GPL(pci_intx_mask_supported); 3078 3079 static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask) 3080 { 3081 struct pci_bus *bus = dev->bus; 3082 bool mask_updated = true; 3083 u32 cmd_status_dword; 3084 u16 origcmd, newcmd; 3085 unsigned long flags; 3086 bool irq_pending; 3087 3088 /* 3089 * We do a single dword read to retrieve both command and status. 3090 * Document assumptions that make this possible. 3091 */ 3092 BUILD_BUG_ON(PCI_COMMAND % 4); 3093 BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS); 3094 3095 raw_spin_lock_irqsave(&pci_lock, flags); 3096 3097 bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword); 3098 3099 irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT; 3100 3101 /* 3102 * Check interrupt status register to see whether our device 3103 * triggered the interrupt (when masking) or the next IRQ is 3104 * already pending (when unmasking). 3105 */ 3106 if (mask != irq_pending) { 3107 mask_updated = false; 3108 goto done; 3109 } 3110 3111 origcmd = cmd_status_dword; 3112 newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE; 3113 if (mask) 3114 newcmd |= PCI_COMMAND_INTX_DISABLE; 3115 if (newcmd != origcmd) 3116 bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd); 3117 3118 done: 3119 raw_spin_unlock_irqrestore(&pci_lock, flags); 3120 3121 return mask_updated; 3122 } 3123 3124 /** 3125 * pci_check_and_mask_intx - mask INTx on pending interrupt 3126 * @dev: the PCI device to operate on 3127 * 3128 * Check if the device dev has its INTx line asserted, mask it and 3129 * return true in that case. False is returned if not interrupt was 3130 * pending. 3131 */ 3132 bool pci_check_and_mask_intx(struct pci_dev *dev) 3133 { 3134 return pci_check_and_set_intx_mask(dev, true); 3135 } 3136 EXPORT_SYMBOL_GPL(pci_check_and_mask_intx); 3137 3138 /** 3139 * pci_check_and_mask_intx - unmask INTx of no interrupt is pending 3140 * @dev: the PCI device to operate on 3141 * 3142 * Check if the device dev has its INTx line asserted, unmask it if not 3143 * and return true. False is returned and the mask remains active if 3144 * there was still an interrupt pending. 3145 */ 3146 bool pci_check_and_unmask_intx(struct pci_dev *dev) 3147 { 3148 return pci_check_and_set_intx_mask(dev, false); 3149 } 3150 EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx); 3151 3152 /** 3153 * pci_msi_off - disables any MSI or MSI-X capabilities 3154 * @dev: the PCI device to operate on 3155 * 3156 * If you want to use MSI, see pci_enable_msi() and friends. 3157 * This is a lower-level primitive that allows us to disable 3158 * MSI operation at the device level. 3159 */ 3160 void pci_msi_off(struct pci_dev *dev) 3161 { 3162 int pos; 3163 u16 control; 3164 3165 /* 3166 * This looks like it could go in msi.c, but we need it even when 3167 * CONFIG_PCI_MSI=n. For the same reason, we can't use 3168 * dev->msi_cap or dev->msix_cap here. 3169 */ 3170 pos = pci_find_capability(dev, PCI_CAP_ID_MSI); 3171 if (pos) { 3172 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); 3173 control &= ~PCI_MSI_FLAGS_ENABLE; 3174 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); 3175 } 3176 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); 3177 if (pos) { 3178 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); 3179 control &= ~PCI_MSIX_FLAGS_ENABLE; 3180 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); 3181 } 3182 } 3183 EXPORT_SYMBOL_GPL(pci_msi_off); 3184 3185 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size) 3186 { 3187 return dma_set_max_seg_size(&dev->dev, size); 3188 } 3189 EXPORT_SYMBOL(pci_set_dma_max_seg_size); 3190 3191 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask) 3192 { 3193 return dma_set_seg_boundary(&dev->dev, mask); 3194 } 3195 EXPORT_SYMBOL(pci_set_dma_seg_boundary); 3196 3197 /** 3198 * pci_wait_for_pending_transaction - waits for pending transaction 3199 * @dev: the PCI device to operate on 3200 * 3201 * Return 0 if transaction is pending 1 otherwise. 3202 */ 3203 int pci_wait_for_pending_transaction(struct pci_dev *dev) 3204 { 3205 int i; 3206 u16 status; 3207 3208 /* Wait for Transaction Pending bit clean */ 3209 for (i = 0; i < 4; i++) { 3210 if (i) 3211 msleep((1 << (i - 1)) * 100); 3212 3213 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status); 3214 if (!(status & PCI_EXP_DEVSTA_TRPND)) 3215 return 1; 3216 } 3217 3218 return 0; 3219 } 3220 EXPORT_SYMBOL(pci_wait_for_pending_transaction); 3221 3222 static int pcie_flr(struct pci_dev *dev, int probe) 3223 { 3224 u32 cap; 3225 3226 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap); 3227 if (!(cap & PCI_EXP_DEVCAP_FLR)) 3228 return -ENOTTY; 3229 3230 if (probe) 3231 return 0; 3232 3233 if (!pci_wait_for_pending_transaction(dev)) 3234 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n"); 3235 3236 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR); 3237 3238 msleep(100); 3239 3240 return 0; 3241 } 3242 3243 static int pci_af_flr(struct pci_dev *dev, int probe) 3244 { 3245 int i; 3246 int pos; 3247 u8 cap; 3248 u8 status; 3249 3250 pos = pci_find_capability(dev, PCI_CAP_ID_AF); 3251 if (!pos) 3252 return -ENOTTY; 3253 3254 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap); 3255 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR)) 3256 return -ENOTTY; 3257 3258 if (probe) 3259 return 0; 3260 3261 /* Wait for Transaction Pending bit clean */ 3262 for (i = 0; i < 4; i++) { 3263 if (i) 3264 msleep((1 << (i - 1)) * 100); 3265 3266 pci_read_config_byte(dev, pos + PCI_AF_STATUS, &status); 3267 if (!(status & PCI_AF_STATUS_TP)) 3268 goto clear; 3269 } 3270 3271 dev_err(&dev->dev, "transaction is not cleared; " 3272 "proceeding with reset anyway\n"); 3273 3274 clear: 3275 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR); 3276 msleep(100); 3277 3278 return 0; 3279 } 3280 3281 /** 3282 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0. 3283 * @dev: Device to reset. 3284 * @probe: If set, only check if the device can be reset this way. 3285 * 3286 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is 3287 * unset, it will be reinitialized internally when going from PCI_D3hot to 3288 * PCI_D0. If that's the case and the device is not in a low-power state 3289 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset. 3290 * 3291 * NOTE: This causes the caller to sleep for twice the device power transition 3292 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms 3293 * by devault (i.e. unless the @dev's d3_delay field has a different value). 3294 * Moreover, only devices in D0 can be reset by this function. 3295 */ 3296 static int pci_pm_reset(struct pci_dev *dev, int probe) 3297 { 3298 u16 csr; 3299 3300 if (!dev->pm_cap) 3301 return -ENOTTY; 3302 3303 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr); 3304 if (csr & PCI_PM_CTRL_NO_SOFT_RESET) 3305 return -ENOTTY; 3306 3307 if (probe) 3308 return 0; 3309 3310 if (dev->current_state != PCI_D0) 3311 return -EINVAL; 3312 3313 csr &= ~PCI_PM_CTRL_STATE_MASK; 3314 csr |= PCI_D3hot; 3315 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); 3316 pci_dev_d3_sleep(dev); 3317 3318 csr &= ~PCI_PM_CTRL_STATE_MASK; 3319 csr |= PCI_D0; 3320 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); 3321 pci_dev_d3_sleep(dev); 3322 3323 return 0; 3324 } 3325 3326 /** 3327 * pci_reset_bridge_secondary_bus - Reset the secondary bus on a PCI bridge. 3328 * @dev: Bridge device 3329 * 3330 * Use the bridge control register to assert reset on the secondary bus. 3331 * Devices on the secondary bus are left in power-on state. 3332 */ 3333 void pci_reset_bridge_secondary_bus(struct pci_dev *dev) 3334 { 3335 u16 ctrl; 3336 3337 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl); 3338 ctrl |= PCI_BRIDGE_CTL_BUS_RESET; 3339 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl); 3340 /* 3341 * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double 3342 * this to 2ms to ensure that we meet the minium requirement. 3343 */ 3344 msleep(2); 3345 3346 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET; 3347 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl); 3348 3349 /* 3350 * Trhfa for conventional PCI is 2^25 clock cycles. 3351 * Assuming a minimum 33MHz clock this results in a 1s 3352 * delay before we can consider subordinate devices to 3353 * be re-initialized. PCIe has some ways to shorten this, 3354 * but we don't make use of them yet. 3355 */ 3356 ssleep(1); 3357 } 3358 EXPORT_SYMBOL_GPL(pci_reset_bridge_secondary_bus); 3359 3360 static int pci_parent_bus_reset(struct pci_dev *dev, int probe) 3361 { 3362 struct pci_dev *pdev; 3363 3364 if (pci_is_root_bus(dev->bus) || dev->subordinate || !dev->bus->self) 3365 return -ENOTTY; 3366 3367 list_for_each_entry(pdev, &dev->bus->devices, bus_list) 3368 if (pdev != dev) 3369 return -ENOTTY; 3370 3371 if (probe) 3372 return 0; 3373 3374 pci_reset_bridge_secondary_bus(dev->bus->self); 3375 3376 return 0; 3377 } 3378 3379 static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, int probe) 3380 { 3381 int rc = -ENOTTY; 3382 3383 if (!hotplug || !try_module_get(hotplug->ops->owner)) 3384 return rc; 3385 3386 if (hotplug->ops->reset_slot) 3387 rc = hotplug->ops->reset_slot(hotplug, probe); 3388 3389 module_put(hotplug->ops->owner); 3390 3391 return rc; 3392 } 3393 3394 static int pci_dev_reset_slot_function(struct pci_dev *dev, int probe) 3395 { 3396 struct pci_dev *pdev; 3397 3398 if (dev->subordinate || !dev->slot) 3399 return -ENOTTY; 3400 3401 list_for_each_entry(pdev, &dev->bus->devices, bus_list) 3402 if (pdev != dev && pdev->slot == dev->slot) 3403 return -ENOTTY; 3404 3405 return pci_reset_hotplug_slot(dev->slot->hotplug, probe); 3406 } 3407 3408 static int __pci_dev_reset(struct pci_dev *dev, int probe) 3409 { 3410 int rc; 3411 3412 might_sleep(); 3413 3414 rc = pci_dev_specific_reset(dev, probe); 3415 if (rc != -ENOTTY) 3416 goto done; 3417 3418 rc = pcie_flr(dev, probe); 3419 if (rc != -ENOTTY) 3420 goto done; 3421 3422 rc = pci_af_flr(dev, probe); 3423 if (rc != -ENOTTY) 3424 goto done; 3425 3426 rc = pci_pm_reset(dev, probe); 3427 if (rc != -ENOTTY) 3428 goto done; 3429 3430 rc = pci_dev_reset_slot_function(dev, probe); 3431 if (rc != -ENOTTY) 3432 goto done; 3433 3434 rc = pci_parent_bus_reset(dev, probe); 3435 done: 3436 return rc; 3437 } 3438 3439 static void pci_dev_lock(struct pci_dev *dev) 3440 { 3441 pci_cfg_access_lock(dev); 3442 /* block PM suspend, driver probe, etc. */ 3443 device_lock(&dev->dev); 3444 } 3445 3446 static void pci_dev_unlock(struct pci_dev *dev) 3447 { 3448 device_unlock(&dev->dev); 3449 pci_cfg_access_unlock(dev); 3450 } 3451 3452 static void pci_dev_save_and_disable(struct pci_dev *dev) 3453 { 3454 /* 3455 * Wake-up device prior to save. PM registers default to D0 after 3456 * reset and a simple register restore doesn't reliably return 3457 * to a non-D0 state anyway. 3458 */ 3459 pci_set_power_state(dev, PCI_D0); 3460 3461 pci_save_state(dev); 3462 /* 3463 * Disable the device by clearing the Command register, except for 3464 * INTx-disable which is set. This not only disables MMIO and I/O port 3465 * BARs, but also prevents the device from being Bus Master, preventing 3466 * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3 3467 * compliant devices, INTx-disable prevents legacy interrupts. 3468 */ 3469 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE); 3470 } 3471 3472 static void pci_dev_restore(struct pci_dev *dev) 3473 { 3474 pci_restore_state(dev); 3475 } 3476 3477 static int pci_dev_reset(struct pci_dev *dev, int probe) 3478 { 3479 int rc; 3480 3481 if (!probe) 3482 pci_dev_lock(dev); 3483 3484 rc = __pci_dev_reset(dev, probe); 3485 3486 if (!probe) 3487 pci_dev_unlock(dev); 3488 3489 return rc; 3490 } 3491 /** 3492 * __pci_reset_function - reset a PCI device function 3493 * @dev: PCI device to reset 3494 * 3495 * Some devices allow an individual function to be reset without affecting 3496 * other functions in the same device. The PCI device must be responsive 3497 * to PCI config space in order to use this function. 3498 * 3499 * The device function is presumed to be unused when this function is called. 3500 * Resetting the device will make the contents of PCI configuration space 3501 * random, so any caller of this must be prepared to reinitialise the 3502 * device including MSI, bus mastering, BARs, decoding IO and memory spaces, 3503 * etc. 3504 * 3505 * Returns 0 if the device function was successfully reset or negative if the 3506 * device doesn't support resetting a single function. 3507 */ 3508 int __pci_reset_function(struct pci_dev *dev) 3509 { 3510 return pci_dev_reset(dev, 0); 3511 } 3512 EXPORT_SYMBOL_GPL(__pci_reset_function); 3513 3514 /** 3515 * __pci_reset_function_locked - reset a PCI device function while holding 3516 * the @dev mutex lock. 3517 * @dev: PCI device to reset 3518 * 3519 * Some devices allow an individual function to be reset without affecting 3520 * other functions in the same device. The PCI device must be responsive 3521 * to PCI config space in order to use this function. 3522 * 3523 * The device function is presumed to be unused and the caller is holding 3524 * the device mutex lock when this function is called. 3525 * Resetting the device will make the contents of PCI configuration space 3526 * random, so any caller of this must be prepared to reinitialise the 3527 * device including MSI, bus mastering, BARs, decoding IO and memory spaces, 3528 * etc. 3529 * 3530 * Returns 0 if the device function was successfully reset or negative if the 3531 * device doesn't support resetting a single function. 3532 */ 3533 int __pci_reset_function_locked(struct pci_dev *dev) 3534 { 3535 return __pci_dev_reset(dev, 0); 3536 } 3537 EXPORT_SYMBOL_GPL(__pci_reset_function_locked); 3538 3539 /** 3540 * pci_probe_reset_function - check whether the device can be safely reset 3541 * @dev: PCI device to reset 3542 * 3543 * Some devices allow an individual function to be reset without affecting 3544 * other functions in the same device. The PCI device must be responsive 3545 * to PCI config space in order to use this function. 3546 * 3547 * Returns 0 if the device function can be reset or negative if the 3548 * device doesn't support resetting a single function. 3549 */ 3550 int pci_probe_reset_function(struct pci_dev *dev) 3551 { 3552 return pci_dev_reset(dev, 1); 3553 } 3554 3555 /** 3556 * pci_reset_function - quiesce and reset a PCI device function 3557 * @dev: PCI device to reset 3558 * 3559 * Some devices allow an individual function to be reset without affecting 3560 * other functions in the same device. The PCI device must be responsive 3561 * to PCI config space in order to use this function. 3562 * 3563 * This function does not just reset the PCI portion of a device, but 3564 * clears all the state associated with the device. This function differs 3565 * from __pci_reset_function in that it saves and restores device state 3566 * over the reset. 3567 * 3568 * Returns 0 if the device function was successfully reset or negative if the 3569 * device doesn't support resetting a single function. 3570 */ 3571 int pci_reset_function(struct pci_dev *dev) 3572 { 3573 int rc; 3574 3575 rc = pci_dev_reset(dev, 1); 3576 if (rc) 3577 return rc; 3578 3579 pci_dev_save_and_disable(dev); 3580 3581 rc = pci_dev_reset(dev, 0); 3582 3583 pci_dev_restore(dev); 3584 3585 return rc; 3586 } 3587 EXPORT_SYMBOL_GPL(pci_reset_function); 3588 3589 /* Lock devices from the top of the tree down */ 3590 static void pci_bus_lock(struct pci_bus *bus) 3591 { 3592 struct pci_dev *dev; 3593 3594 list_for_each_entry(dev, &bus->devices, bus_list) { 3595 pci_dev_lock(dev); 3596 if (dev->subordinate) 3597 pci_bus_lock(dev->subordinate); 3598 } 3599 } 3600 3601 /* Unlock devices from the bottom of the tree up */ 3602 static void pci_bus_unlock(struct pci_bus *bus) 3603 { 3604 struct pci_dev *dev; 3605 3606 list_for_each_entry(dev, &bus->devices, bus_list) { 3607 if (dev->subordinate) 3608 pci_bus_unlock(dev->subordinate); 3609 pci_dev_unlock(dev); 3610 } 3611 } 3612 3613 /* Lock devices from the top of the tree down */ 3614 static void pci_slot_lock(struct pci_slot *slot) 3615 { 3616 struct pci_dev *dev; 3617 3618 list_for_each_entry(dev, &slot->bus->devices, bus_list) { 3619 if (!dev->slot || dev->slot != slot) 3620 continue; 3621 pci_dev_lock(dev); 3622 if (dev->subordinate) 3623 pci_bus_lock(dev->subordinate); 3624 } 3625 } 3626 3627 /* Unlock devices from the bottom of the tree up */ 3628 static void pci_slot_unlock(struct pci_slot *slot) 3629 { 3630 struct pci_dev *dev; 3631 3632 list_for_each_entry(dev, &slot->bus->devices, bus_list) { 3633 if (!dev->slot || dev->slot != slot) 3634 continue; 3635 if (dev->subordinate) 3636 pci_bus_unlock(dev->subordinate); 3637 pci_dev_unlock(dev); 3638 } 3639 } 3640 3641 /* Save and disable devices from the top of the tree down */ 3642 static void pci_bus_save_and_disable(struct pci_bus *bus) 3643 { 3644 struct pci_dev *dev; 3645 3646 list_for_each_entry(dev, &bus->devices, bus_list) { 3647 pci_dev_save_and_disable(dev); 3648 if (dev->subordinate) 3649 pci_bus_save_and_disable(dev->subordinate); 3650 } 3651 } 3652 3653 /* 3654 * Restore devices from top of the tree down - parent bridges need to be 3655 * restored before we can get to subordinate devices. 3656 */ 3657 static void pci_bus_restore(struct pci_bus *bus) 3658 { 3659 struct pci_dev *dev; 3660 3661 list_for_each_entry(dev, &bus->devices, bus_list) { 3662 pci_dev_restore(dev); 3663 if (dev->subordinate) 3664 pci_bus_restore(dev->subordinate); 3665 } 3666 } 3667 3668 /* Save and disable devices from the top of the tree down */ 3669 static void pci_slot_save_and_disable(struct pci_slot *slot) 3670 { 3671 struct pci_dev *dev; 3672 3673 list_for_each_entry(dev, &slot->bus->devices, bus_list) { 3674 if (!dev->slot || dev->slot != slot) 3675 continue; 3676 pci_dev_save_and_disable(dev); 3677 if (dev->subordinate) 3678 pci_bus_save_and_disable(dev->subordinate); 3679 } 3680 } 3681 3682 /* 3683 * Restore devices from top of the tree down - parent bridges need to be 3684 * restored before we can get to subordinate devices. 3685 */ 3686 static void pci_slot_restore(struct pci_slot *slot) 3687 { 3688 struct pci_dev *dev; 3689 3690 list_for_each_entry(dev, &slot->bus->devices, bus_list) { 3691 if (!dev->slot || dev->slot != slot) 3692 continue; 3693 pci_dev_restore(dev); 3694 if (dev->subordinate) 3695 pci_bus_restore(dev->subordinate); 3696 } 3697 } 3698 3699 static int pci_slot_reset(struct pci_slot *slot, int probe) 3700 { 3701 int rc; 3702 3703 if (!slot) 3704 return -ENOTTY; 3705 3706 if (!probe) 3707 pci_slot_lock(slot); 3708 3709 might_sleep(); 3710 3711 rc = pci_reset_hotplug_slot(slot->hotplug, probe); 3712 3713 if (!probe) 3714 pci_slot_unlock(slot); 3715 3716 return rc; 3717 } 3718 3719 /** 3720 * pci_probe_reset_slot - probe whether a PCI slot can be reset 3721 * @slot: PCI slot to probe 3722 * 3723 * Return 0 if slot can be reset, negative if a slot reset is not supported. 3724 */ 3725 int pci_probe_reset_slot(struct pci_slot *slot) 3726 { 3727 return pci_slot_reset(slot, 1); 3728 } 3729 EXPORT_SYMBOL_GPL(pci_probe_reset_slot); 3730 3731 /** 3732 * pci_reset_slot - reset a PCI slot 3733 * @slot: PCI slot to reset 3734 * 3735 * A PCI bus may host multiple slots, each slot may support a reset mechanism 3736 * independent of other slots. For instance, some slots may support slot power 3737 * control. In the case of a 1:1 bus to slot architecture, this function may 3738 * wrap the bus reset to avoid spurious slot related events such as hotplug. 3739 * Generally a slot reset should be attempted before a bus reset. All of the 3740 * function of the slot and any subordinate buses behind the slot are reset 3741 * through this function. PCI config space of all devices in the slot and 3742 * behind the slot is saved before and restored after reset. 3743 * 3744 * Return 0 on success, non-zero on error. 3745 */ 3746 int pci_reset_slot(struct pci_slot *slot) 3747 { 3748 int rc; 3749 3750 rc = pci_slot_reset(slot, 1); 3751 if (rc) 3752 return rc; 3753 3754 pci_slot_save_and_disable(slot); 3755 3756 rc = pci_slot_reset(slot, 0); 3757 3758 pci_slot_restore(slot); 3759 3760 return rc; 3761 } 3762 EXPORT_SYMBOL_GPL(pci_reset_slot); 3763 3764 static int pci_bus_reset(struct pci_bus *bus, int probe) 3765 { 3766 if (!bus->self) 3767 return -ENOTTY; 3768 3769 if (probe) 3770 return 0; 3771 3772 pci_bus_lock(bus); 3773 3774 might_sleep(); 3775 3776 pci_reset_bridge_secondary_bus(bus->self); 3777 3778 pci_bus_unlock(bus); 3779 3780 return 0; 3781 } 3782 3783 /** 3784 * pci_probe_reset_bus - probe whether a PCI bus can be reset 3785 * @bus: PCI bus to probe 3786 * 3787 * Return 0 if bus can be reset, negative if a bus reset is not supported. 3788 */ 3789 int pci_probe_reset_bus(struct pci_bus *bus) 3790 { 3791 return pci_bus_reset(bus, 1); 3792 } 3793 EXPORT_SYMBOL_GPL(pci_probe_reset_bus); 3794 3795 /** 3796 * pci_reset_bus - reset a PCI bus 3797 * @bus: top level PCI bus to reset 3798 * 3799 * Do a bus reset on the given bus and any subordinate buses, saving 3800 * and restoring state of all devices. 3801 * 3802 * Return 0 on success, non-zero on error. 3803 */ 3804 int pci_reset_bus(struct pci_bus *bus) 3805 { 3806 int rc; 3807 3808 rc = pci_bus_reset(bus, 1); 3809 if (rc) 3810 return rc; 3811 3812 pci_bus_save_and_disable(bus); 3813 3814 rc = pci_bus_reset(bus, 0); 3815 3816 pci_bus_restore(bus); 3817 3818 return rc; 3819 } 3820 EXPORT_SYMBOL_GPL(pci_reset_bus); 3821 3822 /** 3823 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count 3824 * @dev: PCI device to query 3825 * 3826 * Returns mmrbc: maximum designed memory read count in bytes 3827 * or appropriate error value. 3828 */ 3829 int pcix_get_max_mmrbc(struct pci_dev *dev) 3830 { 3831 int cap; 3832 u32 stat; 3833 3834 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); 3835 if (!cap) 3836 return -EINVAL; 3837 3838 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat)) 3839 return -EINVAL; 3840 3841 return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21); 3842 } 3843 EXPORT_SYMBOL(pcix_get_max_mmrbc); 3844 3845 /** 3846 * pcix_get_mmrbc - get PCI-X maximum memory read byte count 3847 * @dev: PCI device to query 3848 * 3849 * Returns mmrbc: maximum memory read count in bytes 3850 * or appropriate error value. 3851 */ 3852 int pcix_get_mmrbc(struct pci_dev *dev) 3853 { 3854 int cap; 3855 u16 cmd; 3856 3857 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); 3858 if (!cap) 3859 return -EINVAL; 3860 3861 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd)) 3862 return -EINVAL; 3863 3864 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2); 3865 } 3866 EXPORT_SYMBOL(pcix_get_mmrbc); 3867 3868 /** 3869 * pcix_set_mmrbc - set PCI-X maximum memory read byte count 3870 * @dev: PCI device to query 3871 * @mmrbc: maximum memory read count in bytes 3872 * valid values are 512, 1024, 2048, 4096 3873 * 3874 * If possible sets maximum memory read byte count, some bridges have erratas 3875 * that prevent this. 3876 */ 3877 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc) 3878 { 3879 int cap; 3880 u32 stat, v, o; 3881 u16 cmd; 3882 3883 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc)) 3884 return -EINVAL; 3885 3886 v = ffs(mmrbc) - 10; 3887 3888 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); 3889 if (!cap) 3890 return -EINVAL; 3891 3892 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat)) 3893 return -EINVAL; 3894 3895 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21) 3896 return -E2BIG; 3897 3898 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd)) 3899 return -EINVAL; 3900 3901 o = (cmd & PCI_X_CMD_MAX_READ) >> 2; 3902 if (o != v) { 3903 if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC)) 3904 return -EIO; 3905 3906 cmd &= ~PCI_X_CMD_MAX_READ; 3907 cmd |= v << 2; 3908 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd)) 3909 return -EIO; 3910 } 3911 return 0; 3912 } 3913 EXPORT_SYMBOL(pcix_set_mmrbc); 3914 3915 /** 3916 * pcie_get_readrq - get PCI Express read request size 3917 * @dev: PCI device to query 3918 * 3919 * Returns maximum memory read request in bytes 3920 * or appropriate error value. 3921 */ 3922 int pcie_get_readrq(struct pci_dev *dev) 3923 { 3924 u16 ctl; 3925 3926 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl); 3927 3928 return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12); 3929 } 3930 EXPORT_SYMBOL(pcie_get_readrq); 3931 3932 /** 3933 * pcie_set_readrq - set PCI Express maximum memory read request 3934 * @dev: PCI device to query 3935 * @rq: maximum memory read count in bytes 3936 * valid values are 128, 256, 512, 1024, 2048, 4096 3937 * 3938 * If possible sets maximum memory read request in bytes 3939 */ 3940 int pcie_set_readrq(struct pci_dev *dev, int rq) 3941 { 3942 u16 v; 3943 3944 if (rq < 128 || rq > 4096 || !is_power_of_2(rq)) 3945 return -EINVAL; 3946 3947 /* 3948 * If using the "performance" PCIe config, we clamp the 3949 * read rq size to the max packet size to prevent the 3950 * host bridge generating requests larger than we can 3951 * cope with 3952 */ 3953 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) { 3954 int mps = pcie_get_mps(dev); 3955 3956 if (mps < rq) 3957 rq = mps; 3958 } 3959 3960 v = (ffs(rq) - 8) << 12; 3961 3962 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL, 3963 PCI_EXP_DEVCTL_READRQ, v); 3964 } 3965 EXPORT_SYMBOL(pcie_set_readrq); 3966 3967 /** 3968 * pcie_get_mps - get PCI Express maximum payload size 3969 * @dev: PCI device to query 3970 * 3971 * Returns maximum payload size in bytes 3972 */ 3973 int pcie_get_mps(struct pci_dev *dev) 3974 { 3975 u16 ctl; 3976 3977 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl); 3978 3979 return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5); 3980 } 3981 3982 /** 3983 * pcie_set_mps - set PCI Express maximum payload size 3984 * @dev: PCI device to query 3985 * @mps: maximum payload size in bytes 3986 * valid values are 128, 256, 512, 1024, 2048, 4096 3987 * 3988 * If possible sets maximum payload size 3989 */ 3990 int pcie_set_mps(struct pci_dev *dev, int mps) 3991 { 3992 u16 v; 3993 3994 if (mps < 128 || mps > 4096 || !is_power_of_2(mps)) 3995 return -EINVAL; 3996 3997 v = ffs(mps) - 8; 3998 if (v > dev->pcie_mpss) 3999 return -EINVAL; 4000 v <<= 5; 4001 4002 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL, 4003 PCI_EXP_DEVCTL_PAYLOAD, v); 4004 } 4005 4006 /** 4007 * pcie_get_minimum_link - determine minimum link settings of a PCI device 4008 * @dev: PCI device to query 4009 * @speed: storage for minimum speed 4010 * @width: storage for minimum width 4011 * 4012 * This function will walk up the PCI device chain and determine the minimum 4013 * link width and speed of the device. 4014 */ 4015 int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed, 4016 enum pcie_link_width *width) 4017 { 4018 int ret; 4019 4020 *speed = PCI_SPEED_UNKNOWN; 4021 *width = PCIE_LNK_WIDTH_UNKNOWN; 4022 4023 while (dev) { 4024 u16 lnksta; 4025 enum pci_bus_speed next_speed; 4026 enum pcie_link_width next_width; 4027 4028 ret = pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta); 4029 if (ret) 4030 return ret; 4031 4032 next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS]; 4033 next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >> 4034 PCI_EXP_LNKSTA_NLW_SHIFT; 4035 4036 if (next_speed < *speed) 4037 *speed = next_speed; 4038 4039 if (next_width < *width) 4040 *width = next_width; 4041 4042 dev = dev->bus->self; 4043 } 4044 4045 return 0; 4046 } 4047 EXPORT_SYMBOL(pcie_get_minimum_link); 4048 4049 /** 4050 * pci_select_bars - Make BAR mask from the type of resource 4051 * @dev: the PCI device for which BAR mask is made 4052 * @flags: resource type mask to be selected 4053 * 4054 * This helper routine makes bar mask from the type of resource. 4055 */ 4056 int pci_select_bars(struct pci_dev *dev, unsigned long flags) 4057 { 4058 int i, bars = 0; 4059 for (i = 0; i < PCI_NUM_RESOURCES; i++) 4060 if (pci_resource_flags(dev, i) & flags) 4061 bars |= (1 << i); 4062 return bars; 4063 } 4064 4065 /** 4066 * pci_resource_bar - get position of the BAR associated with a resource 4067 * @dev: the PCI device 4068 * @resno: the resource number 4069 * @type: the BAR type to be filled in 4070 * 4071 * Returns BAR position in config space, or 0 if the BAR is invalid. 4072 */ 4073 int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type) 4074 { 4075 int reg; 4076 4077 if (resno < PCI_ROM_RESOURCE) { 4078 *type = pci_bar_unknown; 4079 return PCI_BASE_ADDRESS_0 + 4 * resno; 4080 } else if (resno == PCI_ROM_RESOURCE) { 4081 *type = pci_bar_mem32; 4082 return dev->rom_base_reg; 4083 } else if (resno < PCI_BRIDGE_RESOURCES) { 4084 /* device specific resource */ 4085 reg = pci_iov_resource_bar(dev, resno, type); 4086 if (reg) 4087 return reg; 4088 } 4089 4090 dev_err(&dev->dev, "BAR %d: invalid resource\n", resno); 4091 return 0; 4092 } 4093 4094 /* Some architectures require additional programming to enable VGA */ 4095 static arch_set_vga_state_t arch_set_vga_state; 4096 4097 void __init pci_register_set_vga_state(arch_set_vga_state_t func) 4098 { 4099 arch_set_vga_state = func; /* NULL disables */ 4100 } 4101 4102 static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode, 4103 unsigned int command_bits, u32 flags) 4104 { 4105 if (arch_set_vga_state) 4106 return arch_set_vga_state(dev, decode, command_bits, 4107 flags); 4108 return 0; 4109 } 4110 4111 /** 4112 * pci_set_vga_state - set VGA decode state on device and parents if requested 4113 * @dev: the PCI device 4114 * @decode: true = enable decoding, false = disable decoding 4115 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY 4116 * @flags: traverse ancestors and change bridges 4117 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE 4118 */ 4119 int pci_set_vga_state(struct pci_dev *dev, bool decode, 4120 unsigned int command_bits, u32 flags) 4121 { 4122 struct pci_bus *bus; 4123 struct pci_dev *bridge; 4124 u16 cmd; 4125 int rc; 4126 4127 WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) & (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY))); 4128 4129 /* ARCH specific VGA enables */ 4130 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags); 4131 if (rc) 4132 return rc; 4133 4134 if (flags & PCI_VGA_STATE_CHANGE_DECODES) { 4135 pci_read_config_word(dev, PCI_COMMAND, &cmd); 4136 if (decode == true) 4137 cmd |= command_bits; 4138 else 4139 cmd &= ~command_bits; 4140 pci_write_config_word(dev, PCI_COMMAND, cmd); 4141 } 4142 4143 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE)) 4144 return 0; 4145 4146 bus = dev->bus; 4147 while (bus) { 4148 bridge = bus->self; 4149 if (bridge) { 4150 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL, 4151 &cmd); 4152 if (decode == true) 4153 cmd |= PCI_BRIDGE_CTL_VGA; 4154 else 4155 cmd &= ~PCI_BRIDGE_CTL_VGA; 4156 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, 4157 cmd); 4158 } 4159 bus = bus->parent; 4160 } 4161 return 0; 4162 } 4163 4164 #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE 4165 static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0}; 4166 static DEFINE_SPINLOCK(resource_alignment_lock); 4167 4168 /** 4169 * pci_specified_resource_alignment - get resource alignment specified by user. 4170 * @dev: the PCI device to get 4171 * 4172 * RETURNS: Resource alignment if it is specified. 4173 * Zero if it is not specified. 4174 */ 4175 static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev) 4176 { 4177 int seg, bus, slot, func, align_order, count; 4178 resource_size_t align = 0; 4179 char *p; 4180 4181 spin_lock(&resource_alignment_lock); 4182 p = resource_alignment_param; 4183 while (*p) { 4184 count = 0; 4185 if (sscanf(p, "%d%n", &align_order, &count) == 1 && 4186 p[count] == '@') { 4187 p += count + 1; 4188 } else { 4189 align_order = -1; 4190 } 4191 if (sscanf(p, "%x:%x:%x.%x%n", 4192 &seg, &bus, &slot, &func, &count) != 4) { 4193 seg = 0; 4194 if (sscanf(p, "%x:%x.%x%n", 4195 &bus, &slot, &func, &count) != 3) { 4196 /* Invalid format */ 4197 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n", 4198 p); 4199 break; 4200 } 4201 } 4202 p += count; 4203 if (seg == pci_domain_nr(dev->bus) && 4204 bus == dev->bus->number && 4205 slot == PCI_SLOT(dev->devfn) && 4206 func == PCI_FUNC(dev->devfn)) { 4207 if (align_order == -1) { 4208 align = PAGE_SIZE; 4209 } else { 4210 align = 1 << align_order; 4211 } 4212 /* Found */ 4213 break; 4214 } 4215 if (*p != ';' && *p != ',') { 4216 /* End of param or invalid format */ 4217 break; 4218 } 4219 p++; 4220 } 4221 spin_unlock(&resource_alignment_lock); 4222 return align; 4223 } 4224 4225 /* 4226 * This function disables memory decoding and releases memory resources 4227 * of the device specified by kernel's boot parameter 'pci=resource_alignment='. 4228 * It also rounds up size to specified alignment. 4229 * Later on, the kernel will assign page-aligned memory resource back 4230 * to the device. 4231 */ 4232 void pci_reassigndev_resource_alignment(struct pci_dev *dev) 4233 { 4234 int i; 4235 struct resource *r; 4236 resource_size_t align, size; 4237 u16 command; 4238 4239 /* check if specified PCI is target device to reassign */ 4240 align = pci_specified_resource_alignment(dev); 4241 if (!align) 4242 return; 4243 4244 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL && 4245 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) { 4246 dev_warn(&dev->dev, 4247 "Can't reassign resources to host bridge.\n"); 4248 return; 4249 } 4250 4251 dev_info(&dev->dev, 4252 "Disabling memory decoding and releasing memory resources.\n"); 4253 pci_read_config_word(dev, PCI_COMMAND, &command); 4254 command &= ~PCI_COMMAND_MEMORY; 4255 pci_write_config_word(dev, PCI_COMMAND, command); 4256 4257 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) { 4258 r = &dev->resource[i]; 4259 if (!(r->flags & IORESOURCE_MEM)) 4260 continue; 4261 size = resource_size(r); 4262 if (size < align) { 4263 size = align; 4264 dev_info(&dev->dev, 4265 "Rounding up size of resource #%d to %#llx.\n", 4266 i, (unsigned long long)size); 4267 } 4268 r->end = size - 1; 4269 r->start = 0; 4270 } 4271 /* Need to disable bridge's resource window, 4272 * to enable the kernel to reassign new resource 4273 * window later on. 4274 */ 4275 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE && 4276 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { 4277 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) { 4278 r = &dev->resource[i]; 4279 if (!(r->flags & IORESOURCE_MEM)) 4280 continue; 4281 r->end = resource_size(r) - 1; 4282 r->start = 0; 4283 } 4284 pci_disable_bridge_window(dev); 4285 } 4286 } 4287 4288 static ssize_t pci_set_resource_alignment_param(const char *buf, size_t count) 4289 { 4290 if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1) 4291 count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1; 4292 spin_lock(&resource_alignment_lock); 4293 strncpy(resource_alignment_param, buf, count); 4294 resource_alignment_param[count] = '\0'; 4295 spin_unlock(&resource_alignment_lock); 4296 return count; 4297 } 4298 4299 static ssize_t pci_get_resource_alignment_param(char *buf, size_t size) 4300 { 4301 size_t count; 4302 spin_lock(&resource_alignment_lock); 4303 count = snprintf(buf, size, "%s", resource_alignment_param); 4304 spin_unlock(&resource_alignment_lock); 4305 return count; 4306 } 4307 4308 static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf) 4309 { 4310 return pci_get_resource_alignment_param(buf, PAGE_SIZE); 4311 } 4312 4313 static ssize_t pci_resource_alignment_store(struct bus_type *bus, 4314 const char *buf, size_t count) 4315 { 4316 return pci_set_resource_alignment_param(buf, count); 4317 } 4318 4319 BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show, 4320 pci_resource_alignment_store); 4321 4322 static int __init pci_resource_alignment_sysfs_init(void) 4323 { 4324 return bus_create_file(&pci_bus_type, 4325 &bus_attr_resource_alignment); 4326 } 4327 4328 late_initcall(pci_resource_alignment_sysfs_init); 4329 4330 static void pci_no_domains(void) 4331 { 4332 #ifdef CONFIG_PCI_DOMAINS 4333 pci_domains_supported = 0; 4334 #endif 4335 } 4336 4337 /** 4338 * pci_ext_cfg_avail - can we access extended PCI config space? 4339 * 4340 * Returns 1 if we can access PCI extended config space (offsets 4341 * greater than 0xff). This is the default implementation. Architecture 4342 * implementations can override this. 4343 */ 4344 int __weak pci_ext_cfg_avail(void) 4345 { 4346 return 1; 4347 } 4348 4349 void __weak pci_fixup_cardbus(struct pci_bus *bus) 4350 { 4351 } 4352 EXPORT_SYMBOL(pci_fixup_cardbus); 4353 4354 static int __init pci_setup(char *str) 4355 { 4356 while (str) { 4357 char *k = strchr(str, ','); 4358 if (k) 4359 *k++ = 0; 4360 if (*str && (str = pcibios_setup(str)) && *str) { 4361 if (!strcmp(str, "nomsi")) { 4362 pci_no_msi(); 4363 } else if (!strcmp(str, "noaer")) { 4364 pci_no_aer(); 4365 } else if (!strncmp(str, "realloc=", 8)) { 4366 pci_realloc_get_opt(str + 8); 4367 } else if (!strncmp(str, "realloc", 7)) { 4368 pci_realloc_get_opt("on"); 4369 } else if (!strcmp(str, "nodomains")) { 4370 pci_no_domains(); 4371 } else if (!strncmp(str, "noari", 5)) { 4372 pcie_ari_disabled = true; 4373 } else if (!strncmp(str, "cbiosize=", 9)) { 4374 pci_cardbus_io_size = memparse(str + 9, &str); 4375 } else if (!strncmp(str, "cbmemsize=", 10)) { 4376 pci_cardbus_mem_size = memparse(str + 10, &str); 4377 } else if (!strncmp(str, "resource_alignment=", 19)) { 4378 pci_set_resource_alignment_param(str + 19, 4379 strlen(str + 19)); 4380 } else if (!strncmp(str, "ecrc=", 5)) { 4381 pcie_ecrc_get_policy(str + 5); 4382 } else if (!strncmp(str, "hpiosize=", 9)) { 4383 pci_hotplug_io_size = memparse(str + 9, &str); 4384 } else if (!strncmp(str, "hpmemsize=", 10)) { 4385 pci_hotplug_mem_size = memparse(str + 10, &str); 4386 } else if (!strncmp(str, "pcie_bus_tune_off", 17)) { 4387 pcie_bus_config = PCIE_BUS_TUNE_OFF; 4388 } else if (!strncmp(str, "pcie_bus_safe", 13)) { 4389 pcie_bus_config = PCIE_BUS_SAFE; 4390 } else if (!strncmp(str, "pcie_bus_perf", 13)) { 4391 pcie_bus_config = PCIE_BUS_PERFORMANCE; 4392 } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) { 4393 pcie_bus_config = PCIE_BUS_PEER2PEER; 4394 } else if (!strncmp(str, "pcie_scan_all", 13)) { 4395 pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS); 4396 } else { 4397 printk(KERN_ERR "PCI: Unknown option `%s'\n", 4398 str); 4399 } 4400 } 4401 str = k; 4402 } 4403 return 0; 4404 } 4405 early_param("pci", pci_setup); 4406 4407 EXPORT_SYMBOL(pci_reenable_device); 4408 EXPORT_SYMBOL(pci_enable_device_io); 4409 EXPORT_SYMBOL(pci_enable_device_mem); 4410 EXPORT_SYMBOL(pci_enable_device); 4411 EXPORT_SYMBOL(pcim_enable_device); 4412 EXPORT_SYMBOL(pcim_pin_device); 4413 EXPORT_SYMBOL(pci_disable_device); 4414 EXPORT_SYMBOL(pci_find_capability); 4415 EXPORT_SYMBOL(pci_bus_find_capability); 4416 EXPORT_SYMBOL(pci_release_regions); 4417 EXPORT_SYMBOL(pci_request_regions); 4418 EXPORT_SYMBOL(pci_request_regions_exclusive); 4419 EXPORT_SYMBOL(pci_release_region); 4420 EXPORT_SYMBOL(pci_request_region); 4421 EXPORT_SYMBOL(pci_request_region_exclusive); 4422 EXPORT_SYMBOL(pci_release_selected_regions); 4423 EXPORT_SYMBOL(pci_request_selected_regions); 4424 EXPORT_SYMBOL(pci_request_selected_regions_exclusive); 4425 EXPORT_SYMBOL(pci_set_master); 4426 EXPORT_SYMBOL(pci_clear_master); 4427 EXPORT_SYMBOL(pci_set_mwi); 4428 EXPORT_SYMBOL(pci_try_set_mwi); 4429 EXPORT_SYMBOL(pci_clear_mwi); 4430 EXPORT_SYMBOL_GPL(pci_intx); 4431 EXPORT_SYMBOL(pci_assign_resource); 4432 EXPORT_SYMBOL(pci_find_parent_resource); 4433 EXPORT_SYMBOL(pci_select_bars); 4434 4435 EXPORT_SYMBOL(pci_set_power_state); 4436 EXPORT_SYMBOL(pci_save_state); 4437 EXPORT_SYMBOL(pci_restore_state); 4438 EXPORT_SYMBOL(pci_pme_capable); 4439 EXPORT_SYMBOL(pci_pme_active); 4440 EXPORT_SYMBOL(pci_wake_from_d3); 4441 EXPORT_SYMBOL(pci_target_state); 4442 EXPORT_SYMBOL(pci_prepare_to_sleep); 4443 EXPORT_SYMBOL(pci_back_from_sleep); 4444 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state); 4445