xref: /openbmc/linux/drivers/pci/pci.c (revision aa0dc6a7)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * PCI Bus Services, see include/linux/pci.h for further explanation.
4  *
5  * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
6  * David Mosberger-Tang
7  *
8  * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
9  */
10 
11 #include <linux/acpi.h>
12 #include <linux/kernel.h>
13 #include <linux/delay.h>
14 #include <linux/dmi.h>
15 #include <linux/init.h>
16 #include <linux/msi.h>
17 #include <linux/of.h>
18 #include <linux/pci.h>
19 #include <linux/pm.h>
20 #include <linux/slab.h>
21 #include <linux/module.h>
22 #include <linux/spinlock.h>
23 #include <linux/string.h>
24 #include <linux/log2.h>
25 #include <linux/logic_pio.h>
26 #include <linux/pm_wakeup.h>
27 #include <linux/interrupt.h>
28 #include <linux/device.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/pci_hotplug.h>
31 #include <linux/vmalloc.h>
32 #include <asm/dma.h>
33 #include <linux/aer.h>
34 #include "pci.h"
35 
36 DEFINE_MUTEX(pci_slot_mutex);
37 
38 const char *pci_power_names[] = {
39 	"error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
40 };
41 EXPORT_SYMBOL_GPL(pci_power_names);
42 
43 int isa_dma_bridge_buggy;
44 EXPORT_SYMBOL(isa_dma_bridge_buggy);
45 
46 int pci_pci_problems;
47 EXPORT_SYMBOL(pci_pci_problems);
48 
49 unsigned int pci_pm_d3hot_delay;
50 
51 static void pci_pme_list_scan(struct work_struct *work);
52 
53 static LIST_HEAD(pci_pme_list);
54 static DEFINE_MUTEX(pci_pme_list_mutex);
55 static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);
56 
57 struct pci_pme_device {
58 	struct list_head list;
59 	struct pci_dev *dev;
60 };
61 
62 #define PME_TIMEOUT 1000 /* How long between PME checks */
63 
64 static void pci_dev_d3_sleep(struct pci_dev *dev)
65 {
66 	unsigned int delay = dev->d3hot_delay;
67 
68 	if (delay < pci_pm_d3hot_delay)
69 		delay = pci_pm_d3hot_delay;
70 
71 	if (delay)
72 		msleep(delay);
73 }
74 
75 #ifdef CONFIG_PCI_DOMAINS
76 int pci_domains_supported = 1;
77 #endif
78 
79 #define DEFAULT_CARDBUS_IO_SIZE		(256)
80 #define DEFAULT_CARDBUS_MEM_SIZE	(64*1024*1024)
81 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
82 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
83 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
84 
85 #define DEFAULT_HOTPLUG_IO_SIZE		(256)
86 #define DEFAULT_HOTPLUG_MMIO_SIZE	(2*1024*1024)
87 #define DEFAULT_HOTPLUG_MMIO_PREF_SIZE	(2*1024*1024)
88 /* hpiosize=nn can override this */
89 unsigned long pci_hotplug_io_size  = DEFAULT_HOTPLUG_IO_SIZE;
90 /*
91  * pci=hpmmiosize=nnM overrides non-prefetchable MMIO size,
92  * pci=hpmmioprefsize=nnM overrides prefetchable MMIO size;
93  * pci=hpmemsize=nnM overrides both
94  */
95 unsigned long pci_hotplug_mmio_size = DEFAULT_HOTPLUG_MMIO_SIZE;
96 unsigned long pci_hotplug_mmio_pref_size = DEFAULT_HOTPLUG_MMIO_PREF_SIZE;
97 
98 #define DEFAULT_HOTPLUG_BUS_SIZE	1
99 unsigned long pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE;
100 
101 
102 /* PCIe MPS/MRRS strategy; can be overridden by kernel command-line param */
103 #ifdef CONFIG_PCIE_BUS_TUNE_OFF
104 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_TUNE_OFF;
105 #elif defined CONFIG_PCIE_BUS_SAFE
106 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_SAFE;
107 #elif defined CONFIG_PCIE_BUS_PERFORMANCE
108 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_PERFORMANCE;
109 #elif defined CONFIG_PCIE_BUS_PEER2PEER
110 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_PEER2PEER;
111 #else
112 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_DEFAULT;
113 #endif
114 
115 /*
116  * The default CLS is used if arch didn't set CLS explicitly and not
117  * all pci devices agree on the same value.  Arch can override either
118  * the dfl or actual value as it sees fit.  Don't forget this is
119  * measured in 32-bit words, not bytes.
120  */
121 u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2;
122 u8 pci_cache_line_size;
123 
124 /*
125  * If we set up a device for bus mastering, we need to check the latency
126  * timer as certain BIOSes forget to set it properly.
127  */
128 unsigned int pcibios_max_latency = 255;
129 
130 /* If set, the PCIe ARI capability will not be used. */
131 static bool pcie_ari_disabled;
132 
133 /* If set, the PCIe ATS capability will not be used. */
134 static bool pcie_ats_disabled;
135 
136 /* If set, the PCI config space of each device is printed during boot. */
137 bool pci_early_dump;
138 
139 bool pci_ats_disabled(void)
140 {
141 	return pcie_ats_disabled;
142 }
143 EXPORT_SYMBOL_GPL(pci_ats_disabled);
144 
145 /* Disable bridge_d3 for all PCIe ports */
146 static bool pci_bridge_d3_disable;
147 /* Force bridge_d3 for all PCIe ports */
148 static bool pci_bridge_d3_force;
149 
150 static int __init pcie_port_pm_setup(char *str)
151 {
152 	if (!strcmp(str, "off"))
153 		pci_bridge_d3_disable = true;
154 	else if (!strcmp(str, "force"))
155 		pci_bridge_d3_force = true;
156 	return 1;
157 }
158 __setup("pcie_port_pm=", pcie_port_pm_setup);
159 
160 /* Time to wait after a reset for device to become responsive */
161 #define PCIE_RESET_READY_POLL_MS 60000
162 
163 /**
164  * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
165  * @bus: pointer to PCI bus structure to search
166  *
167  * Given a PCI bus, returns the highest PCI bus number present in the set
168  * including the given PCI bus and its list of child PCI buses.
169  */
170 unsigned char pci_bus_max_busnr(struct pci_bus *bus)
171 {
172 	struct pci_bus *tmp;
173 	unsigned char max, n;
174 
175 	max = bus->busn_res.end;
176 	list_for_each_entry(tmp, &bus->children, node) {
177 		n = pci_bus_max_busnr(tmp);
178 		if (n > max)
179 			max = n;
180 	}
181 	return max;
182 }
183 EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
184 
185 /**
186  * pci_status_get_and_clear_errors - return and clear error bits in PCI_STATUS
187  * @pdev: the PCI device
188  *
189  * Returns error bits set in PCI_STATUS and clears them.
190  */
191 int pci_status_get_and_clear_errors(struct pci_dev *pdev)
192 {
193 	u16 status;
194 	int ret;
195 
196 	ret = pci_read_config_word(pdev, PCI_STATUS, &status);
197 	if (ret != PCIBIOS_SUCCESSFUL)
198 		return -EIO;
199 
200 	status &= PCI_STATUS_ERROR_BITS;
201 	if (status)
202 		pci_write_config_word(pdev, PCI_STATUS, status);
203 
204 	return status;
205 }
206 EXPORT_SYMBOL_GPL(pci_status_get_and_clear_errors);
207 
208 #ifdef CONFIG_HAS_IOMEM
209 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
210 {
211 	struct resource *res = &pdev->resource[bar];
212 
213 	/*
214 	 * Make sure the BAR is actually a memory resource, not an IO resource
215 	 */
216 	if (res->flags & IORESOURCE_UNSET || !(res->flags & IORESOURCE_MEM)) {
217 		pci_warn(pdev, "can't ioremap BAR %d: %pR\n", bar, res);
218 		return NULL;
219 	}
220 	return ioremap(res->start, resource_size(res));
221 }
222 EXPORT_SYMBOL_GPL(pci_ioremap_bar);
223 
224 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar)
225 {
226 	/*
227 	 * Make sure the BAR is actually a memory resource, not an IO resource
228 	 */
229 	if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
230 		WARN_ON(1);
231 		return NULL;
232 	}
233 	return ioremap_wc(pci_resource_start(pdev, bar),
234 			  pci_resource_len(pdev, bar));
235 }
236 EXPORT_SYMBOL_GPL(pci_ioremap_wc_bar);
237 #endif
238 
239 /**
240  * pci_dev_str_match_path - test if a path string matches a device
241  * @dev: the PCI device to test
242  * @path: string to match the device against
243  * @endptr: pointer to the string after the match
244  *
245  * Test if a string (typically from a kernel parameter) formatted as a
246  * path of device/function addresses matches a PCI device. The string must
247  * be of the form:
248  *
249  *   [<domain>:]<bus>:<device>.<func>[/<device>.<func>]*
250  *
251  * A path for a device can be obtained using 'lspci -t'.  Using a path
252  * is more robust against bus renumbering than using only a single bus,
253  * device and function address.
254  *
255  * Returns 1 if the string matches the device, 0 if it does not and
256  * a negative error code if it fails to parse the string.
257  */
258 static int pci_dev_str_match_path(struct pci_dev *dev, const char *path,
259 				  const char **endptr)
260 {
261 	int ret;
262 	int seg, bus, slot, func;
263 	char *wpath, *p;
264 	char end;
265 
266 	*endptr = strchrnul(path, ';');
267 
268 	wpath = kmemdup_nul(path, *endptr - path, GFP_KERNEL);
269 	if (!wpath)
270 		return -ENOMEM;
271 
272 	while (1) {
273 		p = strrchr(wpath, '/');
274 		if (!p)
275 			break;
276 		ret = sscanf(p, "/%x.%x%c", &slot, &func, &end);
277 		if (ret != 2) {
278 			ret = -EINVAL;
279 			goto free_and_exit;
280 		}
281 
282 		if (dev->devfn != PCI_DEVFN(slot, func)) {
283 			ret = 0;
284 			goto free_and_exit;
285 		}
286 
287 		/*
288 		 * Note: we don't need to get a reference to the upstream
289 		 * bridge because we hold a reference to the top level
290 		 * device which should hold a reference to the bridge,
291 		 * and so on.
292 		 */
293 		dev = pci_upstream_bridge(dev);
294 		if (!dev) {
295 			ret = 0;
296 			goto free_and_exit;
297 		}
298 
299 		*p = 0;
300 	}
301 
302 	ret = sscanf(wpath, "%x:%x:%x.%x%c", &seg, &bus, &slot,
303 		     &func, &end);
304 	if (ret != 4) {
305 		seg = 0;
306 		ret = sscanf(wpath, "%x:%x.%x%c", &bus, &slot, &func, &end);
307 		if (ret != 3) {
308 			ret = -EINVAL;
309 			goto free_and_exit;
310 		}
311 	}
312 
313 	ret = (seg == pci_domain_nr(dev->bus) &&
314 	       bus == dev->bus->number &&
315 	       dev->devfn == PCI_DEVFN(slot, func));
316 
317 free_and_exit:
318 	kfree(wpath);
319 	return ret;
320 }
321 
322 /**
323  * pci_dev_str_match - test if a string matches a device
324  * @dev: the PCI device to test
325  * @p: string to match the device against
326  * @endptr: pointer to the string after the match
327  *
328  * Test if a string (typically from a kernel parameter) matches a specified
329  * PCI device. The string may be of one of the following formats:
330  *
331  *   [<domain>:]<bus>:<device>.<func>[/<device>.<func>]*
332  *   pci:<vendor>:<device>[:<subvendor>:<subdevice>]
333  *
334  * The first format specifies a PCI bus/device/function address which
335  * may change if new hardware is inserted, if motherboard firmware changes,
336  * or due to changes caused in kernel parameters. If the domain is
337  * left unspecified, it is taken to be 0.  In order to be robust against
338  * bus renumbering issues, a path of PCI device/function numbers may be used
339  * to address the specific device.  The path for a device can be determined
340  * through the use of 'lspci -t'.
341  *
342  * The second format matches devices using IDs in the configuration
343  * space which may match multiple devices in the system. A value of 0
344  * for any field will match all devices. (Note: this differs from
345  * in-kernel code that uses PCI_ANY_ID which is ~0; this is for
346  * legacy reasons and convenience so users don't have to specify
347  * FFFFFFFFs on the command line.)
348  *
349  * Returns 1 if the string matches the device, 0 if it does not and
350  * a negative error code if the string cannot be parsed.
351  */
352 static int pci_dev_str_match(struct pci_dev *dev, const char *p,
353 			     const char **endptr)
354 {
355 	int ret;
356 	int count;
357 	unsigned short vendor, device, subsystem_vendor, subsystem_device;
358 
359 	if (strncmp(p, "pci:", 4) == 0) {
360 		/* PCI vendor/device (subvendor/subdevice) IDs are specified */
361 		p += 4;
362 		ret = sscanf(p, "%hx:%hx:%hx:%hx%n", &vendor, &device,
363 			     &subsystem_vendor, &subsystem_device, &count);
364 		if (ret != 4) {
365 			ret = sscanf(p, "%hx:%hx%n", &vendor, &device, &count);
366 			if (ret != 2)
367 				return -EINVAL;
368 
369 			subsystem_vendor = 0;
370 			subsystem_device = 0;
371 		}
372 
373 		p += count;
374 
375 		if ((!vendor || vendor == dev->vendor) &&
376 		    (!device || device == dev->device) &&
377 		    (!subsystem_vendor ||
378 			    subsystem_vendor == dev->subsystem_vendor) &&
379 		    (!subsystem_device ||
380 			    subsystem_device == dev->subsystem_device))
381 			goto found;
382 	} else {
383 		/*
384 		 * PCI Bus, Device, Function IDs are specified
385 		 * (optionally, may include a path of devfns following it)
386 		 */
387 		ret = pci_dev_str_match_path(dev, p, &p);
388 		if (ret < 0)
389 			return ret;
390 		else if (ret)
391 			goto found;
392 	}
393 
394 	*endptr = p;
395 	return 0;
396 
397 found:
398 	*endptr = p;
399 	return 1;
400 }
401 
402 static u8 __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
403 				  u8 pos, int cap, int *ttl)
404 {
405 	u8 id;
406 	u16 ent;
407 
408 	pci_bus_read_config_byte(bus, devfn, pos, &pos);
409 
410 	while ((*ttl)--) {
411 		if (pos < 0x40)
412 			break;
413 		pos &= ~3;
414 		pci_bus_read_config_word(bus, devfn, pos, &ent);
415 
416 		id = ent & 0xff;
417 		if (id == 0xff)
418 			break;
419 		if (id == cap)
420 			return pos;
421 		pos = (ent >> 8);
422 	}
423 	return 0;
424 }
425 
426 static u8 __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
427 			      u8 pos, int cap)
428 {
429 	int ttl = PCI_FIND_CAP_TTL;
430 
431 	return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
432 }
433 
434 u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
435 {
436 	return __pci_find_next_cap(dev->bus, dev->devfn,
437 				   pos + PCI_CAP_LIST_NEXT, cap);
438 }
439 EXPORT_SYMBOL_GPL(pci_find_next_capability);
440 
441 static u8 __pci_bus_find_cap_start(struct pci_bus *bus,
442 				    unsigned int devfn, u8 hdr_type)
443 {
444 	u16 status;
445 
446 	pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
447 	if (!(status & PCI_STATUS_CAP_LIST))
448 		return 0;
449 
450 	switch (hdr_type) {
451 	case PCI_HEADER_TYPE_NORMAL:
452 	case PCI_HEADER_TYPE_BRIDGE:
453 		return PCI_CAPABILITY_LIST;
454 	case PCI_HEADER_TYPE_CARDBUS:
455 		return PCI_CB_CAPABILITY_LIST;
456 	}
457 
458 	return 0;
459 }
460 
461 /**
462  * pci_find_capability - query for devices' capabilities
463  * @dev: PCI device to query
464  * @cap: capability code
465  *
466  * Tell if a device supports a given PCI capability.
467  * Returns the address of the requested capability structure within the
468  * device's PCI configuration space or 0 in case the device does not
469  * support it.  Possible values for @cap include:
470  *
471  *  %PCI_CAP_ID_PM           Power Management
472  *  %PCI_CAP_ID_AGP          Accelerated Graphics Port
473  *  %PCI_CAP_ID_VPD          Vital Product Data
474  *  %PCI_CAP_ID_SLOTID       Slot Identification
475  *  %PCI_CAP_ID_MSI          Message Signalled Interrupts
476  *  %PCI_CAP_ID_CHSWP        CompactPCI HotSwap
477  *  %PCI_CAP_ID_PCIX         PCI-X
478  *  %PCI_CAP_ID_EXP          PCI Express
479  */
480 u8 pci_find_capability(struct pci_dev *dev, int cap)
481 {
482 	u8 pos;
483 
484 	pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
485 	if (pos)
486 		pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
487 
488 	return pos;
489 }
490 EXPORT_SYMBOL(pci_find_capability);
491 
492 /**
493  * pci_bus_find_capability - query for devices' capabilities
494  * @bus: the PCI bus to query
495  * @devfn: PCI device to query
496  * @cap: capability code
497  *
498  * Like pci_find_capability() but works for PCI devices that do not have a
499  * pci_dev structure set up yet.
500  *
501  * Returns the address of the requested capability structure within the
502  * device's PCI configuration space or 0 in case the device does not
503  * support it.
504  */
505 u8 pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
506 {
507 	u8 hdr_type, pos;
508 
509 	pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
510 
511 	pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
512 	if (pos)
513 		pos = __pci_find_next_cap(bus, devfn, pos, cap);
514 
515 	return pos;
516 }
517 EXPORT_SYMBOL(pci_bus_find_capability);
518 
519 /**
520  * pci_find_next_ext_capability - Find an extended capability
521  * @dev: PCI device to query
522  * @start: address at which to start looking (0 to start at beginning of list)
523  * @cap: capability code
524  *
525  * Returns the address of the next matching extended capability structure
526  * within the device's PCI configuration space or 0 if the device does
527  * not support it.  Some capabilities can occur several times, e.g., the
528  * vendor-specific capability, and this provides a way to find them all.
529  */
530 u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 start, int cap)
531 {
532 	u32 header;
533 	int ttl;
534 	u16 pos = PCI_CFG_SPACE_SIZE;
535 
536 	/* minimum 8 bytes per capability */
537 	ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
538 
539 	if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
540 		return 0;
541 
542 	if (start)
543 		pos = start;
544 
545 	if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
546 		return 0;
547 
548 	/*
549 	 * If we have no capabilities, this is indicated by cap ID,
550 	 * cap version and next pointer all being 0.
551 	 */
552 	if (header == 0)
553 		return 0;
554 
555 	while (ttl-- > 0) {
556 		if (PCI_EXT_CAP_ID(header) == cap && pos != start)
557 			return pos;
558 
559 		pos = PCI_EXT_CAP_NEXT(header);
560 		if (pos < PCI_CFG_SPACE_SIZE)
561 			break;
562 
563 		if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
564 			break;
565 	}
566 
567 	return 0;
568 }
569 EXPORT_SYMBOL_GPL(pci_find_next_ext_capability);
570 
571 /**
572  * pci_find_ext_capability - Find an extended capability
573  * @dev: PCI device to query
574  * @cap: capability code
575  *
576  * Returns the address of the requested extended capability structure
577  * within the device's PCI configuration space or 0 if the device does
578  * not support it.  Possible values for @cap include:
579  *
580  *  %PCI_EXT_CAP_ID_ERR		Advanced Error Reporting
581  *  %PCI_EXT_CAP_ID_VC		Virtual Channel
582  *  %PCI_EXT_CAP_ID_DSN		Device Serial Number
583  *  %PCI_EXT_CAP_ID_PWR		Power Budgeting
584  */
585 u16 pci_find_ext_capability(struct pci_dev *dev, int cap)
586 {
587 	return pci_find_next_ext_capability(dev, 0, cap);
588 }
589 EXPORT_SYMBOL_GPL(pci_find_ext_capability);
590 
591 /**
592  * pci_get_dsn - Read and return the 8-byte Device Serial Number
593  * @dev: PCI device to query
594  *
595  * Looks up the PCI_EXT_CAP_ID_DSN and reads the 8 bytes of the Device Serial
596  * Number.
597  *
598  * Returns the DSN, or zero if the capability does not exist.
599  */
600 u64 pci_get_dsn(struct pci_dev *dev)
601 {
602 	u32 dword;
603 	u64 dsn;
604 	int pos;
605 
606 	pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DSN);
607 	if (!pos)
608 		return 0;
609 
610 	/*
611 	 * The Device Serial Number is two dwords offset 4 bytes from the
612 	 * capability position. The specification says that the first dword is
613 	 * the lower half, and the second dword is the upper half.
614 	 */
615 	pos += 4;
616 	pci_read_config_dword(dev, pos, &dword);
617 	dsn = (u64)dword;
618 	pci_read_config_dword(dev, pos + 4, &dword);
619 	dsn |= ((u64)dword) << 32;
620 
621 	return dsn;
622 }
623 EXPORT_SYMBOL_GPL(pci_get_dsn);
624 
625 static u8 __pci_find_next_ht_cap(struct pci_dev *dev, u8 pos, int ht_cap)
626 {
627 	int rc, ttl = PCI_FIND_CAP_TTL;
628 	u8 cap, mask;
629 
630 	if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
631 		mask = HT_3BIT_CAP_MASK;
632 	else
633 		mask = HT_5BIT_CAP_MASK;
634 
635 	pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
636 				      PCI_CAP_ID_HT, &ttl);
637 	while (pos) {
638 		rc = pci_read_config_byte(dev, pos + 3, &cap);
639 		if (rc != PCIBIOS_SUCCESSFUL)
640 			return 0;
641 
642 		if ((cap & mask) == ht_cap)
643 			return pos;
644 
645 		pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
646 					      pos + PCI_CAP_LIST_NEXT,
647 					      PCI_CAP_ID_HT, &ttl);
648 	}
649 
650 	return 0;
651 }
652 
653 /**
654  * pci_find_next_ht_capability - query a device's HyperTransport capabilities
655  * @dev: PCI device to query
656  * @pos: Position from which to continue searching
657  * @ht_cap: HyperTransport capability code
658  *
659  * To be used in conjunction with pci_find_ht_capability() to search for
660  * all capabilities matching @ht_cap. @pos should always be a value returned
661  * from pci_find_ht_capability().
662  *
663  * NB. To be 100% safe against broken PCI devices, the caller should take
664  * steps to avoid an infinite loop.
665  */
666 u8 pci_find_next_ht_capability(struct pci_dev *dev, u8 pos, int ht_cap)
667 {
668 	return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
669 }
670 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
671 
672 /**
673  * pci_find_ht_capability - query a device's HyperTransport capabilities
674  * @dev: PCI device to query
675  * @ht_cap: HyperTransport capability code
676  *
677  * Tell if a device supports a given HyperTransport capability.
678  * Returns an address within the device's PCI configuration space
679  * or 0 in case the device does not support the request capability.
680  * The address points to the PCI capability, of type PCI_CAP_ID_HT,
681  * which has a HyperTransport capability matching @ht_cap.
682  */
683 u8 pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
684 {
685 	u8 pos;
686 
687 	pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
688 	if (pos)
689 		pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
690 
691 	return pos;
692 }
693 EXPORT_SYMBOL_GPL(pci_find_ht_capability);
694 
695 /**
696  * pci_find_vsec_capability - Find a vendor-specific extended capability
697  * @dev: PCI device to query
698  * @vendor: Vendor ID for which capability is defined
699  * @cap: Vendor-specific capability ID
700  *
701  * If @dev has Vendor ID @vendor, search for a VSEC capability with
702  * VSEC ID @cap. If found, return the capability offset in
703  * config space; otherwise return 0.
704  */
705 u16 pci_find_vsec_capability(struct pci_dev *dev, u16 vendor, int cap)
706 {
707 	u16 vsec = 0;
708 	u32 header;
709 
710 	if (vendor != dev->vendor)
711 		return 0;
712 
713 	while ((vsec = pci_find_next_ext_capability(dev, vsec,
714 						     PCI_EXT_CAP_ID_VNDR))) {
715 		if (pci_read_config_dword(dev, vsec + PCI_VNDR_HEADER,
716 					  &header) == PCIBIOS_SUCCESSFUL &&
717 		    PCI_VNDR_HEADER_ID(header) == cap)
718 			return vsec;
719 	}
720 
721 	return 0;
722 }
723 EXPORT_SYMBOL_GPL(pci_find_vsec_capability);
724 
725 /**
726  * pci_find_parent_resource - return resource region of parent bus of given
727  *			      region
728  * @dev: PCI device structure contains resources to be searched
729  * @res: child resource record for which parent is sought
730  *
731  * For given resource region of given device, return the resource region of
732  * parent bus the given region is contained in.
733  */
734 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
735 					  struct resource *res)
736 {
737 	const struct pci_bus *bus = dev->bus;
738 	struct resource *r;
739 	int i;
740 
741 	pci_bus_for_each_resource(bus, r, i) {
742 		if (!r)
743 			continue;
744 		if (resource_contains(r, res)) {
745 
746 			/*
747 			 * If the window is prefetchable but the BAR is
748 			 * not, the allocator made a mistake.
749 			 */
750 			if (r->flags & IORESOURCE_PREFETCH &&
751 			    !(res->flags & IORESOURCE_PREFETCH))
752 				return NULL;
753 
754 			/*
755 			 * If we're below a transparent bridge, there may
756 			 * be both a positively-decoded aperture and a
757 			 * subtractively-decoded region that contain the BAR.
758 			 * We want the positively-decoded one, so this depends
759 			 * on pci_bus_for_each_resource() giving us those
760 			 * first.
761 			 */
762 			return r;
763 		}
764 	}
765 	return NULL;
766 }
767 EXPORT_SYMBOL(pci_find_parent_resource);
768 
769 /**
770  * pci_find_resource - Return matching PCI device resource
771  * @dev: PCI device to query
772  * @res: Resource to look for
773  *
774  * Goes over standard PCI resources (BARs) and checks if the given resource
775  * is partially or fully contained in any of them. In that case the
776  * matching resource is returned, %NULL otherwise.
777  */
778 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res)
779 {
780 	int i;
781 
782 	for (i = 0; i < PCI_STD_NUM_BARS; i++) {
783 		struct resource *r = &dev->resource[i];
784 
785 		if (r->start && resource_contains(r, res))
786 			return r;
787 	}
788 
789 	return NULL;
790 }
791 EXPORT_SYMBOL(pci_find_resource);
792 
793 /**
794  * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos
795  * @dev: the PCI device to operate on
796  * @pos: config space offset of status word
797  * @mask: mask of bit(s) to care about in status word
798  *
799  * Return 1 when mask bit(s) in status word clear, 0 otherwise.
800  */
801 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask)
802 {
803 	int i;
804 
805 	/* Wait for Transaction Pending bit clean */
806 	for (i = 0; i < 4; i++) {
807 		u16 status;
808 		if (i)
809 			msleep((1 << (i - 1)) * 100);
810 
811 		pci_read_config_word(dev, pos, &status);
812 		if (!(status & mask))
813 			return 1;
814 	}
815 
816 	return 0;
817 }
818 
819 static int pci_acs_enable;
820 
821 /**
822  * pci_request_acs - ask for ACS to be enabled if supported
823  */
824 void pci_request_acs(void)
825 {
826 	pci_acs_enable = 1;
827 }
828 
829 static const char *disable_acs_redir_param;
830 
831 /**
832  * pci_disable_acs_redir - disable ACS redirect capabilities
833  * @dev: the PCI device
834  *
835  * For only devices specified in the disable_acs_redir parameter.
836  */
837 static void pci_disable_acs_redir(struct pci_dev *dev)
838 {
839 	int ret = 0;
840 	const char *p;
841 	int pos;
842 	u16 ctrl;
843 
844 	if (!disable_acs_redir_param)
845 		return;
846 
847 	p = disable_acs_redir_param;
848 	while (*p) {
849 		ret = pci_dev_str_match(dev, p, &p);
850 		if (ret < 0) {
851 			pr_info_once("PCI: Can't parse disable_acs_redir parameter: %s\n",
852 				     disable_acs_redir_param);
853 
854 			break;
855 		} else if (ret == 1) {
856 			/* Found a match */
857 			break;
858 		}
859 
860 		if (*p != ';' && *p != ',') {
861 			/* End of param or invalid format */
862 			break;
863 		}
864 		p++;
865 	}
866 
867 	if (ret != 1)
868 		return;
869 
870 	if (!pci_dev_specific_disable_acs_redir(dev))
871 		return;
872 
873 	pos = dev->acs_cap;
874 	if (!pos) {
875 		pci_warn(dev, "cannot disable ACS redirect for this hardware as it does not have ACS capabilities\n");
876 		return;
877 	}
878 
879 	pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
880 
881 	/* P2P Request & Completion Redirect */
882 	ctrl &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC);
883 
884 	pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
885 
886 	pci_info(dev, "disabled ACS redirect\n");
887 }
888 
889 /**
890  * pci_std_enable_acs - enable ACS on devices using standard ACS capabilities
891  * @dev: the PCI device
892  */
893 static void pci_std_enable_acs(struct pci_dev *dev)
894 {
895 	int pos;
896 	u16 cap;
897 	u16 ctrl;
898 
899 	pos = dev->acs_cap;
900 	if (!pos)
901 		return;
902 
903 	pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
904 	pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
905 
906 	/* Source Validation */
907 	ctrl |= (cap & PCI_ACS_SV);
908 
909 	/* P2P Request Redirect */
910 	ctrl |= (cap & PCI_ACS_RR);
911 
912 	/* P2P Completion Redirect */
913 	ctrl |= (cap & PCI_ACS_CR);
914 
915 	/* Upstream Forwarding */
916 	ctrl |= (cap & PCI_ACS_UF);
917 
918 	/* Enable Translation Blocking for external devices */
919 	if (dev->external_facing || dev->untrusted)
920 		ctrl |= (cap & PCI_ACS_TB);
921 
922 	pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
923 }
924 
925 /**
926  * pci_enable_acs - enable ACS if hardware support it
927  * @dev: the PCI device
928  */
929 static void pci_enable_acs(struct pci_dev *dev)
930 {
931 	if (!pci_acs_enable)
932 		goto disable_acs_redir;
933 
934 	if (!pci_dev_specific_enable_acs(dev))
935 		goto disable_acs_redir;
936 
937 	pci_std_enable_acs(dev);
938 
939 disable_acs_redir:
940 	/*
941 	 * Note: pci_disable_acs_redir() must be called even if ACS was not
942 	 * enabled by the kernel because it may have been enabled by
943 	 * platform firmware.  So if we are told to disable it, we should
944 	 * always disable it after setting the kernel's default
945 	 * preferences.
946 	 */
947 	pci_disable_acs_redir(dev);
948 }
949 
950 /**
951  * pci_restore_bars - restore a device's BAR values (e.g. after wake-up)
952  * @dev: PCI device to have its BARs restored
953  *
954  * Restore the BAR values for a given device, so as to make it
955  * accessible by its driver.
956  */
957 static void pci_restore_bars(struct pci_dev *dev)
958 {
959 	int i;
960 
961 	for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
962 		pci_update_resource(dev, i);
963 }
964 
965 static const struct pci_platform_pm_ops *pci_platform_pm;
966 
967 int pci_set_platform_pm(const struct pci_platform_pm_ops *ops)
968 {
969 	if (!ops->is_manageable || !ops->set_state  || !ops->get_state ||
970 	    !ops->choose_state  || !ops->set_wakeup || !ops->need_resume)
971 		return -EINVAL;
972 	pci_platform_pm = ops;
973 	return 0;
974 }
975 
976 static inline bool platform_pci_power_manageable(struct pci_dev *dev)
977 {
978 	return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
979 }
980 
981 static inline int platform_pci_set_power_state(struct pci_dev *dev,
982 					       pci_power_t t)
983 {
984 	return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
985 }
986 
987 static inline pci_power_t platform_pci_get_power_state(struct pci_dev *dev)
988 {
989 	return pci_platform_pm ? pci_platform_pm->get_state(dev) : PCI_UNKNOWN;
990 }
991 
992 static inline void platform_pci_refresh_power_state(struct pci_dev *dev)
993 {
994 	if (pci_platform_pm && pci_platform_pm->refresh_state)
995 		pci_platform_pm->refresh_state(dev);
996 }
997 
998 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
999 {
1000 	return pci_platform_pm ?
1001 			pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
1002 }
1003 
1004 static inline int platform_pci_set_wakeup(struct pci_dev *dev, bool enable)
1005 {
1006 	return pci_platform_pm ?
1007 			pci_platform_pm->set_wakeup(dev, enable) : -ENODEV;
1008 }
1009 
1010 static inline bool platform_pci_need_resume(struct pci_dev *dev)
1011 {
1012 	return pci_platform_pm ? pci_platform_pm->need_resume(dev) : false;
1013 }
1014 
1015 static inline bool platform_pci_bridge_d3(struct pci_dev *dev)
1016 {
1017 	if (pci_platform_pm && pci_platform_pm->bridge_d3)
1018 		return pci_platform_pm->bridge_d3(dev);
1019 	return false;
1020 }
1021 
1022 /**
1023  * pci_raw_set_power_state - Use PCI PM registers to set the power state of
1024  *			     given PCI device
1025  * @dev: PCI device to handle.
1026  * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
1027  *
1028  * RETURN VALUE:
1029  * -EINVAL if the requested state is invalid.
1030  * -EIO if device does not support PCI PM or its PM capabilities register has a
1031  * wrong version, or device doesn't support the requested state.
1032  * 0 if device already is in the requested state.
1033  * 0 if device's power state has been successfully changed.
1034  */
1035 static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
1036 {
1037 	u16 pmcsr;
1038 	bool need_restore = false;
1039 
1040 	/* Check if we're already there */
1041 	if (dev->current_state == state)
1042 		return 0;
1043 
1044 	if (!dev->pm_cap)
1045 		return -EIO;
1046 
1047 	if (state < PCI_D0 || state > PCI_D3hot)
1048 		return -EINVAL;
1049 
1050 	/*
1051 	 * Validate transition: We can enter D0 from any state, but if
1052 	 * we're already in a low-power state, we can only go deeper.  E.g.,
1053 	 * we can go from D1 to D3, but we can't go directly from D3 to D1;
1054 	 * we'd have to go from D3 to D0, then to D1.
1055 	 */
1056 	if (state != PCI_D0 && dev->current_state <= PCI_D3cold
1057 	    && dev->current_state > state) {
1058 		pci_err(dev, "invalid power transition (from %s to %s)\n",
1059 			pci_power_name(dev->current_state),
1060 			pci_power_name(state));
1061 		return -EINVAL;
1062 	}
1063 
1064 	/* Check if this device supports the desired state */
1065 	if ((state == PCI_D1 && !dev->d1_support)
1066 	   || (state == PCI_D2 && !dev->d2_support))
1067 		return -EIO;
1068 
1069 	pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1070 	if (pmcsr == (u16) ~0) {
1071 		pci_err(dev, "can't change power state from %s to %s (config space inaccessible)\n",
1072 			pci_power_name(dev->current_state),
1073 			pci_power_name(state));
1074 		return -EIO;
1075 	}
1076 
1077 	/*
1078 	 * If we're (effectively) in D3, force entire word to 0.
1079 	 * This doesn't affect PME_Status, disables PME_En, and
1080 	 * sets PowerState to 0.
1081 	 */
1082 	switch (dev->current_state) {
1083 	case PCI_D0:
1084 	case PCI_D1:
1085 	case PCI_D2:
1086 		pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
1087 		pmcsr |= state;
1088 		break;
1089 	case PCI_D3hot:
1090 	case PCI_D3cold:
1091 	case PCI_UNKNOWN: /* Boot-up */
1092 		if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
1093 		 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
1094 			need_restore = true;
1095 		fallthrough;	/* force to D0 */
1096 	default:
1097 		pmcsr = 0;
1098 		break;
1099 	}
1100 
1101 	/* Enter specified state */
1102 	pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1103 
1104 	/*
1105 	 * Mandatory power management transition delays; see PCI PM 1.1
1106 	 * 5.6.1 table 18
1107 	 */
1108 	if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
1109 		pci_dev_d3_sleep(dev);
1110 	else if (state == PCI_D2 || dev->current_state == PCI_D2)
1111 		udelay(PCI_PM_D2_DELAY);
1112 
1113 	pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1114 	dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
1115 	if (dev->current_state != state)
1116 		pci_info_ratelimited(dev, "refused to change power state from %s to %s\n",
1117 			 pci_power_name(dev->current_state),
1118 			 pci_power_name(state));
1119 
1120 	/*
1121 	 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
1122 	 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
1123 	 * from D3hot to D0 _may_ perform an internal reset, thereby
1124 	 * going to "D0 Uninitialized" rather than "D0 Initialized".
1125 	 * For example, at least some versions of the 3c905B and the
1126 	 * 3c556B exhibit this behaviour.
1127 	 *
1128 	 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
1129 	 * devices in a D3hot state at boot.  Consequently, we need to
1130 	 * restore at least the BARs so that the device will be
1131 	 * accessible to its driver.
1132 	 */
1133 	if (need_restore)
1134 		pci_restore_bars(dev);
1135 
1136 	if (dev->bus->self)
1137 		pcie_aspm_pm_state_change(dev->bus->self);
1138 
1139 	return 0;
1140 }
1141 
1142 /**
1143  * pci_update_current_state - Read power state of given device and cache it
1144  * @dev: PCI device to handle.
1145  * @state: State to cache in case the device doesn't have the PM capability
1146  *
1147  * The power state is read from the PMCSR register, which however is
1148  * inaccessible in D3cold.  The platform firmware is therefore queried first
1149  * to detect accessibility of the register.  In case the platform firmware
1150  * reports an incorrect state or the device isn't power manageable by the
1151  * platform at all, we try to detect D3cold by testing accessibility of the
1152  * vendor ID in config space.
1153  */
1154 void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
1155 {
1156 	if (platform_pci_get_power_state(dev) == PCI_D3cold ||
1157 	    !pci_device_is_present(dev)) {
1158 		dev->current_state = PCI_D3cold;
1159 	} else if (dev->pm_cap) {
1160 		u16 pmcsr;
1161 
1162 		pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1163 		dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
1164 	} else {
1165 		dev->current_state = state;
1166 	}
1167 }
1168 
1169 /**
1170  * pci_refresh_power_state - Refresh the given device's power state data
1171  * @dev: Target PCI device.
1172  *
1173  * Ask the platform to refresh the devices power state information and invoke
1174  * pci_update_current_state() to update its current PCI power state.
1175  */
1176 void pci_refresh_power_state(struct pci_dev *dev)
1177 {
1178 	if (platform_pci_power_manageable(dev))
1179 		platform_pci_refresh_power_state(dev);
1180 
1181 	pci_update_current_state(dev, dev->current_state);
1182 }
1183 
1184 /**
1185  * pci_platform_power_transition - Use platform to change device power state
1186  * @dev: PCI device to handle.
1187  * @state: State to put the device into.
1188  */
1189 int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
1190 {
1191 	int error;
1192 
1193 	if (platform_pci_power_manageable(dev)) {
1194 		error = platform_pci_set_power_state(dev, state);
1195 		if (!error)
1196 			pci_update_current_state(dev, state);
1197 	} else
1198 		error = -ENODEV;
1199 
1200 	if (error && !dev->pm_cap) /* Fall back to PCI_D0 */
1201 		dev->current_state = PCI_D0;
1202 
1203 	return error;
1204 }
1205 EXPORT_SYMBOL_GPL(pci_platform_power_transition);
1206 
1207 static int pci_resume_one(struct pci_dev *pci_dev, void *ign)
1208 {
1209 	pm_request_resume(&pci_dev->dev);
1210 	return 0;
1211 }
1212 
1213 /**
1214  * pci_resume_bus - Walk given bus and runtime resume devices on it
1215  * @bus: Top bus of the subtree to walk.
1216  */
1217 void pci_resume_bus(struct pci_bus *bus)
1218 {
1219 	if (bus)
1220 		pci_walk_bus(bus, pci_resume_one, NULL);
1221 }
1222 
1223 static int pci_dev_wait(struct pci_dev *dev, char *reset_type, int timeout)
1224 {
1225 	int delay = 1;
1226 	u32 id;
1227 
1228 	/*
1229 	 * After reset, the device should not silently discard config
1230 	 * requests, but it may still indicate that it needs more time by
1231 	 * responding to them with CRS completions.  The Root Port will
1232 	 * generally synthesize ~0 data to complete the read (except when
1233 	 * CRS SV is enabled and the read was for the Vendor ID; in that
1234 	 * case it synthesizes 0x0001 data).
1235 	 *
1236 	 * Wait for the device to return a non-CRS completion.  Read the
1237 	 * Command register instead of Vendor ID so we don't have to
1238 	 * contend with the CRS SV value.
1239 	 */
1240 	pci_read_config_dword(dev, PCI_COMMAND, &id);
1241 	while (id == ~0) {
1242 		if (delay > timeout) {
1243 			pci_warn(dev, "not ready %dms after %s; giving up\n",
1244 				 delay - 1, reset_type);
1245 			return -ENOTTY;
1246 		}
1247 
1248 		if (delay > 1000)
1249 			pci_info(dev, "not ready %dms after %s; waiting\n",
1250 				 delay - 1, reset_type);
1251 
1252 		msleep(delay);
1253 		delay *= 2;
1254 		pci_read_config_dword(dev, PCI_COMMAND, &id);
1255 	}
1256 
1257 	if (delay > 1000)
1258 		pci_info(dev, "ready %dms after %s\n", delay - 1,
1259 			 reset_type);
1260 
1261 	return 0;
1262 }
1263 
1264 /**
1265  * pci_power_up - Put the given device into D0
1266  * @dev: PCI device to power up
1267  */
1268 int pci_power_up(struct pci_dev *dev)
1269 {
1270 	pci_platform_power_transition(dev, PCI_D0);
1271 
1272 	/*
1273 	 * Mandatory power management transition delays are handled in
1274 	 * pci_pm_resume_noirq() and pci_pm_runtime_resume() of the
1275 	 * corresponding bridge.
1276 	 */
1277 	if (dev->runtime_d3cold) {
1278 		/*
1279 		 * When powering on a bridge from D3cold, the whole hierarchy
1280 		 * may be powered on into D0uninitialized state, resume them to
1281 		 * give them a chance to suspend again
1282 		 */
1283 		pci_resume_bus(dev->subordinate);
1284 	}
1285 
1286 	return pci_raw_set_power_state(dev, PCI_D0);
1287 }
1288 
1289 /**
1290  * __pci_dev_set_current_state - Set current state of a PCI device
1291  * @dev: Device to handle
1292  * @data: pointer to state to be set
1293  */
1294 static int __pci_dev_set_current_state(struct pci_dev *dev, void *data)
1295 {
1296 	pci_power_t state = *(pci_power_t *)data;
1297 
1298 	dev->current_state = state;
1299 	return 0;
1300 }
1301 
1302 /**
1303  * pci_bus_set_current_state - Walk given bus and set current state of devices
1304  * @bus: Top bus of the subtree to walk.
1305  * @state: state to be set
1306  */
1307 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state)
1308 {
1309 	if (bus)
1310 		pci_walk_bus(bus, __pci_dev_set_current_state, &state);
1311 }
1312 
1313 /**
1314  * pci_set_power_state - Set the power state of a PCI device
1315  * @dev: PCI device to handle.
1316  * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
1317  *
1318  * Transition a device to a new power state, using the platform firmware and/or
1319  * the device's PCI PM registers.
1320  *
1321  * RETURN VALUE:
1322  * -EINVAL if the requested state is invalid.
1323  * -EIO if device does not support PCI PM or its PM capabilities register has a
1324  * wrong version, or device doesn't support the requested state.
1325  * 0 if the transition is to D1 or D2 but D1 and D2 are not supported.
1326  * 0 if device already is in the requested state.
1327  * 0 if the transition is to D3 but D3 is not supported.
1328  * 0 if device's power state has been successfully changed.
1329  */
1330 int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1331 {
1332 	int error;
1333 
1334 	/* Bound the state we're entering */
1335 	if (state > PCI_D3cold)
1336 		state = PCI_D3cold;
1337 	else if (state < PCI_D0)
1338 		state = PCI_D0;
1339 	else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
1340 
1341 		/*
1342 		 * If the device or the parent bridge do not support PCI
1343 		 * PM, ignore the request if we're doing anything other
1344 		 * than putting it into D0 (which would only happen on
1345 		 * boot).
1346 		 */
1347 		return 0;
1348 
1349 	/* Check if we're already there */
1350 	if (dev->current_state == state)
1351 		return 0;
1352 
1353 	if (state == PCI_D0)
1354 		return pci_power_up(dev);
1355 
1356 	/*
1357 	 * This device is quirked not to be put into D3, so don't put it in
1358 	 * D3
1359 	 */
1360 	if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
1361 		return 0;
1362 
1363 	/*
1364 	 * To put device in D3cold, we put device into D3hot in native
1365 	 * way, then put device into D3cold with platform ops
1366 	 */
1367 	error = pci_raw_set_power_state(dev, state > PCI_D3hot ?
1368 					PCI_D3hot : state);
1369 
1370 	if (pci_platform_power_transition(dev, state))
1371 		return error;
1372 
1373 	/* Powering off a bridge may power off the whole hierarchy */
1374 	if (state == PCI_D3cold)
1375 		pci_bus_set_current_state(dev->subordinate, PCI_D3cold);
1376 
1377 	return 0;
1378 }
1379 EXPORT_SYMBOL(pci_set_power_state);
1380 
1381 /**
1382  * pci_choose_state - Choose the power state of a PCI device
1383  * @dev: PCI device to be suspended
1384  * @state: target sleep state for the whole system. This is the value
1385  *	   that is passed to suspend() function.
1386  *
1387  * Returns PCI power state suitable for given device and given system
1388  * message.
1389  */
1390 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
1391 {
1392 	pci_power_t ret;
1393 
1394 	if (!dev->pm_cap)
1395 		return PCI_D0;
1396 
1397 	ret = platform_pci_choose_state(dev);
1398 	if (ret != PCI_POWER_ERROR)
1399 		return ret;
1400 
1401 	switch (state.event) {
1402 	case PM_EVENT_ON:
1403 		return PCI_D0;
1404 	case PM_EVENT_FREEZE:
1405 	case PM_EVENT_PRETHAW:
1406 		/* REVISIT both freeze and pre-thaw "should" use D0 */
1407 	case PM_EVENT_SUSPEND:
1408 	case PM_EVENT_HIBERNATE:
1409 		return PCI_D3hot;
1410 	default:
1411 		pci_info(dev, "unrecognized suspend event %d\n",
1412 			 state.event);
1413 		BUG();
1414 	}
1415 	return PCI_D0;
1416 }
1417 EXPORT_SYMBOL(pci_choose_state);
1418 
1419 #define PCI_EXP_SAVE_REGS	7
1420 
1421 static struct pci_cap_saved_state *_pci_find_saved_cap(struct pci_dev *pci_dev,
1422 						       u16 cap, bool extended)
1423 {
1424 	struct pci_cap_saved_state *tmp;
1425 
1426 	hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) {
1427 		if (tmp->cap.cap_extended == extended && tmp->cap.cap_nr == cap)
1428 			return tmp;
1429 	}
1430 	return NULL;
1431 }
1432 
1433 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap)
1434 {
1435 	return _pci_find_saved_cap(dev, cap, false);
1436 }
1437 
1438 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, u16 cap)
1439 {
1440 	return _pci_find_saved_cap(dev, cap, true);
1441 }
1442 
1443 static int pci_save_pcie_state(struct pci_dev *dev)
1444 {
1445 	int i = 0;
1446 	struct pci_cap_saved_state *save_state;
1447 	u16 *cap;
1448 
1449 	if (!pci_is_pcie(dev))
1450 		return 0;
1451 
1452 	save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
1453 	if (!save_state) {
1454 		pci_err(dev, "buffer not found in %s\n", __func__);
1455 		return -ENOMEM;
1456 	}
1457 
1458 	cap = (u16 *)&save_state->cap.data[0];
1459 	pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]);
1460 	pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]);
1461 	pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]);
1462 	pcie_capability_read_word(dev, PCI_EXP_RTCTL,  &cap[i++]);
1463 	pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]);
1464 	pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]);
1465 	pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]);
1466 
1467 	return 0;
1468 }
1469 
1470 static void pci_restore_pcie_state(struct pci_dev *dev)
1471 {
1472 	int i = 0;
1473 	struct pci_cap_saved_state *save_state;
1474 	u16 *cap;
1475 
1476 	save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
1477 	if (!save_state)
1478 		return;
1479 
1480 	cap = (u16 *)&save_state->cap.data[0];
1481 	pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]);
1482 	pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]);
1483 	pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]);
1484 	pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]);
1485 	pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]);
1486 	pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]);
1487 	pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]);
1488 }
1489 
1490 static int pci_save_pcix_state(struct pci_dev *dev)
1491 {
1492 	int pos;
1493 	struct pci_cap_saved_state *save_state;
1494 
1495 	pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1496 	if (!pos)
1497 		return 0;
1498 
1499 	save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1500 	if (!save_state) {
1501 		pci_err(dev, "buffer not found in %s\n", __func__);
1502 		return -ENOMEM;
1503 	}
1504 
1505 	pci_read_config_word(dev, pos + PCI_X_CMD,
1506 			     (u16 *)save_state->cap.data);
1507 
1508 	return 0;
1509 }
1510 
1511 static void pci_restore_pcix_state(struct pci_dev *dev)
1512 {
1513 	int i = 0, pos;
1514 	struct pci_cap_saved_state *save_state;
1515 	u16 *cap;
1516 
1517 	save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1518 	pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1519 	if (!save_state || !pos)
1520 		return;
1521 	cap = (u16 *)&save_state->cap.data[0];
1522 
1523 	pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
1524 }
1525 
1526 static void pci_save_ltr_state(struct pci_dev *dev)
1527 {
1528 	int ltr;
1529 	struct pci_cap_saved_state *save_state;
1530 	u16 *cap;
1531 
1532 	if (!pci_is_pcie(dev))
1533 		return;
1534 
1535 	ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
1536 	if (!ltr)
1537 		return;
1538 
1539 	save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR);
1540 	if (!save_state) {
1541 		pci_err(dev, "no suspend buffer for LTR; ASPM issues possible after resume\n");
1542 		return;
1543 	}
1544 
1545 	cap = (u16 *)&save_state->cap.data[0];
1546 	pci_read_config_word(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, cap++);
1547 	pci_read_config_word(dev, ltr + PCI_LTR_MAX_NOSNOOP_LAT, cap++);
1548 }
1549 
1550 static void pci_restore_ltr_state(struct pci_dev *dev)
1551 {
1552 	struct pci_cap_saved_state *save_state;
1553 	int ltr;
1554 	u16 *cap;
1555 
1556 	save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR);
1557 	ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
1558 	if (!save_state || !ltr)
1559 		return;
1560 
1561 	cap = (u16 *)&save_state->cap.data[0];
1562 	pci_write_config_word(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, *cap++);
1563 	pci_write_config_word(dev, ltr + PCI_LTR_MAX_NOSNOOP_LAT, *cap++);
1564 }
1565 
1566 /**
1567  * pci_save_state - save the PCI configuration space of a device before
1568  *		    suspending
1569  * @dev: PCI device that we're dealing with
1570  */
1571 int pci_save_state(struct pci_dev *dev)
1572 {
1573 	int i;
1574 	/* XXX: 100% dword access ok here? */
1575 	for (i = 0; i < 16; i++) {
1576 		pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
1577 		pci_dbg(dev, "saving config space at offset %#x (reading %#x)\n",
1578 			i * 4, dev->saved_config_space[i]);
1579 	}
1580 	dev->state_saved = true;
1581 
1582 	i = pci_save_pcie_state(dev);
1583 	if (i != 0)
1584 		return i;
1585 
1586 	i = pci_save_pcix_state(dev);
1587 	if (i != 0)
1588 		return i;
1589 
1590 	pci_save_ltr_state(dev);
1591 	pci_save_dpc_state(dev);
1592 	pci_save_aer_state(dev);
1593 	pci_save_ptm_state(dev);
1594 	return pci_save_vc_state(dev);
1595 }
1596 EXPORT_SYMBOL(pci_save_state);
1597 
1598 static void pci_restore_config_dword(struct pci_dev *pdev, int offset,
1599 				     u32 saved_val, int retry, bool force)
1600 {
1601 	u32 val;
1602 
1603 	pci_read_config_dword(pdev, offset, &val);
1604 	if (!force && val == saved_val)
1605 		return;
1606 
1607 	for (;;) {
1608 		pci_dbg(pdev, "restoring config space at offset %#x (was %#x, writing %#x)\n",
1609 			offset, val, saved_val);
1610 		pci_write_config_dword(pdev, offset, saved_val);
1611 		if (retry-- <= 0)
1612 			return;
1613 
1614 		pci_read_config_dword(pdev, offset, &val);
1615 		if (val == saved_val)
1616 			return;
1617 
1618 		mdelay(1);
1619 	}
1620 }
1621 
1622 static void pci_restore_config_space_range(struct pci_dev *pdev,
1623 					   int start, int end, int retry,
1624 					   bool force)
1625 {
1626 	int index;
1627 
1628 	for (index = end; index >= start; index--)
1629 		pci_restore_config_dword(pdev, 4 * index,
1630 					 pdev->saved_config_space[index],
1631 					 retry, force);
1632 }
1633 
1634 static void pci_restore_config_space(struct pci_dev *pdev)
1635 {
1636 	if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) {
1637 		pci_restore_config_space_range(pdev, 10, 15, 0, false);
1638 		/* Restore BARs before the command register. */
1639 		pci_restore_config_space_range(pdev, 4, 9, 10, false);
1640 		pci_restore_config_space_range(pdev, 0, 3, 0, false);
1641 	} else if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
1642 		pci_restore_config_space_range(pdev, 12, 15, 0, false);
1643 
1644 		/*
1645 		 * Force rewriting of prefetch registers to avoid S3 resume
1646 		 * issues on Intel PCI bridges that occur when these
1647 		 * registers are not explicitly written.
1648 		 */
1649 		pci_restore_config_space_range(pdev, 9, 11, 0, true);
1650 		pci_restore_config_space_range(pdev, 0, 8, 0, false);
1651 	} else {
1652 		pci_restore_config_space_range(pdev, 0, 15, 0, false);
1653 	}
1654 }
1655 
1656 static void pci_restore_rebar_state(struct pci_dev *pdev)
1657 {
1658 	unsigned int pos, nbars, i;
1659 	u32 ctrl;
1660 
1661 	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR);
1662 	if (!pos)
1663 		return;
1664 
1665 	pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
1666 	nbars = (ctrl & PCI_REBAR_CTRL_NBAR_MASK) >>
1667 		    PCI_REBAR_CTRL_NBAR_SHIFT;
1668 
1669 	for (i = 0; i < nbars; i++, pos += 8) {
1670 		struct resource *res;
1671 		int bar_idx, size;
1672 
1673 		pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
1674 		bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX;
1675 		res = pdev->resource + bar_idx;
1676 		size = pci_rebar_bytes_to_size(resource_size(res));
1677 		ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE;
1678 		ctrl |= size << PCI_REBAR_CTRL_BAR_SHIFT;
1679 		pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl);
1680 	}
1681 }
1682 
1683 /**
1684  * pci_restore_state - Restore the saved state of a PCI device
1685  * @dev: PCI device that we're dealing with
1686  */
1687 void pci_restore_state(struct pci_dev *dev)
1688 {
1689 	if (!dev->state_saved)
1690 		return;
1691 
1692 	/*
1693 	 * Restore max latencies (in the LTR capability) before enabling
1694 	 * LTR itself (in the PCIe capability).
1695 	 */
1696 	pci_restore_ltr_state(dev);
1697 
1698 	pci_restore_pcie_state(dev);
1699 	pci_restore_pasid_state(dev);
1700 	pci_restore_pri_state(dev);
1701 	pci_restore_ats_state(dev);
1702 	pci_restore_vc_state(dev);
1703 	pci_restore_rebar_state(dev);
1704 	pci_restore_dpc_state(dev);
1705 	pci_restore_ptm_state(dev);
1706 
1707 	pci_aer_clear_status(dev);
1708 	pci_restore_aer_state(dev);
1709 
1710 	pci_restore_config_space(dev);
1711 
1712 	pci_restore_pcix_state(dev);
1713 	pci_restore_msi_state(dev);
1714 
1715 	/* Restore ACS and IOV configuration state */
1716 	pci_enable_acs(dev);
1717 	pci_restore_iov_state(dev);
1718 
1719 	dev->state_saved = false;
1720 }
1721 EXPORT_SYMBOL(pci_restore_state);
1722 
1723 struct pci_saved_state {
1724 	u32 config_space[16];
1725 	struct pci_cap_saved_data cap[];
1726 };
1727 
1728 /**
1729  * pci_store_saved_state - Allocate and return an opaque struct containing
1730  *			   the device saved state.
1731  * @dev: PCI device that we're dealing with
1732  *
1733  * Return NULL if no state or error.
1734  */
1735 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
1736 {
1737 	struct pci_saved_state *state;
1738 	struct pci_cap_saved_state *tmp;
1739 	struct pci_cap_saved_data *cap;
1740 	size_t size;
1741 
1742 	if (!dev->state_saved)
1743 		return NULL;
1744 
1745 	size = sizeof(*state) + sizeof(struct pci_cap_saved_data);
1746 
1747 	hlist_for_each_entry(tmp, &dev->saved_cap_space, next)
1748 		size += sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1749 
1750 	state = kzalloc(size, GFP_KERNEL);
1751 	if (!state)
1752 		return NULL;
1753 
1754 	memcpy(state->config_space, dev->saved_config_space,
1755 	       sizeof(state->config_space));
1756 
1757 	cap = state->cap;
1758 	hlist_for_each_entry(tmp, &dev->saved_cap_space, next) {
1759 		size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1760 		memcpy(cap, &tmp->cap, len);
1761 		cap = (struct pci_cap_saved_data *)((u8 *)cap + len);
1762 	}
1763 	/* Empty cap_save terminates list */
1764 
1765 	return state;
1766 }
1767 EXPORT_SYMBOL_GPL(pci_store_saved_state);
1768 
1769 /**
1770  * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1771  * @dev: PCI device that we're dealing with
1772  * @state: Saved state returned from pci_store_saved_state()
1773  */
1774 int pci_load_saved_state(struct pci_dev *dev,
1775 			 struct pci_saved_state *state)
1776 {
1777 	struct pci_cap_saved_data *cap;
1778 
1779 	dev->state_saved = false;
1780 
1781 	if (!state)
1782 		return 0;
1783 
1784 	memcpy(dev->saved_config_space, state->config_space,
1785 	       sizeof(state->config_space));
1786 
1787 	cap = state->cap;
1788 	while (cap->size) {
1789 		struct pci_cap_saved_state *tmp;
1790 
1791 		tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended);
1792 		if (!tmp || tmp->cap.size != cap->size)
1793 			return -EINVAL;
1794 
1795 		memcpy(tmp->cap.data, cap->data, tmp->cap.size);
1796 		cap = (struct pci_cap_saved_data *)((u8 *)cap +
1797 		       sizeof(struct pci_cap_saved_data) + cap->size);
1798 	}
1799 
1800 	dev->state_saved = true;
1801 	return 0;
1802 }
1803 EXPORT_SYMBOL_GPL(pci_load_saved_state);
1804 
1805 /**
1806  * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1807  *				   and free the memory allocated for it.
1808  * @dev: PCI device that we're dealing with
1809  * @state: Pointer to saved state returned from pci_store_saved_state()
1810  */
1811 int pci_load_and_free_saved_state(struct pci_dev *dev,
1812 				  struct pci_saved_state **state)
1813 {
1814 	int ret = pci_load_saved_state(dev, *state);
1815 	kfree(*state);
1816 	*state = NULL;
1817 	return ret;
1818 }
1819 EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state);
1820 
1821 int __weak pcibios_enable_device(struct pci_dev *dev, int bars)
1822 {
1823 	return pci_enable_resources(dev, bars);
1824 }
1825 
1826 static int do_pci_enable_device(struct pci_dev *dev, int bars)
1827 {
1828 	int err;
1829 	struct pci_dev *bridge;
1830 	u16 cmd;
1831 	u8 pin;
1832 
1833 	err = pci_set_power_state(dev, PCI_D0);
1834 	if (err < 0 && err != -EIO)
1835 		return err;
1836 
1837 	bridge = pci_upstream_bridge(dev);
1838 	if (bridge)
1839 		pcie_aspm_powersave_config_link(bridge);
1840 
1841 	err = pcibios_enable_device(dev, bars);
1842 	if (err < 0)
1843 		return err;
1844 	pci_fixup_device(pci_fixup_enable, dev);
1845 
1846 	if (dev->msi_enabled || dev->msix_enabled)
1847 		return 0;
1848 
1849 	pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1850 	if (pin) {
1851 		pci_read_config_word(dev, PCI_COMMAND, &cmd);
1852 		if (cmd & PCI_COMMAND_INTX_DISABLE)
1853 			pci_write_config_word(dev, PCI_COMMAND,
1854 					      cmd & ~PCI_COMMAND_INTX_DISABLE);
1855 	}
1856 
1857 	return 0;
1858 }
1859 
1860 /**
1861  * pci_reenable_device - Resume abandoned device
1862  * @dev: PCI device to be resumed
1863  *
1864  * NOTE: This function is a backend of pci_default_resume() and is not supposed
1865  * to be called by normal code, write proper resume handler and use it instead.
1866  */
1867 int pci_reenable_device(struct pci_dev *dev)
1868 {
1869 	if (pci_is_enabled(dev))
1870 		return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
1871 	return 0;
1872 }
1873 EXPORT_SYMBOL(pci_reenable_device);
1874 
1875 static void pci_enable_bridge(struct pci_dev *dev)
1876 {
1877 	struct pci_dev *bridge;
1878 	int retval;
1879 
1880 	bridge = pci_upstream_bridge(dev);
1881 	if (bridge)
1882 		pci_enable_bridge(bridge);
1883 
1884 	if (pci_is_enabled(dev)) {
1885 		if (!dev->is_busmaster)
1886 			pci_set_master(dev);
1887 		return;
1888 	}
1889 
1890 	retval = pci_enable_device(dev);
1891 	if (retval)
1892 		pci_err(dev, "Error enabling bridge (%d), continuing\n",
1893 			retval);
1894 	pci_set_master(dev);
1895 }
1896 
1897 static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags)
1898 {
1899 	struct pci_dev *bridge;
1900 	int err;
1901 	int i, bars = 0;
1902 
1903 	/*
1904 	 * Power state could be unknown at this point, either due to a fresh
1905 	 * boot or a device removal call.  So get the current power state
1906 	 * so that things like MSI message writing will behave as expected
1907 	 * (e.g. if the device really is in D0 at enable time).
1908 	 */
1909 	if (dev->pm_cap) {
1910 		u16 pmcsr;
1911 		pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1912 		dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
1913 	}
1914 
1915 	if (atomic_inc_return(&dev->enable_cnt) > 1)
1916 		return 0;		/* already enabled */
1917 
1918 	bridge = pci_upstream_bridge(dev);
1919 	if (bridge)
1920 		pci_enable_bridge(bridge);
1921 
1922 	/* only skip sriov related */
1923 	for (i = 0; i <= PCI_ROM_RESOURCE; i++)
1924 		if (dev->resource[i].flags & flags)
1925 			bars |= (1 << i);
1926 	for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++)
1927 		if (dev->resource[i].flags & flags)
1928 			bars |= (1 << i);
1929 
1930 	err = do_pci_enable_device(dev, bars);
1931 	if (err < 0)
1932 		atomic_dec(&dev->enable_cnt);
1933 	return err;
1934 }
1935 
1936 /**
1937  * pci_enable_device_io - Initialize a device for use with IO space
1938  * @dev: PCI device to be initialized
1939  *
1940  * Initialize device before it's used by a driver. Ask low-level code
1941  * to enable I/O resources. Wake up the device if it was suspended.
1942  * Beware, this function can fail.
1943  */
1944 int pci_enable_device_io(struct pci_dev *dev)
1945 {
1946 	return pci_enable_device_flags(dev, IORESOURCE_IO);
1947 }
1948 EXPORT_SYMBOL(pci_enable_device_io);
1949 
1950 /**
1951  * pci_enable_device_mem - Initialize a device for use with Memory space
1952  * @dev: PCI device to be initialized
1953  *
1954  * Initialize device before it's used by a driver. Ask low-level code
1955  * to enable Memory resources. Wake up the device if it was suspended.
1956  * Beware, this function can fail.
1957  */
1958 int pci_enable_device_mem(struct pci_dev *dev)
1959 {
1960 	return pci_enable_device_flags(dev, IORESOURCE_MEM);
1961 }
1962 EXPORT_SYMBOL(pci_enable_device_mem);
1963 
1964 /**
1965  * pci_enable_device - Initialize device before it's used by a driver.
1966  * @dev: PCI device to be initialized
1967  *
1968  * Initialize device before it's used by a driver. Ask low-level code
1969  * to enable I/O and memory. Wake up the device if it was suspended.
1970  * Beware, this function can fail.
1971  *
1972  * Note we don't actually enable the device many times if we call
1973  * this function repeatedly (we just increment the count).
1974  */
1975 int pci_enable_device(struct pci_dev *dev)
1976 {
1977 	return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
1978 }
1979 EXPORT_SYMBOL(pci_enable_device);
1980 
1981 /*
1982  * Managed PCI resources.  This manages device on/off, INTx/MSI/MSI-X
1983  * on/off and BAR regions.  pci_dev itself records MSI/MSI-X status, so
1984  * there's no need to track it separately.  pci_devres is initialized
1985  * when a device is enabled using managed PCI device enable interface.
1986  */
1987 struct pci_devres {
1988 	unsigned int enabled:1;
1989 	unsigned int pinned:1;
1990 	unsigned int orig_intx:1;
1991 	unsigned int restore_intx:1;
1992 	unsigned int mwi:1;
1993 	u32 region_mask;
1994 };
1995 
1996 static void pcim_release(struct device *gendev, void *res)
1997 {
1998 	struct pci_dev *dev = to_pci_dev(gendev);
1999 	struct pci_devres *this = res;
2000 	int i;
2001 
2002 	if (dev->msi_enabled)
2003 		pci_disable_msi(dev);
2004 	if (dev->msix_enabled)
2005 		pci_disable_msix(dev);
2006 
2007 	for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
2008 		if (this->region_mask & (1 << i))
2009 			pci_release_region(dev, i);
2010 
2011 	if (this->mwi)
2012 		pci_clear_mwi(dev);
2013 
2014 	if (this->restore_intx)
2015 		pci_intx(dev, this->orig_intx);
2016 
2017 	if (this->enabled && !this->pinned)
2018 		pci_disable_device(dev);
2019 }
2020 
2021 static struct pci_devres *get_pci_dr(struct pci_dev *pdev)
2022 {
2023 	struct pci_devres *dr, *new_dr;
2024 
2025 	dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
2026 	if (dr)
2027 		return dr;
2028 
2029 	new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
2030 	if (!new_dr)
2031 		return NULL;
2032 	return devres_get(&pdev->dev, new_dr, NULL, NULL);
2033 }
2034 
2035 static struct pci_devres *find_pci_dr(struct pci_dev *pdev)
2036 {
2037 	if (pci_is_managed(pdev))
2038 		return devres_find(&pdev->dev, pcim_release, NULL, NULL);
2039 	return NULL;
2040 }
2041 
2042 /**
2043  * pcim_enable_device - Managed pci_enable_device()
2044  * @pdev: PCI device to be initialized
2045  *
2046  * Managed pci_enable_device().
2047  */
2048 int pcim_enable_device(struct pci_dev *pdev)
2049 {
2050 	struct pci_devres *dr;
2051 	int rc;
2052 
2053 	dr = get_pci_dr(pdev);
2054 	if (unlikely(!dr))
2055 		return -ENOMEM;
2056 	if (dr->enabled)
2057 		return 0;
2058 
2059 	rc = pci_enable_device(pdev);
2060 	if (!rc) {
2061 		pdev->is_managed = 1;
2062 		dr->enabled = 1;
2063 	}
2064 	return rc;
2065 }
2066 EXPORT_SYMBOL(pcim_enable_device);
2067 
2068 /**
2069  * pcim_pin_device - Pin managed PCI device
2070  * @pdev: PCI device to pin
2071  *
2072  * Pin managed PCI device @pdev.  Pinned device won't be disabled on
2073  * driver detach.  @pdev must have been enabled with
2074  * pcim_enable_device().
2075  */
2076 void pcim_pin_device(struct pci_dev *pdev)
2077 {
2078 	struct pci_devres *dr;
2079 
2080 	dr = find_pci_dr(pdev);
2081 	WARN_ON(!dr || !dr->enabled);
2082 	if (dr)
2083 		dr->pinned = 1;
2084 }
2085 EXPORT_SYMBOL(pcim_pin_device);
2086 
2087 /*
2088  * pcibios_add_device - provide arch specific hooks when adding device dev
2089  * @dev: the PCI device being added
2090  *
2091  * Permits the platform to provide architecture specific functionality when
2092  * devices are added. This is the default implementation. Architecture
2093  * implementations can override this.
2094  */
2095 int __weak pcibios_add_device(struct pci_dev *dev)
2096 {
2097 	return 0;
2098 }
2099 
2100 /**
2101  * pcibios_release_device - provide arch specific hooks when releasing
2102  *			    device dev
2103  * @dev: the PCI device being released
2104  *
2105  * Permits the platform to provide architecture specific functionality when
2106  * devices are released. This is the default implementation. Architecture
2107  * implementations can override this.
2108  */
2109 void __weak pcibios_release_device(struct pci_dev *dev) {}
2110 
2111 /**
2112  * pcibios_disable_device - disable arch specific PCI resources for device dev
2113  * @dev: the PCI device to disable
2114  *
2115  * Disables architecture specific PCI resources for the device. This
2116  * is the default implementation. Architecture implementations can
2117  * override this.
2118  */
2119 void __weak pcibios_disable_device(struct pci_dev *dev) {}
2120 
2121 /**
2122  * pcibios_penalize_isa_irq - penalize an ISA IRQ
2123  * @irq: ISA IRQ to penalize
2124  * @active: IRQ active or not
2125  *
2126  * Permits the platform to provide architecture-specific functionality when
2127  * penalizing ISA IRQs. This is the default implementation. Architecture
2128  * implementations can override this.
2129  */
2130 void __weak pcibios_penalize_isa_irq(int irq, int active) {}
2131 
2132 static void do_pci_disable_device(struct pci_dev *dev)
2133 {
2134 	u16 pci_command;
2135 
2136 	pci_read_config_word(dev, PCI_COMMAND, &pci_command);
2137 	if (pci_command & PCI_COMMAND_MASTER) {
2138 		pci_command &= ~PCI_COMMAND_MASTER;
2139 		pci_write_config_word(dev, PCI_COMMAND, pci_command);
2140 	}
2141 
2142 	pcibios_disable_device(dev);
2143 }
2144 
2145 /**
2146  * pci_disable_enabled_device - Disable device without updating enable_cnt
2147  * @dev: PCI device to disable
2148  *
2149  * NOTE: This function is a backend of PCI power management routines and is
2150  * not supposed to be called drivers.
2151  */
2152 void pci_disable_enabled_device(struct pci_dev *dev)
2153 {
2154 	if (pci_is_enabled(dev))
2155 		do_pci_disable_device(dev);
2156 }
2157 
2158 /**
2159  * pci_disable_device - Disable PCI device after use
2160  * @dev: PCI device to be disabled
2161  *
2162  * Signal to the system that the PCI device is not in use by the system
2163  * anymore.  This only involves disabling PCI bus-mastering, if active.
2164  *
2165  * Note we don't actually disable the device until all callers of
2166  * pci_enable_device() have called pci_disable_device().
2167  */
2168 void pci_disable_device(struct pci_dev *dev)
2169 {
2170 	struct pci_devres *dr;
2171 
2172 	dr = find_pci_dr(dev);
2173 	if (dr)
2174 		dr->enabled = 0;
2175 
2176 	dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0,
2177 		      "disabling already-disabled device");
2178 
2179 	if (atomic_dec_return(&dev->enable_cnt) != 0)
2180 		return;
2181 
2182 	do_pci_disable_device(dev);
2183 
2184 	dev->is_busmaster = 0;
2185 }
2186 EXPORT_SYMBOL(pci_disable_device);
2187 
2188 /**
2189  * pcibios_set_pcie_reset_state - set reset state for device dev
2190  * @dev: the PCIe device reset
2191  * @state: Reset state to enter into
2192  *
2193  * Set the PCIe reset state for the device. This is the default
2194  * implementation. Architecture implementations can override this.
2195  */
2196 int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev,
2197 					enum pcie_reset_state state)
2198 {
2199 	return -EINVAL;
2200 }
2201 
2202 /**
2203  * pci_set_pcie_reset_state - set reset state for device dev
2204  * @dev: the PCIe device reset
2205  * @state: Reset state to enter into
2206  *
2207  * Sets the PCI reset state for the device.
2208  */
2209 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
2210 {
2211 	return pcibios_set_pcie_reset_state(dev, state);
2212 }
2213 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);
2214 
2215 void pcie_clear_device_status(struct pci_dev *dev)
2216 {
2217 	u16 sta;
2218 
2219 	pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &sta);
2220 	pcie_capability_write_word(dev, PCI_EXP_DEVSTA, sta);
2221 }
2222 
2223 /**
2224  * pcie_clear_root_pme_status - Clear root port PME interrupt status.
2225  * @dev: PCIe root port or event collector.
2226  */
2227 void pcie_clear_root_pme_status(struct pci_dev *dev)
2228 {
2229 	pcie_capability_set_dword(dev, PCI_EXP_RTSTA, PCI_EXP_RTSTA_PME);
2230 }
2231 
2232 /**
2233  * pci_check_pme_status - Check if given device has generated PME.
2234  * @dev: Device to check.
2235  *
2236  * Check the PME status of the device and if set, clear it and clear PME enable
2237  * (if set).  Return 'true' if PME status and PME enable were both set or
2238  * 'false' otherwise.
2239  */
2240 bool pci_check_pme_status(struct pci_dev *dev)
2241 {
2242 	int pmcsr_pos;
2243 	u16 pmcsr;
2244 	bool ret = false;
2245 
2246 	if (!dev->pm_cap)
2247 		return false;
2248 
2249 	pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
2250 	pci_read_config_word(dev, pmcsr_pos, &pmcsr);
2251 	if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
2252 		return false;
2253 
2254 	/* Clear PME status. */
2255 	pmcsr |= PCI_PM_CTRL_PME_STATUS;
2256 	if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
2257 		/* Disable PME to avoid interrupt flood. */
2258 		pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
2259 		ret = true;
2260 	}
2261 
2262 	pci_write_config_word(dev, pmcsr_pos, pmcsr);
2263 
2264 	return ret;
2265 }
2266 
2267 /**
2268  * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
2269  * @dev: Device to handle.
2270  * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
2271  *
2272  * Check if @dev has generated PME and queue a resume request for it in that
2273  * case.
2274  */
2275 static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset)
2276 {
2277 	if (pme_poll_reset && dev->pme_poll)
2278 		dev->pme_poll = false;
2279 
2280 	if (pci_check_pme_status(dev)) {
2281 		pci_wakeup_event(dev);
2282 		pm_request_resume(&dev->dev);
2283 	}
2284 	return 0;
2285 }
2286 
2287 /**
2288  * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
2289  * @bus: Top bus of the subtree to walk.
2290  */
2291 void pci_pme_wakeup_bus(struct pci_bus *bus)
2292 {
2293 	if (bus)
2294 		pci_walk_bus(bus, pci_pme_wakeup, (void *)true);
2295 }
2296 
2297 
2298 /**
2299  * pci_pme_capable - check the capability of PCI device to generate PME#
2300  * @dev: PCI device to handle.
2301  * @state: PCI state from which device will issue PME#.
2302  */
2303 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
2304 {
2305 	if (!dev->pm_cap)
2306 		return false;
2307 
2308 	return !!(dev->pme_support & (1 << state));
2309 }
2310 EXPORT_SYMBOL(pci_pme_capable);
2311 
2312 static void pci_pme_list_scan(struct work_struct *work)
2313 {
2314 	struct pci_pme_device *pme_dev, *n;
2315 
2316 	mutex_lock(&pci_pme_list_mutex);
2317 	list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) {
2318 		if (pme_dev->dev->pme_poll) {
2319 			struct pci_dev *bridge;
2320 
2321 			bridge = pme_dev->dev->bus->self;
2322 			/*
2323 			 * If bridge is in low power state, the
2324 			 * configuration space of subordinate devices
2325 			 * may be not accessible
2326 			 */
2327 			if (bridge && bridge->current_state != PCI_D0)
2328 				continue;
2329 			/*
2330 			 * If the device is in D3cold it should not be
2331 			 * polled either.
2332 			 */
2333 			if (pme_dev->dev->current_state == PCI_D3cold)
2334 				continue;
2335 
2336 			pci_pme_wakeup(pme_dev->dev, NULL);
2337 		} else {
2338 			list_del(&pme_dev->list);
2339 			kfree(pme_dev);
2340 		}
2341 	}
2342 	if (!list_empty(&pci_pme_list))
2343 		queue_delayed_work(system_freezable_wq, &pci_pme_work,
2344 				   msecs_to_jiffies(PME_TIMEOUT));
2345 	mutex_unlock(&pci_pme_list_mutex);
2346 }
2347 
2348 static void __pci_pme_active(struct pci_dev *dev, bool enable)
2349 {
2350 	u16 pmcsr;
2351 
2352 	if (!dev->pme_support)
2353 		return;
2354 
2355 	pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
2356 	/* Clear PME_Status by writing 1 to it and enable PME# */
2357 	pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
2358 	if (!enable)
2359 		pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
2360 
2361 	pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
2362 }
2363 
2364 /**
2365  * pci_pme_restore - Restore PME configuration after config space restore.
2366  * @dev: PCI device to update.
2367  */
2368 void pci_pme_restore(struct pci_dev *dev)
2369 {
2370 	u16 pmcsr;
2371 
2372 	if (!dev->pme_support)
2373 		return;
2374 
2375 	pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
2376 	if (dev->wakeup_prepared) {
2377 		pmcsr |= PCI_PM_CTRL_PME_ENABLE;
2378 		pmcsr &= ~PCI_PM_CTRL_PME_STATUS;
2379 	} else {
2380 		pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
2381 		pmcsr |= PCI_PM_CTRL_PME_STATUS;
2382 	}
2383 	pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
2384 }
2385 
2386 /**
2387  * pci_pme_active - enable or disable PCI device's PME# function
2388  * @dev: PCI device to handle.
2389  * @enable: 'true' to enable PME# generation; 'false' to disable it.
2390  *
2391  * The caller must verify that the device is capable of generating PME# before
2392  * calling this function with @enable equal to 'true'.
2393  */
2394 void pci_pme_active(struct pci_dev *dev, bool enable)
2395 {
2396 	__pci_pme_active(dev, enable);
2397 
2398 	/*
2399 	 * PCI (as opposed to PCIe) PME requires that the device have
2400 	 * its PME# line hooked up correctly. Not all hardware vendors
2401 	 * do this, so the PME never gets delivered and the device
2402 	 * remains asleep. The easiest way around this is to
2403 	 * periodically walk the list of suspended devices and check
2404 	 * whether any have their PME flag set. The assumption is that
2405 	 * we'll wake up often enough anyway that this won't be a huge
2406 	 * hit, and the power savings from the devices will still be a
2407 	 * win.
2408 	 *
2409 	 * Although PCIe uses in-band PME message instead of PME# line
2410 	 * to report PME, PME does not work for some PCIe devices in
2411 	 * reality.  For example, there are devices that set their PME
2412 	 * status bits, but don't really bother to send a PME message;
2413 	 * there are PCI Express Root Ports that don't bother to
2414 	 * trigger interrupts when they receive PME messages from the
2415 	 * devices below.  So PME poll is used for PCIe devices too.
2416 	 */
2417 
2418 	if (dev->pme_poll) {
2419 		struct pci_pme_device *pme_dev;
2420 		if (enable) {
2421 			pme_dev = kmalloc(sizeof(struct pci_pme_device),
2422 					  GFP_KERNEL);
2423 			if (!pme_dev) {
2424 				pci_warn(dev, "can't enable PME#\n");
2425 				return;
2426 			}
2427 			pme_dev->dev = dev;
2428 			mutex_lock(&pci_pme_list_mutex);
2429 			list_add(&pme_dev->list, &pci_pme_list);
2430 			if (list_is_singular(&pci_pme_list))
2431 				queue_delayed_work(system_freezable_wq,
2432 						   &pci_pme_work,
2433 						   msecs_to_jiffies(PME_TIMEOUT));
2434 			mutex_unlock(&pci_pme_list_mutex);
2435 		} else {
2436 			mutex_lock(&pci_pme_list_mutex);
2437 			list_for_each_entry(pme_dev, &pci_pme_list, list) {
2438 				if (pme_dev->dev == dev) {
2439 					list_del(&pme_dev->list);
2440 					kfree(pme_dev);
2441 					break;
2442 				}
2443 			}
2444 			mutex_unlock(&pci_pme_list_mutex);
2445 		}
2446 	}
2447 
2448 	pci_dbg(dev, "PME# %s\n", enable ? "enabled" : "disabled");
2449 }
2450 EXPORT_SYMBOL(pci_pme_active);
2451 
2452 /**
2453  * __pci_enable_wake - enable PCI device as wakeup event source
2454  * @dev: PCI device affected
2455  * @state: PCI state from which device will issue wakeup events
2456  * @enable: True to enable event generation; false to disable
2457  *
2458  * This enables the device as a wakeup event source, or disables it.
2459  * When such events involves platform-specific hooks, those hooks are
2460  * called automatically by this routine.
2461  *
2462  * Devices with legacy power management (no standard PCI PM capabilities)
2463  * always require such platform hooks.
2464  *
2465  * RETURN VALUE:
2466  * 0 is returned on success
2467  * -EINVAL is returned if device is not supposed to wake up the system
2468  * Error code depending on the platform is returned if both the platform and
2469  * the native mechanism fail to enable the generation of wake-up events
2470  */
2471 static int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable)
2472 {
2473 	int ret = 0;
2474 
2475 	/*
2476 	 * Bridges that are not power-manageable directly only signal
2477 	 * wakeup on behalf of subordinate devices which is set up
2478 	 * elsewhere, so skip them. However, bridges that are
2479 	 * power-manageable may signal wakeup for themselves (for example,
2480 	 * on a hotplug event) and they need to be covered here.
2481 	 */
2482 	if (!pci_power_manageable(dev))
2483 		return 0;
2484 
2485 	/* Don't do the same thing twice in a row for one device. */
2486 	if (!!enable == !!dev->wakeup_prepared)
2487 		return 0;
2488 
2489 	/*
2490 	 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
2491 	 * Anderson we should be doing PME# wake enable followed by ACPI wake
2492 	 * enable.  To disable wake-up we call the platform first, for symmetry.
2493 	 */
2494 
2495 	if (enable) {
2496 		int error;
2497 
2498 		if (pci_pme_capable(dev, state))
2499 			pci_pme_active(dev, true);
2500 		else
2501 			ret = 1;
2502 		error = platform_pci_set_wakeup(dev, true);
2503 		if (ret)
2504 			ret = error;
2505 		if (!ret)
2506 			dev->wakeup_prepared = true;
2507 	} else {
2508 		platform_pci_set_wakeup(dev, false);
2509 		pci_pme_active(dev, false);
2510 		dev->wakeup_prepared = false;
2511 	}
2512 
2513 	return ret;
2514 }
2515 
2516 /**
2517  * pci_enable_wake - change wakeup settings for a PCI device
2518  * @pci_dev: Target device
2519  * @state: PCI state from which device will issue wakeup events
2520  * @enable: Whether or not to enable event generation
2521  *
2522  * If @enable is set, check device_may_wakeup() for the device before calling
2523  * __pci_enable_wake() for it.
2524  */
2525 int pci_enable_wake(struct pci_dev *pci_dev, pci_power_t state, bool enable)
2526 {
2527 	if (enable && !device_may_wakeup(&pci_dev->dev))
2528 		return -EINVAL;
2529 
2530 	return __pci_enable_wake(pci_dev, state, enable);
2531 }
2532 EXPORT_SYMBOL(pci_enable_wake);
2533 
2534 /**
2535  * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
2536  * @dev: PCI device to prepare
2537  * @enable: True to enable wake-up event generation; false to disable
2538  *
2539  * Many drivers want the device to wake up the system from D3_hot or D3_cold
2540  * and this function allows them to set that up cleanly - pci_enable_wake()
2541  * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
2542  * ordering constraints.
2543  *
2544  * This function only returns error code if the device is not allowed to wake
2545  * up the system from sleep or it is not capable of generating PME# from both
2546  * D3_hot and D3_cold and the platform is unable to enable wake-up power for it.
2547  */
2548 int pci_wake_from_d3(struct pci_dev *dev, bool enable)
2549 {
2550 	return pci_pme_capable(dev, PCI_D3cold) ?
2551 			pci_enable_wake(dev, PCI_D3cold, enable) :
2552 			pci_enable_wake(dev, PCI_D3hot, enable);
2553 }
2554 EXPORT_SYMBOL(pci_wake_from_d3);
2555 
2556 /**
2557  * pci_target_state - find an appropriate low power state for a given PCI dev
2558  * @dev: PCI device
2559  * @wakeup: Whether or not wakeup functionality will be enabled for the device.
2560  *
2561  * Use underlying platform code to find a supported low power state for @dev.
2562  * If the platform can't manage @dev, return the deepest state from which it
2563  * can generate wake events, based on any available PME info.
2564  */
2565 static pci_power_t pci_target_state(struct pci_dev *dev, bool wakeup)
2566 {
2567 	pci_power_t target_state = PCI_D3hot;
2568 
2569 	if (platform_pci_power_manageable(dev)) {
2570 		/*
2571 		 * Call the platform to find the target state for the device.
2572 		 */
2573 		pci_power_t state = platform_pci_choose_state(dev);
2574 
2575 		switch (state) {
2576 		case PCI_POWER_ERROR:
2577 		case PCI_UNKNOWN:
2578 			break;
2579 		case PCI_D1:
2580 		case PCI_D2:
2581 			if (pci_no_d1d2(dev))
2582 				break;
2583 			fallthrough;
2584 		default:
2585 			target_state = state;
2586 		}
2587 
2588 		return target_state;
2589 	}
2590 
2591 	if (!dev->pm_cap)
2592 		target_state = PCI_D0;
2593 
2594 	/*
2595 	 * If the device is in D3cold even though it's not power-manageable by
2596 	 * the platform, it may have been powered down by non-standard means.
2597 	 * Best to let it slumber.
2598 	 */
2599 	if (dev->current_state == PCI_D3cold)
2600 		target_state = PCI_D3cold;
2601 
2602 	if (wakeup) {
2603 		/*
2604 		 * Find the deepest state from which the device can generate
2605 		 * PME#.
2606 		 */
2607 		if (dev->pme_support) {
2608 			while (target_state
2609 			      && !(dev->pme_support & (1 << target_state)))
2610 				target_state--;
2611 		}
2612 	}
2613 
2614 	return target_state;
2615 }
2616 
2617 /**
2618  * pci_prepare_to_sleep - prepare PCI device for system-wide transition
2619  *			  into a sleep state
2620  * @dev: Device to handle.
2621  *
2622  * Choose the power state appropriate for the device depending on whether
2623  * it can wake up the system and/or is power manageable by the platform
2624  * (PCI_D3hot is the default) and put the device into that state.
2625  */
2626 int pci_prepare_to_sleep(struct pci_dev *dev)
2627 {
2628 	bool wakeup = device_may_wakeup(&dev->dev);
2629 	pci_power_t target_state = pci_target_state(dev, wakeup);
2630 	int error;
2631 
2632 	if (target_state == PCI_POWER_ERROR)
2633 		return -EIO;
2634 
2635 	/*
2636 	 * There are systems (for example, Intel mobile chips since Coffee
2637 	 * Lake) where the power drawn while suspended can be significantly
2638 	 * reduced by disabling PTM on PCIe root ports as this allows the
2639 	 * port to enter a lower-power PM state and the SoC to reach a
2640 	 * lower-power idle state as a whole.
2641 	 */
2642 	if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2643 		pci_disable_ptm(dev);
2644 
2645 	pci_enable_wake(dev, target_state, wakeup);
2646 
2647 	error = pci_set_power_state(dev, target_state);
2648 
2649 	if (error) {
2650 		pci_enable_wake(dev, target_state, false);
2651 		pci_restore_ptm_state(dev);
2652 	}
2653 
2654 	return error;
2655 }
2656 EXPORT_SYMBOL(pci_prepare_to_sleep);
2657 
2658 /**
2659  * pci_back_from_sleep - turn PCI device on during system-wide transition
2660  *			 into working state
2661  * @dev: Device to handle.
2662  *
2663  * Disable device's system wake-up capability and put it into D0.
2664  */
2665 int pci_back_from_sleep(struct pci_dev *dev)
2666 {
2667 	pci_enable_wake(dev, PCI_D0, false);
2668 	return pci_set_power_state(dev, PCI_D0);
2669 }
2670 EXPORT_SYMBOL(pci_back_from_sleep);
2671 
2672 /**
2673  * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
2674  * @dev: PCI device being suspended.
2675  *
2676  * Prepare @dev to generate wake-up events at run time and put it into a low
2677  * power state.
2678  */
2679 int pci_finish_runtime_suspend(struct pci_dev *dev)
2680 {
2681 	pci_power_t target_state;
2682 	int error;
2683 
2684 	target_state = pci_target_state(dev, device_can_wakeup(&dev->dev));
2685 	if (target_state == PCI_POWER_ERROR)
2686 		return -EIO;
2687 
2688 	dev->runtime_d3cold = target_state == PCI_D3cold;
2689 
2690 	/*
2691 	 * There are systems (for example, Intel mobile chips since Coffee
2692 	 * Lake) where the power drawn while suspended can be significantly
2693 	 * reduced by disabling PTM on PCIe root ports as this allows the
2694 	 * port to enter a lower-power PM state and the SoC to reach a
2695 	 * lower-power idle state as a whole.
2696 	 */
2697 	if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2698 		pci_disable_ptm(dev);
2699 
2700 	__pci_enable_wake(dev, target_state, pci_dev_run_wake(dev));
2701 
2702 	error = pci_set_power_state(dev, target_state);
2703 
2704 	if (error) {
2705 		pci_enable_wake(dev, target_state, false);
2706 		pci_restore_ptm_state(dev);
2707 		dev->runtime_d3cold = false;
2708 	}
2709 
2710 	return error;
2711 }
2712 
2713 /**
2714  * pci_dev_run_wake - Check if device can generate run-time wake-up events.
2715  * @dev: Device to check.
2716  *
2717  * Return true if the device itself is capable of generating wake-up events
2718  * (through the platform or using the native PCIe PME) or if the device supports
2719  * PME and one of its upstream bridges can generate wake-up events.
2720  */
2721 bool pci_dev_run_wake(struct pci_dev *dev)
2722 {
2723 	struct pci_bus *bus = dev->bus;
2724 
2725 	if (!dev->pme_support)
2726 		return false;
2727 
2728 	/* PME-capable in principle, but not from the target power state */
2729 	if (!pci_pme_capable(dev, pci_target_state(dev, true)))
2730 		return false;
2731 
2732 	if (device_can_wakeup(&dev->dev))
2733 		return true;
2734 
2735 	while (bus->parent) {
2736 		struct pci_dev *bridge = bus->self;
2737 
2738 		if (device_can_wakeup(&bridge->dev))
2739 			return true;
2740 
2741 		bus = bus->parent;
2742 	}
2743 
2744 	/* We have reached the root bus. */
2745 	if (bus->bridge)
2746 		return device_can_wakeup(bus->bridge);
2747 
2748 	return false;
2749 }
2750 EXPORT_SYMBOL_GPL(pci_dev_run_wake);
2751 
2752 /**
2753  * pci_dev_need_resume - Check if it is necessary to resume the device.
2754  * @pci_dev: Device to check.
2755  *
2756  * Return 'true' if the device is not runtime-suspended or it has to be
2757  * reconfigured due to wakeup settings difference between system and runtime
2758  * suspend, or the current power state of it is not suitable for the upcoming
2759  * (system-wide) transition.
2760  */
2761 bool pci_dev_need_resume(struct pci_dev *pci_dev)
2762 {
2763 	struct device *dev = &pci_dev->dev;
2764 	pci_power_t target_state;
2765 
2766 	if (!pm_runtime_suspended(dev) || platform_pci_need_resume(pci_dev))
2767 		return true;
2768 
2769 	target_state = pci_target_state(pci_dev, device_may_wakeup(dev));
2770 
2771 	/*
2772 	 * If the earlier platform check has not triggered, D3cold is just power
2773 	 * removal on top of D3hot, so no need to resume the device in that
2774 	 * case.
2775 	 */
2776 	return target_state != pci_dev->current_state &&
2777 		target_state != PCI_D3cold &&
2778 		pci_dev->current_state != PCI_D3hot;
2779 }
2780 
2781 /**
2782  * pci_dev_adjust_pme - Adjust PME setting for a suspended device.
2783  * @pci_dev: Device to check.
2784  *
2785  * If the device is suspended and it is not configured for system wakeup,
2786  * disable PME for it to prevent it from waking up the system unnecessarily.
2787  *
2788  * Note that if the device's power state is D3cold and the platform check in
2789  * pci_dev_need_resume() has not triggered, the device's configuration need not
2790  * be changed.
2791  */
2792 void pci_dev_adjust_pme(struct pci_dev *pci_dev)
2793 {
2794 	struct device *dev = &pci_dev->dev;
2795 
2796 	spin_lock_irq(&dev->power.lock);
2797 
2798 	if (pm_runtime_suspended(dev) && !device_may_wakeup(dev) &&
2799 	    pci_dev->current_state < PCI_D3cold)
2800 		__pci_pme_active(pci_dev, false);
2801 
2802 	spin_unlock_irq(&dev->power.lock);
2803 }
2804 
2805 /**
2806  * pci_dev_complete_resume - Finalize resume from system sleep for a device.
2807  * @pci_dev: Device to handle.
2808  *
2809  * If the device is runtime suspended and wakeup-capable, enable PME for it as
2810  * it might have been disabled during the prepare phase of system suspend if
2811  * the device was not configured for system wakeup.
2812  */
2813 void pci_dev_complete_resume(struct pci_dev *pci_dev)
2814 {
2815 	struct device *dev = &pci_dev->dev;
2816 
2817 	if (!pci_dev_run_wake(pci_dev))
2818 		return;
2819 
2820 	spin_lock_irq(&dev->power.lock);
2821 
2822 	if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold)
2823 		__pci_pme_active(pci_dev, true);
2824 
2825 	spin_unlock_irq(&dev->power.lock);
2826 }
2827 
2828 void pci_config_pm_runtime_get(struct pci_dev *pdev)
2829 {
2830 	struct device *dev = &pdev->dev;
2831 	struct device *parent = dev->parent;
2832 
2833 	if (parent)
2834 		pm_runtime_get_sync(parent);
2835 	pm_runtime_get_noresume(dev);
2836 	/*
2837 	 * pdev->current_state is set to PCI_D3cold during suspending,
2838 	 * so wait until suspending completes
2839 	 */
2840 	pm_runtime_barrier(dev);
2841 	/*
2842 	 * Only need to resume devices in D3cold, because config
2843 	 * registers are still accessible for devices suspended but
2844 	 * not in D3cold.
2845 	 */
2846 	if (pdev->current_state == PCI_D3cold)
2847 		pm_runtime_resume(dev);
2848 }
2849 
2850 void pci_config_pm_runtime_put(struct pci_dev *pdev)
2851 {
2852 	struct device *dev = &pdev->dev;
2853 	struct device *parent = dev->parent;
2854 
2855 	pm_runtime_put(dev);
2856 	if (parent)
2857 		pm_runtime_put_sync(parent);
2858 }
2859 
2860 static const struct dmi_system_id bridge_d3_blacklist[] = {
2861 #ifdef CONFIG_X86
2862 	{
2863 		/*
2864 		 * Gigabyte X299 root port is not marked as hotplug capable
2865 		 * which allows Linux to power manage it.  However, this
2866 		 * confuses the BIOS SMI handler so don't power manage root
2867 		 * ports on that system.
2868 		 */
2869 		.ident = "X299 DESIGNARE EX-CF",
2870 		.matches = {
2871 			DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),
2872 			DMI_MATCH(DMI_BOARD_NAME, "X299 DESIGNARE EX-CF"),
2873 		},
2874 	},
2875 #endif
2876 	{ }
2877 };
2878 
2879 /**
2880  * pci_bridge_d3_possible - Is it possible to put the bridge into D3
2881  * @bridge: Bridge to check
2882  *
2883  * This function checks if it is possible to move the bridge to D3.
2884  * Currently we only allow D3 for recent enough PCIe ports and Thunderbolt.
2885  */
2886 bool pci_bridge_d3_possible(struct pci_dev *bridge)
2887 {
2888 	if (!pci_is_pcie(bridge))
2889 		return false;
2890 
2891 	switch (pci_pcie_type(bridge)) {
2892 	case PCI_EXP_TYPE_ROOT_PORT:
2893 	case PCI_EXP_TYPE_UPSTREAM:
2894 	case PCI_EXP_TYPE_DOWNSTREAM:
2895 		if (pci_bridge_d3_disable)
2896 			return false;
2897 
2898 		/*
2899 		 * Hotplug ports handled by firmware in System Management Mode
2900 		 * may not be put into D3 by the OS (Thunderbolt on non-Macs).
2901 		 */
2902 		if (bridge->is_hotplug_bridge && !pciehp_is_native(bridge))
2903 			return false;
2904 
2905 		if (pci_bridge_d3_force)
2906 			return true;
2907 
2908 		/* Even the oldest 2010 Thunderbolt controller supports D3. */
2909 		if (bridge->is_thunderbolt)
2910 			return true;
2911 
2912 		/* Platform might know better if the bridge supports D3 */
2913 		if (platform_pci_bridge_d3(bridge))
2914 			return true;
2915 
2916 		/*
2917 		 * Hotplug ports handled natively by the OS were not validated
2918 		 * by vendors for runtime D3 at least until 2018 because there
2919 		 * was no OS support.
2920 		 */
2921 		if (bridge->is_hotplug_bridge)
2922 			return false;
2923 
2924 		if (dmi_check_system(bridge_d3_blacklist))
2925 			return false;
2926 
2927 		/*
2928 		 * It should be safe to put PCIe ports from 2015 or newer
2929 		 * to D3.
2930 		 */
2931 		if (dmi_get_bios_year() >= 2015)
2932 			return true;
2933 		break;
2934 	}
2935 
2936 	return false;
2937 }
2938 
2939 static int pci_dev_check_d3cold(struct pci_dev *dev, void *data)
2940 {
2941 	bool *d3cold_ok = data;
2942 
2943 	if (/* The device needs to be allowed to go D3cold ... */
2944 	    dev->no_d3cold || !dev->d3cold_allowed ||
2945 
2946 	    /* ... and if it is wakeup capable to do so from D3cold. */
2947 	    (device_may_wakeup(&dev->dev) &&
2948 	     !pci_pme_capable(dev, PCI_D3cold)) ||
2949 
2950 	    /* If it is a bridge it must be allowed to go to D3. */
2951 	    !pci_power_manageable(dev))
2952 
2953 		*d3cold_ok = false;
2954 
2955 	return !*d3cold_ok;
2956 }
2957 
2958 /*
2959  * pci_bridge_d3_update - Update bridge D3 capabilities
2960  * @dev: PCI device which is changed
2961  *
2962  * Update upstream bridge PM capabilities accordingly depending on if the
2963  * device PM configuration was changed or the device is being removed.  The
2964  * change is also propagated upstream.
2965  */
2966 void pci_bridge_d3_update(struct pci_dev *dev)
2967 {
2968 	bool remove = !device_is_registered(&dev->dev);
2969 	struct pci_dev *bridge;
2970 	bool d3cold_ok = true;
2971 
2972 	bridge = pci_upstream_bridge(dev);
2973 	if (!bridge || !pci_bridge_d3_possible(bridge))
2974 		return;
2975 
2976 	/*
2977 	 * If D3 is currently allowed for the bridge, removing one of its
2978 	 * children won't change that.
2979 	 */
2980 	if (remove && bridge->bridge_d3)
2981 		return;
2982 
2983 	/*
2984 	 * If D3 is currently allowed for the bridge and a child is added or
2985 	 * changed, disallowance of D3 can only be caused by that child, so
2986 	 * we only need to check that single device, not any of its siblings.
2987 	 *
2988 	 * If D3 is currently not allowed for the bridge, checking the device
2989 	 * first may allow us to skip checking its siblings.
2990 	 */
2991 	if (!remove)
2992 		pci_dev_check_d3cold(dev, &d3cold_ok);
2993 
2994 	/*
2995 	 * If D3 is currently not allowed for the bridge, this may be caused
2996 	 * either by the device being changed/removed or any of its siblings,
2997 	 * so we need to go through all children to find out if one of them
2998 	 * continues to block D3.
2999 	 */
3000 	if (d3cold_ok && !bridge->bridge_d3)
3001 		pci_walk_bus(bridge->subordinate, pci_dev_check_d3cold,
3002 			     &d3cold_ok);
3003 
3004 	if (bridge->bridge_d3 != d3cold_ok) {
3005 		bridge->bridge_d3 = d3cold_ok;
3006 		/* Propagate change to upstream bridges */
3007 		pci_bridge_d3_update(bridge);
3008 	}
3009 }
3010 
3011 /**
3012  * pci_d3cold_enable - Enable D3cold for device
3013  * @dev: PCI device to handle
3014  *
3015  * This function can be used in drivers to enable D3cold from the device
3016  * they handle.  It also updates upstream PCI bridge PM capabilities
3017  * accordingly.
3018  */
3019 void pci_d3cold_enable(struct pci_dev *dev)
3020 {
3021 	if (dev->no_d3cold) {
3022 		dev->no_d3cold = false;
3023 		pci_bridge_d3_update(dev);
3024 	}
3025 }
3026 EXPORT_SYMBOL_GPL(pci_d3cold_enable);
3027 
3028 /**
3029  * pci_d3cold_disable - Disable D3cold for device
3030  * @dev: PCI device to handle
3031  *
3032  * This function can be used in drivers to disable D3cold from the device
3033  * they handle.  It also updates upstream PCI bridge PM capabilities
3034  * accordingly.
3035  */
3036 void pci_d3cold_disable(struct pci_dev *dev)
3037 {
3038 	if (!dev->no_d3cold) {
3039 		dev->no_d3cold = true;
3040 		pci_bridge_d3_update(dev);
3041 	}
3042 }
3043 EXPORT_SYMBOL_GPL(pci_d3cold_disable);
3044 
3045 /**
3046  * pci_pm_init - Initialize PM functions of given PCI device
3047  * @dev: PCI device to handle.
3048  */
3049 void pci_pm_init(struct pci_dev *dev)
3050 {
3051 	int pm;
3052 	u16 status;
3053 	u16 pmc;
3054 
3055 	pm_runtime_forbid(&dev->dev);
3056 	pm_runtime_set_active(&dev->dev);
3057 	pm_runtime_enable(&dev->dev);
3058 	device_enable_async_suspend(&dev->dev);
3059 	dev->wakeup_prepared = false;
3060 
3061 	dev->pm_cap = 0;
3062 	dev->pme_support = 0;
3063 
3064 	/* find PCI PM capability in list */
3065 	pm = pci_find_capability(dev, PCI_CAP_ID_PM);
3066 	if (!pm)
3067 		return;
3068 	/* Check device's ability to generate PME# */
3069 	pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
3070 
3071 	if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
3072 		pci_err(dev, "unsupported PM cap regs version (%u)\n",
3073 			pmc & PCI_PM_CAP_VER_MASK);
3074 		return;
3075 	}
3076 
3077 	dev->pm_cap = pm;
3078 	dev->d3hot_delay = PCI_PM_D3HOT_WAIT;
3079 	dev->d3cold_delay = PCI_PM_D3COLD_WAIT;
3080 	dev->bridge_d3 = pci_bridge_d3_possible(dev);
3081 	dev->d3cold_allowed = true;
3082 
3083 	dev->d1_support = false;
3084 	dev->d2_support = false;
3085 	if (!pci_no_d1d2(dev)) {
3086 		if (pmc & PCI_PM_CAP_D1)
3087 			dev->d1_support = true;
3088 		if (pmc & PCI_PM_CAP_D2)
3089 			dev->d2_support = true;
3090 
3091 		if (dev->d1_support || dev->d2_support)
3092 			pci_info(dev, "supports%s%s\n",
3093 				   dev->d1_support ? " D1" : "",
3094 				   dev->d2_support ? " D2" : "");
3095 	}
3096 
3097 	pmc &= PCI_PM_CAP_PME_MASK;
3098 	if (pmc) {
3099 		pci_info(dev, "PME# supported from%s%s%s%s%s\n",
3100 			 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
3101 			 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
3102 			 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
3103 			 (pmc & PCI_PM_CAP_PME_D3hot) ? " D3hot" : "",
3104 			 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
3105 		dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
3106 		dev->pme_poll = true;
3107 		/*
3108 		 * Make device's PM flags reflect the wake-up capability, but
3109 		 * let the user space enable it to wake up the system as needed.
3110 		 */
3111 		device_set_wakeup_capable(&dev->dev, true);
3112 		/* Disable the PME# generation functionality */
3113 		pci_pme_active(dev, false);
3114 	}
3115 
3116 	pci_read_config_word(dev, PCI_STATUS, &status);
3117 	if (status & PCI_STATUS_IMM_READY)
3118 		dev->imm_ready = 1;
3119 }
3120 
3121 static unsigned long pci_ea_flags(struct pci_dev *dev, u8 prop)
3122 {
3123 	unsigned long flags = IORESOURCE_PCI_FIXED | IORESOURCE_PCI_EA_BEI;
3124 
3125 	switch (prop) {
3126 	case PCI_EA_P_MEM:
3127 	case PCI_EA_P_VF_MEM:
3128 		flags |= IORESOURCE_MEM;
3129 		break;
3130 	case PCI_EA_P_MEM_PREFETCH:
3131 	case PCI_EA_P_VF_MEM_PREFETCH:
3132 		flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
3133 		break;
3134 	case PCI_EA_P_IO:
3135 		flags |= IORESOURCE_IO;
3136 		break;
3137 	default:
3138 		return 0;
3139 	}
3140 
3141 	return flags;
3142 }
3143 
3144 static struct resource *pci_ea_get_resource(struct pci_dev *dev, u8 bei,
3145 					    u8 prop)
3146 {
3147 	if (bei <= PCI_EA_BEI_BAR5 && prop <= PCI_EA_P_IO)
3148 		return &dev->resource[bei];
3149 #ifdef CONFIG_PCI_IOV
3150 	else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5 &&
3151 		 (prop == PCI_EA_P_VF_MEM || prop == PCI_EA_P_VF_MEM_PREFETCH))
3152 		return &dev->resource[PCI_IOV_RESOURCES +
3153 				      bei - PCI_EA_BEI_VF_BAR0];
3154 #endif
3155 	else if (bei == PCI_EA_BEI_ROM)
3156 		return &dev->resource[PCI_ROM_RESOURCE];
3157 	else
3158 		return NULL;
3159 }
3160 
3161 /* Read an Enhanced Allocation (EA) entry */
3162 static int pci_ea_read(struct pci_dev *dev, int offset)
3163 {
3164 	struct resource *res;
3165 	int ent_size, ent_offset = offset;
3166 	resource_size_t start, end;
3167 	unsigned long flags;
3168 	u32 dw0, bei, base, max_offset;
3169 	u8 prop;
3170 	bool support_64 = (sizeof(resource_size_t) >= 8);
3171 
3172 	pci_read_config_dword(dev, ent_offset, &dw0);
3173 	ent_offset += 4;
3174 
3175 	/* Entry size field indicates DWORDs after 1st */
3176 	ent_size = ((dw0 & PCI_EA_ES) + 1) << 2;
3177 
3178 	if (!(dw0 & PCI_EA_ENABLE)) /* Entry not enabled */
3179 		goto out;
3180 
3181 	bei = (dw0 & PCI_EA_BEI) >> 4;
3182 	prop = (dw0 & PCI_EA_PP) >> 8;
3183 
3184 	/*
3185 	 * If the Property is in the reserved range, try the Secondary
3186 	 * Property instead.
3187 	 */
3188 	if (prop > PCI_EA_P_BRIDGE_IO && prop < PCI_EA_P_MEM_RESERVED)
3189 		prop = (dw0 & PCI_EA_SP) >> 16;
3190 	if (prop > PCI_EA_P_BRIDGE_IO)
3191 		goto out;
3192 
3193 	res = pci_ea_get_resource(dev, bei, prop);
3194 	if (!res) {
3195 		pci_err(dev, "Unsupported EA entry BEI: %u\n", bei);
3196 		goto out;
3197 	}
3198 
3199 	flags = pci_ea_flags(dev, prop);
3200 	if (!flags) {
3201 		pci_err(dev, "Unsupported EA properties: %#x\n", prop);
3202 		goto out;
3203 	}
3204 
3205 	/* Read Base */
3206 	pci_read_config_dword(dev, ent_offset, &base);
3207 	start = (base & PCI_EA_FIELD_MASK);
3208 	ent_offset += 4;
3209 
3210 	/* Read MaxOffset */
3211 	pci_read_config_dword(dev, ent_offset, &max_offset);
3212 	ent_offset += 4;
3213 
3214 	/* Read Base MSBs (if 64-bit entry) */
3215 	if (base & PCI_EA_IS_64) {
3216 		u32 base_upper;
3217 
3218 		pci_read_config_dword(dev, ent_offset, &base_upper);
3219 		ent_offset += 4;
3220 
3221 		flags |= IORESOURCE_MEM_64;
3222 
3223 		/* entry starts above 32-bit boundary, can't use */
3224 		if (!support_64 && base_upper)
3225 			goto out;
3226 
3227 		if (support_64)
3228 			start |= ((u64)base_upper << 32);
3229 	}
3230 
3231 	end = start + (max_offset | 0x03);
3232 
3233 	/* Read MaxOffset MSBs (if 64-bit entry) */
3234 	if (max_offset & PCI_EA_IS_64) {
3235 		u32 max_offset_upper;
3236 
3237 		pci_read_config_dword(dev, ent_offset, &max_offset_upper);
3238 		ent_offset += 4;
3239 
3240 		flags |= IORESOURCE_MEM_64;
3241 
3242 		/* entry too big, can't use */
3243 		if (!support_64 && max_offset_upper)
3244 			goto out;
3245 
3246 		if (support_64)
3247 			end += ((u64)max_offset_upper << 32);
3248 	}
3249 
3250 	if (end < start) {
3251 		pci_err(dev, "EA Entry crosses address boundary\n");
3252 		goto out;
3253 	}
3254 
3255 	if (ent_size != ent_offset - offset) {
3256 		pci_err(dev, "EA Entry Size (%d) does not match length read (%d)\n",
3257 			ent_size, ent_offset - offset);
3258 		goto out;
3259 	}
3260 
3261 	res->name = pci_name(dev);
3262 	res->start = start;
3263 	res->end = end;
3264 	res->flags = flags;
3265 
3266 	if (bei <= PCI_EA_BEI_BAR5)
3267 		pci_info(dev, "BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
3268 			   bei, res, prop);
3269 	else if (bei == PCI_EA_BEI_ROM)
3270 		pci_info(dev, "ROM: %pR (from Enhanced Allocation, properties %#02x)\n",
3271 			   res, prop);
3272 	else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5)
3273 		pci_info(dev, "VF BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
3274 			   bei - PCI_EA_BEI_VF_BAR0, res, prop);
3275 	else
3276 		pci_info(dev, "BEI %d res: %pR (from Enhanced Allocation, properties %#02x)\n",
3277 			   bei, res, prop);
3278 
3279 out:
3280 	return offset + ent_size;
3281 }
3282 
3283 /* Enhanced Allocation Initialization */
3284 void pci_ea_init(struct pci_dev *dev)
3285 {
3286 	int ea;
3287 	u8 num_ent;
3288 	int offset;
3289 	int i;
3290 
3291 	/* find PCI EA capability in list */
3292 	ea = pci_find_capability(dev, PCI_CAP_ID_EA);
3293 	if (!ea)
3294 		return;
3295 
3296 	/* determine the number of entries */
3297 	pci_bus_read_config_byte(dev->bus, dev->devfn, ea + PCI_EA_NUM_ENT,
3298 					&num_ent);
3299 	num_ent &= PCI_EA_NUM_ENT_MASK;
3300 
3301 	offset = ea + PCI_EA_FIRST_ENT;
3302 
3303 	/* Skip DWORD 2 for type 1 functions */
3304 	if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
3305 		offset += 4;
3306 
3307 	/* parse each EA entry */
3308 	for (i = 0; i < num_ent; ++i)
3309 		offset = pci_ea_read(dev, offset);
3310 }
3311 
3312 static void pci_add_saved_cap(struct pci_dev *pci_dev,
3313 	struct pci_cap_saved_state *new_cap)
3314 {
3315 	hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
3316 }
3317 
3318 /**
3319  * _pci_add_cap_save_buffer - allocate buffer for saving given
3320  *			      capability registers
3321  * @dev: the PCI device
3322  * @cap: the capability to allocate the buffer for
3323  * @extended: Standard or Extended capability ID
3324  * @size: requested size of the buffer
3325  */
3326 static int _pci_add_cap_save_buffer(struct pci_dev *dev, u16 cap,
3327 				    bool extended, unsigned int size)
3328 {
3329 	int pos;
3330 	struct pci_cap_saved_state *save_state;
3331 
3332 	if (extended)
3333 		pos = pci_find_ext_capability(dev, cap);
3334 	else
3335 		pos = pci_find_capability(dev, cap);
3336 
3337 	if (!pos)
3338 		return 0;
3339 
3340 	save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
3341 	if (!save_state)
3342 		return -ENOMEM;
3343 
3344 	save_state->cap.cap_nr = cap;
3345 	save_state->cap.cap_extended = extended;
3346 	save_state->cap.size = size;
3347 	pci_add_saved_cap(dev, save_state);
3348 
3349 	return 0;
3350 }
3351 
3352 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size)
3353 {
3354 	return _pci_add_cap_save_buffer(dev, cap, false, size);
3355 }
3356 
3357 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, u16 cap, unsigned int size)
3358 {
3359 	return _pci_add_cap_save_buffer(dev, cap, true, size);
3360 }
3361 
3362 /**
3363  * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
3364  * @dev: the PCI device
3365  */
3366 void pci_allocate_cap_save_buffers(struct pci_dev *dev)
3367 {
3368 	int error;
3369 
3370 	error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
3371 					PCI_EXP_SAVE_REGS * sizeof(u16));
3372 	if (error)
3373 		pci_err(dev, "unable to preallocate PCI Express save buffer\n");
3374 
3375 	error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
3376 	if (error)
3377 		pci_err(dev, "unable to preallocate PCI-X save buffer\n");
3378 
3379 	error = pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_LTR,
3380 					    2 * sizeof(u16));
3381 	if (error)
3382 		pci_err(dev, "unable to allocate suspend buffer for LTR\n");
3383 
3384 	pci_allocate_vc_save_buffers(dev);
3385 }
3386 
3387 void pci_free_cap_save_buffers(struct pci_dev *dev)
3388 {
3389 	struct pci_cap_saved_state *tmp;
3390 	struct hlist_node *n;
3391 
3392 	hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next)
3393 		kfree(tmp);
3394 }
3395 
3396 /**
3397  * pci_configure_ari - enable or disable ARI forwarding
3398  * @dev: the PCI device
3399  *
3400  * If @dev and its upstream bridge both support ARI, enable ARI in the
3401  * bridge.  Otherwise, disable ARI in the bridge.
3402  */
3403 void pci_configure_ari(struct pci_dev *dev)
3404 {
3405 	u32 cap;
3406 	struct pci_dev *bridge;
3407 
3408 	if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)
3409 		return;
3410 
3411 	bridge = dev->bus->self;
3412 	if (!bridge)
3413 		return;
3414 
3415 	pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
3416 	if (!(cap & PCI_EXP_DEVCAP2_ARI))
3417 		return;
3418 
3419 	if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) {
3420 		pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2,
3421 					 PCI_EXP_DEVCTL2_ARI);
3422 		bridge->ari_enabled = 1;
3423 	} else {
3424 		pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2,
3425 					   PCI_EXP_DEVCTL2_ARI);
3426 		bridge->ari_enabled = 0;
3427 	}
3428 }
3429 
3430 static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags)
3431 {
3432 	int pos;
3433 	u16 cap, ctrl;
3434 
3435 	pos = pdev->acs_cap;
3436 	if (!pos)
3437 		return false;
3438 
3439 	/*
3440 	 * Except for egress control, capabilities are either required
3441 	 * or only required if controllable.  Features missing from the
3442 	 * capability field can therefore be assumed as hard-wired enabled.
3443 	 */
3444 	pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap);
3445 	acs_flags &= (cap | PCI_ACS_EC);
3446 
3447 	pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl);
3448 	return (ctrl & acs_flags) == acs_flags;
3449 }
3450 
3451 /**
3452  * pci_acs_enabled - test ACS against required flags for a given device
3453  * @pdev: device to test
3454  * @acs_flags: required PCI ACS flags
3455  *
3456  * Return true if the device supports the provided flags.  Automatically
3457  * filters out flags that are not implemented on multifunction devices.
3458  *
3459  * Note that this interface checks the effective ACS capabilities of the
3460  * device rather than the actual capabilities.  For instance, most single
3461  * function endpoints are not required to support ACS because they have no
3462  * opportunity for peer-to-peer access.  We therefore return 'true'
3463  * regardless of whether the device exposes an ACS capability.  This makes
3464  * it much easier for callers of this function to ignore the actual type
3465  * or topology of the device when testing ACS support.
3466  */
3467 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
3468 {
3469 	int ret;
3470 
3471 	ret = pci_dev_specific_acs_enabled(pdev, acs_flags);
3472 	if (ret >= 0)
3473 		return ret > 0;
3474 
3475 	/*
3476 	 * Conventional PCI and PCI-X devices never support ACS, either
3477 	 * effectively or actually.  The shared bus topology implies that
3478 	 * any device on the bus can receive or snoop DMA.
3479 	 */
3480 	if (!pci_is_pcie(pdev))
3481 		return false;
3482 
3483 	switch (pci_pcie_type(pdev)) {
3484 	/*
3485 	 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec,
3486 	 * but since their primary interface is PCI/X, we conservatively
3487 	 * handle them as we would a non-PCIe device.
3488 	 */
3489 	case PCI_EXP_TYPE_PCIE_BRIDGE:
3490 	/*
3491 	 * PCIe 3.0, 6.12.1 excludes ACS on these devices.  "ACS is never
3492 	 * applicable... must never implement an ACS Extended Capability...".
3493 	 * This seems arbitrary, but we take a conservative interpretation
3494 	 * of this statement.
3495 	 */
3496 	case PCI_EXP_TYPE_PCI_BRIDGE:
3497 	case PCI_EXP_TYPE_RC_EC:
3498 		return false;
3499 	/*
3500 	 * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should
3501 	 * implement ACS in order to indicate their peer-to-peer capabilities,
3502 	 * regardless of whether they are single- or multi-function devices.
3503 	 */
3504 	case PCI_EXP_TYPE_DOWNSTREAM:
3505 	case PCI_EXP_TYPE_ROOT_PORT:
3506 		return pci_acs_flags_enabled(pdev, acs_flags);
3507 	/*
3508 	 * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be
3509 	 * implemented by the remaining PCIe types to indicate peer-to-peer
3510 	 * capabilities, but only when they are part of a multifunction
3511 	 * device.  The footnote for section 6.12 indicates the specific
3512 	 * PCIe types included here.
3513 	 */
3514 	case PCI_EXP_TYPE_ENDPOINT:
3515 	case PCI_EXP_TYPE_UPSTREAM:
3516 	case PCI_EXP_TYPE_LEG_END:
3517 	case PCI_EXP_TYPE_RC_END:
3518 		if (!pdev->multifunction)
3519 			break;
3520 
3521 		return pci_acs_flags_enabled(pdev, acs_flags);
3522 	}
3523 
3524 	/*
3525 	 * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable
3526 	 * to single function devices with the exception of downstream ports.
3527 	 */
3528 	return true;
3529 }
3530 
3531 /**
3532  * pci_acs_path_enabled - test ACS flags from start to end in a hierarchy
3533  * @start: starting downstream device
3534  * @end: ending upstream device or NULL to search to the root bus
3535  * @acs_flags: required flags
3536  *
3537  * Walk up a device tree from start to end testing PCI ACS support.  If
3538  * any step along the way does not support the required flags, return false.
3539  */
3540 bool pci_acs_path_enabled(struct pci_dev *start,
3541 			  struct pci_dev *end, u16 acs_flags)
3542 {
3543 	struct pci_dev *pdev, *parent = start;
3544 
3545 	do {
3546 		pdev = parent;
3547 
3548 		if (!pci_acs_enabled(pdev, acs_flags))
3549 			return false;
3550 
3551 		if (pci_is_root_bus(pdev->bus))
3552 			return (end == NULL);
3553 
3554 		parent = pdev->bus->self;
3555 	} while (pdev != end);
3556 
3557 	return true;
3558 }
3559 
3560 /**
3561  * pci_acs_init - Initialize ACS if hardware supports it
3562  * @dev: the PCI device
3563  */
3564 void pci_acs_init(struct pci_dev *dev)
3565 {
3566 	dev->acs_cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
3567 
3568 	/*
3569 	 * Attempt to enable ACS regardless of capability because some Root
3570 	 * Ports (e.g. those quirked with *_intel_pch_acs_*) do not have
3571 	 * the standard ACS capability but still support ACS via those
3572 	 * quirks.
3573 	 */
3574 	pci_enable_acs(dev);
3575 }
3576 
3577 /**
3578  * pci_rebar_find_pos - find position of resize ctrl reg for BAR
3579  * @pdev: PCI device
3580  * @bar: BAR to find
3581  *
3582  * Helper to find the position of the ctrl register for a BAR.
3583  * Returns -ENOTSUPP if resizable BARs are not supported at all.
3584  * Returns -ENOENT if no ctrl register for the BAR could be found.
3585  */
3586 static int pci_rebar_find_pos(struct pci_dev *pdev, int bar)
3587 {
3588 	unsigned int pos, nbars, i;
3589 	u32 ctrl;
3590 
3591 	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR);
3592 	if (!pos)
3593 		return -ENOTSUPP;
3594 
3595 	pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3596 	nbars = (ctrl & PCI_REBAR_CTRL_NBAR_MASK) >>
3597 		    PCI_REBAR_CTRL_NBAR_SHIFT;
3598 
3599 	for (i = 0; i < nbars; i++, pos += 8) {
3600 		int bar_idx;
3601 
3602 		pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3603 		bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX;
3604 		if (bar_idx == bar)
3605 			return pos;
3606 	}
3607 
3608 	return -ENOENT;
3609 }
3610 
3611 /**
3612  * pci_rebar_get_possible_sizes - get possible sizes for BAR
3613  * @pdev: PCI device
3614  * @bar: BAR to query
3615  *
3616  * Get the possible sizes of a resizable BAR as bitmask defined in the spec
3617  * (bit 0=1MB, bit 19=512GB). Returns 0 if BAR isn't resizable.
3618  */
3619 u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar)
3620 {
3621 	int pos;
3622 	u32 cap;
3623 
3624 	pos = pci_rebar_find_pos(pdev, bar);
3625 	if (pos < 0)
3626 		return 0;
3627 
3628 	pci_read_config_dword(pdev, pos + PCI_REBAR_CAP, &cap);
3629 	cap &= PCI_REBAR_CAP_SIZES;
3630 
3631 	/* Sapphire RX 5600 XT Pulse has an invalid cap dword for BAR 0 */
3632 	if (pdev->vendor == PCI_VENDOR_ID_ATI && pdev->device == 0x731f &&
3633 	    bar == 0 && cap == 0x7000)
3634 		cap = 0x3f000;
3635 
3636 	return cap >> 4;
3637 }
3638 EXPORT_SYMBOL(pci_rebar_get_possible_sizes);
3639 
3640 /**
3641  * pci_rebar_get_current_size - get the current size of a BAR
3642  * @pdev: PCI device
3643  * @bar: BAR to set size to
3644  *
3645  * Read the size of a BAR from the resizable BAR config.
3646  * Returns size if found or negative error code.
3647  */
3648 int pci_rebar_get_current_size(struct pci_dev *pdev, int bar)
3649 {
3650 	int pos;
3651 	u32 ctrl;
3652 
3653 	pos = pci_rebar_find_pos(pdev, bar);
3654 	if (pos < 0)
3655 		return pos;
3656 
3657 	pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3658 	return (ctrl & PCI_REBAR_CTRL_BAR_SIZE) >> PCI_REBAR_CTRL_BAR_SHIFT;
3659 }
3660 
3661 /**
3662  * pci_rebar_set_size - set a new size for a BAR
3663  * @pdev: PCI device
3664  * @bar: BAR to set size to
3665  * @size: new size as defined in the spec (0=1MB, 19=512GB)
3666  *
3667  * Set the new size of a BAR as defined in the spec.
3668  * Returns zero if resizing was successful, error code otherwise.
3669  */
3670 int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size)
3671 {
3672 	int pos;
3673 	u32 ctrl;
3674 
3675 	pos = pci_rebar_find_pos(pdev, bar);
3676 	if (pos < 0)
3677 		return pos;
3678 
3679 	pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3680 	ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE;
3681 	ctrl |= size << PCI_REBAR_CTRL_BAR_SHIFT;
3682 	pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl);
3683 	return 0;
3684 }
3685 
3686 /**
3687  * pci_enable_atomic_ops_to_root - enable AtomicOp requests to root port
3688  * @dev: the PCI device
3689  * @cap_mask: mask of desired AtomicOp sizes, including one or more of:
3690  *	PCI_EXP_DEVCAP2_ATOMIC_COMP32
3691  *	PCI_EXP_DEVCAP2_ATOMIC_COMP64
3692  *	PCI_EXP_DEVCAP2_ATOMIC_COMP128
3693  *
3694  * Return 0 if all upstream bridges support AtomicOp routing, egress
3695  * blocking is disabled on all upstream ports, and the root port supports
3696  * the requested completion capabilities (32-bit, 64-bit and/or 128-bit
3697  * AtomicOp completion), or negative otherwise.
3698  */
3699 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask)
3700 {
3701 	struct pci_bus *bus = dev->bus;
3702 	struct pci_dev *bridge;
3703 	u32 cap, ctl2;
3704 
3705 	if (!pci_is_pcie(dev))
3706 		return -EINVAL;
3707 
3708 	/*
3709 	 * Per PCIe r4.0, sec 6.15, endpoints and root ports may be
3710 	 * AtomicOp requesters.  For now, we only support endpoints as
3711 	 * requesters and root ports as completers.  No endpoints as
3712 	 * completers, and no peer-to-peer.
3713 	 */
3714 
3715 	switch (pci_pcie_type(dev)) {
3716 	case PCI_EXP_TYPE_ENDPOINT:
3717 	case PCI_EXP_TYPE_LEG_END:
3718 	case PCI_EXP_TYPE_RC_END:
3719 		break;
3720 	default:
3721 		return -EINVAL;
3722 	}
3723 
3724 	while (bus->parent) {
3725 		bridge = bus->self;
3726 
3727 		pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
3728 
3729 		switch (pci_pcie_type(bridge)) {
3730 		/* Ensure switch ports support AtomicOp routing */
3731 		case PCI_EXP_TYPE_UPSTREAM:
3732 		case PCI_EXP_TYPE_DOWNSTREAM:
3733 			if (!(cap & PCI_EXP_DEVCAP2_ATOMIC_ROUTE))
3734 				return -EINVAL;
3735 			break;
3736 
3737 		/* Ensure root port supports all the sizes we care about */
3738 		case PCI_EXP_TYPE_ROOT_PORT:
3739 			if ((cap & cap_mask) != cap_mask)
3740 				return -EINVAL;
3741 			break;
3742 		}
3743 
3744 		/* Ensure upstream ports don't block AtomicOps on egress */
3745 		if (pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM) {
3746 			pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2,
3747 						   &ctl2);
3748 			if (ctl2 & PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK)
3749 				return -EINVAL;
3750 		}
3751 
3752 		bus = bus->parent;
3753 	}
3754 
3755 	pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
3756 				 PCI_EXP_DEVCTL2_ATOMIC_REQ);
3757 	return 0;
3758 }
3759 EXPORT_SYMBOL(pci_enable_atomic_ops_to_root);
3760 
3761 /**
3762  * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
3763  * @dev: the PCI device
3764  * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD)
3765  *
3766  * Perform INTx swizzling for a device behind one level of bridge.  This is
3767  * required by section 9.1 of the PCI-to-PCI bridge specification for devices
3768  * behind bridges on add-in cards.  For devices with ARI enabled, the slot
3769  * number is always 0 (see the Implementation Note in section 2.2.8.1 of
3770  * the PCI Express Base Specification, Revision 2.1)
3771  */
3772 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin)
3773 {
3774 	int slot;
3775 
3776 	if (pci_ari_enabled(dev->bus))
3777 		slot = 0;
3778 	else
3779 		slot = PCI_SLOT(dev->devfn);
3780 
3781 	return (((pin - 1) + slot) % 4) + 1;
3782 }
3783 
3784 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
3785 {
3786 	u8 pin;
3787 
3788 	pin = dev->pin;
3789 	if (!pin)
3790 		return -1;
3791 
3792 	while (!pci_is_root_bus(dev->bus)) {
3793 		pin = pci_swizzle_interrupt_pin(dev, pin);
3794 		dev = dev->bus->self;
3795 	}
3796 	*bridge = dev;
3797 	return pin;
3798 }
3799 
3800 /**
3801  * pci_common_swizzle - swizzle INTx all the way to root bridge
3802  * @dev: the PCI device
3803  * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
3804  *
3805  * Perform INTx swizzling for a device.  This traverses through all PCI-to-PCI
3806  * bridges all the way up to a PCI root bus.
3807  */
3808 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
3809 {
3810 	u8 pin = *pinp;
3811 
3812 	while (!pci_is_root_bus(dev->bus)) {
3813 		pin = pci_swizzle_interrupt_pin(dev, pin);
3814 		dev = dev->bus->self;
3815 	}
3816 	*pinp = pin;
3817 	return PCI_SLOT(dev->devfn);
3818 }
3819 EXPORT_SYMBOL_GPL(pci_common_swizzle);
3820 
3821 /**
3822  * pci_release_region - Release a PCI bar
3823  * @pdev: PCI device whose resources were previously reserved by
3824  *	  pci_request_region()
3825  * @bar: BAR to release
3826  *
3827  * Releases the PCI I/O and memory resources previously reserved by a
3828  * successful call to pci_request_region().  Call this function only
3829  * after all use of the PCI regions has ceased.
3830  */
3831 void pci_release_region(struct pci_dev *pdev, int bar)
3832 {
3833 	struct pci_devres *dr;
3834 
3835 	if (pci_resource_len(pdev, bar) == 0)
3836 		return;
3837 	if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
3838 		release_region(pci_resource_start(pdev, bar),
3839 				pci_resource_len(pdev, bar));
3840 	else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
3841 		release_mem_region(pci_resource_start(pdev, bar),
3842 				pci_resource_len(pdev, bar));
3843 
3844 	dr = find_pci_dr(pdev);
3845 	if (dr)
3846 		dr->region_mask &= ~(1 << bar);
3847 }
3848 EXPORT_SYMBOL(pci_release_region);
3849 
3850 /**
3851  * __pci_request_region - Reserved PCI I/O and memory resource
3852  * @pdev: PCI device whose resources are to be reserved
3853  * @bar: BAR to be reserved
3854  * @res_name: Name to be associated with resource.
3855  * @exclusive: whether the region access is exclusive or not
3856  *
3857  * Mark the PCI region associated with PCI device @pdev BAR @bar as
3858  * being reserved by owner @res_name.  Do not access any
3859  * address inside the PCI regions unless this call returns
3860  * successfully.
3861  *
3862  * If @exclusive is set, then the region is marked so that userspace
3863  * is explicitly not allowed to map the resource via /dev/mem or
3864  * sysfs MMIO access.
3865  *
3866  * Returns 0 on success, or %EBUSY on error.  A warning
3867  * message is also printed on failure.
3868  */
3869 static int __pci_request_region(struct pci_dev *pdev, int bar,
3870 				const char *res_name, int exclusive)
3871 {
3872 	struct pci_devres *dr;
3873 
3874 	if (pci_resource_len(pdev, bar) == 0)
3875 		return 0;
3876 
3877 	if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
3878 		if (!request_region(pci_resource_start(pdev, bar),
3879 			    pci_resource_len(pdev, bar), res_name))
3880 			goto err_out;
3881 	} else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
3882 		if (!__request_mem_region(pci_resource_start(pdev, bar),
3883 					pci_resource_len(pdev, bar), res_name,
3884 					exclusive))
3885 			goto err_out;
3886 	}
3887 
3888 	dr = find_pci_dr(pdev);
3889 	if (dr)
3890 		dr->region_mask |= 1 << bar;
3891 
3892 	return 0;
3893 
3894 err_out:
3895 	pci_warn(pdev, "BAR %d: can't reserve %pR\n", bar,
3896 		 &pdev->resource[bar]);
3897 	return -EBUSY;
3898 }
3899 
3900 /**
3901  * pci_request_region - Reserve PCI I/O and memory resource
3902  * @pdev: PCI device whose resources are to be reserved
3903  * @bar: BAR to be reserved
3904  * @res_name: Name to be associated with resource
3905  *
3906  * Mark the PCI region associated with PCI device @pdev BAR @bar as
3907  * being reserved by owner @res_name.  Do not access any
3908  * address inside the PCI regions unless this call returns
3909  * successfully.
3910  *
3911  * Returns 0 on success, or %EBUSY on error.  A warning
3912  * message is also printed on failure.
3913  */
3914 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
3915 {
3916 	return __pci_request_region(pdev, bar, res_name, 0);
3917 }
3918 EXPORT_SYMBOL(pci_request_region);
3919 
3920 /**
3921  * pci_release_selected_regions - Release selected PCI I/O and memory resources
3922  * @pdev: PCI device whose resources were previously reserved
3923  * @bars: Bitmask of BARs to be released
3924  *
3925  * Release selected PCI I/O and memory resources previously reserved.
3926  * Call this function only after all use of the PCI regions has ceased.
3927  */
3928 void pci_release_selected_regions(struct pci_dev *pdev, int bars)
3929 {
3930 	int i;
3931 
3932 	for (i = 0; i < PCI_STD_NUM_BARS; i++)
3933 		if (bars & (1 << i))
3934 			pci_release_region(pdev, i);
3935 }
3936 EXPORT_SYMBOL(pci_release_selected_regions);
3937 
3938 static int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
3939 					  const char *res_name, int excl)
3940 {
3941 	int i;
3942 
3943 	for (i = 0; i < PCI_STD_NUM_BARS; i++)
3944 		if (bars & (1 << i))
3945 			if (__pci_request_region(pdev, i, res_name, excl))
3946 				goto err_out;
3947 	return 0;
3948 
3949 err_out:
3950 	while (--i >= 0)
3951 		if (bars & (1 << i))
3952 			pci_release_region(pdev, i);
3953 
3954 	return -EBUSY;
3955 }
3956 
3957 
3958 /**
3959  * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
3960  * @pdev: PCI device whose resources are to be reserved
3961  * @bars: Bitmask of BARs to be requested
3962  * @res_name: Name to be associated with resource
3963  */
3964 int pci_request_selected_regions(struct pci_dev *pdev, int bars,
3965 				 const char *res_name)
3966 {
3967 	return __pci_request_selected_regions(pdev, bars, res_name, 0);
3968 }
3969 EXPORT_SYMBOL(pci_request_selected_regions);
3970 
3971 int pci_request_selected_regions_exclusive(struct pci_dev *pdev, int bars,
3972 					   const char *res_name)
3973 {
3974 	return __pci_request_selected_regions(pdev, bars, res_name,
3975 			IORESOURCE_EXCLUSIVE);
3976 }
3977 EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
3978 
3979 /**
3980  * pci_release_regions - Release reserved PCI I/O and memory resources
3981  * @pdev: PCI device whose resources were previously reserved by
3982  *	  pci_request_regions()
3983  *
3984  * Releases all PCI I/O and memory resources previously reserved by a
3985  * successful call to pci_request_regions().  Call this function only
3986  * after all use of the PCI regions has ceased.
3987  */
3988 
3989 void pci_release_regions(struct pci_dev *pdev)
3990 {
3991 	pci_release_selected_regions(pdev, (1 << PCI_STD_NUM_BARS) - 1);
3992 }
3993 EXPORT_SYMBOL(pci_release_regions);
3994 
3995 /**
3996  * pci_request_regions - Reserve PCI I/O and memory resources
3997  * @pdev: PCI device whose resources are to be reserved
3998  * @res_name: Name to be associated with resource.
3999  *
4000  * Mark all PCI regions associated with PCI device @pdev as
4001  * being reserved by owner @res_name.  Do not access any
4002  * address inside the PCI regions unless this call returns
4003  * successfully.
4004  *
4005  * Returns 0 on success, or %EBUSY on error.  A warning
4006  * message is also printed on failure.
4007  */
4008 int pci_request_regions(struct pci_dev *pdev, const char *res_name)
4009 {
4010 	return pci_request_selected_regions(pdev,
4011 			((1 << PCI_STD_NUM_BARS) - 1), res_name);
4012 }
4013 EXPORT_SYMBOL(pci_request_regions);
4014 
4015 /**
4016  * pci_request_regions_exclusive - Reserve PCI I/O and memory resources
4017  * @pdev: PCI device whose resources are to be reserved
4018  * @res_name: Name to be associated with resource.
4019  *
4020  * Mark all PCI regions associated with PCI device @pdev as being reserved
4021  * by owner @res_name.  Do not access any address inside the PCI regions
4022  * unless this call returns successfully.
4023  *
4024  * pci_request_regions_exclusive() will mark the region so that /dev/mem
4025  * and the sysfs MMIO access will not be allowed.
4026  *
4027  * Returns 0 on success, or %EBUSY on error.  A warning message is also
4028  * printed on failure.
4029  */
4030 int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
4031 {
4032 	return pci_request_selected_regions_exclusive(pdev,
4033 				((1 << PCI_STD_NUM_BARS) - 1), res_name);
4034 }
4035 EXPORT_SYMBOL(pci_request_regions_exclusive);
4036 
4037 /*
4038  * Record the PCI IO range (expressed as CPU physical address + size).
4039  * Return a negative value if an error has occurred, zero otherwise
4040  */
4041 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
4042 			resource_size_t	size)
4043 {
4044 	int ret = 0;
4045 #ifdef PCI_IOBASE
4046 	struct logic_pio_hwaddr *range;
4047 
4048 	if (!size || addr + size < addr)
4049 		return -EINVAL;
4050 
4051 	range = kzalloc(sizeof(*range), GFP_ATOMIC);
4052 	if (!range)
4053 		return -ENOMEM;
4054 
4055 	range->fwnode = fwnode;
4056 	range->size = size;
4057 	range->hw_start = addr;
4058 	range->flags = LOGIC_PIO_CPU_MMIO;
4059 
4060 	ret = logic_pio_register_range(range);
4061 	if (ret)
4062 		kfree(range);
4063 
4064 	/* Ignore duplicates due to deferred probing */
4065 	if (ret == -EEXIST)
4066 		ret = 0;
4067 #endif
4068 
4069 	return ret;
4070 }
4071 
4072 phys_addr_t pci_pio_to_address(unsigned long pio)
4073 {
4074 	phys_addr_t address = (phys_addr_t)OF_BAD_ADDR;
4075 
4076 #ifdef PCI_IOBASE
4077 	if (pio >= MMIO_UPPER_LIMIT)
4078 		return address;
4079 
4080 	address = logic_pio_to_hwaddr(pio);
4081 #endif
4082 
4083 	return address;
4084 }
4085 EXPORT_SYMBOL_GPL(pci_pio_to_address);
4086 
4087 unsigned long __weak pci_address_to_pio(phys_addr_t address)
4088 {
4089 #ifdef PCI_IOBASE
4090 	return logic_pio_trans_cpuaddr(address);
4091 #else
4092 	if (address > IO_SPACE_LIMIT)
4093 		return (unsigned long)-1;
4094 
4095 	return (unsigned long) address;
4096 #endif
4097 }
4098 
4099 /**
4100  * pci_remap_iospace - Remap the memory mapped I/O space
4101  * @res: Resource describing the I/O space
4102  * @phys_addr: physical address of range to be mapped
4103  *
4104  * Remap the memory mapped I/O space described by the @res and the CPU
4105  * physical address @phys_addr into virtual address space.  Only
4106  * architectures that have memory mapped IO functions defined (and the
4107  * PCI_IOBASE value defined) should call this function.
4108  */
4109 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr)
4110 {
4111 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
4112 	unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
4113 
4114 	if (!(res->flags & IORESOURCE_IO))
4115 		return -EINVAL;
4116 
4117 	if (res->end > IO_SPACE_LIMIT)
4118 		return -EINVAL;
4119 
4120 	return ioremap_page_range(vaddr, vaddr + resource_size(res), phys_addr,
4121 				  pgprot_device(PAGE_KERNEL));
4122 #else
4123 	/*
4124 	 * This architecture does not have memory mapped I/O space,
4125 	 * so this function should never be called
4126 	 */
4127 	WARN_ONCE(1, "This architecture does not support memory mapped I/O\n");
4128 	return -ENODEV;
4129 #endif
4130 }
4131 EXPORT_SYMBOL(pci_remap_iospace);
4132 
4133 /**
4134  * pci_unmap_iospace - Unmap the memory mapped I/O space
4135  * @res: resource to be unmapped
4136  *
4137  * Unmap the CPU virtual address @res from virtual address space.  Only
4138  * architectures that have memory mapped IO functions defined (and the
4139  * PCI_IOBASE value defined) should call this function.
4140  */
4141 void pci_unmap_iospace(struct resource *res)
4142 {
4143 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
4144 	unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
4145 
4146 	vunmap_range(vaddr, vaddr + resource_size(res));
4147 #endif
4148 }
4149 EXPORT_SYMBOL(pci_unmap_iospace);
4150 
4151 static void devm_pci_unmap_iospace(struct device *dev, void *ptr)
4152 {
4153 	struct resource **res = ptr;
4154 
4155 	pci_unmap_iospace(*res);
4156 }
4157 
4158 /**
4159  * devm_pci_remap_iospace - Managed pci_remap_iospace()
4160  * @dev: Generic device to remap IO address for
4161  * @res: Resource describing the I/O space
4162  * @phys_addr: physical address of range to be mapped
4163  *
4164  * Managed pci_remap_iospace().  Map is automatically unmapped on driver
4165  * detach.
4166  */
4167 int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
4168 			   phys_addr_t phys_addr)
4169 {
4170 	const struct resource **ptr;
4171 	int error;
4172 
4173 	ptr = devres_alloc(devm_pci_unmap_iospace, sizeof(*ptr), GFP_KERNEL);
4174 	if (!ptr)
4175 		return -ENOMEM;
4176 
4177 	error = pci_remap_iospace(res, phys_addr);
4178 	if (error) {
4179 		devres_free(ptr);
4180 	} else	{
4181 		*ptr = res;
4182 		devres_add(dev, ptr);
4183 	}
4184 
4185 	return error;
4186 }
4187 EXPORT_SYMBOL(devm_pci_remap_iospace);
4188 
4189 /**
4190  * devm_pci_remap_cfgspace - Managed pci_remap_cfgspace()
4191  * @dev: Generic device to remap IO address for
4192  * @offset: Resource address to map
4193  * @size: Size of map
4194  *
4195  * Managed pci_remap_cfgspace().  Map is automatically unmapped on driver
4196  * detach.
4197  */
4198 void __iomem *devm_pci_remap_cfgspace(struct device *dev,
4199 				      resource_size_t offset,
4200 				      resource_size_t size)
4201 {
4202 	void __iomem **ptr, *addr;
4203 
4204 	ptr = devres_alloc(devm_ioremap_release, sizeof(*ptr), GFP_KERNEL);
4205 	if (!ptr)
4206 		return NULL;
4207 
4208 	addr = pci_remap_cfgspace(offset, size);
4209 	if (addr) {
4210 		*ptr = addr;
4211 		devres_add(dev, ptr);
4212 	} else
4213 		devres_free(ptr);
4214 
4215 	return addr;
4216 }
4217 EXPORT_SYMBOL(devm_pci_remap_cfgspace);
4218 
4219 /**
4220  * devm_pci_remap_cfg_resource - check, request region and ioremap cfg resource
4221  * @dev: generic device to handle the resource for
4222  * @res: configuration space resource to be handled
4223  *
4224  * Checks that a resource is a valid memory region, requests the memory
4225  * region and ioremaps with pci_remap_cfgspace() API that ensures the
4226  * proper PCI configuration space memory attributes are guaranteed.
4227  *
4228  * All operations are managed and will be undone on driver detach.
4229  *
4230  * Returns a pointer to the remapped memory or an ERR_PTR() encoded error code
4231  * on failure. Usage example::
4232  *
4233  *	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4234  *	base = devm_pci_remap_cfg_resource(&pdev->dev, res);
4235  *	if (IS_ERR(base))
4236  *		return PTR_ERR(base);
4237  */
4238 void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
4239 					  struct resource *res)
4240 {
4241 	resource_size_t size;
4242 	const char *name;
4243 	void __iomem *dest_ptr;
4244 
4245 	BUG_ON(!dev);
4246 
4247 	if (!res || resource_type(res) != IORESOURCE_MEM) {
4248 		dev_err(dev, "invalid resource\n");
4249 		return IOMEM_ERR_PTR(-EINVAL);
4250 	}
4251 
4252 	size = resource_size(res);
4253 
4254 	if (res->name)
4255 		name = devm_kasprintf(dev, GFP_KERNEL, "%s %s", dev_name(dev),
4256 				      res->name);
4257 	else
4258 		name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL);
4259 	if (!name)
4260 		return IOMEM_ERR_PTR(-ENOMEM);
4261 
4262 	if (!devm_request_mem_region(dev, res->start, size, name)) {
4263 		dev_err(dev, "can't request region for resource %pR\n", res);
4264 		return IOMEM_ERR_PTR(-EBUSY);
4265 	}
4266 
4267 	dest_ptr = devm_pci_remap_cfgspace(dev, res->start, size);
4268 	if (!dest_ptr) {
4269 		dev_err(dev, "ioremap failed for resource %pR\n", res);
4270 		devm_release_mem_region(dev, res->start, size);
4271 		dest_ptr = IOMEM_ERR_PTR(-ENOMEM);
4272 	}
4273 
4274 	return dest_ptr;
4275 }
4276 EXPORT_SYMBOL(devm_pci_remap_cfg_resource);
4277 
4278 static void __pci_set_master(struct pci_dev *dev, bool enable)
4279 {
4280 	u16 old_cmd, cmd;
4281 
4282 	pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
4283 	if (enable)
4284 		cmd = old_cmd | PCI_COMMAND_MASTER;
4285 	else
4286 		cmd = old_cmd & ~PCI_COMMAND_MASTER;
4287 	if (cmd != old_cmd) {
4288 		pci_dbg(dev, "%s bus mastering\n",
4289 			enable ? "enabling" : "disabling");
4290 		pci_write_config_word(dev, PCI_COMMAND, cmd);
4291 	}
4292 	dev->is_busmaster = enable;
4293 }
4294 
4295 /**
4296  * pcibios_setup - process "pci=" kernel boot arguments
4297  * @str: string used to pass in "pci=" kernel boot arguments
4298  *
4299  * Process kernel boot arguments.  This is the default implementation.
4300  * Architecture specific implementations can override this as necessary.
4301  */
4302 char * __weak __init pcibios_setup(char *str)
4303 {
4304 	return str;
4305 }
4306 
4307 /**
4308  * pcibios_set_master - enable PCI bus-mastering for device dev
4309  * @dev: the PCI device to enable
4310  *
4311  * Enables PCI bus-mastering for the device.  This is the default
4312  * implementation.  Architecture specific implementations can override
4313  * this if necessary.
4314  */
4315 void __weak pcibios_set_master(struct pci_dev *dev)
4316 {
4317 	u8 lat;
4318 
4319 	/* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */
4320 	if (pci_is_pcie(dev))
4321 		return;
4322 
4323 	pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
4324 	if (lat < 16)
4325 		lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
4326 	else if (lat > pcibios_max_latency)
4327 		lat = pcibios_max_latency;
4328 	else
4329 		return;
4330 
4331 	pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
4332 }
4333 
4334 /**
4335  * pci_set_master - enables bus-mastering for device dev
4336  * @dev: the PCI device to enable
4337  *
4338  * Enables bus-mastering on the device and calls pcibios_set_master()
4339  * to do the needed arch specific settings.
4340  */
4341 void pci_set_master(struct pci_dev *dev)
4342 {
4343 	__pci_set_master(dev, true);
4344 	pcibios_set_master(dev);
4345 }
4346 EXPORT_SYMBOL(pci_set_master);
4347 
4348 /**
4349  * pci_clear_master - disables bus-mastering for device dev
4350  * @dev: the PCI device to disable
4351  */
4352 void pci_clear_master(struct pci_dev *dev)
4353 {
4354 	__pci_set_master(dev, false);
4355 }
4356 EXPORT_SYMBOL(pci_clear_master);
4357 
4358 /**
4359  * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
4360  * @dev: the PCI device for which MWI is to be enabled
4361  *
4362  * Helper function for pci_set_mwi.
4363  * Originally copied from drivers/net/acenic.c.
4364  * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
4365  *
4366  * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4367  */
4368 int pci_set_cacheline_size(struct pci_dev *dev)
4369 {
4370 	u8 cacheline_size;
4371 
4372 	if (!pci_cache_line_size)
4373 		return -EINVAL;
4374 
4375 	/* Validate current setting: the PCI_CACHE_LINE_SIZE must be
4376 	   equal to or multiple of the right value. */
4377 	pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
4378 	if (cacheline_size >= pci_cache_line_size &&
4379 	    (cacheline_size % pci_cache_line_size) == 0)
4380 		return 0;
4381 
4382 	/* Write the correct value. */
4383 	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
4384 	/* Read it back. */
4385 	pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
4386 	if (cacheline_size == pci_cache_line_size)
4387 		return 0;
4388 
4389 	pci_dbg(dev, "cache line size of %d is not supported\n",
4390 		   pci_cache_line_size << 2);
4391 
4392 	return -EINVAL;
4393 }
4394 EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
4395 
4396 /**
4397  * pci_set_mwi - enables memory-write-invalidate PCI transaction
4398  * @dev: the PCI device for which MWI is enabled
4399  *
4400  * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
4401  *
4402  * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4403  */
4404 int pci_set_mwi(struct pci_dev *dev)
4405 {
4406 #ifdef PCI_DISABLE_MWI
4407 	return 0;
4408 #else
4409 	int rc;
4410 	u16 cmd;
4411 
4412 	rc = pci_set_cacheline_size(dev);
4413 	if (rc)
4414 		return rc;
4415 
4416 	pci_read_config_word(dev, PCI_COMMAND, &cmd);
4417 	if (!(cmd & PCI_COMMAND_INVALIDATE)) {
4418 		pci_dbg(dev, "enabling Mem-Wr-Inval\n");
4419 		cmd |= PCI_COMMAND_INVALIDATE;
4420 		pci_write_config_word(dev, PCI_COMMAND, cmd);
4421 	}
4422 	return 0;
4423 #endif
4424 }
4425 EXPORT_SYMBOL(pci_set_mwi);
4426 
4427 /**
4428  * pcim_set_mwi - a device-managed pci_set_mwi()
4429  * @dev: the PCI device for which MWI is enabled
4430  *
4431  * Managed pci_set_mwi().
4432  *
4433  * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4434  */
4435 int pcim_set_mwi(struct pci_dev *dev)
4436 {
4437 	struct pci_devres *dr;
4438 
4439 	dr = find_pci_dr(dev);
4440 	if (!dr)
4441 		return -ENOMEM;
4442 
4443 	dr->mwi = 1;
4444 	return pci_set_mwi(dev);
4445 }
4446 EXPORT_SYMBOL(pcim_set_mwi);
4447 
4448 /**
4449  * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
4450  * @dev: the PCI device for which MWI is enabled
4451  *
4452  * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
4453  * Callers are not required to check the return value.
4454  *
4455  * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4456  */
4457 int pci_try_set_mwi(struct pci_dev *dev)
4458 {
4459 #ifdef PCI_DISABLE_MWI
4460 	return 0;
4461 #else
4462 	return pci_set_mwi(dev);
4463 #endif
4464 }
4465 EXPORT_SYMBOL(pci_try_set_mwi);
4466 
4467 /**
4468  * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
4469  * @dev: the PCI device to disable
4470  *
4471  * Disables PCI Memory-Write-Invalidate transaction on the device
4472  */
4473 void pci_clear_mwi(struct pci_dev *dev)
4474 {
4475 #ifndef PCI_DISABLE_MWI
4476 	u16 cmd;
4477 
4478 	pci_read_config_word(dev, PCI_COMMAND, &cmd);
4479 	if (cmd & PCI_COMMAND_INVALIDATE) {
4480 		cmd &= ~PCI_COMMAND_INVALIDATE;
4481 		pci_write_config_word(dev, PCI_COMMAND, cmd);
4482 	}
4483 #endif
4484 }
4485 EXPORT_SYMBOL(pci_clear_mwi);
4486 
4487 /**
4488  * pci_disable_parity - disable parity checking for device
4489  * @dev: the PCI device to operate on
4490  *
4491  * Disable parity checking for device @dev
4492  */
4493 void pci_disable_parity(struct pci_dev *dev)
4494 {
4495 	u16 cmd;
4496 
4497 	pci_read_config_word(dev, PCI_COMMAND, &cmd);
4498 	if (cmd & PCI_COMMAND_PARITY) {
4499 		cmd &= ~PCI_COMMAND_PARITY;
4500 		pci_write_config_word(dev, PCI_COMMAND, cmd);
4501 	}
4502 }
4503 
4504 /**
4505  * pci_intx - enables/disables PCI INTx for device dev
4506  * @pdev: the PCI device to operate on
4507  * @enable: boolean: whether to enable or disable PCI INTx
4508  *
4509  * Enables/disables PCI INTx for device @pdev
4510  */
4511 void pci_intx(struct pci_dev *pdev, int enable)
4512 {
4513 	u16 pci_command, new;
4514 
4515 	pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
4516 
4517 	if (enable)
4518 		new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
4519 	else
4520 		new = pci_command | PCI_COMMAND_INTX_DISABLE;
4521 
4522 	if (new != pci_command) {
4523 		struct pci_devres *dr;
4524 
4525 		pci_write_config_word(pdev, PCI_COMMAND, new);
4526 
4527 		dr = find_pci_dr(pdev);
4528 		if (dr && !dr->restore_intx) {
4529 			dr->restore_intx = 1;
4530 			dr->orig_intx = !enable;
4531 		}
4532 	}
4533 }
4534 EXPORT_SYMBOL_GPL(pci_intx);
4535 
4536 static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask)
4537 {
4538 	struct pci_bus *bus = dev->bus;
4539 	bool mask_updated = true;
4540 	u32 cmd_status_dword;
4541 	u16 origcmd, newcmd;
4542 	unsigned long flags;
4543 	bool irq_pending;
4544 
4545 	/*
4546 	 * We do a single dword read to retrieve both command and status.
4547 	 * Document assumptions that make this possible.
4548 	 */
4549 	BUILD_BUG_ON(PCI_COMMAND % 4);
4550 	BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS);
4551 
4552 	raw_spin_lock_irqsave(&pci_lock, flags);
4553 
4554 	bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword);
4555 
4556 	irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT;
4557 
4558 	/*
4559 	 * Check interrupt status register to see whether our device
4560 	 * triggered the interrupt (when masking) or the next IRQ is
4561 	 * already pending (when unmasking).
4562 	 */
4563 	if (mask != irq_pending) {
4564 		mask_updated = false;
4565 		goto done;
4566 	}
4567 
4568 	origcmd = cmd_status_dword;
4569 	newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE;
4570 	if (mask)
4571 		newcmd |= PCI_COMMAND_INTX_DISABLE;
4572 	if (newcmd != origcmd)
4573 		bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd);
4574 
4575 done:
4576 	raw_spin_unlock_irqrestore(&pci_lock, flags);
4577 
4578 	return mask_updated;
4579 }
4580 
4581 /**
4582  * pci_check_and_mask_intx - mask INTx on pending interrupt
4583  * @dev: the PCI device to operate on
4584  *
4585  * Check if the device dev has its INTx line asserted, mask it and return
4586  * true in that case. False is returned if no interrupt was pending.
4587  */
4588 bool pci_check_and_mask_intx(struct pci_dev *dev)
4589 {
4590 	return pci_check_and_set_intx_mask(dev, true);
4591 }
4592 EXPORT_SYMBOL_GPL(pci_check_and_mask_intx);
4593 
4594 /**
4595  * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending
4596  * @dev: the PCI device to operate on
4597  *
4598  * Check if the device dev has its INTx line asserted, unmask it if not and
4599  * return true. False is returned and the mask remains active if there was
4600  * still an interrupt pending.
4601  */
4602 bool pci_check_and_unmask_intx(struct pci_dev *dev)
4603 {
4604 	return pci_check_and_set_intx_mask(dev, false);
4605 }
4606 EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx);
4607 
4608 /**
4609  * pci_wait_for_pending_transaction - wait for pending transaction
4610  * @dev: the PCI device to operate on
4611  *
4612  * Return 0 if transaction is pending 1 otherwise.
4613  */
4614 int pci_wait_for_pending_transaction(struct pci_dev *dev)
4615 {
4616 	if (!pci_is_pcie(dev))
4617 		return 1;
4618 
4619 	return pci_wait_for_pending(dev, pci_pcie_cap(dev) + PCI_EXP_DEVSTA,
4620 				    PCI_EXP_DEVSTA_TRPND);
4621 }
4622 EXPORT_SYMBOL(pci_wait_for_pending_transaction);
4623 
4624 /**
4625  * pcie_has_flr - check if a device supports function level resets
4626  * @dev: device to check
4627  *
4628  * Returns true if the device advertises support for PCIe function level
4629  * resets.
4630  */
4631 bool pcie_has_flr(struct pci_dev *dev)
4632 {
4633 	u32 cap;
4634 
4635 	if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET)
4636 		return false;
4637 
4638 	pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
4639 	return cap & PCI_EXP_DEVCAP_FLR;
4640 }
4641 EXPORT_SYMBOL_GPL(pcie_has_flr);
4642 
4643 /**
4644  * pcie_flr - initiate a PCIe function level reset
4645  * @dev: device to reset
4646  *
4647  * Initiate a function level reset on @dev.  The caller should ensure the
4648  * device supports FLR before calling this function, e.g. by using the
4649  * pcie_has_flr() helper.
4650  */
4651 int pcie_flr(struct pci_dev *dev)
4652 {
4653 	if (!pci_wait_for_pending_transaction(dev))
4654 		pci_err(dev, "timed out waiting for pending transaction; performing function level reset anyway\n");
4655 
4656 	pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
4657 
4658 	if (dev->imm_ready)
4659 		return 0;
4660 
4661 	/*
4662 	 * Per PCIe r4.0, sec 6.6.2, a device must complete an FLR within
4663 	 * 100ms, but may silently discard requests while the FLR is in
4664 	 * progress.  Wait 100ms before trying to access the device.
4665 	 */
4666 	msleep(100);
4667 
4668 	return pci_dev_wait(dev, "FLR", PCIE_RESET_READY_POLL_MS);
4669 }
4670 EXPORT_SYMBOL_GPL(pcie_flr);
4671 
4672 static int pci_af_flr(struct pci_dev *dev, int probe)
4673 {
4674 	int pos;
4675 	u8 cap;
4676 
4677 	pos = pci_find_capability(dev, PCI_CAP_ID_AF);
4678 	if (!pos)
4679 		return -ENOTTY;
4680 
4681 	if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET)
4682 		return -ENOTTY;
4683 
4684 	pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
4685 	if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
4686 		return -ENOTTY;
4687 
4688 	if (probe)
4689 		return 0;
4690 
4691 	/*
4692 	 * Wait for Transaction Pending bit to clear.  A word-aligned test
4693 	 * is used, so we use the control offset rather than status and shift
4694 	 * the test bit to match.
4695 	 */
4696 	if (!pci_wait_for_pending(dev, pos + PCI_AF_CTRL,
4697 				 PCI_AF_STATUS_TP << 8))
4698 		pci_err(dev, "timed out waiting for pending transaction; performing AF function level reset anyway\n");
4699 
4700 	pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
4701 
4702 	if (dev->imm_ready)
4703 		return 0;
4704 
4705 	/*
4706 	 * Per Advanced Capabilities for Conventional PCI ECN, 13 April 2006,
4707 	 * updated 27 July 2006; a device must complete an FLR within
4708 	 * 100ms, but may silently discard requests while the FLR is in
4709 	 * progress.  Wait 100ms before trying to access the device.
4710 	 */
4711 	msleep(100);
4712 
4713 	return pci_dev_wait(dev, "AF_FLR", PCIE_RESET_READY_POLL_MS);
4714 }
4715 
4716 /**
4717  * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
4718  * @dev: Device to reset.
4719  * @probe: If set, only check if the device can be reset this way.
4720  *
4721  * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
4722  * unset, it will be reinitialized internally when going from PCI_D3hot to
4723  * PCI_D0.  If that's the case and the device is not in a low-power state
4724  * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
4725  *
4726  * NOTE: This causes the caller to sleep for twice the device power transition
4727  * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
4728  * by default (i.e. unless the @dev's d3hot_delay field has a different value).
4729  * Moreover, only devices in D0 can be reset by this function.
4730  */
4731 static int pci_pm_reset(struct pci_dev *dev, int probe)
4732 {
4733 	u16 csr;
4734 
4735 	if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET)
4736 		return -ENOTTY;
4737 
4738 	pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
4739 	if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
4740 		return -ENOTTY;
4741 
4742 	if (probe)
4743 		return 0;
4744 
4745 	if (dev->current_state != PCI_D0)
4746 		return -EINVAL;
4747 
4748 	csr &= ~PCI_PM_CTRL_STATE_MASK;
4749 	csr |= PCI_D3hot;
4750 	pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
4751 	pci_dev_d3_sleep(dev);
4752 
4753 	csr &= ~PCI_PM_CTRL_STATE_MASK;
4754 	csr |= PCI_D0;
4755 	pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
4756 	pci_dev_d3_sleep(dev);
4757 
4758 	return pci_dev_wait(dev, "PM D3hot->D0", PCIE_RESET_READY_POLL_MS);
4759 }
4760 
4761 /**
4762  * pcie_wait_for_link_delay - Wait until link is active or inactive
4763  * @pdev: Bridge device
4764  * @active: waiting for active or inactive?
4765  * @delay: Delay to wait after link has become active (in ms)
4766  *
4767  * Use this to wait till link becomes active or inactive.
4768  */
4769 static bool pcie_wait_for_link_delay(struct pci_dev *pdev, bool active,
4770 				     int delay)
4771 {
4772 	int timeout = 1000;
4773 	bool ret;
4774 	u16 lnk_status;
4775 
4776 	/*
4777 	 * Some controllers might not implement link active reporting. In this
4778 	 * case, we wait for 1000 ms + any delay requested by the caller.
4779 	 */
4780 	if (!pdev->link_active_reporting) {
4781 		msleep(timeout + delay);
4782 		return true;
4783 	}
4784 
4785 	/*
4786 	 * PCIe r4.0 sec 6.6.1, a component must enter LTSSM Detect within 20ms,
4787 	 * after which we should expect an link active if the reset was
4788 	 * successful. If so, software must wait a minimum 100ms before sending
4789 	 * configuration requests to devices downstream this port.
4790 	 *
4791 	 * If the link fails to activate, either the device was physically
4792 	 * removed or the link is permanently failed.
4793 	 */
4794 	if (active)
4795 		msleep(20);
4796 	for (;;) {
4797 		pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
4798 		ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA);
4799 		if (ret == active)
4800 			break;
4801 		if (timeout <= 0)
4802 			break;
4803 		msleep(10);
4804 		timeout -= 10;
4805 	}
4806 	if (active && ret)
4807 		msleep(delay);
4808 
4809 	return ret == active;
4810 }
4811 
4812 /**
4813  * pcie_wait_for_link - Wait until link is active or inactive
4814  * @pdev: Bridge device
4815  * @active: waiting for active or inactive?
4816  *
4817  * Use this to wait till link becomes active or inactive.
4818  */
4819 bool pcie_wait_for_link(struct pci_dev *pdev, bool active)
4820 {
4821 	return pcie_wait_for_link_delay(pdev, active, 100);
4822 }
4823 
4824 /*
4825  * Find maximum D3cold delay required by all the devices on the bus.  The
4826  * spec says 100 ms, but firmware can lower it and we allow drivers to
4827  * increase it as well.
4828  *
4829  * Called with @pci_bus_sem locked for reading.
4830  */
4831 static int pci_bus_max_d3cold_delay(const struct pci_bus *bus)
4832 {
4833 	const struct pci_dev *pdev;
4834 	int min_delay = 100;
4835 	int max_delay = 0;
4836 
4837 	list_for_each_entry(pdev, &bus->devices, bus_list) {
4838 		if (pdev->d3cold_delay < min_delay)
4839 			min_delay = pdev->d3cold_delay;
4840 		if (pdev->d3cold_delay > max_delay)
4841 			max_delay = pdev->d3cold_delay;
4842 	}
4843 
4844 	return max(min_delay, max_delay);
4845 }
4846 
4847 /**
4848  * pci_bridge_wait_for_secondary_bus - Wait for secondary bus to be accessible
4849  * @dev: PCI bridge
4850  *
4851  * Handle necessary delays before access to the devices on the secondary
4852  * side of the bridge are permitted after D3cold to D0 transition.
4853  *
4854  * For PCIe this means the delays in PCIe 5.0 section 6.6.1. For
4855  * conventional PCI it means Tpvrh + Trhfa specified in PCI 3.0 section
4856  * 4.3.2.
4857  */
4858 void pci_bridge_wait_for_secondary_bus(struct pci_dev *dev)
4859 {
4860 	struct pci_dev *child;
4861 	int delay;
4862 
4863 	if (pci_dev_is_disconnected(dev))
4864 		return;
4865 
4866 	if (!pci_is_bridge(dev) || !dev->bridge_d3)
4867 		return;
4868 
4869 	down_read(&pci_bus_sem);
4870 
4871 	/*
4872 	 * We only deal with devices that are present currently on the bus.
4873 	 * For any hot-added devices the access delay is handled in pciehp
4874 	 * board_added(). In case of ACPI hotplug the firmware is expected
4875 	 * to configure the devices before OS is notified.
4876 	 */
4877 	if (!dev->subordinate || list_empty(&dev->subordinate->devices)) {
4878 		up_read(&pci_bus_sem);
4879 		return;
4880 	}
4881 
4882 	/* Take d3cold_delay requirements into account */
4883 	delay = pci_bus_max_d3cold_delay(dev->subordinate);
4884 	if (!delay) {
4885 		up_read(&pci_bus_sem);
4886 		return;
4887 	}
4888 
4889 	child = list_first_entry(&dev->subordinate->devices, struct pci_dev,
4890 				 bus_list);
4891 	up_read(&pci_bus_sem);
4892 
4893 	/*
4894 	 * Conventional PCI and PCI-X we need to wait Tpvrh + Trhfa before
4895 	 * accessing the device after reset (that is 1000 ms + 100 ms). In
4896 	 * practice this should not be needed because we don't do power
4897 	 * management for them (see pci_bridge_d3_possible()).
4898 	 */
4899 	if (!pci_is_pcie(dev)) {
4900 		pci_dbg(dev, "waiting %d ms for secondary bus\n", 1000 + delay);
4901 		msleep(1000 + delay);
4902 		return;
4903 	}
4904 
4905 	/*
4906 	 * For PCIe downstream and root ports that do not support speeds
4907 	 * greater than 5 GT/s need to wait minimum 100 ms. For higher
4908 	 * speeds (gen3) we need to wait first for the data link layer to
4909 	 * become active.
4910 	 *
4911 	 * However, 100 ms is the minimum and the PCIe spec says the
4912 	 * software must allow at least 1s before it can determine that the
4913 	 * device that did not respond is a broken device. There is
4914 	 * evidence that 100 ms is not always enough, for example certain
4915 	 * Titan Ridge xHCI controller does not always respond to
4916 	 * configuration requests if we only wait for 100 ms (see
4917 	 * https://bugzilla.kernel.org/show_bug.cgi?id=203885).
4918 	 *
4919 	 * Therefore we wait for 100 ms and check for the device presence.
4920 	 * If it is still not present give it an additional 100 ms.
4921 	 */
4922 	if (!pcie_downstream_port(dev))
4923 		return;
4924 
4925 	if (pcie_get_speed_cap(dev) <= PCIE_SPEED_5_0GT) {
4926 		pci_dbg(dev, "waiting %d ms for downstream link\n", delay);
4927 		msleep(delay);
4928 	} else {
4929 		pci_dbg(dev, "waiting %d ms for downstream link, after activation\n",
4930 			delay);
4931 		if (!pcie_wait_for_link_delay(dev, true, delay)) {
4932 			/* Did not train, no need to wait any further */
4933 			pci_info(dev, "Data Link Layer Link Active not set in 1000 msec\n");
4934 			return;
4935 		}
4936 	}
4937 
4938 	if (!pci_device_is_present(child)) {
4939 		pci_dbg(child, "waiting additional %d ms to become accessible\n", delay);
4940 		msleep(delay);
4941 	}
4942 }
4943 
4944 void pci_reset_secondary_bus(struct pci_dev *dev)
4945 {
4946 	u16 ctrl;
4947 
4948 	pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
4949 	ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
4950 	pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
4951 
4952 	/*
4953 	 * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms.  Double
4954 	 * this to 2ms to ensure that we meet the minimum requirement.
4955 	 */
4956 	msleep(2);
4957 
4958 	ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
4959 	pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
4960 
4961 	/*
4962 	 * Trhfa for conventional PCI is 2^25 clock cycles.
4963 	 * Assuming a minimum 33MHz clock this results in a 1s
4964 	 * delay before we can consider subordinate devices to
4965 	 * be re-initialized.  PCIe has some ways to shorten this,
4966 	 * but we don't make use of them yet.
4967 	 */
4968 	ssleep(1);
4969 }
4970 
4971 void __weak pcibios_reset_secondary_bus(struct pci_dev *dev)
4972 {
4973 	pci_reset_secondary_bus(dev);
4974 }
4975 
4976 /**
4977  * pci_bridge_secondary_bus_reset - Reset the secondary bus on a PCI bridge.
4978  * @dev: Bridge device
4979  *
4980  * Use the bridge control register to assert reset on the secondary bus.
4981  * Devices on the secondary bus are left in power-on state.
4982  */
4983 int pci_bridge_secondary_bus_reset(struct pci_dev *dev)
4984 {
4985 	pcibios_reset_secondary_bus(dev);
4986 
4987 	return pci_dev_wait(dev, "bus reset", PCIE_RESET_READY_POLL_MS);
4988 }
4989 EXPORT_SYMBOL_GPL(pci_bridge_secondary_bus_reset);
4990 
4991 static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
4992 {
4993 	struct pci_dev *pdev;
4994 
4995 	if (pci_is_root_bus(dev->bus) || dev->subordinate ||
4996 	    !dev->bus->self || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
4997 		return -ENOTTY;
4998 
4999 	list_for_each_entry(pdev, &dev->bus->devices, bus_list)
5000 		if (pdev != dev)
5001 			return -ENOTTY;
5002 
5003 	if (probe)
5004 		return 0;
5005 
5006 	return pci_bridge_secondary_bus_reset(dev->bus->self);
5007 }
5008 
5009 static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, int probe)
5010 {
5011 	int rc = -ENOTTY;
5012 
5013 	if (!hotplug || !try_module_get(hotplug->owner))
5014 		return rc;
5015 
5016 	if (hotplug->ops->reset_slot)
5017 		rc = hotplug->ops->reset_slot(hotplug, probe);
5018 
5019 	module_put(hotplug->owner);
5020 
5021 	return rc;
5022 }
5023 
5024 static int pci_dev_reset_slot_function(struct pci_dev *dev, int probe)
5025 {
5026 	if (dev->multifunction || dev->subordinate || !dev->slot ||
5027 	    dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
5028 		return -ENOTTY;
5029 
5030 	return pci_reset_hotplug_slot(dev->slot->hotplug, probe);
5031 }
5032 
5033 static int pci_reset_bus_function(struct pci_dev *dev, int probe)
5034 {
5035 	int rc;
5036 
5037 	rc = pci_dev_reset_slot_function(dev, probe);
5038 	if (rc != -ENOTTY)
5039 		return rc;
5040 	return pci_parent_bus_reset(dev, probe);
5041 }
5042 
5043 static void pci_dev_lock(struct pci_dev *dev)
5044 {
5045 	pci_cfg_access_lock(dev);
5046 	/* block PM suspend, driver probe, etc. */
5047 	device_lock(&dev->dev);
5048 }
5049 
5050 /* Return 1 on successful lock, 0 on contention */
5051 int pci_dev_trylock(struct pci_dev *dev)
5052 {
5053 	if (pci_cfg_access_trylock(dev)) {
5054 		if (device_trylock(&dev->dev))
5055 			return 1;
5056 		pci_cfg_access_unlock(dev);
5057 	}
5058 
5059 	return 0;
5060 }
5061 EXPORT_SYMBOL_GPL(pci_dev_trylock);
5062 
5063 void pci_dev_unlock(struct pci_dev *dev)
5064 {
5065 	device_unlock(&dev->dev);
5066 	pci_cfg_access_unlock(dev);
5067 }
5068 EXPORT_SYMBOL_GPL(pci_dev_unlock);
5069 
5070 static void pci_dev_save_and_disable(struct pci_dev *dev)
5071 {
5072 	const struct pci_error_handlers *err_handler =
5073 			dev->driver ? dev->driver->err_handler : NULL;
5074 
5075 	/*
5076 	 * dev->driver->err_handler->reset_prepare() is protected against
5077 	 * races with ->remove() by the device lock, which must be held by
5078 	 * the caller.
5079 	 */
5080 	if (err_handler && err_handler->reset_prepare)
5081 		err_handler->reset_prepare(dev);
5082 
5083 	/*
5084 	 * Wake-up device prior to save.  PM registers default to D0 after
5085 	 * reset and a simple register restore doesn't reliably return
5086 	 * to a non-D0 state anyway.
5087 	 */
5088 	pci_set_power_state(dev, PCI_D0);
5089 
5090 	pci_save_state(dev);
5091 	/*
5092 	 * Disable the device by clearing the Command register, except for
5093 	 * INTx-disable which is set.  This not only disables MMIO and I/O port
5094 	 * BARs, but also prevents the device from being Bus Master, preventing
5095 	 * DMA from the device including MSI/MSI-X interrupts.  For PCI 2.3
5096 	 * compliant devices, INTx-disable prevents legacy interrupts.
5097 	 */
5098 	pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
5099 }
5100 
5101 static void pci_dev_restore(struct pci_dev *dev)
5102 {
5103 	const struct pci_error_handlers *err_handler =
5104 			dev->driver ? dev->driver->err_handler : NULL;
5105 
5106 	pci_restore_state(dev);
5107 
5108 	/*
5109 	 * dev->driver->err_handler->reset_done() is protected against
5110 	 * races with ->remove() by the device lock, which must be held by
5111 	 * the caller.
5112 	 */
5113 	if (err_handler && err_handler->reset_done)
5114 		err_handler->reset_done(dev);
5115 }
5116 
5117 /**
5118  * __pci_reset_function_locked - reset a PCI device function while holding
5119  * the @dev mutex lock.
5120  * @dev: PCI device to reset
5121  *
5122  * Some devices allow an individual function to be reset without affecting
5123  * other functions in the same device.  The PCI device must be responsive
5124  * to PCI config space in order to use this function.
5125  *
5126  * The device function is presumed to be unused and the caller is holding
5127  * the device mutex lock when this function is called.
5128  *
5129  * Resetting the device will make the contents of PCI configuration space
5130  * random, so any caller of this must be prepared to reinitialise the
5131  * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
5132  * etc.
5133  *
5134  * Returns 0 if the device function was successfully reset or negative if the
5135  * device doesn't support resetting a single function.
5136  */
5137 int __pci_reset_function_locked(struct pci_dev *dev)
5138 {
5139 	int rc;
5140 
5141 	might_sleep();
5142 
5143 	/*
5144 	 * A reset method returns -ENOTTY if it doesn't support this device
5145 	 * and we should try the next method.
5146 	 *
5147 	 * If it returns 0 (success), we're finished.  If it returns any
5148 	 * other error, we're also finished: this indicates that further
5149 	 * reset mechanisms might be broken on the device.
5150 	 */
5151 	rc = pci_dev_specific_reset(dev, 0);
5152 	if (rc != -ENOTTY)
5153 		return rc;
5154 	if (pcie_has_flr(dev)) {
5155 		rc = pcie_flr(dev);
5156 		if (rc != -ENOTTY)
5157 			return rc;
5158 	}
5159 	rc = pci_af_flr(dev, 0);
5160 	if (rc != -ENOTTY)
5161 		return rc;
5162 	rc = pci_pm_reset(dev, 0);
5163 	if (rc != -ENOTTY)
5164 		return rc;
5165 	return pci_reset_bus_function(dev, 0);
5166 }
5167 EXPORT_SYMBOL_GPL(__pci_reset_function_locked);
5168 
5169 /**
5170  * pci_probe_reset_function - check whether the device can be safely reset
5171  * @dev: PCI device to reset
5172  *
5173  * Some devices allow an individual function to be reset without affecting
5174  * other functions in the same device.  The PCI device must be responsive
5175  * to PCI config space in order to use this function.
5176  *
5177  * Returns 0 if the device function can be reset or negative if the
5178  * device doesn't support resetting a single function.
5179  */
5180 int pci_probe_reset_function(struct pci_dev *dev)
5181 {
5182 	int rc;
5183 
5184 	might_sleep();
5185 
5186 	rc = pci_dev_specific_reset(dev, 1);
5187 	if (rc != -ENOTTY)
5188 		return rc;
5189 	if (pcie_has_flr(dev))
5190 		return 0;
5191 	rc = pci_af_flr(dev, 1);
5192 	if (rc != -ENOTTY)
5193 		return rc;
5194 	rc = pci_pm_reset(dev, 1);
5195 	if (rc != -ENOTTY)
5196 		return rc;
5197 
5198 	return pci_reset_bus_function(dev, 1);
5199 }
5200 
5201 /**
5202  * pci_reset_function - quiesce and reset a PCI device function
5203  * @dev: PCI device to reset
5204  *
5205  * Some devices allow an individual function to be reset without affecting
5206  * other functions in the same device.  The PCI device must be responsive
5207  * to PCI config space in order to use this function.
5208  *
5209  * This function does not just reset the PCI portion of a device, but
5210  * clears all the state associated with the device.  This function differs
5211  * from __pci_reset_function_locked() in that it saves and restores device state
5212  * over the reset and takes the PCI device lock.
5213  *
5214  * Returns 0 if the device function was successfully reset or negative if the
5215  * device doesn't support resetting a single function.
5216  */
5217 int pci_reset_function(struct pci_dev *dev)
5218 {
5219 	int rc;
5220 
5221 	if (!dev->reset_fn)
5222 		return -ENOTTY;
5223 
5224 	pci_dev_lock(dev);
5225 	pci_dev_save_and_disable(dev);
5226 
5227 	rc = __pci_reset_function_locked(dev);
5228 
5229 	pci_dev_restore(dev);
5230 	pci_dev_unlock(dev);
5231 
5232 	return rc;
5233 }
5234 EXPORT_SYMBOL_GPL(pci_reset_function);
5235 
5236 /**
5237  * pci_reset_function_locked - quiesce and reset a PCI device function
5238  * @dev: PCI device to reset
5239  *
5240  * Some devices allow an individual function to be reset without affecting
5241  * other functions in the same device.  The PCI device must be responsive
5242  * to PCI config space in order to use this function.
5243  *
5244  * This function does not just reset the PCI portion of a device, but
5245  * clears all the state associated with the device.  This function differs
5246  * from __pci_reset_function_locked() in that it saves and restores device state
5247  * over the reset.  It also differs from pci_reset_function() in that it
5248  * requires the PCI device lock to be held.
5249  *
5250  * Returns 0 if the device function was successfully reset or negative if the
5251  * device doesn't support resetting a single function.
5252  */
5253 int pci_reset_function_locked(struct pci_dev *dev)
5254 {
5255 	int rc;
5256 
5257 	if (!dev->reset_fn)
5258 		return -ENOTTY;
5259 
5260 	pci_dev_save_and_disable(dev);
5261 
5262 	rc = __pci_reset_function_locked(dev);
5263 
5264 	pci_dev_restore(dev);
5265 
5266 	return rc;
5267 }
5268 EXPORT_SYMBOL_GPL(pci_reset_function_locked);
5269 
5270 /**
5271  * pci_try_reset_function - quiesce and reset a PCI device function
5272  * @dev: PCI device to reset
5273  *
5274  * Same as above, except return -EAGAIN if unable to lock device.
5275  */
5276 int pci_try_reset_function(struct pci_dev *dev)
5277 {
5278 	int rc;
5279 
5280 	if (!dev->reset_fn)
5281 		return -ENOTTY;
5282 
5283 	if (!pci_dev_trylock(dev))
5284 		return -EAGAIN;
5285 
5286 	pci_dev_save_and_disable(dev);
5287 	rc = __pci_reset_function_locked(dev);
5288 	pci_dev_restore(dev);
5289 	pci_dev_unlock(dev);
5290 
5291 	return rc;
5292 }
5293 EXPORT_SYMBOL_GPL(pci_try_reset_function);
5294 
5295 /* Do any devices on or below this bus prevent a bus reset? */
5296 static bool pci_bus_resetable(struct pci_bus *bus)
5297 {
5298 	struct pci_dev *dev;
5299 
5300 
5301 	if (bus->self && (bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET))
5302 		return false;
5303 
5304 	list_for_each_entry(dev, &bus->devices, bus_list) {
5305 		if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
5306 		    (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
5307 			return false;
5308 	}
5309 
5310 	return true;
5311 }
5312 
5313 /* Lock devices from the top of the tree down */
5314 static void pci_bus_lock(struct pci_bus *bus)
5315 {
5316 	struct pci_dev *dev;
5317 
5318 	list_for_each_entry(dev, &bus->devices, bus_list) {
5319 		pci_dev_lock(dev);
5320 		if (dev->subordinate)
5321 			pci_bus_lock(dev->subordinate);
5322 	}
5323 }
5324 
5325 /* Unlock devices from the bottom of the tree up */
5326 static void pci_bus_unlock(struct pci_bus *bus)
5327 {
5328 	struct pci_dev *dev;
5329 
5330 	list_for_each_entry(dev, &bus->devices, bus_list) {
5331 		if (dev->subordinate)
5332 			pci_bus_unlock(dev->subordinate);
5333 		pci_dev_unlock(dev);
5334 	}
5335 }
5336 
5337 /* Return 1 on successful lock, 0 on contention */
5338 static int pci_bus_trylock(struct pci_bus *bus)
5339 {
5340 	struct pci_dev *dev;
5341 
5342 	list_for_each_entry(dev, &bus->devices, bus_list) {
5343 		if (!pci_dev_trylock(dev))
5344 			goto unlock;
5345 		if (dev->subordinate) {
5346 			if (!pci_bus_trylock(dev->subordinate)) {
5347 				pci_dev_unlock(dev);
5348 				goto unlock;
5349 			}
5350 		}
5351 	}
5352 	return 1;
5353 
5354 unlock:
5355 	list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) {
5356 		if (dev->subordinate)
5357 			pci_bus_unlock(dev->subordinate);
5358 		pci_dev_unlock(dev);
5359 	}
5360 	return 0;
5361 }
5362 
5363 /* Do any devices on or below this slot prevent a bus reset? */
5364 static bool pci_slot_resetable(struct pci_slot *slot)
5365 {
5366 	struct pci_dev *dev;
5367 
5368 	if (slot->bus->self &&
5369 	    (slot->bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET))
5370 		return false;
5371 
5372 	list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5373 		if (!dev->slot || dev->slot != slot)
5374 			continue;
5375 		if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
5376 		    (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
5377 			return false;
5378 	}
5379 
5380 	return true;
5381 }
5382 
5383 /* Lock devices from the top of the tree down */
5384 static void pci_slot_lock(struct pci_slot *slot)
5385 {
5386 	struct pci_dev *dev;
5387 
5388 	list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5389 		if (!dev->slot || dev->slot != slot)
5390 			continue;
5391 		pci_dev_lock(dev);
5392 		if (dev->subordinate)
5393 			pci_bus_lock(dev->subordinate);
5394 	}
5395 }
5396 
5397 /* Unlock devices from the bottom of the tree up */
5398 static void pci_slot_unlock(struct pci_slot *slot)
5399 {
5400 	struct pci_dev *dev;
5401 
5402 	list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5403 		if (!dev->slot || dev->slot != slot)
5404 			continue;
5405 		if (dev->subordinate)
5406 			pci_bus_unlock(dev->subordinate);
5407 		pci_dev_unlock(dev);
5408 	}
5409 }
5410 
5411 /* Return 1 on successful lock, 0 on contention */
5412 static int pci_slot_trylock(struct pci_slot *slot)
5413 {
5414 	struct pci_dev *dev;
5415 
5416 	list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5417 		if (!dev->slot || dev->slot != slot)
5418 			continue;
5419 		if (!pci_dev_trylock(dev))
5420 			goto unlock;
5421 		if (dev->subordinate) {
5422 			if (!pci_bus_trylock(dev->subordinate)) {
5423 				pci_dev_unlock(dev);
5424 				goto unlock;
5425 			}
5426 		}
5427 	}
5428 	return 1;
5429 
5430 unlock:
5431 	list_for_each_entry_continue_reverse(dev,
5432 					     &slot->bus->devices, bus_list) {
5433 		if (!dev->slot || dev->slot != slot)
5434 			continue;
5435 		if (dev->subordinate)
5436 			pci_bus_unlock(dev->subordinate);
5437 		pci_dev_unlock(dev);
5438 	}
5439 	return 0;
5440 }
5441 
5442 /*
5443  * Save and disable devices from the top of the tree down while holding
5444  * the @dev mutex lock for the entire tree.
5445  */
5446 static void pci_bus_save_and_disable_locked(struct pci_bus *bus)
5447 {
5448 	struct pci_dev *dev;
5449 
5450 	list_for_each_entry(dev, &bus->devices, bus_list) {
5451 		pci_dev_save_and_disable(dev);
5452 		if (dev->subordinate)
5453 			pci_bus_save_and_disable_locked(dev->subordinate);
5454 	}
5455 }
5456 
5457 /*
5458  * Restore devices from top of the tree down while holding @dev mutex lock
5459  * for the entire tree.  Parent bridges need to be restored before we can
5460  * get to subordinate devices.
5461  */
5462 static void pci_bus_restore_locked(struct pci_bus *bus)
5463 {
5464 	struct pci_dev *dev;
5465 
5466 	list_for_each_entry(dev, &bus->devices, bus_list) {
5467 		pci_dev_restore(dev);
5468 		if (dev->subordinate)
5469 			pci_bus_restore_locked(dev->subordinate);
5470 	}
5471 }
5472 
5473 /*
5474  * Save and disable devices from the top of the tree down while holding
5475  * the @dev mutex lock for the entire tree.
5476  */
5477 static void pci_slot_save_and_disable_locked(struct pci_slot *slot)
5478 {
5479 	struct pci_dev *dev;
5480 
5481 	list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5482 		if (!dev->slot || dev->slot != slot)
5483 			continue;
5484 		pci_dev_save_and_disable(dev);
5485 		if (dev->subordinate)
5486 			pci_bus_save_and_disable_locked(dev->subordinate);
5487 	}
5488 }
5489 
5490 /*
5491  * Restore devices from top of the tree down while holding @dev mutex lock
5492  * for the entire tree.  Parent bridges need to be restored before we can
5493  * get to subordinate devices.
5494  */
5495 static void pci_slot_restore_locked(struct pci_slot *slot)
5496 {
5497 	struct pci_dev *dev;
5498 
5499 	list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5500 		if (!dev->slot || dev->slot != slot)
5501 			continue;
5502 		pci_dev_restore(dev);
5503 		if (dev->subordinate)
5504 			pci_bus_restore_locked(dev->subordinate);
5505 	}
5506 }
5507 
5508 static int pci_slot_reset(struct pci_slot *slot, int probe)
5509 {
5510 	int rc;
5511 
5512 	if (!slot || !pci_slot_resetable(slot))
5513 		return -ENOTTY;
5514 
5515 	if (!probe)
5516 		pci_slot_lock(slot);
5517 
5518 	might_sleep();
5519 
5520 	rc = pci_reset_hotplug_slot(slot->hotplug, probe);
5521 
5522 	if (!probe)
5523 		pci_slot_unlock(slot);
5524 
5525 	return rc;
5526 }
5527 
5528 /**
5529  * pci_probe_reset_slot - probe whether a PCI slot can be reset
5530  * @slot: PCI slot to probe
5531  *
5532  * Return 0 if slot can be reset, negative if a slot reset is not supported.
5533  */
5534 int pci_probe_reset_slot(struct pci_slot *slot)
5535 {
5536 	return pci_slot_reset(slot, 1);
5537 }
5538 EXPORT_SYMBOL_GPL(pci_probe_reset_slot);
5539 
5540 /**
5541  * __pci_reset_slot - Try to reset a PCI slot
5542  * @slot: PCI slot to reset
5543  *
5544  * A PCI bus may host multiple slots, each slot may support a reset mechanism
5545  * independent of other slots.  For instance, some slots may support slot power
5546  * control.  In the case of a 1:1 bus to slot architecture, this function may
5547  * wrap the bus reset to avoid spurious slot related events such as hotplug.
5548  * Generally a slot reset should be attempted before a bus reset.  All of the
5549  * function of the slot and any subordinate buses behind the slot are reset
5550  * through this function.  PCI config space of all devices in the slot and
5551  * behind the slot is saved before and restored after reset.
5552  *
5553  * Same as above except return -EAGAIN if the slot cannot be locked
5554  */
5555 static int __pci_reset_slot(struct pci_slot *slot)
5556 {
5557 	int rc;
5558 
5559 	rc = pci_slot_reset(slot, 1);
5560 	if (rc)
5561 		return rc;
5562 
5563 	if (pci_slot_trylock(slot)) {
5564 		pci_slot_save_and_disable_locked(slot);
5565 		might_sleep();
5566 		rc = pci_reset_hotplug_slot(slot->hotplug, 0);
5567 		pci_slot_restore_locked(slot);
5568 		pci_slot_unlock(slot);
5569 	} else
5570 		rc = -EAGAIN;
5571 
5572 	return rc;
5573 }
5574 
5575 static int pci_bus_reset(struct pci_bus *bus, int probe)
5576 {
5577 	int ret;
5578 
5579 	if (!bus->self || !pci_bus_resetable(bus))
5580 		return -ENOTTY;
5581 
5582 	if (probe)
5583 		return 0;
5584 
5585 	pci_bus_lock(bus);
5586 
5587 	might_sleep();
5588 
5589 	ret = pci_bridge_secondary_bus_reset(bus->self);
5590 
5591 	pci_bus_unlock(bus);
5592 
5593 	return ret;
5594 }
5595 
5596 /**
5597  * pci_bus_error_reset - reset the bridge's subordinate bus
5598  * @bridge: The parent device that connects to the bus to reset
5599  *
5600  * This function will first try to reset the slots on this bus if the method is
5601  * available. If slot reset fails or is not available, this will fall back to a
5602  * secondary bus reset.
5603  */
5604 int pci_bus_error_reset(struct pci_dev *bridge)
5605 {
5606 	struct pci_bus *bus = bridge->subordinate;
5607 	struct pci_slot *slot;
5608 
5609 	if (!bus)
5610 		return -ENOTTY;
5611 
5612 	mutex_lock(&pci_slot_mutex);
5613 	if (list_empty(&bus->slots))
5614 		goto bus_reset;
5615 
5616 	list_for_each_entry(slot, &bus->slots, list)
5617 		if (pci_probe_reset_slot(slot))
5618 			goto bus_reset;
5619 
5620 	list_for_each_entry(slot, &bus->slots, list)
5621 		if (pci_slot_reset(slot, 0))
5622 			goto bus_reset;
5623 
5624 	mutex_unlock(&pci_slot_mutex);
5625 	return 0;
5626 bus_reset:
5627 	mutex_unlock(&pci_slot_mutex);
5628 	return pci_bus_reset(bridge->subordinate, 0);
5629 }
5630 
5631 /**
5632  * pci_probe_reset_bus - probe whether a PCI bus can be reset
5633  * @bus: PCI bus to probe
5634  *
5635  * Return 0 if bus can be reset, negative if a bus reset is not supported.
5636  */
5637 int pci_probe_reset_bus(struct pci_bus *bus)
5638 {
5639 	return pci_bus_reset(bus, 1);
5640 }
5641 EXPORT_SYMBOL_GPL(pci_probe_reset_bus);
5642 
5643 /**
5644  * __pci_reset_bus - Try to reset a PCI bus
5645  * @bus: top level PCI bus to reset
5646  *
5647  * Same as above except return -EAGAIN if the bus cannot be locked
5648  */
5649 static int __pci_reset_bus(struct pci_bus *bus)
5650 {
5651 	int rc;
5652 
5653 	rc = pci_bus_reset(bus, 1);
5654 	if (rc)
5655 		return rc;
5656 
5657 	if (pci_bus_trylock(bus)) {
5658 		pci_bus_save_and_disable_locked(bus);
5659 		might_sleep();
5660 		rc = pci_bridge_secondary_bus_reset(bus->self);
5661 		pci_bus_restore_locked(bus);
5662 		pci_bus_unlock(bus);
5663 	} else
5664 		rc = -EAGAIN;
5665 
5666 	return rc;
5667 }
5668 
5669 /**
5670  * pci_reset_bus - Try to reset a PCI bus
5671  * @pdev: top level PCI device to reset via slot/bus
5672  *
5673  * Same as above except return -EAGAIN if the bus cannot be locked
5674  */
5675 int pci_reset_bus(struct pci_dev *pdev)
5676 {
5677 	return (!pci_probe_reset_slot(pdev->slot)) ?
5678 	    __pci_reset_slot(pdev->slot) : __pci_reset_bus(pdev->bus);
5679 }
5680 EXPORT_SYMBOL_GPL(pci_reset_bus);
5681 
5682 /**
5683  * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
5684  * @dev: PCI device to query
5685  *
5686  * Returns mmrbc: maximum designed memory read count in bytes or
5687  * appropriate error value.
5688  */
5689 int pcix_get_max_mmrbc(struct pci_dev *dev)
5690 {
5691 	int cap;
5692 	u32 stat;
5693 
5694 	cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
5695 	if (!cap)
5696 		return -EINVAL;
5697 
5698 	if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
5699 		return -EINVAL;
5700 
5701 	return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
5702 }
5703 EXPORT_SYMBOL(pcix_get_max_mmrbc);
5704 
5705 /**
5706  * pcix_get_mmrbc - get PCI-X maximum memory read byte count
5707  * @dev: PCI device to query
5708  *
5709  * Returns mmrbc: maximum memory read count in bytes or appropriate error
5710  * value.
5711  */
5712 int pcix_get_mmrbc(struct pci_dev *dev)
5713 {
5714 	int cap;
5715 	u16 cmd;
5716 
5717 	cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
5718 	if (!cap)
5719 		return -EINVAL;
5720 
5721 	if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
5722 		return -EINVAL;
5723 
5724 	return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
5725 }
5726 EXPORT_SYMBOL(pcix_get_mmrbc);
5727 
5728 /**
5729  * pcix_set_mmrbc - set PCI-X maximum memory read byte count
5730  * @dev: PCI device to query
5731  * @mmrbc: maximum memory read count in bytes
5732  *    valid values are 512, 1024, 2048, 4096
5733  *
5734  * If possible sets maximum memory read byte count, some bridges have errata
5735  * that prevent this.
5736  */
5737 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
5738 {
5739 	int cap;
5740 	u32 stat, v, o;
5741 	u16 cmd;
5742 
5743 	if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
5744 		return -EINVAL;
5745 
5746 	v = ffs(mmrbc) - 10;
5747 
5748 	cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
5749 	if (!cap)
5750 		return -EINVAL;
5751 
5752 	if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
5753 		return -EINVAL;
5754 
5755 	if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
5756 		return -E2BIG;
5757 
5758 	if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
5759 		return -EINVAL;
5760 
5761 	o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
5762 	if (o != v) {
5763 		if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
5764 			return -EIO;
5765 
5766 		cmd &= ~PCI_X_CMD_MAX_READ;
5767 		cmd |= v << 2;
5768 		if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
5769 			return -EIO;
5770 	}
5771 	return 0;
5772 }
5773 EXPORT_SYMBOL(pcix_set_mmrbc);
5774 
5775 /**
5776  * pcie_get_readrq - get PCI Express read request size
5777  * @dev: PCI device to query
5778  *
5779  * Returns maximum memory read request in bytes or appropriate error value.
5780  */
5781 int pcie_get_readrq(struct pci_dev *dev)
5782 {
5783 	u16 ctl;
5784 
5785 	pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
5786 
5787 	return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
5788 }
5789 EXPORT_SYMBOL(pcie_get_readrq);
5790 
5791 /**
5792  * pcie_set_readrq - set PCI Express maximum memory read request
5793  * @dev: PCI device to query
5794  * @rq: maximum memory read count in bytes
5795  *    valid values are 128, 256, 512, 1024, 2048, 4096
5796  *
5797  * If possible sets maximum memory read request in bytes
5798  */
5799 int pcie_set_readrq(struct pci_dev *dev, int rq)
5800 {
5801 	u16 v;
5802 	int ret;
5803 
5804 	if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
5805 		return -EINVAL;
5806 
5807 	/*
5808 	 * If using the "performance" PCIe config, we clamp the read rq
5809 	 * size to the max packet size to keep the host bridge from
5810 	 * generating requests larger than we can cope with.
5811 	 */
5812 	if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
5813 		int mps = pcie_get_mps(dev);
5814 
5815 		if (mps < rq)
5816 			rq = mps;
5817 	}
5818 
5819 	v = (ffs(rq) - 8) << 12;
5820 
5821 	ret = pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
5822 						  PCI_EXP_DEVCTL_READRQ, v);
5823 
5824 	return pcibios_err_to_errno(ret);
5825 }
5826 EXPORT_SYMBOL(pcie_set_readrq);
5827 
5828 /**
5829  * pcie_get_mps - get PCI Express maximum payload size
5830  * @dev: PCI device to query
5831  *
5832  * Returns maximum payload size in bytes
5833  */
5834 int pcie_get_mps(struct pci_dev *dev)
5835 {
5836 	u16 ctl;
5837 
5838 	pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
5839 
5840 	return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
5841 }
5842 EXPORT_SYMBOL(pcie_get_mps);
5843 
5844 /**
5845  * pcie_set_mps - set PCI Express maximum payload size
5846  * @dev: PCI device to query
5847  * @mps: maximum payload size in bytes
5848  *    valid values are 128, 256, 512, 1024, 2048, 4096
5849  *
5850  * If possible sets maximum payload size
5851  */
5852 int pcie_set_mps(struct pci_dev *dev, int mps)
5853 {
5854 	u16 v;
5855 	int ret;
5856 
5857 	if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
5858 		return -EINVAL;
5859 
5860 	v = ffs(mps) - 8;
5861 	if (v > dev->pcie_mpss)
5862 		return -EINVAL;
5863 	v <<= 5;
5864 
5865 	ret = pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
5866 						  PCI_EXP_DEVCTL_PAYLOAD, v);
5867 
5868 	return pcibios_err_to_errno(ret);
5869 }
5870 EXPORT_SYMBOL(pcie_set_mps);
5871 
5872 /**
5873  * pcie_bandwidth_available - determine minimum link settings of a PCIe
5874  *			      device and its bandwidth limitation
5875  * @dev: PCI device to query
5876  * @limiting_dev: storage for device causing the bandwidth limitation
5877  * @speed: storage for speed of limiting device
5878  * @width: storage for width of limiting device
5879  *
5880  * Walk up the PCI device chain and find the point where the minimum
5881  * bandwidth is available.  Return the bandwidth available there and (if
5882  * limiting_dev, speed, and width pointers are supplied) information about
5883  * that point.  The bandwidth returned is in Mb/s, i.e., megabits/second of
5884  * raw bandwidth.
5885  */
5886 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
5887 			     enum pci_bus_speed *speed,
5888 			     enum pcie_link_width *width)
5889 {
5890 	u16 lnksta;
5891 	enum pci_bus_speed next_speed;
5892 	enum pcie_link_width next_width;
5893 	u32 bw, next_bw;
5894 
5895 	if (speed)
5896 		*speed = PCI_SPEED_UNKNOWN;
5897 	if (width)
5898 		*width = PCIE_LNK_WIDTH_UNKNOWN;
5899 
5900 	bw = 0;
5901 
5902 	while (dev) {
5903 		pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
5904 
5905 		next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS];
5906 		next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >>
5907 			PCI_EXP_LNKSTA_NLW_SHIFT;
5908 
5909 		next_bw = next_width * PCIE_SPEED2MBS_ENC(next_speed);
5910 
5911 		/* Check if current device limits the total bandwidth */
5912 		if (!bw || next_bw <= bw) {
5913 			bw = next_bw;
5914 
5915 			if (limiting_dev)
5916 				*limiting_dev = dev;
5917 			if (speed)
5918 				*speed = next_speed;
5919 			if (width)
5920 				*width = next_width;
5921 		}
5922 
5923 		dev = pci_upstream_bridge(dev);
5924 	}
5925 
5926 	return bw;
5927 }
5928 EXPORT_SYMBOL(pcie_bandwidth_available);
5929 
5930 /**
5931  * pcie_get_speed_cap - query for the PCI device's link speed capability
5932  * @dev: PCI device to query
5933  *
5934  * Query the PCI device speed capability.  Return the maximum link speed
5935  * supported by the device.
5936  */
5937 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev)
5938 {
5939 	u32 lnkcap2, lnkcap;
5940 
5941 	/*
5942 	 * Link Capabilities 2 was added in PCIe r3.0, sec 7.8.18.  The
5943 	 * implementation note there recommends using the Supported Link
5944 	 * Speeds Vector in Link Capabilities 2 when supported.
5945 	 *
5946 	 * Without Link Capabilities 2, i.e., prior to PCIe r3.0, software
5947 	 * should use the Supported Link Speeds field in Link Capabilities,
5948 	 * where only 2.5 GT/s and 5.0 GT/s speeds were defined.
5949 	 */
5950 	pcie_capability_read_dword(dev, PCI_EXP_LNKCAP2, &lnkcap2);
5951 
5952 	/* PCIe r3.0-compliant */
5953 	if (lnkcap2)
5954 		return PCIE_LNKCAP2_SLS2SPEED(lnkcap2);
5955 
5956 	pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
5957 	if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_5_0GB)
5958 		return PCIE_SPEED_5_0GT;
5959 	else if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_2_5GB)
5960 		return PCIE_SPEED_2_5GT;
5961 
5962 	return PCI_SPEED_UNKNOWN;
5963 }
5964 EXPORT_SYMBOL(pcie_get_speed_cap);
5965 
5966 /**
5967  * pcie_get_width_cap - query for the PCI device's link width capability
5968  * @dev: PCI device to query
5969  *
5970  * Query the PCI device width capability.  Return the maximum link width
5971  * supported by the device.
5972  */
5973 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev)
5974 {
5975 	u32 lnkcap;
5976 
5977 	pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
5978 	if (lnkcap)
5979 		return (lnkcap & PCI_EXP_LNKCAP_MLW) >> 4;
5980 
5981 	return PCIE_LNK_WIDTH_UNKNOWN;
5982 }
5983 EXPORT_SYMBOL(pcie_get_width_cap);
5984 
5985 /**
5986  * pcie_bandwidth_capable - calculate a PCI device's link bandwidth capability
5987  * @dev: PCI device
5988  * @speed: storage for link speed
5989  * @width: storage for link width
5990  *
5991  * Calculate a PCI device's link bandwidth by querying for its link speed
5992  * and width, multiplying them, and applying encoding overhead.  The result
5993  * is in Mb/s, i.e., megabits/second of raw bandwidth.
5994  */
5995 u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
5996 			   enum pcie_link_width *width)
5997 {
5998 	*speed = pcie_get_speed_cap(dev);
5999 	*width = pcie_get_width_cap(dev);
6000 
6001 	if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN)
6002 		return 0;
6003 
6004 	return *width * PCIE_SPEED2MBS_ENC(*speed);
6005 }
6006 
6007 /**
6008  * __pcie_print_link_status - Report the PCI device's link speed and width
6009  * @dev: PCI device to query
6010  * @verbose: Print info even when enough bandwidth is available
6011  *
6012  * If the available bandwidth at the device is less than the device is
6013  * capable of, report the device's maximum possible bandwidth and the
6014  * upstream link that limits its performance.  If @verbose, always print
6015  * the available bandwidth, even if the device isn't constrained.
6016  */
6017 void __pcie_print_link_status(struct pci_dev *dev, bool verbose)
6018 {
6019 	enum pcie_link_width width, width_cap;
6020 	enum pci_bus_speed speed, speed_cap;
6021 	struct pci_dev *limiting_dev = NULL;
6022 	u32 bw_avail, bw_cap;
6023 
6024 	bw_cap = pcie_bandwidth_capable(dev, &speed_cap, &width_cap);
6025 	bw_avail = pcie_bandwidth_available(dev, &limiting_dev, &speed, &width);
6026 
6027 	if (bw_avail >= bw_cap && verbose)
6028 		pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth (%s x%d link)\n",
6029 			 bw_cap / 1000, bw_cap % 1000,
6030 			 pci_speed_string(speed_cap), width_cap);
6031 	else if (bw_avail < bw_cap)
6032 		pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth, limited by %s x%d link at %s (capable of %u.%03u Gb/s with %s x%d link)\n",
6033 			 bw_avail / 1000, bw_avail % 1000,
6034 			 pci_speed_string(speed), width,
6035 			 limiting_dev ? pci_name(limiting_dev) : "<unknown>",
6036 			 bw_cap / 1000, bw_cap % 1000,
6037 			 pci_speed_string(speed_cap), width_cap);
6038 }
6039 
6040 /**
6041  * pcie_print_link_status - Report the PCI device's link speed and width
6042  * @dev: PCI device to query
6043  *
6044  * Report the available bandwidth at the device.
6045  */
6046 void pcie_print_link_status(struct pci_dev *dev)
6047 {
6048 	__pcie_print_link_status(dev, true);
6049 }
6050 EXPORT_SYMBOL(pcie_print_link_status);
6051 
6052 /**
6053  * pci_select_bars - Make BAR mask from the type of resource
6054  * @dev: the PCI device for which BAR mask is made
6055  * @flags: resource type mask to be selected
6056  *
6057  * This helper routine makes bar mask from the type of resource.
6058  */
6059 int pci_select_bars(struct pci_dev *dev, unsigned long flags)
6060 {
6061 	int i, bars = 0;
6062 	for (i = 0; i < PCI_NUM_RESOURCES; i++)
6063 		if (pci_resource_flags(dev, i) & flags)
6064 			bars |= (1 << i);
6065 	return bars;
6066 }
6067 EXPORT_SYMBOL(pci_select_bars);
6068 
6069 /* Some architectures require additional programming to enable VGA */
6070 static arch_set_vga_state_t arch_set_vga_state;
6071 
6072 void __init pci_register_set_vga_state(arch_set_vga_state_t func)
6073 {
6074 	arch_set_vga_state = func;	/* NULL disables */
6075 }
6076 
6077 static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
6078 				  unsigned int command_bits, u32 flags)
6079 {
6080 	if (arch_set_vga_state)
6081 		return arch_set_vga_state(dev, decode, command_bits,
6082 						flags);
6083 	return 0;
6084 }
6085 
6086 /**
6087  * pci_set_vga_state - set VGA decode state on device and parents if requested
6088  * @dev: the PCI device
6089  * @decode: true = enable decoding, false = disable decoding
6090  * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
6091  * @flags: traverse ancestors and change bridges
6092  * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
6093  */
6094 int pci_set_vga_state(struct pci_dev *dev, bool decode,
6095 		      unsigned int command_bits, u32 flags)
6096 {
6097 	struct pci_bus *bus;
6098 	struct pci_dev *bridge;
6099 	u16 cmd;
6100 	int rc;
6101 
6102 	WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) && (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
6103 
6104 	/* ARCH specific VGA enables */
6105 	rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
6106 	if (rc)
6107 		return rc;
6108 
6109 	if (flags & PCI_VGA_STATE_CHANGE_DECODES) {
6110 		pci_read_config_word(dev, PCI_COMMAND, &cmd);
6111 		if (decode)
6112 			cmd |= command_bits;
6113 		else
6114 			cmd &= ~command_bits;
6115 		pci_write_config_word(dev, PCI_COMMAND, cmd);
6116 	}
6117 
6118 	if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
6119 		return 0;
6120 
6121 	bus = dev->bus;
6122 	while (bus) {
6123 		bridge = bus->self;
6124 		if (bridge) {
6125 			pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
6126 					     &cmd);
6127 			if (decode)
6128 				cmd |= PCI_BRIDGE_CTL_VGA;
6129 			else
6130 				cmd &= ~PCI_BRIDGE_CTL_VGA;
6131 			pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
6132 					      cmd);
6133 		}
6134 		bus = bus->parent;
6135 	}
6136 	return 0;
6137 }
6138 
6139 #ifdef CONFIG_ACPI
6140 bool pci_pr3_present(struct pci_dev *pdev)
6141 {
6142 	struct acpi_device *adev;
6143 
6144 	if (acpi_disabled)
6145 		return false;
6146 
6147 	adev = ACPI_COMPANION(&pdev->dev);
6148 	if (!adev)
6149 		return false;
6150 
6151 	return adev->power.flags.power_resources &&
6152 		acpi_has_method(adev->handle, "_PR3");
6153 }
6154 EXPORT_SYMBOL_GPL(pci_pr3_present);
6155 #endif
6156 
6157 /**
6158  * pci_add_dma_alias - Add a DMA devfn alias for a device
6159  * @dev: the PCI device for which alias is added
6160  * @devfn_from: alias slot and function
6161  * @nr_devfns: number of subsequent devfns to alias
6162  *
6163  * This helper encodes an 8-bit devfn as a bit number in dma_alias_mask
6164  * which is used to program permissible bus-devfn source addresses for DMA
6165  * requests in an IOMMU.  These aliases factor into IOMMU group creation
6166  * and are useful for devices generating DMA requests beyond or different
6167  * from their logical bus-devfn.  Examples include device quirks where the
6168  * device simply uses the wrong devfn, as well as non-transparent bridges
6169  * where the alias may be a proxy for devices in another domain.
6170  *
6171  * IOMMU group creation is performed during device discovery or addition,
6172  * prior to any potential DMA mapping and therefore prior to driver probing
6173  * (especially for userspace assigned devices where IOMMU group definition
6174  * cannot be left as a userspace activity).  DMA aliases should therefore
6175  * be configured via quirks, such as the PCI fixup header quirk.
6176  */
6177 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns)
6178 {
6179 	int devfn_to;
6180 
6181 	nr_devfns = min(nr_devfns, (unsigned) MAX_NR_DEVFNS - devfn_from);
6182 	devfn_to = devfn_from + nr_devfns - 1;
6183 
6184 	if (!dev->dma_alias_mask)
6185 		dev->dma_alias_mask = bitmap_zalloc(MAX_NR_DEVFNS, GFP_KERNEL);
6186 	if (!dev->dma_alias_mask) {
6187 		pci_warn(dev, "Unable to allocate DMA alias mask\n");
6188 		return;
6189 	}
6190 
6191 	bitmap_set(dev->dma_alias_mask, devfn_from, nr_devfns);
6192 
6193 	if (nr_devfns == 1)
6194 		pci_info(dev, "Enabling fixed DMA alias to %02x.%d\n",
6195 				PCI_SLOT(devfn_from), PCI_FUNC(devfn_from));
6196 	else if (nr_devfns > 1)
6197 		pci_info(dev, "Enabling fixed DMA alias for devfn range from %02x.%d to %02x.%d\n",
6198 				PCI_SLOT(devfn_from), PCI_FUNC(devfn_from),
6199 				PCI_SLOT(devfn_to), PCI_FUNC(devfn_to));
6200 }
6201 
6202 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2)
6203 {
6204 	return (dev1->dma_alias_mask &&
6205 		test_bit(dev2->devfn, dev1->dma_alias_mask)) ||
6206 	       (dev2->dma_alias_mask &&
6207 		test_bit(dev1->devfn, dev2->dma_alias_mask)) ||
6208 	       pci_real_dma_dev(dev1) == dev2 ||
6209 	       pci_real_dma_dev(dev2) == dev1;
6210 }
6211 
6212 bool pci_device_is_present(struct pci_dev *pdev)
6213 {
6214 	u32 v;
6215 
6216 	if (pci_dev_is_disconnected(pdev))
6217 		return false;
6218 	return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0);
6219 }
6220 EXPORT_SYMBOL_GPL(pci_device_is_present);
6221 
6222 void pci_ignore_hotplug(struct pci_dev *dev)
6223 {
6224 	struct pci_dev *bridge = dev->bus->self;
6225 
6226 	dev->ignore_hotplug = 1;
6227 	/* Propagate the "ignore hotplug" setting to the parent bridge. */
6228 	if (bridge)
6229 		bridge->ignore_hotplug = 1;
6230 }
6231 EXPORT_SYMBOL_GPL(pci_ignore_hotplug);
6232 
6233 /**
6234  * pci_real_dma_dev - Get PCI DMA device for PCI device
6235  * @dev: the PCI device that may have a PCI DMA alias
6236  *
6237  * Permits the platform to provide architecture-specific functionality to
6238  * devices needing to alias DMA to another PCI device on another PCI bus. If
6239  * the PCI device is on the same bus, it is recommended to use
6240  * pci_add_dma_alias(). This is the default implementation. Architecture
6241  * implementations can override this.
6242  */
6243 struct pci_dev __weak *pci_real_dma_dev(struct pci_dev *dev)
6244 {
6245 	return dev;
6246 }
6247 
6248 resource_size_t __weak pcibios_default_alignment(void)
6249 {
6250 	return 0;
6251 }
6252 
6253 /*
6254  * Arches that don't want to expose struct resource to userland as-is in
6255  * sysfs and /proc can implement their own pci_resource_to_user().
6256  */
6257 void __weak pci_resource_to_user(const struct pci_dev *dev, int bar,
6258 				 const struct resource *rsrc,
6259 				 resource_size_t *start, resource_size_t *end)
6260 {
6261 	*start = rsrc->start;
6262 	*end = rsrc->end;
6263 }
6264 
6265 static char *resource_alignment_param;
6266 static DEFINE_SPINLOCK(resource_alignment_lock);
6267 
6268 /**
6269  * pci_specified_resource_alignment - get resource alignment specified by user.
6270  * @dev: the PCI device to get
6271  * @resize: whether or not to change resources' size when reassigning alignment
6272  *
6273  * RETURNS: Resource alignment if it is specified.
6274  *          Zero if it is not specified.
6275  */
6276 static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev,
6277 							bool *resize)
6278 {
6279 	int align_order, count;
6280 	resource_size_t align = pcibios_default_alignment();
6281 	const char *p;
6282 	int ret;
6283 
6284 	spin_lock(&resource_alignment_lock);
6285 	p = resource_alignment_param;
6286 	if (!p || !*p)
6287 		goto out;
6288 	if (pci_has_flag(PCI_PROBE_ONLY)) {
6289 		align = 0;
6290 		pr_info_once("PCI: Ignoring requested alignments (PCI_PROBE_ONLY)\n");
6291 		goto out;
6292 	}
6293 
6294 	while (*p) {
6295 		count = 0;
6296 		if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
6297 		    p[count] == '@') {
6298 			p += count + 1;
6299 			if (align_order > 63) {
6300 				pr_err("PCI: Invalid requested alignment (order %d)\n",
6301 				       align_order);
6302 				align_order = PAGE_SHIFT;
6303 			}
6304 		} else {
6305 			align_order = PAGE_SHIFT;
6306 		}
6307 
6308 		ret = pci_dev_str_match(dev, p, &p);
6309 		if (ret == 1) {
6310 			*resize = true;
6311 			align = 1ULL << align_order;
6312 			break;
6313 		} else if (ret < 0) {
6314 			pr_err("PCI: Can't parse resource_alignment parameter: %s\n",
6315 			       p);
6316 			break;
6317 		}
6318 
6319 		if (*p != ';' && *p != ',') {
6320 			/* End of param or invalid format */
6321 			break;
6322 		}
6323 		p++;
6324 	}
6325 out:
6326 	spin_unlock(&resource_alignment_lock);
6327 	return align;
6328 }
6329 
6330 static void pci_request_resource_alignment(struct pci_dev *dev, int bar,
6331 					   resource_size_t align, bool resize)
6332 {
6333 	struct resource *r = &dev->resource[bar];
6334 	resource_size_t size;
6335 
6336 	if (!(r->flags & IORESOURCE_MEM))
6337 		return;
6338 
6339 	if (r->flags & IORESOURCE_PCI_FIXED) {
6340 		pci_info(dev, "BAR%d %pR: ignoring requested alignment %#llx\n",
6341 			 bar, r, (unsigned long long)align);
6342 		return;
6343 	}
6344 
6345 	size = resource_size(r);
6346 	if (size >= align)
6347 		return;
6348 
6349 	/*
6350 	 * Increase the alignment of the resource.  There are two ways we
6351 	 * can do this:
6352 	 *
6353 	 * 1) Increase the size of the resource.  BARs are aligned on their
6354 	 *    size, so when we reallocate space for this resource, we'll
6355 	 *    allocate it with the larger alignment.  This also prevents
6356 	 *    assignment of any other BARs inside the alignment region, so
6357 	 *    if we're requesting page alignment, this means no other BARs
6358 	 *    will share the page.
6359 	 *
6360 	 *    The disadvantage is that this makes the resource larger than
6361 	 *    the hardware BAR, which may break drivers that compute things
6362 	 *    based on the resource size, e.g., to find registers at a
6363 	 *    fixed offset before the end of the BAR.
6364 	 *
6365 	 * 2) Retain the resource size, but use IORESOURCE_STARTALIGN and
6366 	 *    set r->start to the desired alignment.  By itself this
6367 	 *    doesn't prevent other BARs being put inside the alignment
6368 	 *    region, but if we realign *every* resource of every device in
6369 	 *    the system, none of them will share an alignment region.
6370 	 *
6371 	 * When the user has requested alignment for only some devices via
6372 	 * the "pci=resource_alignment" argument, "resize" is true and we
6373 	 * use the first method.  Otherwise we assume we're aligning all
6374 	 * devices and we use the second.
6375 	 */
6376 
6377 	pci_info(dev, "BAR%d %pR: requesting alignment to %#llx\n",
6378 		 bar, r, (unsigned long long)align);
6379 
6380 	if (resize) {
6381 		r->start = 0;
6382 		r->end = align - 1;
6383 	} else {
6384 		r->flags &= ~IORESOURCE_SIZEALIGN;
6385 		r->flags |= IORESOURCE_STARTALIGN;
6386 		r->start = align;
6387 		r->end = r->start + size - 1;
6388 	}
6389 	r->flags |= IORESOURCE_UNSET;
6390 }
6391 
6392 /*
6393  * This function disables memory decoding and releases memory resources
6394  * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
6395  * It also rounds up size to specified alignment.
6396  * Later on, the kernel will assign page-aligned memory resource back
6397  * to the device.
6398  */
6399 void pci_reassigndev_resource_alignment(struct pci_dev *dev)
6400 {
6401 	int i;
6402 	struct resource *r;
6403 	resource_size_t align;
6404 	u16 command;
6405 	bool resize = false;
6406 
6407 	/*
6408 	 * VF BARs are read-only zero according to SR-IOV spec r1.1, sec
6409 	 * 3.4.1.11.  Their resources are allocated from the space
6410 	 * described by the VF BARx register in the PF's SR-IOV capability.
6411 	 * We can't influence their alignment here.
6412 	 */
6413 	if (dev->is_virtfn)
6414 		return;
6415 
6416 	/* check if specified PCI is target device to reassign */
6417 	align = pci_specified_resource_alignment(dev, &resize);
6418 	if (!align)
6419 		return;
6420 
6421 	if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
6422 	    (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
6423 		pci_warn(dev, "Can't reassign resources to host bridge\n");
6424 		return;
6425 	}
6426 
6427 	pci_read_config_word(dev, PCI_COMMAND, &command);
6428 	command &= ~PCI_COMMAND_MEMORY;
6429 	pci_write_config_word(dev, PCI_COMMAND, command);
6430 
6431 	for (i = 0; i <= PCI_ROM_RESOURCE; i++)
6432 		pci_request_resource_alignment(dev, i, align, resize);
6433 
6434 	/*
6435 	 * Need to disable bridge's resource window,
6436 	 * to enable the kernel to reassign new resource
6437 	 * window later on.
6438 	 */
6439 	if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
6440 		for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
6441 			r = &dev->resource[i];
6442 			if (!(r->flags & IORESOURCE_MEM))
6443 				continue;
6444 			r->flags |= IORESOURCE_UNSET;
6445 			r->end = resource_size(r) - 1;
6446 			r->start = 0;
6447 		}
6448 		pci_disable_bridge_window(dev);
6449 	}
6450 }
6451 
6452 static ssize_t resource_alignment_show(struct bus_type *bus, char *buf)
6453 {
6454 	size_t count = 0;
6455 
6456 	spin_lock(&resource_alignment_lock);
6457 	if (resource_alignment_param)
6458 		count = sysfs_emit(buf, "%s\n", resource_alignment_param);
6459 	spin_unlock(&resource_alignment_lock);
6460 
6461 	return count;
6462 }
6463 
6464 static ssize_t resource_alignment_store(struct bus_type *bus,
6465 					const char *buf, size_t count)
6466 {
6467 	char *param, *old, *end;
6468 
6469 	if (count >= (PAGE_SIZE - 1))
6470 		return -EINVAL;
6471 
6472 	param = kstrndup(buf, count, GFP_KERNEL);
6473 	if (!param)
6474 		return -ENOMEM;
6475 
6476 	end = strchr(param, '\n');
6477 	if (end)
6478 		*end = '\0';
6479 
6480 	spin_lock(&resource_alignment_lock);
6481 	old = resource_alignment_param;
6482 	if (strlen(param)) {
6483 		resource_alignment_param = param;
6484 	} else {
6485 		kfree(param);
6486 		resource_alignment_param = NULL;
6487 	}
6488 	spin_unlock(&resource_alignment_lock);
6489 
6490 	kfree(old);
6491 
6492 	return count;
6493 }
6494 
6495 static BUS_ATTR_RW(resource_alignment);
6496 
6497 static int __init pci_resource_alignment_sysfs_init(void)
6498 {
6499 	return bus_create_file(&pci_bus_type,
6500 					&bus_attr_resource_alignment);
6501 }
6502 late_initcall(pci_resource_alignment_sysfs_init);
6503 
6504 static void pci_no_domains(void)
6505 {
6506 #ifdef CONFIG_PCI_DOMAINS
6507 	pci_domains_supported = 0;
6508 #endif
6509 }
6510 
6511 #ifdef CONFIG_PCI_DOMAINS_GENERIC
6512 static atomic_t __domain_nr = ATOMIC_INIT(-1);
6513 
6514 static int pci_get_new_domain_nr(void)
6515 {
6516 	return atomic_inc_return(&__domain_nr);
6517 }
6518 
6519 static int of_pci_bus_find_domain_nr(struct device *parent)
6520 {
6521 	static int use_dt_domains = -1;
6522 	int domain = -1;
6523 
6524 	if (parent)
6525 		domain = of_get_pci_domain_nr(parent->of_node);
6526 
6527 	/*
6528 	 * Check DT domain and use_dt_domains values.
6529 	 *
6530 	 * If DT domain property is valid (domain >= 0) and
6531 	 * use_dt_domains != 0, the DT assignment is valid since this means
6532 	 * we have not previously allocated a domain number by using
6533 	 * pci_get_new_domain_nr(); we should also update use_dt_domains to
6534 	 * 1, to indicate that we have just assigned a domain number from
6535 	 * DT.
6536 	 *
6537 	 * If DT domain property value is not valid (ie domain < 0), and we
6538 	 * have not previously assigned a domain number from DT
6539 	 * (use_dt_domains != 1) we should assign a domain number by
6540 	 * using the:
6541 	 *
6542 	 * pci_get_new_domain_nr()
6543 	 *
6544 	 * API and update the use_dt_domains value to keep track of method we
6545 	 * are using to assign domain numbers (use_dt_domains = 0).
6546 	 *
6547 	 * All other combinations imply we have a platform that is trying
6548 	 * to mix domain numbers obtained from DT and pci_get_new_domain_nr(),
6549 	 * which is a recipe for domain mishandling and it is prevented by
6550 	 * invalidating the domain value (domain = -1) and printing a
6551 	 * corresponding error.
6552 	 */
6553 	if (domain >= 0 && use_dt_domains) {
6554 		use_dt_domains = 1;
6555 	} else if (domain < 0 && use_dt_domains != 1) {
6556 		use_dt_domains = 0;
6557 		domain = pci_get_new_domain_nr();
6558 	} else {
6559 		if (parent)
6560 			pr_err("Node %pOF has ", parent->of_node);
6561 		pr_err("Inconsistent \"linux,pci-domain\" property in DT\n");
6562 		domain = -1;
6563 	}
6564 
6565 	return domain;
6566 }
6567 
6568 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent)
6569 {
6570 	return acpi_disabled ? of_pci_bus_find_domain_nr(parent) :
6571 			       acpi_pci_bus_find_domain_nr(bus);
6572 }
6573 #endif
6574 
6575 /**
6576  * pci_ext_cfg_avail - can we access extended PCI config space?
6577  *
6578  * Returns 1 if we can access PCI extended config space (offsets
6579  * greater than 0xff). This is the default implementation. Architecture
6580  * implementations can override this.
6581  */
6582 int __weak pci_ext_cfg_avail(void)
6583 {
6584 	return 1;
6585 }
6586 
6587 void __weak pci_fixup_cardbus(struct pci_bus *bus)
6588 {
6589 }
6590 EXPORT_SYMBOL(pci_fixup_cardbus);
6591 
6592 static int __init pci_setup(char *str)
6593 {
6594 	while (str) {
6595 		char *k = strchr(str, ',');
6596 		if (k)
6597 			*k++ = 0;
6598 		if (*str && (str = pcibios_setup(str)) && *str) {
6599 			if (!strcmp(str, "nomsi")) {
6600 				pci_no_msi();
6601 			} else if (!strncmp(str, "noats", 5)) {
6602 				pr_info("PCIe: ATS is disabled\n");
6603 				pcie_ats_disabled = true;
6604 			} else if (!strcmp(str, "noaer")) {
6605 				pci_no_aer();
6606 			} else if (!strcmp(str, "earlydump")) {
6607 				pci_early_dump = true;
6608 			} else if (!strncmp(str, "realloc=", 8)) {
6609 				pci_realloc_get_opt(str + 8);
6610 			} else if (!strncmp(str, "realloc", 7)) {
6611 				pci_realloc_get_opt("on");
6612 			} else if (!strcmp(str, "nodomains")) {
6613 				pci_no_domains();
6614 			} else if (!strncmp(str, "noari", 5)) {
6615 				pcie_ari_disabled = true;
6616 			} else if (!strncmp(str, "cbiosize=", 9)) {
6617 				pci_cardbus_io_size = memparse(str + 9, &str);
6618 			} else if (!strncmp(str, "cbmemsize=", 10)) {
6619 				pci_cardbus_mem_size = memparse(str + 10, &str);
6620 			} else if (!strncmp(str, "resource_alignment=", 19)) {
6621 				resource_alignment_param = str + 19;
6622 			} else if (!strncmp(str, "ecrc=", 5)) {
6623 				pcie_ecrc_get_policy(str + 5);
6624 			} else if (!strncmp(str, "hpiosize=", 9)) {
6625 				pci_hotplug_io_size = memparse(str + 9, &str);
6626 			} else if (!strncmp(str, "hpmmiosize=", 11)) {
6627 				pci_hotplug_mmio_size = memparse(str + 11, &str);
6628 			} else if (!strncmp(str, "hpmmioprefsize=", 15)) {
6629 				pci_hotplug_mmio_pref_size = memparse(str + 15, &str);
6630 			} else if (!strncmp(str, "hpmemsize=", 10)) {
6631 				pci_hotplug_mmio_size = memparse(str + 10, &str);
6632 				pci_hotplug_mmio_pref_size = pci_hotplug_mmio_size;
6633 			} else if (!strncmp(str, "hpbussize=", 10)) {
6634 				pci_hotplug_bus_size =
6635 					simple_strtoul(str + 10, &str, 0);
6636 				if (pci_hotplug_bus_size > 0xff)
6637 					pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE;
6638 			} else if (!strncmp(str, "pcie_bus_tune_off", 17)) {
6639 				pcie_bus_config = PCIE_BUS_TUNE_OFF;
6640 			} else if (!strncmp(str, "pcie_bus_safe", 13)) {
6641 				pcie_bus_config = PCIE_BUS_SAFE;
6642 			} else if (!strncmp(str, "pcie_bus_perf", 13)) {
6643 				pcie_bus_config = PCIE_BUS_PERFORMANCE;
6644 			} else if (!strncmp(str, "pcie_bus_peer2peer", 18)) {
6645 				pcie_bus_config = PCIE_BUS_PEER2PEER;
6646 			} else if (!strncmp(str, "pcie_scan_all", 13)) {
6647 				pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS);
6648 			} else if (!strncmp(str, "disable_acs_redir=", 18)) {
6649 				disable_acs_redir_param = str + 18;
6650 			} else {
6651 				pr_err("PCI: Unknown option `%s'\n", str);
6652 			}
6653 		}
6654 		str = k;
6655 	}
6656 	return 0;
6657 }
6658 early_param("pci", pci_setup);
6659 
6660 /*
6661  * 'resource_alignment_param' and 'disable_acs_redir_param' are initialized
6662  * in pci_setup(), above, to point to data in the __initdata section which
6663  * will be freed after the init sequence is complete. We can't allocate memory
6664  * in pci_setup() because some architectures do not have any memory allocation
6665  * service available during an early_param() call. So we allocate memory and
6666  * copy the variable here before the init section is freed.
6667  *
6668  */
6669 static int __init pci_realloc_setup_params(void)
6670 {
6671 	resource_alignment_param = kstrdup(resource_alignment_param,
6672 					   GFP_KERNEL);
6673 	disable_acs_redir_param = kstrdup(disable_acs_redir_param, GFP_KERNEL);
6674 
6675 	return 0;
6676 }
6677 pure_initcall(pci_realloc_setup_params);
6678