1 /* 2 * PCI Bus Services, see include/linux/pci.h for further explanation. 3 * 4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter, 5 * David Mosberger-Tang 6 * 7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz> 8 */ 9 10 #include <linux/kernel.h> 11 #include <linux/delay.h> 12 #include <linux/init.h> 13 #include <linux/of.h> 14 #include <linux/of_pci.h> 15 #include <linux/pci.h> 16 #include <linux/pm.h> 17 #include <linux/slab.h> 18 #include <linux/module.h> 19 #include <linux/spinlock.h> 20 #include <linux/string.h> 21 #include <linux/log2.h> 22 #include <linux/pci-aspm.h> 23 #include <linux/pm_wakeup.h> 24 #include <linux/interrupt.h> 25 #include <linux/device.h> 26 #include <linux/pm_runtime.h> 27 #include <linux/pci_hotplug.h> 28 #include <asm/setup.h> 29 #include <linux/aer.h> 30 #include "pci.h" 31 32 const char *pci_power_names[] = { 33 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown", 34 }; 35 EXPORT_SYMBOL_GPL(pci_power_names); 36 37 int isa_dma_bridge_buggy; 38 EXPORT_SYMBOL(isa_dma_bridge_buggy); 39 40 int pci_pci_problems; 41 EXPORT_SYMBOL(pci_pci_problems); 42 43 unsigned int pci_pm_d3_delay; 44 45 static void pci_pme_list_scan(struct work_struct *work); 46 47 static LIST_HEAD(pci_pme_list); 48 static DEFINE_MUTEX(pci_pme_list_mutex); 49 static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan); 50 51 struct pci_pme_device { 52 struct list_head list; 53 struct pci_dev *dev; 54 }; 55 56 #define PME_TIMEOUT 1000 /* How long between PME checks */ 57 58 static void pci_dev_d3_sleep(struct pci_dev *dev) 59 { 60 unsigned int delay = dev->d3_delay; 61 62 if (delay < pci_pm_d3_delay) 63 delay = pci_pm_d3_delay; 64 65 msleep(delay); 66 } 67 68 #ifdef CONFIG_PCI_DOMAINS 69 int pci_domains_supported = 1; 70 #endif 71 72 #define DEFAULT_CARDBUS_IO_SIZE (256) 73 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024) 74 /* pci=cbmemsize=nnM,cbiosize=nn can override this */ 75 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE; 76 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE; 77 78 #define DEFAULT_HOTPLUG_IO_SIZE (256) 79 #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024) 80 /* pci=hpmemsize=nnM,hpiosize=nn can override this */ 81 unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE; 82 unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE; 83 84 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_DEFAULT; 85 86 /* 87 * The default CLS is used if arch didn't set CLS explicitly and not 88 * all pci devices agree on the same value. Arch can override either 89 * the dfl or actual value as it sees fit. Don't forget this is 90 * measured in 32-bit words, not bytes. 91 */ 92 u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2; 93 u8 pci_cache_line_size; 94 95 /* 96 * If we set up a device for bus mastering, we need to check the latency 97 * timer as certain BIOSes forget to set it properly. 98 */ 99 unsigned int pcibios_max_latency = 255; 100 101 /* If set, the PCIe ARI capability will not be used. */ 102 static bool pcie_ari_disabled; 103 104 /** 105 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children 106 * @bus: pointer to PCI bus structure to search 107 * 108 * Given a PCI bus, returns the highest PCI bus number present in the set 109 * including the given PCI bus and its list of child PCI buses. 110 */ 111 unsigned char pci_bus_max_busnr(struct pci_bus *bus) 112 { 113 struct pci_bus *tmp; 114 unsigned char max, n; 115 116 max = bus->busn_res.end; 117 list_for_each_entry(tmp, &bus->children, node) { 118 n = pci_bus_max_busnr(tmp); 119 if (n > max) 120 max = n; 121 } 122 return max; 123 } 124 EXPORT_SYMBOL_GPL(pci_bus_max_busnr); 125 126 #ifdef CONFIG_HAS_IOMEM 127 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar) 128 { 129 struct resource *res = &pdev->resource[bar]; 130 131 /* 132 * Make sure the BAR is actually a memory resource, not an IO resource 133 */ 134 if (res->flags & IORESOURCE_UNSET || !(res->flags & IORESOURCE_MEM)) { 135 dev_warn(&pdev->dev, "can't ioremap BAR %d: %pR\n", bar, res); 136 return NULL; 137 } 138 return ioremap_nocache(res->start, resource_size(res)); 139 } 140 EXPORT_SYMBOL_GPL(pci_ioremap_bar); 141 142 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar) 143 { 144 /* 145 * Make sure the BAR is actually a memory resource, not an IO resource 146 */ 147 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { 148 WARN_ON(1); 149 return NULL; 150 } 151 return ioremap_wc(pci_resource_start(pdev, bar), 152 pci_resource_len(pdev, bar)); 153 } 154 EXPORT_SYMBOL_GPL(pci_ioremap_wc_bar); 155 #endif 156 157 158 static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn, 159 u8 pos, int cap, int *ttl) 160 { 161 u8 id; 162 u16 ent; 163 164 pci_bus_read_config_byte(bus, devfn, pos, &pos); 165 166 while ((*ttl)--) { 167 if (pos < 0x40) 168 break; 169 pos &= ~3; 170 pci_bus_read_config_word(bus, devfn, pos, &ent); 171 172 id = ent & 0xff; 173 if (id == 0xff) 174 break; 175 if (id == cap) 176 return pos; 177 pos = (ent >> 8); 178 } 179 return 0; 180 } 181 182 static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn, 183 u8 pos, int cap) 184 { 185 int ttl = PCI_FIND_CAP_TTL; 186 187 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl); 188 } 189 190 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap) 191 { 192 return __pci_find_next_cap(dev->bus, dev->devfn, 193 pos + PCI_CAP_LIST_NEXT, cap); 194 } 195 EXPORT_SYMBOL_GPL(pci_find_next_capability); 196 197 static int __pci_bus_find_cap_start(struct pci_bus *bus, 198 unsigned int devfn, u8 hdr_type) 199 { 200 u16 status; 201 202 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status); 203 if (!(status & PCI_STATUS_CAP_LIST)) 204 return 0; 205 206 switch (hdr_type) { 207 case PCI_HEADER_TYPE_NORMAL: 208 case PCI_HEADER_TYPE_BRIDGE: 209 return PCI_CAPABILITY_LIST; 210 case PCI_HEADER_TYPE_CARDBUS: 211 return PCI_CB_CAPABILITY_LIST; 212 } 213 214 return 0; 215 } 216 217 /** 218 * pci_find_capability - query for devices' capabilities 219 * @dev: PCI device to query 220 * @cap: capability code 221 * 222 * Tell if a device supports a given PCI capability. 223 * Returns the address of the requested capability structure within the 224 * device's PCI configuration space or 0 in case the device does not 225 * support it. Possible values for @cap: 226 * 227 * %PCI_CAP_ID_PM Power Management 228 * %PCI_CAP_ID_AGP Accelerated Graphics Port 229 * %PCI_CAP_ID_VPD Vital Product Data 230 * %PCI_CAP_ID_SLOTID Slot Identification 231 * %PCI_CAP_ID_MSI Message Signalled Interrupts 232 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap 233 * %PCI_CAP_ID_PCIX PCI-X 234 * %PCI_CAP_ID_EXP PCI Express 235 */ 236 int pci_find_capability(struct pci_dev *dev, int cap) 237 { 238 int pos; 239 240 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); 241 if (pos) 242 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap); 243 244 return pos; 245 } 246 EXPORT_SYMBOL(pci_find_capability); 247 248 /** 249 * pci_bus_find_capability - query for devices' capabilities 250 * @bus: the PCI bus to query 251 * @devfn: PCI device to query 252 * @cap: capability code 253 * 254 * Like pci_find_capability() but works for pci devices that do not have a 255 * pci_dev structure set up yet. 256 * 257 * Returns the address of the requested capability structure within the 258 * device's PCI configuration space or 0 in case the device does not 259 * support it. 260 */ 261 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap) 262 { 263 int pos; 264 u8 hdr_type; 265 266 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type); 267 268 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f); 269 if (pos) 270 pos = __pci_find_next_cap(bus, devfn, pos, cap); 271 272 return pos; 273 } 274 EXPORT_SYMBOL(pci_bus_find_capability); 275 276 /** 277 * pci_find_next_ext_capability - Find an extended capability 278 * @dev: PCI device to query 279 * @start: address at which to start looking (0 to start at beginning of list) 280 * @cap: capability code 281 * 282 * Returns the address of the next matching extended capability structure 283 * within the device's PCI configuration space or 0 if the device does 284 * not support it. Some capabilities can occur several times, e.g., the 285 * vendor-specific capability, and this provides a way to find them all. 286 */ 287 int pci_find_next_ext_capability(struct pci_dev *dev, int start, int cap) 288 { 289 u32 header; 290 int ttl; 291 int pos = PCI_CFG_SPACE_SIZE; 292 293 /* minimum 8 bytes per capability */ 294 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; 295 296 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE) 297 return 0; 298 299 if (start) 300 pos = start; 301 302 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) 303 return 0; 304 305 /* 306 * If we have no capabilities, this is indicated by cap ID, 307 * cap version and next pointer all being 0. 308 */ 309 if (header == 0) 310 return 0; 311 312 while (ttl-- > 0) { 313 if (PCI_EXT_CAP_ID(header) == cap && pos != start) 314 return pos; 315 316 pos = PCI_EXT_CAP_NEXT(header); 317 if (pos < PCI_CFG_SPACE_SIZE) 318 break; 319 320 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) 321 break; 322 } 323 324 return 0; 325 } 326 EXPORT_SYMBOL_GPL(pci_find_next_ext_capability); 327 328 /** 329 * pci_find_ext_capability - Find an extended capability 330 * @dev: PCI device to query 331 * @cap: capability code 332 * 333 * Returns the address of the requested extended capability structure 334 * within the device's PCI configuration space or 0 if the device does 335 * not support it. Possible values for @cap: 336 * 337 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting 338 * %PCI_EXT_CAP_ID_VC Virtual Channel 339 * %PCI_EXT_CAP_ID_DSN Device Serial Number 340 * %PCI_EXT_CAP_ID_PWR Power Budgeting 341 */ 342 int pci_find_ext_capability(struct pci_dev *dev, int cap) 343 { 344 return pci_find_next_ext_capability(dev, 0, cap); 345 } 346 EXPORT_SYMBOL_GPL(pci_find_ext_capability); 347 348 static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap) 349 { 350 int rc, ttl = PCI_FIND_CAP_TTL; 351 u8 cap, mask; 352 353 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST) 354 mask = HT_3BIT_CAP_MASK; 355 else 356 mask = HT_5BIT_CAP_MASK; 357 358 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos, 359 PCI_CAP_ID_HT, &ttl); 360 while (pos) { 361 rc = pci_read_config_byte(dev, pos + 3, &cap); 362 if (rc != PCIBIOS_SUCCESSFUL) 363 return 0; 364 365 if ((cap & mask) == ht_cap) 366 return pos; 367 368 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, 369 pos + PCI_CAP_LIST_NEXT, 370 PCI_CAP_ID_HT, &ttl); 371 } 372 373 return 0; 374 } 375 /** 376 * pci_find_next_ht_capability - query a device's Hypertransport capabilities 377 * @dev: PCI device to query 378 * @pos: Position from which to continue searching 379 * @ht_cap: Hypertransport capability code 380 * 381 * To be used in conjunction with pci_find_ht_capability() to search for 382 * all capabilities matching @ht_cap. @pos should always be a value returned 383 * from pci_find_ht_capability(). 384 * 385 * NB. To be 100% safe against broken PCI devices, the caller should take 386 * steps to avoid an infinite loop. 387 */ 388 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap) 389 { 390 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap); 391 } 392 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability); 393 394 /** 395 * pci_find_ht_capability - query a device's Hypertransport capabilities 396 * @dev: PCI device to query 397 * @ht_cap: Hypertransport capability code 398 * 399 * Tell if a device supports a given Hypertransport capability. 400 * Returns an address within the device's PCI configuration space 401 * or 0 in case the device does not support the request capability. 402 * The address points to the PCI capability, of type PCI_CAP_ID_HT, 403 * which has a Hypertransport capability matching @ht_cap. 404 */ 405 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap) 406 { 407 int pos; 408 409 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); 410 if (pos) 411 pos = __pci_find_next_ht_cap(dev, pos, ht_cap); 412 413 return pos; 414 } 415 EXPORT_SYMBOL_GPL(pci_find_ht_capability); 416 417 /** 418 * pci_find_parent_resource - return resource region of parent bus of given region 419 * @dev: PCI device structure contains resources to be searched 420 * @res: child resource record for which parent is sought 421 * 422 * For given resource region of given device, return the resource 423 * region of parent bus the given region is contained in. 424 */ 425 struct resource *pci_find_parent_resource(const struct pci_dev *dev, 426 struct resource *res) 427 { 428 const struct pci_bus *bus = dev->bus; 429 struct resource *r; 430 int i; 431 432 pci_bus_for_each_resource(bus, r, i) { 433 if (!r) 434 continue; 435 if (res->start && resource_contains(r, res)) { 436 437 /* 438 * If the window is prefetchable but the BAR is 439 * not, the allocator made a mistake. 440 */ 441 if (r->flags & IORESOURCE_PREFETCH && 442 !(res->flags & IORESOURCE_PREFETCH)) 443 return NULL; 444 445 /* 446 * If we're below a transparent bridge, there may 447 * be both a positively-decoded aperture and a 448 * subtractively-decoded region that contain the BAR. 449 * We want the positively-decoded one, so this depends 450 * on pci_bus_for_each_resource() giving us those 451 * first. 452 */ 453 return r; 454 } 455 } 456 return NULL; 457 } 458 EXPORT_SYMBOL(pci_find_parent_resource); 459 460 /** 461 * pci_find_pcie_root_port - return PCIe Root Port 462 * @dev: PCI device to query 463 * 464 * Traverse up the parent chain and return the PCIe Root Port PCI Device 465 * for a given PCI Device. 466 */ 467 struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev) 468 { 469 struct pci_dev *bridge, *highest_pcie_bridge = NULL; 470 471 bridge = pci_upstream_bridge(dev); 472 while (bridge && pci_is_pcie(bridge)) { 473 highest_pcie_bridge = bridge; 474 bridge = pci_upstream_bridge(bridge); 475 } 476 477 if (pci_pcie_type(highest_pcie_bridge) != PCI_EXP_TYPE_ROOT_PORT) 478 return NULL; 479 480 return highest_pcie_bridge; 481 } 482 EXPORT_SYMBOL(pci_find_pcie_root_port); 483 484 /** 485 * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos 486 * @dev: the PCI device to operate on 487 * @pos: config space offset of status word 488 * @mask: mask of bit(s) to care about in status word 489 * 490 * Return 1 when mask bit(s) in status word clear, 0 otherwise. 491 */ 492 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask) 493 { 494 int i; 495 496 /* Wait for Transaction Pending bit clean */ 497 for (i = 0; i < 4; i++) { 498 u16 status; 499 if (i) 500 msleep((1 << (i - 1)) * 100); 501 502 pci_read_config_word(dev, pos, &status); 503 if (!(status & mask)) 504 return 1; 505 } 506 507 return 0; 508 } 509 510 /** 511 * pci_restore_bars - restore a device's BAR values (e.g. after wake-up) 512 * @dev: PCI device to have its BARs restored 513 * 514 * Restore the BAR values for a given device, so as to make it 515 * accessible by its driver. 516 */ 517 static void pci_restore_bars(struct pci_dev *dev) 518 { 519 int i; 520 521 /* Per SR-IOV spec 3.4.1.11, VF BARs are RO zero */ 522 if (dev->is_virtfn) 523 return; 524 525 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) 526 pci_update_resource(dev, i); 527 } 528 529 static const struct pci_platform_pm_ops *pci_platform_pm; 530 531 int pci_set_platform_pm(const struct pci_platform_pm_ops *ops) 532 { 533 if (!ops->is_manageable || !ops->set_state || !ops->choose_state 534 || !ops->sleep_wake) 535 return -EINVAL; 536 pci_platform_pm = ops; 537 return 0; 538 } 539 540 static inline bool platform_pci_power_manageable(struct pci_dev *dev) 541 { 542 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false; 543 } 544 545 static inline int platform_pci_set_power_state(struct pci_dev *dev, 546 pci_power_t t) 547 { 548 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS; 549 } 550 551 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev) 552 { 553 return pci_platform_pm ? 554 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR; 555 } 556 557 static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable) 558 { 559 return pci_platform_pm ? 560 pci_platform_pm->sleep_wake(dev, enable) : -ENODEV; 561 } 562 563 static inline int platform_pci_run_wake(struct pci_dev *dev, bool enable) 564 { 565 return pci_platform_pm ? 566 pci_platform_pm->run_wake(dev, enable) : -ENODEV; 567 } 568 569 static inline bool platform_pci_need_resume(struct pci_dev *dev) 570 { 571 return pci_platform_pm ? pci_platform_pm->need_resume(dev) : false; 572 } 573 574 /** 575 * pci_raw_set_power_state - Use PCI PM registers to set the power state of 576 * given PCI device 577 * @dev: PCI device to handle. 578 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into. 579 * 580 * RETURN VALUE: 581 * -EINVAL if the requested state is invalid. 582 * -EIO if device does not support PCI PM or its PM capabilities register has a 583 * wrong version, or device doesn't support the requested state. 584 * 0 if device already is in the requested state. 585 * 0 if device's power state has been successfully changed. 586 */ 587 static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state) 588 { 589 u16 pmcsr; 590 bool need_restore = false; 591 592 /* Check if we're already there */ 593 if (dev->current_state == state) 594 return 0; 595 596 if (!dev->pm_cap) 597 return -EIO; 598 599 if (state < PCI_D0 || state > PCI_D3hot) 600 return -EINVAL; 601 602 /* Validate current state: 603 * Can enter D0 from any state, but if we can only go deeper 604 * to sleep if we're already in a low power state 605 */ 606 if (state != PCI_D0 && dev->current_state <= PCI_D3cold 607 && dev->current_state > state) { 608 dev_err(&dev->dev, "invalid power transition (from state %d to %d)\n", 609 dev->current_state, state); 610 return -EINVAL; 611 } 612 613 /* check if this device supports the desired state */ 614 if ((state == PCI_D1 && !dev->d1_support) 615 || (state == PCI_D2 && !dev->d2_support)) 616 return -EIO; 617 618 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); 619 620 /* If we're (effectively) in D3, force entire word to 0. 621 * This doesn't affect PME_Status, disables PME_En, and 622 * sets PowerState to 0. 623 */ 624 switch (dev->current_state) { 625 case PCI_D0: 626 case PCI_D1: 627 case PCI_D2: 628 pmcsr &= ~PCI_PM_CTRL_STATE_MASK; 629 pmcsr |= state; 630 break; 631 case PCI_D3hot: 632 case PCI_D3cold: 633 case PCI_UNKNOWN: /* Boot-up */ 634 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot 635 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET)) 636 need_restore = true; 637 /* Fall-through: force to D0 */ 638 default: 639 pmcsr = 0; 640 break; 641 } 642 643 /* enter specified state */ 644 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); 645 646 /* Mandatory power management transition delays */ 647 /* see PCI PM 1.1 5.6.1 table 18 */ 648 if (state == PCI_D3hot || dev->current_state == PCI_D3hot) 649 pci_dev_d3_sleep(dev); 650 else if (state == PCI_D2 || dev->current_state == PCI_D2) 651 udelay(PCI_PM_D2_DELAY); 652 653 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); 654 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); 655 if (dev->current_state != state && printk_ratelimit()) 656 dev_info(&dev->dev, "Refused to change power state, currently in D%d\n", 657 dev->current_state); 658 659 /* 660 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT 661 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning 662 * from D3hot to D0 _may_ perform an internal reset, thereby 663 * going to "D0 Uninitialized" rather than "D0 Initialized". 664 * For example, at least some versions of the 3c905B and the 665 * 3c556B exhibit this behaviour. 666 * 667 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave 668 * devices in a D3hot state at boot. Consequently, we need to 669 * restore at least the BARs so that the device will be 670 * accessible to its driver. 671 */ 672 if (need_restore) 673 pci_restore_bars(dev); 674 675 if (dev->bus->self) 676 pcie_aspm_pm_state_change(dev->bus->self); 677 678 return 0; 679 } 680 681 /** 682 * pci_update_current_state - Read PCI power state of given device from its 683 * PCI PM registers and cache it 684 * @dev: PCI device to handle. 685 * @state: State to cache in case the device doesn't have the PM capability 686 */ 687 void pci_update_current_state(struct pci_dev *dev, pci_power_t state) 688 { 689 if (dev->pm_cap) { 690 u16 pmcsr; 691 692 /* 693 * Configuration space is not accessible for device in 694 * D3cold, so just keep or set D3cold for safety 695 */ 696 if (dev->current_state == PCI_D3cold) 697 return; 698 if (state == PCI_D3cold) { 699 dev->current_state = PCI_D3cold; 700 return; 701 } 702 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); 703 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); 704 } else { 705 dev->current_state = state; 706 } 707 } 708 709 /** 710 * pci_power_up - Put the given device into D0 forcibly 711 * @dev: PCI device to power up 712 */ 713 void pci_power_up(struct pci_dev *dev) 714 { 715 if (platform_pci_power_manageable(dev)) 716 platform_pci_set_power_state(dev, PCI_D0); 717 718 pci_raw_set_power_state(dev, PCI_D0); 719 pci_update_current_state(dev, PCI_D0); 720 } 721 722 /** 723 * pci_platform_power_transition - Use platform to change device power state 724 * @dev: PCI device to handle. 725 * @state: State to put the device into. 726 */ 727 static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state) 728 { 729 int error; 730 731 if (platform_pci_power_manageable(dev)) { 732 error = platform_pci_set_power_state(dev, state); 733 if (!error) 734 pci_update_current_state(dev, state); 735 } else 736 error = -ENODEV; 737 738 if (error && !dev->pm_cap) /* Fall back to PCI_D0 */ 739 dev->current_state = PCI_D0; 740 741 return error; 742 } 743 744 /** 745 * pci_wakeup - Wake up a PCI device 746 * @pci_dev: Device to handle. 747 * @ign: ignored parameter 748 */ 749 static int pci_wakeup(struct pci_dev *pci_dev, void *ign) 750 { 751 pci_wakeup_event(pci_dev); 752 pm_request_resume(&pci_dev->dev); 753 return 0; 754 } 755 756 /** 757 * pci_wakeup_bus - Walk given bus and wake up devices on it 758 * @bus: Top bus of the subtree to walk. 759 */ 760 static void pci_wakeup_bus(struct pci_bus *bus) 761 { 762 if (bus) 763 pci_walk_bus(bus, pci_wakeup, NULL); 764 } 765 766 /** 767 * __pci_start_power_transition - Start power transition of a PCI device 768 * @dev: PCI device to handle. 769 * @state: State to put the device into. 770 */ 771 static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state) 772 { 773 if (state == PCI_D0) { 774 pci_platform_power_transition(dev, PCI_D0); 775 /* 776 * Mandatory power management transition delays, see 777 * PCI Express Base Specification Revision 2.0 Section 778 * 6.6.1: Conventional Reset. Do not delay for 779 * devices powered on/off by corresponding bridge, 780 * because have already delayed for the bridge. 781 */ 782 if (dev->runtime_d3cold) { 783 msleep(dev->d3cold_delay); 784 /* 785 * When powering on a bridge from D3cold, the 786 * whole hierarchy may be powered on into 787 * D0uninitialized state, resume them to give 788 * them a chance to suspend again 789 */ 790 pci_wakeup_bus(dev->subordinate); 791 } 792 } 793 } 794 795 /** 796 * __pci_dev_set_current_state - Set current state of a PCI device 797 * @dev: Device to handle 798 * @data: pointer to state to be set 799 */ 800 static int __pci_dev_set_current_state(struct pci_dev *dev, void *data) 801 { 802 pci_power_t state = *(pci_power_t *)data; 803 804 dev->current_state = state; 805 return 0; 806 } 807 808 /** 809 * __pci_bus_set_current_state - Walk given bus and set current state of devices 810 * @bus: Top bus of the subtree to walk. 811 * @state: state to be set 812 */ 813 static void __pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state) 814 { 815 if (bus) 816 pci_walk_bus(bus, __pci_dev_set_current_state, &state); 817 } 818 819 /** 820 * __pci_complete_power_transition - Complete power transition of a PCI device 821 * @dev: PCI device to handle. 822 * @state: State to put the device into. 823 * 824 * This function should not be called directly by device drivers. 825 */ 826 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state) 827 { 828 int ret; 829 830 if (state <= PCI_D0) 831 return -EINVAL; 832 ret = pci_platform_power_transition(dev, state); 833 /* Power off the bridge may power off the whole hierarchy */ 834 if (!ret && state == PCI_D3cold) 835 __pci_bus_set_current_state(dev->subordinate, PCI_D3cold); 836 return ret; 837 } 838 EXPORT_SYMBOL_GPL(__pci_complete_power_transition); 839 840 /** 841 * pci_set_power_state - Set the power state of a PCI device 842 * @dev: PCI device to handle. 843 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into. 844 * 845 * Transition a device to a new power state, using the platform firmware and/or 846 * the device's PCI PM registers. 847 * 848 * RETURN VALUE: 849 * -EINVAL if the requested state is invalid. 850 * -EIO if device does not support PCI PM or its PM capabilities register has a 851 * wrong version, or device doesn't support the requested state. 852 * 0 if device already is in the requested state. 853 * 0 if device's power state has been successfully changed. 854 */ 855 int pci_set_power_state(struct pci_dev *dev, pci_power_t state) 856 { 857 int error; 858 859 /* bound the state we're entering */ 860 if (state > PCI_D3cold) 861 state = PCI_D3cold; 862 else if (state < PCI_D0) 863 state = PCI_D0; 864 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev)) 865 /* 866 * If the device or the parent bridge do not support PCI PM, 867 * ignore the request if we're doing anything other than putting 868 * it into D0 (which would only happen on boot). 869 */ 870 return 0; 871 872 /* Check if we're already there */ 873 if (dev->current_state == state) 874 return 0; 875 876 __pci_start_power_transition(dev, state); 877 878 /* This device is quirked not to be put into D3, so 879 don't put it in D3 */ 880 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3)) 881 return 0; 882 883 /* 884 * To put device in D3cold, we put device into D3hot in native 885 * way, then put device into D3cold with platform ops 886 */ 887 error = pci_raw_set_power_state(dev, state > PCI_D3hot ? 888 PCI_D3hot : state); 889 890 if (!__pci_complete_power_transition(dev, state)) 891 error = 0; 892 893 return error; 894 } 895 EXPORT_SYMBOL(pci_set_power_state); 896 897 /** 898 * pci_choose_state - Choose the power state of a PCI device 899 * @dev: PCI device to be suspended 900 * @state: target sleep state for the whole system. This is the value 901 * that is passed to suspend() function. 902 * 903 * Returns PCI power state suitable for given device and given system 904 * message. 905 */ 906 907 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state) 908 { 909 pci_power_t ret; 910 911 if (!dev->pm_cap) 912 return PCI_D0; 913 914 ret = platform_pci_choose_state(dev); 915 if (ret != PCI_POWER_ERROR) 916 return ret; 917 918 switch (state.event) { 919 case PM_EVENT_ON: 920 return PCI_D0; 921 case PM_EVENT_FREEZE: 922 case PM_EVENT_PRETHAW: 923 /* REVISIT both freeze and pre-thaw "should" use D0 */ 924 case PM_EVENT_SUSPEND: 925 case PM_EVENT_HIBERNATE: 926 return PCI_D3hot; 927 default: 928 dev_info(&dev->dev, "unrecognized suspend event %d\n", 929 state.event); 930 BUG(); 931 } 932 return PCI_D0; 933 } 934 EXPORT_SYMBOL(pci_choose_state); 935 936 #define PCI_EXP_SAVE_REGS 7 937 938 static struct pci_cap_saved_state *_pci_find_saved_cap(struct pci_dev *pci_dev, 939 u16 cap, bool extended) 940 { 941 struct pci_cap_saved_state *tmp; 942 943 hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) { 944 if (tmp->cap.cap_extended == extended && tmp->cap.cap_nr == cap) 945 return tmp; 946 } 947 return NULL; 948 } 949 950 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap) 951 { 952 return _pci_find_saved_cap(dev, cap, false); 953 } 954 955 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, u16 cap) 956 { 957 return _pci_find_saved_cap(dev, cap, true); 958 } 959 960 static int pci_save_pcie_state(struct pci_dev *dev) 961 { 962 int i = 0; 963 struct pci_cap_saved_state *save_state; 964 u16 *cap; 965 966 if (!pci_is_pcie(dev)) 967 return 0; 968 969 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); 970 if (!save_state) { 971 dev_err(&dev->dev, "buffer not found in %s\n", __func__); 972 return -ENOMEM; 973 } 974 975 cap = (u16 *)&save_state->cap.data[0]; 976 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]); 977 pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]); 978 pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]); 979 pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]); 980 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]); 981 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]); 982 pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]); 983 984 return 0; 985 } 986 987 static void pci_restore_pcie_state(struct pci_dev *dev) 988 { 989 int i = 0; 990 struct pci_cap_saved_state *save_state; 991 u16 *cap; 992 993 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); 994 if (!save_state) 995 return; 996 997 cap = (u16 *)&save_state->cap.data[0]; 998 pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]); 999 pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]); 1000 pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]); 1001 pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]); 1002 pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]); 1003 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]); 1004 pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]); 1005 } 1006 1007 1008 static int pci_save_pcix_state(struct pci_dev *dev) 1009 { 1010 int pos; 1011 struct pci_cap_saved_state *save_state; 1012 1013 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); 1014 if (!pos) 1015 return 0; 1016 1017 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); 1018 if (!save_state) { 1019 dev_err(&dev->dev, "buffer not found in %s\n", __func__); 1020 return -ENOMEM; 1021 } 1022 1023 pci_read_config_word(dev, pos + PCI_X_CMD, 1024 (u16 *)save_state->cap.data); 1025 1026 return 0; 1027 } 1028 1029 static void pci_restore_pcix_state(struct pci_dev *dev) 1030 { 1031 int i = 0, pos; 1032 struct pci_cap_saved_state *save_state; 1033 u16 *cap; 1034 1035 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); 1036 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); 1037 if (!save_state || !pos) 1038 return; 1039 cap = (u16 *)&save_state->cap.data[0]; 1040 1041 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]); 1042 } 1043 1044 1045 /** 1046 * pci_save_state - save the PCI configuration space of a device before suspending 1047 * @dev: - PCI device that we're dealing with 1048 */ 1049 int pci_save_state(struct pci_dev *dev) 1050 { 1051 int i; 1052 /* XXX: 100% dword access ok here? */ 1053 for (i = 0; i < 16; i++) 1054 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]); 1055 dev->state_saved = true; 1056 1057 i = pci_save_pcie_state(dev); 1058 if (i != 0) 1059 return i; 1060 1061 i = pci_save_pcix_state(dev); 1062 if (i != 0) 1063 return i; 1064 1065 return pci_save_vc_state(dev); 1066 } 1067 EXPORT_SYMBOL(pci_save_state); 1068 1069 static void pci_restore_config_dword(struct pci_dev *pdev, int offset, 1070 u32 saved_val, int retry) 1071 { 1072 u32 val; 1073 1074 pci_read_config_dword(pdev, offset, &val); 1075 if (val == saved_val) 1076 return; 1077 1078 for (;;) { 1079 dev_dbg(&pdev->dev, "restoring config space at offset %#x (was %#x, writing %#x)\n", 1080 offset, val, saved_val); 1081 pci_write_config_dword(pdev, offset, saved_val); 1082 if (retry-- <= 0) 1083 return; 1084 1085 pci_read_config_dword(pdev, offset, &val); 1086 if (val == saved_val) 1087 return; 1088 1089 mdelay(1); 1090 } 1091 } 1092 1093 static void pci_restore_config_space_range(struct pci_dev *pdev, 1094 int start, int end, int retry) 1095 { 1096 int index; 1097 1098 for (index = end; index >= start; index--) 1099 pci_restore_config_dword(pdev, 4 * index, 1100 pdev->saved_config_space[index], 1101 retry); 1102 } 1103 1104 static void pci_restore_config_space(struct pci_dev *pdev) 1105 { 1106 if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) { 1107 pci_restore_config_space_range(pdev, 10, 15, 0); 1108 /* Restore BARs before the command register. */ 1109 pci_restore_config_space_range(pdev, 4, 9, 10); 1110 pci_restore_config_space_range(pdev, 0, 3, 0); 1111 } else { 1112 pci_restore_config_space_range(pdev, 0, 15, 0); 1113 } 1114 } 1115 1116 /** 1117 * pci_restore_state - Restore the saved state of a PCI device 1118 * @dev: - PCI device that we're dealing with 1119 */ 1120 void pci_restore_state(struct pci_dev *dev) 1121 { 1122 if (!dev->state_saved) 1123 return; 1124 1125 /* PCI Express register must be restored first */ 1126 pci_restore_pcie_state(dev); 1127 pci_restore_ats_state(dev); 1128 pci_restore_vc_state(dev); 1129 1130 pci_cleanup_aer_error_status_regs(dev); 1131 1132 pci_restore_config_space(dev); 1133 1134 pci_restore_pcix_state(dev); 1135 pci_restore_msi_state(dev); 1136 1137 /* Restore ACS and IOV configuration state */ 1138 pci_enable_acs(dev); 1139 pci_restore_iov_state(dev); 1140 1141 dev->state_saved = false; 1142 } 1143 EXPORT_SYMBOL(pci_restore_state); 1144 1145 struct pci_saved_state { 1146 u32 config_space[16]; 1147 struct pci_cap_saved_data cap[0]; 1148 }; 1149 1150 /** 1151 * pci_store_saved_state - Allocate and return an opaque struct containing 1152 * the device saved state. 1153 * @dev: PCI device that we're dealing with 1154 * 1155 * Return NULL if no state or error. 1156 */ 1157 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev) 1158 { 1159 struct pci_saved_state *state; 1160 struct pci_cap_saved_state *tmp; 1161 struct pci_cap_saved_data *cap; 1162 size_t size; 1163 1164 if (!dev->state_saved) 1165 return NULL; 1166 1167 size = sizeof(*state) + sizeof(struct pci_cap_saved_data); 1168 1169 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) 1170 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size; 1171 1172 state = kzalloc(size, GFP_KERNEL); 1173 if (!state) 1174 return NULL; 1175 1176 memcpy(state->config_space, dev->saved_config_space, 1177 sizeof(state->config_space)); 1178 1179 cap = state->cap; 1180 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) { 1181 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size; 1182 memcpy(cap, &tmp->cap, len); 1183 cap = (struct pci_cap_saved_data *)((u8 *)cap + len); 1184 } 1185 /* Empty cap_save terminates list */ 1186 1187 return state; 1188 } 1189 EXPORT_SYMBOL_GPL(pci_store_saved_state); 1190 1191 /** 1192 * pci_load_saved_state - Reload the provided save state into struct pci_dev. 1193 * @dev: PCI device that we're dealing with 1194 * @state: Saved state returned from pci_store_saved_state() 1195 */ 1196 int pci_load_saved_state(struct pci_dev *dev, 1197 struct pci_saved_state *state) 1198 { 1199 struct pci_cap_saved_data *cap; 1200 1201 dev->state_saved = false; 1202 1203 if (!state) 1204 return 0; 1205 1206 memcpy(dev->saved_config_space, state->config_space, 1207 sizeof(state->config_space)); 1208 1209 cap = state->cap; 1210 while (cap->size) { 1211 struct pci_cap_saved_state *tmp; 1212 1213 tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended); 1214 if (!tmp || tmp->cap.size != cap->size) 1215 return -EINVAL; 1216 1217 memcpy(tmp->cap.data, cap->data, tmp->cap.size); 1218 cap = (struct pci_cap_saved_data *)((u8 *)cap + 1219 sizeof(struct pci_cap_saved_data) + cap->size); 1220 } 1221 1222 dev->state_saved = true; 1223 return 0; 1224 } 1225 EXPORT_SYMBOL_GPL(pci_load_saved_state); 1226 1227 /** 1228 * pci_load_and_free_saved_state - Reload the save state pointed to by state, 1229 * and free the memory allocated for it. 1230 * @dev: PCI device that we're dealing with 1231 * @state: Pointer to saved state returned from pci_store_saved_state() 1232 */ 1233 int pci_load_and_free_saved_state(struct pci_dev *dev, 1234 struct pci_saved_state **state) 1235 { 1236 int ret = pci_load_saved_state(dev, *state); 1237 kfree(*state); 1238 *state = NULL; 1239 return ret; 1240 } 1241 EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state); 1242 1243 int __weak pcibios_enable_device(struct pci_dev *dev, int bars) 1244 { 1245 return pci_enable_resources(dev, bars); 1246 } 1247 1248 static int do_pci_enable_device(struct pci_dev *dev, int bars) 1249 { 1250 int err; 1251 struct pci_dev *bridge; 1252 u16 cmd; 1253 u8 pin; 1254 1255 err = pci_set_power_state(dev, PCI_D0); 1256 if (err < 0 && err != -EIO) 1257 return err; 1258 1259 bridge = pci_upstream_bridge(dev); 1260 if (bridge) 1261 pcie_aspm_powersave_config_link(bridge); 1262 1263 err = pcibios_enable_device(dev, bars); 1264 if (err < 0) 1265 return err; 1266 pci_fixup_device(pci_fixup_enable, dev); 1267 1268 if (dev->msi_enabled || dev->msix_enabled) 1269 return 0; 1270 1271 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); 1272 if (pin) { 1273 pci_read_config_word(dev, PCI_COMMAND, &cmd); 1274 if (cmd & PCI_COMMAND_INTX_DISABLE) 1275 pci_write_config_word(dev, PCI_COMMAND, 1276 cmd & ~PCI_COMMAND_INTX_DISABLE); 1277 } 1278 1279 return 0; 1280 } 1281 1282 /** 1283 * pci_reenable_device - Resume abandoned device 1284 * @dev: PCI device to be resumed 1285 * 1286 * Note this function is a backend of pci_default_resume and is not supposed 1287 * to be called by normal code, write proper resume handler and use it instead. 1288 */ 1289 int pci_reenable_device(struct pci_dev *dev) 1290 { 1291 if (pci_is_enabled(dev)) 1292 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1); 1293 return 0; 1294 } 1295 EXPORT_SYMBOL(pci_reenable_device); 1296 1297 static void pci_enable_bridge(struct pci_dev *dev) 1298 { 1299 struct pci_dev *bridge; 1300 int retval; 1301 1302 bridge = pci_upstream_bridge(dev); 1303 if (bridge) 1304 pci_enable_bridge(bridge); 1305 1306 if (pci_is_enabled(dev)) { 1307 if (!dev->is_busmaster) 1308 pci_set_master(dev); 1309 return; 1310 } 1311 1312 retval = pci_enable_device(dev); 1313 if (retval) 1314 dev_err(&dev->dev, "Error enabling bridge (%d), continuing\n", 1315 retval); 1316 pci_set_master(dev); 1317 } 1318 1319 static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags) 1320 { 1321 struct pci_dev *bridge; 1322 int err; 1323 int i, bars = 0; 1324 1325 /* 1326 * Power state could be unknown at this point, either due to a fresh 1327 * boot or a device removal call. So get the current power state 1328 * so that things like MSI message writing will behave as expected 1329 * (e.g. if the device really is in D0 at enable time). 1330 */ 1331 if (dev->pm_cap) { 1332 u16 pmcsr; 1333 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); 1334 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); 1335 } 1336 1337 if (atomic_inc_return(&dev->enable_cnt) > 1) 1338 return 0; /* already enabled */ 1339 1340 bridge = pci_upstream_bridge(dev); 1341 if (bridge) 1342 pci_enable_bridge(bridge); 1343 1344 /* only skip sriov related */ 1345 for (i = 0; i <= PCI_ROM_RESOURCE; i++) 1346 if (dev->resource[i].flags & flags) 1347 bars |= (1 << i); 1348 for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++) 1349 if (dev->resource[i].flags & flags) 1350 bars |= (1 << i); 1351 1352 err = do_pci_enable_device(dev, bars); 1353 if (err < 0) 1354 atomic_dec(&dev->enable_cnt); 1355 return err; 1356 } 1357 1358 /** 1359 * pci_enable_device_io - Initialize a device for use with IO space 1360 * @dev: PCI device to be initialized 1361 * 1362 * Initialize device before it's used by a driver. Ask low-level code 1363 * to enable I/O resources. Wake up the device if it was suspended. 1364 * Beware, this function can fail. 1365 */ 1366 int pci_enable_device_io(struct pci_dev *dev) 1367 { 1368 return pci_enable_device_flags(dev, IORESOURCE_IO); 1369 } 1370 EXPORT_SYMBOL(pci_enable_device_io); 1371 1372 /** 1373 * pci_enable_device_mem - Initialize a device for use with Memory space 1374 * @dev: PCI device to be initialized 1375 * 1376 * Initialize device before it's used by a driver. Ask low-level code 1377 * to enable Memory resources. Wake up the device if it was suspended. 1378 * Beware, this function can fail. 1379 */ 1380 int pci_enable_device_mem(struct pci_dev *dev) 1381 { 1382 return pci_enable_device_flags(dev, IORESOURCE_MEM); 1383 } 1384 EXPORT_SYMBOL(pci_enable_device_mem); 1385 1386 /** 1387 * pci_enable_device - Initialize device before it's used by a driver. 1388 * @dev: PCI device to be initialized 1389 * 1390 * Initialize device before it's used by a driver. Ask low-level code 1391 * to enable I/O and memory. Wake up the device if it was suspended. 1392 * Beware, this function can fail. 1393 * 1394 * Note we don't actually enable the device many times if we call 1395 * this function repeatedly (we just increment the count). 1396 */ 1397 int pci_enable_device(struct pci_dev *dev) 1398 { 1399 return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO); 1400 } 1401 EXPORT_SYMBOL(pci_enable_device); 1402 1403 /* 1404 * Managed PCI resources. This manages device on/off, intx/msi/msix 1405 * on/off and BAR regions. pci_dev itself records msi/msix status, so 1406 * there's no need to track it separately. pci_devres is initialized 1407 * when a device is enabled using managed PCI device enable interface. 1408 */ 1409 struct pci_devres { 1410 unsigned int enabled:1; 1411 unsigned int pinned:1; 1412 unsigned int orig_intx:1; 1413 unsigned int restore_intx:1; 1414 u32 region_mask; 1415 }; 1416 1417 static void pcim_release(struct device *gendev, void *res) 1418 { 1419 struct pci_dev *dev = to_pci_dev(gendev); 1420 struct pci_devres *this = res; 1421 int i; 1422 1423 if (dev->msi_enabled) 1424 pci_disable_msi(dev); 1425 if (dev->msix_enabled) 1426 pci_disable_msix(dev); 1427 1428 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) 1429 if (this->region_mask & (1 << i)) 1430 pci_release_region(dev, i); 1431 1432 if (this->restore_intx) 1433 pci_intx(dev, this->orig_intx); 1434 1435 if (this->enabled && !this->pinned) 1436 pci_disable_device(dev); 1437 } 1438 1439 static struct pci_devres *get_pci_dr(struct pci_dev *pdev) 1440 { 1441 struct pci_devres *dr, *new_dr; 1442 1443 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL); 1444 if (dr) 1445 return dr; 1446 1447 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL); 1448 if (!new_dr) 1449 return NULL; 1450 return devres_get(&pdev->dev, new_dr, NULL, NULL); 1451 } 1452 1453 static struct pci_devres *find_pci_dr(struct pci_dev *pdev) 1454 { 1455 if (pci_is_managed(pdev)) 1456 return devres_find(&pdev->dev, pcim_release, NULL, NULL); 1457 return NULL; 1458 } 1459 1460 /** 1461 * pcim_enable_device - Managed pci_enable_device() 1462 * @pdev: PCI device to be initialized 1463 * 1464 * Managed pci_enable_device(). 1465 */ 1466 int pcim_enable_device(struct pci_dev *pdev) 1467 { 1468 struct pci_devres *dr; 1469 int rc; 1470 1471 dr = get_pci_dr(pdev); 1472 if (unlikely(!dr)) 1473 return -ENOMEM; 1474 if (dr->enabled) 1475 return 0; 1476 1477 rc = pci_enable_device(pdev); 1478 if (!rc) { 1479 pdev->is_managed = 1; 1480 dr->enabled = 1; 1481 } 1482 return rc; 1483 } 1484 EXPORT_SYMBOL(pcim_enable_device); 1485 1486 /** 1487 * pcim_pin_device - Pin managed PCI device 1488 * @pdev: PCI device to pin 1489 * 1490 * Pin managed PCI device @pdev. Pinned device won't be disabled on 1491 * driver detach. @pdev must have been enabled with 1492 * pcim_enable_device(). 1493 */ 1494 void pcim_pin_device(struct pci_dev *pdev) 1495 { 1496 struct pci_devres *dr; 1497 1498 dr = find_pci_dr(pdev); 1499 WARN_ON(!dr || !dr->enabled); 1500 if (dr) 1501 dr->pinned = 1; 1502 } 1503 EXPORT_SYMBOL(pcim_pin_device); 1504 1505 /* 1506 * pcibios_add_device - provide arch specific hooks when adding device dev 1507 * @dev: the PCI device being added 1508 * 1509 * Permits the platform to provide architecture specific functionality when 1510 * devices are added. This is the default implementation. Architecture 1511 * implementations can override this. 1512 */ 1513 int __weak pcibios_add_device(struct pci_dev *dev) 1514 { 1515 return 0; 1516 } 1517 1518 /** 1519 * pcibios_release_device - provide arch specific hooks when releasing device dev 1520 * @dev: the PCI device being released 1521 * 1522 * Permits the platform to provide architecture specific functionality when 1523 * devices are released. This is the default implementation. Architecture 1524 * implementations can override this. 1525 */ 1526 void __weak pcibios_release_device(struct pci_dev *dev) {} 1527 1528 /** 1529 * pcibios_disable_device - disable arch specific PCI resources for device dev 1530 * @dev: the PCI device to disable 1531 * 1532 * Disables architecture specific PCI resources for the device. This 1533 * is the default implementation. Architecture implementations can 1534 * override this. 1535 */ 1536 void __weak pcibios_disable_device(struct pci_dev *dev) {} 1537 1538 /** 1539 * pcibios_penalize_isa_irq - penalize an ISA IRQ 1540 * @irq: ISA IRQ to penalize 1541 * @active: IRQ active or not 1542 * 1543 * Permits the platform to provide architecture-specific functionality when 1544 * penalizing ISA IRQs. This is the default implementation. Architecture 1545 * implementations can override this. 1546 */ 1547 void __weak pcibios_penalize_isa_irq(int irq, int active) {} 1548 1549 static void do_pci_disable_device(struct pci_dev *dev) 1550 { 1551 u16 pci_command; 1552 1553 pci_read_config_word(dev, PCI_COMMAND, &pci_command); 1554 if (pci_command & PCI_COMMAND_MASTER) { 1555 pci_command &= ~PCI_COMMAND_MASTER; 1556 pci_write_config_word(dev, PCI_COMMAND, pci_command); 1557 } 1558 1559 pcibios_disable_device(dev); 1560 } 1561 1562 /** 1563 * pci_disable_enabled_device - Disable device without updating enable_cnt 1564 * @dev: PCI device to disable 1565 * 1566 * NOTE: This function is a backend of PCI power management routines and is 1567 * not supposed to be called drivers. 1568 */ 1569 void pci_disable_enabled_device(struct pci_dev *dev) 1570 { 1571 if (pci_is_enabled(dev)) 1572 do_pci_disable_device(dev); 1573 } 1574 1575 /** 1576 * pci_disable_device - Disable PCI device after use 1577 * @dev: PCI device to be disabled 1578 * 1579 * Signal to the system that the PCI device is not in use by the system 1580 * anymore. This only involves disabling PCI bus-mastering, if active. 1581 * 1582 * Note we don't actually disable the device until all callers of 1583 * pci_enable_device() have called pci_disable_device(). 1584 */ 1585 void pci_disable_device(struct pci_dev *dev) 1586 { 1587 struct pci_devres *dr; 1588 1589 dr = find_pci_dr(dev); 1590 if (dr) 1591 dr->enabled = 0; 1592 1593 dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0, 1594 "disabling already-disabled device"); 1595 1596 if (atomic_dec_return(&dev->enable_cnt) != 0) 1597 return; 1598 1599 do_pci_disable_device(dev); 1600 1601 dev->is_busmaster = 0; 1602 } 1603 EXPORT_SYMBOL(pci_disable_device); 1604 1605 /** 1606 * pcibios_set_pcie_reset_state - set reset state for device dev 1607 * @dev: the PCIe device reset 1608 * @state: Reset state to enter into 1609 * 1610 * 1611 * Sets the PCIe reset state for the device. This is the default 1612 * implementation. Architecture implementations can override this. 1613 */ 1614 int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev, 1615 enum pcie_reset_state state) 1616 { 1617 return -EINVAL; 1618 } 1619 1620 /** 1621 * pci_set_pcie_reset_state - set reset state for device dev 1622 * @dev: the PCIe device reset 1623 * @state: Reset state to enter into 1624 * 1625 * 1626 * Sets the PCI reset state for the device. 1627 */ 1628 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state) 1629 { 1630 return pcibios_set_pcie_reset_state(dev, state); 1631 } 1632 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state); 1633 1634 /** 1635 * pci_check_pme_status - Check if given device has generated PME. 1636 * @dev: Device to check. 1637 * 1638 * Check the PME status of the device and if set, clear it and clear PME enable 1639 * (if set). Return 'true' if PME status and PME enable were both set or 1640 * 'false' otherwise. 1641 */ 1642 bool pci_check_pme_status(struct pci_dev *dev) 1643 { 1644 int pmcsr_pos; 1645 u16 pmcsr; 1646 bool ret = false; 1647 1648 if (!dev->pm_cap) 1649 return false; 1650 1651 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL; 1652 pci_read_config_word(dev, pmcsr_pos, &pmcsr); 1653 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS)) 1654 return false; 1655 1656 /* Clear PME status. */ 1657 pmcsr |= PCI_PM_CTRL_PME_STATUS; 1658 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) { 1659 /* Disable PME to avoid interrupt flood. */ 1660 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE; 1661 ret = true; 1662 } 1663 1664 pci_write_config_word(dev, pmcsr_pos, pmcsr); 1665 1666 return ret; 1667 } 1668 1669 /** 1670 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set. 1671 * @dev: Device to handle. 1672 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag. 1673 * 1674 * Check if @dev has generated PME and queue a resume request for it in that 1675 * case. 1676 */ 1677 static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset) 1678 { 1679 if (pme_poll_reset && dev->pme_poll) 1680 dev->pme_poll = false; 1681 1682 if (pci_check_pme_status(dev)) { 1683 pci_wakeup_event(dev); 1684 pm_request_resume(&dev->dev); 1685 } 1686 return 0; 1687 } 1688 1689 /** 1690 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary. 1691 * @bus: Top bus of the subtree to walk. 1692 */ 1693 void pci_pme_wakeup_bus(struct pci_bus *bus) 1694 { 1695 if (bus) 1696 pci_walk_bus(bus, pci_pme_wakeup, (void *)true); 1697 } 1698 1699 1700 /** 1701 * pci_pme_capable - check the capability of PCI device to generate PME# 1702 * @dev: PCI device to handle. 1703 * @state: PCI state from which device will issue PME#. 1704 */ 1705 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state) 1706 { 1707 if (!dev->pm_cap) 1708 return false; 1709 1710 return !!(dev->pme_support & (1 << state)); 1711 } 1712 EXPORT_SYMBOL(pci_pme_capable); 1713 1714 static void pci_pme_list_scan(struct work_struct *work) 1715 { 1716 struct pci_pme_device *pme_dev, *n; 1717 1718 mutex_lock(&pci_pme_list_mutex); 1719 list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) { 1720 if (pme_dev->dev->pme_poll) { 1721 struct pci_dev *bridge; 1722 1723 bridge = pme_dev->dev->bus->self; 1724 /* 1725 * If bridge is in low power state, the 1726 * configuration space of subordinate devices 1727 * may be not accessible 1728 */ 1729 if (bridge && bridge->current_state != PCI_D0) 1730 continue; 1731 pci_pme_wakeup(pme_dev->dev, NULL); 1732 } else { 1733 list_del(&pme_dev->list); 1734 kfree(pme_dev); 1735 } 1736 } 1737 if (!list_empty(&pci_pme_list)) 1738 schedule_delayed_work(&pci_pme_work, 1739 msecs_to_jiffies(PME_TIMEOUT)); 1740 mutex_unlock(&pci_pme_list_mutex); 1741 } 1742 1743 static void __pci_pme_active(struct pci_dev *dev, bool enable) 1744 { 1745 u16 pmcsr; 1746 1747 if (!dev->pme_support) 1748 return; 1749 1750 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); 1751 /* Clear PME_Status by writing 1 to it and enable PME# */ 1752 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE; 1753 if (!enable) 1754 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE; 1755 1756 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); 1757 } 1758 1759 /** 1760 * pci_pme_active - enable or disable PCI device's PME# function 1761 * @dev: PCI device to handle. 1762 * @enable: 'true' to enable PME# generation; 'false' to disable it. 1763 * 1764 * The caller must verify that the device is capable of generating PME# before 1765 * calling this function with @enable equal to 'true'. 1766 */ 1767 void pci_pme_active(struct pci_dev *dev, bool enable) 1768 { 1769 __pci_pme_active(dev, enable); 1770 1771 /* 1772 * PCI (as opposed to PCIe) PME requires that the device have 1773 * its PME# line hooked up correctly. Not all hardware vendors 1774 * do this, so the PME never gets delivered and the device 1775 * remains asleep. The easiest way around this is to 1776 * periodically walk the list of suspended devices and check 1777 * whether any have their PME flag set. The assumption is that 1778 * we'll wake up often enough anyway that this won't be a huge 1779 * hit, and the power savings from the devices will still be a 1780 * win. 1781 * 1782 * Although PCIe uses in-band PME message instead of PME# line 1783 * to report PME, PME does not work for some PCIe devices in 1784 * reality. For example, there are devices that set their PME 1785 * status bits, but don't really bother to send a PME message; 1786 * there are PCI Express Root Ports that don't bother to 1787 * trigger interrupts when they receive PME messages from the 1788 * devices below. So PME poll is used for PCIe devices too. 1789 */ 1790 1791 if (dev->pme_poll) { 1792 struct pci_pme_device *pme_dev; 1793 if (enable) { 1794 pme_dev = kmalloc(sizeof(struct pci_pme_device), 1795 GFP_KERNEL); 1796 if (!pme_dev) { 1797 dev_warn(&dev->dev, "can't enable PME#\n"); 1798 return; 1799 } 1800 pme_dev->dev = dev; 1801 mutex_lock(&pci_pme_list_mutex); 1802 list_add(&pme_dev->list, &pci_pme_list); 1803 if (list_is_singular(&pci_pme_list)) 1804 schedule_delayed_work(&pci_pme_work, 1805 msecs_to_jiffies(PME_TIMEOUT)); 1806 mutex_unlock(&pci_pme_list_mutex); 1807 } else { 1808 mutex_lock(&pci_pme_list_mutex); 1809 list_for_each_entry(pme_dev, &pci_pme_list, list) { 1810 if (pme_dev->dev == dev) { 1811 list_del(&pme_dev->list); 1812 kfree(pme_dev); 1813 break; 1814 } 1815 } 1816 mutex_unlock(&pci_pme_list_mutex); 1817 } 1818 } 1819 1820 dev_dbg(&dev->dev, "PME# %s\n", enable ? "enabled" : "disabled"); 1821 } 1822 EXPORT_SYMBOL(pci_pme_active); 1823 1824 /** 1825 * __pci_enable_wake - enable PCI device as wakeup event source 1826 * @dev: PCI device affected 1827 * @state: PCI state from which device will issue wakeup events 1828 * @runtime: True if the events are to be generated at run time 1829 * @enable: True to enable event generation; false to disable 1830 * 1831 * This enables the device as a wakeup event source, or disables it. 1832 * When such events involves platform-specific hooks, those hooks are 1833 * called automatically by this routine. 1834 * 1835 * Devices with legacy power management (no standard PCI PM capabilities) 1836 * always require such platform hooks. 1837 * 1838 * RETURN VALUE: 1839 * 0 is returned on success 1840 * -EINVAL is returned if device is not supposed to wake up the system 1841 * Error code depending on the platform is returned if both the platform and 1842 * the native mechanism fail to enable the generation of wake-up events 1843 */ 1844 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, 1845 bool runtime, bool enable) 1846 { 1847 int ret = 0; 1848 1849 if (enable && !runtime && !device_may_wakeup(&dev->dev)) 1850 return -EINVAL; 1851 1852 /* Don't do the same thing twice in a row for one device. */ 1853 if (!!enable == !!dev->wakeup_prepared) 1854 return 0; 1855 1856 /* 1857 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don 1858 * Anderson we should be doing PME# wake enable followed by ACPI wake 1859 * enable. To disable wake-up we call the platform first, for symmetry. 1860 */ 1861 1862 if (enable) { 1863 int error; 1864 1865 if (pci_pme_capable(dev, state)) 1866 pci_pme_active(dev, true); 1867 else 1868 ret = 1; 1869 error = runtime ? platform_pci_run_wake(dev, true) : 1870 platform_pci_sleep_wake(dev, true); 1871 if (ret) 1872 ret = error; 1873 if (!ret) 1874 dev->wakeup_prepared = true; 1875 } else { 1876 if (runtime) 1877 platform_pci_run_wake(dev, false); 1878 else 1879 platform_pci_sleep_wake(dev, false); 1880 pci_pme_active(dev, false); 1881 dev->wakeup_prepared = false; 1882 } 1883 1884 return ret; 1885 } 1886 EXPORT_SYMBOL(__pci_enable_wake); 1887 1888 /** 1889 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold 1890 * @dev: PCI device to prepare 1891 * @enable: True to enable wake-up event generation; false to disable 1892 * 1893 * Many drivers want the device to wake up the system from D3_hot or D3_cold 1894 * and this function allows them to set that up cleanly - pci_enable_wake() 1895 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI 1896 * ordering constraints. 1897 * 1898 * This function only returns error code if the device is not capable of 1899 * generating PME# from both D3_hot and D3_cold, and the platform is unable to 1900 * enable wake-up power for it. 1901 */ 1902 int pci_wake_from_d3(struct pci_dev *dev, bool enable) 1903 { 1904 return pci_pme_capable(dev, PCI_D3cold) ? 1905 pci_enable_wake(dev, PCI_D3cold, enable) : 1906 pci_enable_wake(dev, PCI_D3hot, enable); 1907 } 1908 EXPORT_SYMBOL(pci_wake_from_d3); 1909 1910 /** 1911 * pci_target_state - find an appropriate low power state for a given PCI dev 1912 * @dev: PCI device 1913 * 1914 * Use underlying platform code to find a supported low power state for @dev. 1915 * If the platform can't manage @dev, return the deepest state from which it 1916 * can generate wake events, based on any available PME info. 1917 */ 1918 static pci_power_t pci_target_state(struct pci_dev *dev) 1919 { 1920 pci_power_t target_state = PCI_D3hot; 1921 1922 if (platform_pci_power_manageable(dev)) { 1923 /* 1924 * Call the platform to choose the target state of the device 1925 * and enable wake-up from this state if supported. 1926 */ 1927 pci_power_t state = platform_pci_choose_state(dev); 1928 1929 switch (state) { 1930 case PCI_POWER_ERROR: 1931 case PCI_UNKNOWN: 1932 break; 1933 case PCI_D1: 1934 case PCI_D2: 1935 if (pci_no_d1d2(dev)) 1936 break; 1937 default: 1938 target_state = state; 1939 } 1940 } else if (!dev->pm_cap) { 1941 target_state = PCI_D0; 1942 } else if (device_may_wakeup(&dev->dev)) { 1943 /* 1944 * Find the deepest state from which the device can generate 1945 * wake-up events, make it the target state and enable device 1946 * to generate PME#. 1947 */ 1948 if (dev->pme_support) { 1949 while (target_state 1950 && !(dev->pme_support & (1 << target_state))) 1951 target_state--; 1952 } 1953 } 1954 1955 return target_state; 1956 } 1957 1958 /** 1959 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state 1960 * @dev: Device to handle. 1961 * 1962 * Choose the power state appropriate for the device depending on whether 1963 * it can wake up the system and/or is power manageable by the platform 1964 * (PCI_D3hot is the default) and put the device into that state. 1965 */ 1966 int pci_prepare_to_sleep(struct pci_dev *dev) 1967 { 1968 pci_power_t target_state = pci_target_state(dev); 1969 int error; 1970 1971 if (target_state == PCI_POWER_ERROR) 1972 return -EIO; 1973 1974 pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev)); 1975 1976 error = pci_set_power_state(dev, target_state); 1977 1978 if (error) 1979 pci_enable_wake(dev, target_state, false); 1980 1981 return error; 1982 } 1983 EXPORT_SYMBOL(pci_prepare_to_sleep); 1984 1985 /** 1986 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state 1987 * @dev: Device to handle. 1988 * 1989 * Disable device's system wake-up capability and put it into D0. 1990 */ 1991 int pci_back_from_sleep(struct pci_dev *dev) 1992 { 1993 pci_enable_wake(dev, PCI_D0, false); 1994 return pci_set_power_state(dev, PCI_D0); 1995 } 1996 EXPORT_SYMBOL(pci_back_from_sleep); 1997 1998 /** 1999 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend. 2000 * @dev: PCI device being suspended. 2001 * 2002 * Prepare @dev to generate wake-up events at run time and put it into a low 2003 * power state. 2004 */ 2005 int pci_finish_runtime_suspend(struct pci_dev *dev) 2006 { 2007 pci_power_t target_state = pci_target_state(dev); 2008 int error; 2009 2010 if (target_state == PCI_POWER_ERROR) 2011 return -EIO; 2012 2013 dev->runtime_d3cold = target_state == PCI_D3cold; 2014 2015 __pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev)); 2016 2017 error = pci_set_power_state(dev, target_state); 2018 2019 if (error) { 2020 __pci_enable_wake(dev, target_state, true, false); 2021 dev->runtime_d3cold = false; 2022 } 2023 2024 return error; 2025 } 2026 2027 /** 2028 * pci_dev_run_wake - Check if device can generate run-time wake-up events. 2029 * @dev: Device to check. 2030 * 2031 * Return true if the device itself is capable of generating wake-up events 2032 * (through the platform or using the native PCIe PME) or if the device supports 2033 * PME and one of its upstream bridges can generate wake-up events. 2034 */ 2035 bool pci_dev_run_wake(struct pci_dev *dev) 2036 { 2037 struct pci_bus *bus = dev->bus; 2038 2039 if (device_run_wake(&dev->dev)) 2040 return true; 2041 2042 if (!dev->pme_support) 2043 return false; 2044 2045 while (bus->parent) { 2046 struct pci_dev *bridge = bus->self; 2047 2048 if (device_run_wake(&bridge->dev)) 2049 return true; 2050 2051 bus = bus->parent; 2052 } 2053 2054 /* We have reached the root bus. */ 2055 if (bus->bridge) 2056 return device_run_wake(bus->bridge); 2057 2058 return false; 2059 } 2060 EXPORT_SYMBOL_GPL(pci_dev_run_wake); 2061 2062 /** 2063 * pci_dev_keep_suspended - Check if the device can stay in the suspended state. 2064 * @pci_dev: Device to check. 2065 * 2066 * Return 'true' if the device is runtime-suspended, it doesn't have to be 2067 * reconfigured due to wakeup settings difference between system and runtime 2068 * suspend and the current power state of it is suitable for the upcoming 2069 * (system) transition. 2070 * 2071 * If the device is not configured for system wakeup, disable PME for it before 2072 * returning 'true' to prevent it from waking up the system unnecessarily. 2073 */ 2074 bool pci_dev_keep_suspended(struct pci_dev *pci_dev) 2075 { 2076 struct device *dev = &pci_dev->dev; 2077 2078 if (!pm_runtime_suspended(dev) 2079 || pci_target_state(pci_dev) != pci_dev->current_state 2080 || platform_pci_need_resume(pci_dev)) 2081 return false; 2082 2083 /* 2084 * At this point the device is good to go unless it's been configured 2085 * to generate PME at the runtime suspend time, but it is not supposed 2086 * to wake up the system. In that case, simply disable PME for it 2087 * (it will have to be re-enabled on exit from system resume). 2088 * 2089 * If the device's power state is D3cold and the platform check above 2090 * hasn't triggered, the device's configuration is suitable and we don't 2091 * need to manipulate it at all. 2092 */ 2093 spin_lock_irq(&dev->power.lock); 2094 2095 if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold && 2096 !device_may_wakeup(dev)) 2097 __pci_pme_active(pci_dev, false); 2098 2099 spin_unlock_irq(&dev->power.lock); 2100 return true; 2101 } 2102 2103 /** 2104 * pci_dev_complete_resume - Finalize resume from system sleep for a device. 2105 * @pci_dev: Device to handle. 2106 * 2107 * If the device is runtime suspended and wakeup-capable, enable PME for it as 2108 * it might have been disabled during the prepare phase of system suspend if 2109 * the device was not configured for system wakeup. 2110 */ 2111 void pci_dev_complete_resume(struct pci_dev *pci_dev) 2112 { 2113 struct device *dev = &pci_dev->dev; 2114 2115 if (!pci_dev_run_wake(pci_dev)) 2116 return; 2117 2118 spin_lock_irq(&dev->power.lock); 2119 2120 if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold) 2121 __pci_pme_active(pci_dev, true); 2122 2123 spin_unlock_irq(&dev->power.lock); 2124 } 2125 2126 void pci_config_pm_runtime_get(struct pci_dev *pdev) 2127 { 2128 struct device *dev = &pdev->dev; 2129 struct device *parent = dev->parent; 2130 2131 if (parent) 2132 pm_runtime_get_sync(parent); 2133 pm_runtime_get_noresume(dev); 2134 /* 2135 * pdev->current_state is set to PCI_D3cold during suspending, 2136 * so wait until suspending completes 2137 */ 2138 pm_runtime_barrier(dev); 2139 /* 2140 * Only need to resume devices in D3cold, because config 2141 * registers are still accessible for devices suspended but 2142 * not in D3cold. 2143 */ 2144 if (pdev->current_state == PCI_D3cold) 2145 pm_runtime_resume(dev); 2146 } 2147 2148 void pci_config_pm_runtime_put(struct pci_dev *pdev) 2149 { 2150 struct device *dev = &pdev->dev; 2151 struct device *parent = dev->parent; 2152 2153 pm_runtime_put(dev); 2154 if (parent) 2155 pm_runtime_put_sync(parent); 2156 } 2157 2158 /** 2159 * pci_pm_init - Initialize PM functions of given PCI device 2160 * @dev: PCI device to handle. 2161 */ 2162 void pci_pm_init(struct pci_dev *dev) 2163 { 2164 int pm; 2165 u16 pmc; 2166 2167 pm_runtime_forbid(&dev->dev); 2168 pm_runtime_set_active(&dev->dev); 2169 pm_runtime_enable(&dev->dev); 2170 device_enable_async_suspend(&dev->dev); 2171 dev->wakeup_prepared = false; 2172 2173 dev->pm_cap = 0; 2174 dev->pme_support = 0; 2175 2176 /* find PCI PM capability in list */ 2177 pm = pci_find_capability(dev, PCI_CAP_ID_PM); 2178 if (!pm) 2179 return; 2180 /* Check device's ability to generate PME# */ 2181 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc); 2182 2183 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) { 2184 dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n", 2185 pmc & PCI_PM_CAP_VER_MASK); 2186 return; 2187 } 2188 2189 dev->pm_cap = pm; 2190 dev->d3_delay = PCI_PM_D3_WAIT; 2191 dev->d3cold_delay = PCI_PM_D3COLD_WAIT; 2192 dev->d3cold_allowed = true; 2193 2194 dev->d1_support = false; 2195 dev->d2_support = false; 2196 if (!pci_no_d1d2(dev)) { 2197 if (pmc & PCI_PM_CAP_D1) 2198 dev->d1_support = true; 2199 if (pmc & PCI_PM_CAP_D2) 2200 dev->d2_support = true; 2201 2202 if (dev->d1_support || dev->d2_support) 2203 dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n", 2204 dev->d1_support ? " D1" : "", 2205 dev->d2_support ? " D2" : ""); 2206 } 2207 2208 pmc &= PCI_PM_CAP_PME_MASK; 2209 if (pmc) { 2210 dev_printk(KERN_DEBUG, &dev->dev, 2211 "PME# supported from%s%s%s%s%s\n", 2212 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "", 2213 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "", 2214 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "", 2215 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "", 2216 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : ""); 2217 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT; 2218 dev->pme_poll = true; 2219 /* 2220 * Make device's PM flags reflect the wake-up capability, but 2221 * let the user space enable it to wake up the system as needed. 2222 */ 2223 device_set_wakeup_capable(&dev->dev, true); 2224 /* Disable the PME# generation functionality */ 2225 pci_pme_active(dev, false); 2226 } 2227 } 2228 2229 static unsigned long pci_ea_flags(struct pci_dev *dev, u8 prop) 2230 { 2231 unsigned long flags = IORESOURCE_PCI_FIXED | IORESOURCE_PCI_EA_BEI; 2232 2233 switch (prop) { 2234 case PCI_EA_P_MEM: 2235 case PCI_EA_P_VF_MEM: 2236 flags |= IORESOURCE_MEM; 2237 break; 2238 case PCI_EA_P_MEM_PREFETCH: 2239 case PCI_EA_P_VF_MEM_PREFETCH: 2240 flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH; 2241 break; 2242 case PCI_EA_P_IO: 2243 flags |= IORESOURCE_IO; 2244 break; 2245 default: 2246 return 0; 2247 } 2248 2249 return flags; 2250 } 2251 2252 static struct resource *pci_ea_get_resource(struct pci_dev *dev, u8 bei, 2253 u8 prop) 2254 { 2255 if (bei <= PCI_EA_BEI_BAR5 && prop <= PCI_EA_P_IO) 2256 return &dev->resource[bei]; 2257 #ifdef CONFIG_PCI_IOV 2258 else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5 && 2259 (prop == PCI_EA_P_VF_MEM || prop == PCI_EA_P_VF_MEM_PREFETCH)) 2260 return &dev->resource[PCI_IOV_RESOURCES + 2261 bei - PCI_EA_BEI_VF_BAR0]; 2262 #endif 2263 else if (bei == PCI_EA_BEI_ROM) 2264 return &dev->resource[PCI_ROM_RESOURCE]; 2265 else 2266 return NULL; 2267 } 2268 2269 /* Read an Enhanced Allocation (EA) entry */ 2270 static int pci_ea_read(struct pci_dev *dev, int offset) 2271 { 2272 struct resource *res; 2273 int ent_size, ent_offset = offset; 2274 resource_size_t start, end; 2275 unsigned long flags; 2276 u32 dw0, bei, base, max_offset; 2277 u8 prop; 2278 bool support_64 = (sizeof(resource_size_t) >= 8); 2279 2280 pci_read_config_dword(dev, ent_offset, &dw0); 2281 ent_offset += 4; 2282 2283 /* Entry size field indicates DWORDs after 1st */ 2284 ent_size = ((dw0 & PCI_EA_ES) + 1) << 2; 2285 2286 if (!(dw0 & PCI_EA_ENABLE)) /* Entry not enabled */ 2287 goto out; 2288 2289 bei = (dw0 & PCI_EA_BEI) >> 4; 2290 prop = (dw0 & PCI_EA_PP) >> 8; 2291 2292 /* 2293 * If the Property is in the reserved range, try the Secondary 2294 * Property instead. 2295 */ 2296 if (prop > PCI_EA_P_BRIDGE_IO && prop < PCI_EA_P_MEM_RESERVED) 2297 prop = (dw0 & PCI_EA_SP) >> 16; 2298 if (prop > PCI_EA_P_BRIDGE_IO) 2299 goto out; 2300 2301 res = pci_ea_get_resource(dev, bei, prop); 2302 if (!res) { 2303 dev_err(&dev->dev, "Unsupported EA entry BEI: %u\n", bei); 2304 goto out; 2305 } 2306 2307 flags = pci_ea_flags(dev, prop); 2308 if (!flags) { 2309 dev_err(&dev->dev, "Unsupported EA properties: %#x\n", prop); 2310 goto out; 2311 } 2312 2313 /* Read Base */ 2314 pci_read_config_dword(dev, ent_offset, &base); 2315 start = (base & PCI_EA_FIELD_MASK); 2316 ent_offset += 4; 2317 2318 /* Read MaxOffset */ 2319 pci_read_config_dword(dev, ent_offset, &max_offset); 2320 ent_offset += 4; 2321 2322 /* Read Base MSBs (if 64-bit entry) */ 2323 if (base & PCI_EA_IS_64) { 2324 u32 base_upper; 2325 2326 pci_read_config_dword(dev, ent_offset, &base_upper); 2327 ent_offset += 4; 2328 2329 flags |= IORESOURCE_MEM_64; 2330 2331 /* entry starts above 32-bit boundary, can't use */ 2332 if (!support_64 && base_upper) 2333 goto out; 2334 2335 if (support_64) 2336 start |= ((u64)base_upper << 32); 2337 } 2338 2339 end = start + (max_offset | 0x03); 2340 2341 /* Read MaxOffset MSBs (if 64-bit entry) */ 2342 if (max_offset & PCI_EA_IS_64) { 2343 u32 max_offset_upper; 2344 2345 pci_read_config_dword(dev, ent_offset, &max_offset_upper); 2346 ent_offset += 4; 2347 2348 flags |= IORESOURCE_MEM_64; 2349 2350 /* entry too big, can't use */ 2351 if (!support_64 && max_offset_upper) 2352 goto out; 2353 2354 if (support_64) 2355 end += ((u64)max_offset_upper << 32); 2356 } 2357 2358 if (end < start) { 2359 dev_err(&dev->dev, "EA Entry crosses address boundary\n"); 2360 goto out; 2361 } 2362 2363 if (ent_size != ent_offset - offset) { 2364 dev_err(&dev->dev, 2365 "EA Entry Size (%d) does not match length read (%d)\n", 2366 ent_size, ent_offset - offset); 2367 goto out; 2368 } 2369 2370 res->name = pci_name(dev); 2371 res->start = start; 2372 res->end = end; 2373 res->flags = flags; 2374 2375 if (bei <= PCI_EA_BEI_BAR5) 2376 dev_printk(KERN_DEBUG, &dev->dev, "BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n", 2377 bei, res, prop); 2378 else if (bei == PCI_EA_BEI_ROM) 2379 dev_printk(KERN_DEBUG, &dev->dev, "ROM: %pR (from Enhanced Allocation, properties %#02x)\n", 2380 res, prop); 2381 else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5) 2382 dev_printk(KERN_DEBUG, &dev->dev, "VF BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n", 2383 bei - PCI_EA_BEI_VF_BAR0, res, prop); 2384 else 2385 dev_printk(KERN_DEBUG, &dev->dev, "BEI %d res: %pR (from Enhanced Allocation, properties %#02x)\n", 2386 bei, res, prop); 2387 2388 out: 2389 return offset + ent_size; 2390 } 2391 2392 /* Enhanced Allocation Initialization */ 2393 void pci_ea_init(struct pci_dev *dev) 2394 { 2395 int ea; 2396 u8 num_ent; 2397 int offset; 2398 int i; 2399 2400 /* find PCI EA capability in list */ 2401 ea = pci_find_capability(dev, PCI_CAP_ID_EA); 2402 if (!ea) 2403 return; 2404 2405 /* determine the number of entries */ 2406 pci_bus_read_config_byte(dev->bus, dev->devfn, ea + PCI_EA_NUM_ENT, 2407 &num_ent); 2408 num_ent &= PCI_EA_NUM_ENT_MASK; 2409 2410 offset = ea + PCI_EA_FIRST_ENT; 2411 2412 /* Skip DWORD 2 for type 1 functions */ 2413 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) 2414 offset += 4; 2415 2416 /* parse each EA entry */ 2417 for (i = 0; i < num_ent; ++i) 2418 offset = pci_ea_read(dev, offset); 2419 } 2420 2421 static void pci_add_saved_cap(struct pci_dev *pci_dev, 2422 struct pci_cap_saved_state *new_cap) 2423 { 2424 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space); 2425 } 2426 2427 /** 2428 * _pci_add_cap_save_buffer - allocate buffer for saving given 2429 * capability registers 2430 * @dev: the PCI device 2431 * @cap: the capability to allocate the buffer for 2432 * @extended: Standard or Extended capability ID 2433 * @size: requested size of the buffer 2434 */ 2435 static int _pci_add_cap_save_buffer(struct pci_dev *dev, u16 cap, 2436 bool extended, unsigned int size) 2437 { 2438 int pos; 2439 struct pci_cap_saved_state *save_state; 2440 2441 if (extended) 2442 pos = pci_find_ext_capability(dev, cap); 2443 else 2444 pos = pci_find_capability(dev, cap); 2445 2446 if (!pos) 2447 return 0; 2448 2449 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL); 2450 if (!save_state) 2451 return -ENOMEM; 2452 2453 save_state->cap.cap_nr = cap; 2454 save_state->cap.cap_extended = extended; 2455 save_state->cap.size = size; 2456 pci_add_saved_cap(dev, save_state); 2457 2458 return 0; 2459 } 2460 2461 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size) 2462 { 2463 return _pci_add_cap_save_buffer(dev, cap, false, size); 2464 } 2465 2466 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, u16 cap, unsigned int size) 2467 { 2468 return _pci_add_cap_save_buffer(dev, cap, true, size); 2469 } 2470 2471 /** 2472 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities 2473 * @dev: the PCI device 2474 */ 2475 void pci_allocate_cap_save_buffers(struct pci_dev *dev) 2476 { 2477 int error; 2478 2479 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP, 2480 PCI_EXP_SAVE_REGS * sizeof(u16)); 2481 if (error) 2482 dev_err(&dev->dev, 2483 "unable to preallocate PCI Express save buffer\n"); 2484 2485 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16)); 2486 if (error) 2487 dev_err(&dev->dev, 2488 "unable to preallocate PCI-X save buffer\n"); 2489 2490 pci_allocate_vc_save_buffers(dev); 2491 } 2492 2493 void pci_free_cap_save_buffers(struct pci_dev *dev) 2494 { 2495 struct pci_cap_saved_state *tmp; 2496 struct hlist_node *n; 2497 2498 hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next) 2499 kfree(tmp); 2500 } 2501 2502 /** 2503 * pci_configure_ari - enable or disable ARI forwarding 2504 * @dev: the PCI device 2505 * 2506 * If @dev and its upstream bridge both support ARI, enable ARI in the 2507 * bridge. Otherwise, disable ARI in the bridge. 2508 */ 2509 void pci_configure_ari(struct pci_dev *dev) 2510 { 2511 u32 cap; 2512 struct pci_dev *bridge; 2513 2514 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn) 2515 return; 2516 2517 bridge = dev->bus->self; 2518 if (!bridge) 2519 return; 2520 2521 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap); 2522 if (!(cap & PCI_EXP_DEVCAP2_ARI)) 2523 return; 2524 2525 if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) { 2526 pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2, 2527 PCI_EXP_DEVCTL2_ARI); 2528 bridge->ari_enabled = 1; 2529 } else { 2530 pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2, 2531 PCI_EXP_DEVCTL2_ARI); 2532 bridge->ari_enabled = 0; 2533 } 2534 } 2535 2536 static int pci_acs_enable; 2537 2538 /** 2539 * pci_request_acs - ask for ACS to be enabled if supported 2540 */ 2541 void pci_request_acs(void) 2542 { 2543 pci_acs_enable = 1; 2544 } 2545 2546 /** 2547 * pci_std_enable_acs - enable ACS on devices using standard ACS capabilites 2548 * @dev: the PCI device 2549 */ 2550 static void pci_std_enable_acs(struct pci_dev *dev) 2551 { 2552 int pos; 2553 u16 cap; 2554 u16 ctrl; 2555 2556 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS); 2557 if (!pos) 2558 return; 2559 2560 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap); 2561 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl); 2562 2563 /* Source Validation */ 2564 ctrl |= (cap & PCI_ACS_SV); 2565 2566 /* P2P Request Redirect */ 2567 ctrl |= (cap & PCI_ACS_RR); 2568 2569 /* P2P Completion Redirect */ 2570 ctrl |= (cap & PCI_ACS_CR); 2571 2572 /* Upstream Forwarding */ 2573 ctrl |= (cap & PCI_ACS_UF); 2574 2575 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl); 2576 } 2577 2578 /** 2579 * pci_enable_acs - enable ACS if hardware support it 2580 * @dev: the PCI device 2581 */ 2582 void pci_enable_acs(struct pci_dev *dev) 2583 { 2584 if (!pci_acs_enable) 2585 return; 2586 2587 if (!pci_dev_specific_enable_acs(dev)) 2588 return; 2589 2590 pci_std_enable_acs(dev); 2591 } 2592 2593 static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags) 2594 { 2595 int pos; 2596 u16 cap, ctrl; 2597 2598 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ACS); 2599 if (!pos) 2600 return false; 2601 2602 /* 2603 * Except for egress control, capabilities are either required 2604 * or only required if controllable. Features missing from the 2605 * capability field can therefore be assumed as hard-wired enabled. 2606 */ 2607 pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap); 2608 acs_flags &= (cap | PCI_ACS_EC); 2609 2610 pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl); 2611 return (ctrl & acs_flags) == acs_flags; 2612 } 2613 2614 /** 2615 * pci_acs_enabled - test ACS against required flags for a given device 2616 * @pdev: device to test 2617 * @acs_flags: required PCI ACS flags 2618 * 2619 * Return true if the device supports the provided flags. Automatically 2620 * filters out flags that are not implemented on multifunction devices. 2621 * 2622 * Note that this interface checks the effective ACS capabilities of the 2623 * device rather than the actual capabilities. For instance, most single 2624 * function endpoints are not required to support ACS because they have no 2625 * opportunity for peer-to-peer access. We therefore return 'true' 2626 * regardless of whether the device exposes an ACS capability. This makes 2627 * it much easier for callers of this function to ignore the actual type 2628 * or topology of the device when testing ACS support. 2629 */ 2630 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags) 2631 { 2632 int ret; 2633 2634 ret = pci_dev_specific_acs_enabled(pdev, acs_flags); 2635 if (ret >= 0) 2636 return ret > 0; 2637 2638 /* 2639 * Conventional PCI and PCI-X devices never support ACS, either 2640 * effectively or actually. The shared bus topology implies that 2641 * any device on the bus can receive or snoop DMA. 2642 */ 2643 if (!pci_is_pcie(pdev)) 2644 return false; 2645 2646 switch (pci_pcie_type(pdev)) { 2647 /* 2648 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec, 2649 * but since their primary interface is PCI/X, we conservatively 2650 * handle them as we would a non-PCIe device. 2651 */ 2652 case PCI_EXP_TYPE_PCIE_BRIDGE: 2653 /* 2654 * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never 2655 * applicable... must never implement an ACS Extended Capability...". 2656 * This seems arbitrary, but we take a conservative interpretation 2657 * of this statement. 2658 */ 2659 case PCI_EXP_TYPE_PCI_BRIDGE: 2660 case PCI_EXP_TYPE_RC_EC: 2661 return false; 2662 /* 2663 * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should 2664 * implement ACS in order to indicate their peer-to-peer capabilities, 2665 * regardless of whether they are single- or multi-function devices. 2666 */ 2667 case PCI_EXP_TYPE_DOWNSTREAM: 2668 case PCI_EXP_TYPE_ROOT_PORT: 2669 return pci_acs_flags_enabled(pdev, acs_flags); 2670 /* 2671 * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be 2672 * implemented by the remaining PCIe types to indicate peer-to-peer 2673 * capabilities, but only when they are part of a multifunction 2674 * device. The footnote for section 6.12 indicates the specific 2675 * PCIe types included here. 2676 */ 2677 case PCI_EXP_TYPE_ENDPOINT: 2678 case PCI_EXP_TYPE_UPSTREAM: 2679 case PCI_EXP_TYPE_LEG_END: 2680 case PCI_EXP_TYPE_RC_END: 2681 if (!pdev->multifunction) 2682 break; 2683 2684 return pci_acs_flags_enabled(pdev, acs_flags); 2685 } 2686 2687 /* 2688 * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable 2689 * to single function devices with the exception of downstream ports. 2690 */ 2691 return true; 2692 } 2693 2694 /** 2695 * pci_acs_path_enable - test ACS flags from start to end in a hierarchy 2696 * @start: starting downstream device 2697 * @end: ending upstream device or NULL to search to the root bus 2698 * @acs_flags: required flags 2699 * 2700 * Walk up a device tree from start to end testing PCI ACS support. If 2701 * any step along the way does not support the required flags, return false. 2702 */ 2703 bool pci_acs_path_enabled(struct pci_dev *start, 2704 struct pci_dev *end, u16 acs_flags) 2705 { 2706 struct pci_dev *pdev, *parent = start; 2707 2708 do { 2709 pdev = parent; 2710 2711 if (!pci_acs_enabled(pdev, acs_flags)) 2712 return false; 2713 2714 if (pci_is_root_bus(pdev->bus)) 2715 return (end == NULL); 2716 2717 parent = pdev->bus->self; 2718 } while (pdev != end); 2719 2720 return true; 2721 } 2722 2723 /** 2724 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge 2725 * @dev: the PCI device 2726 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD) 2727 * 2728 * Perform INTx swizzling for a device behind one level of bridge. This is 2729 * required by section 9.1 of the PCI-to-PCI bridge specification for devices 2730 * behind bridges on add-in cards. For devices with ARI enabled, the slot 2731 * number is always 0 (see the Implementation Note in section 2.2.8.1 of 2732 * the PCI Express Base Specification, Revision 2.1) 2733 */ 2734 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin) 2735 { 2736 int slot; 2737 2738 if (pci_ari_enabled(dev->bus)) 2739 slot = 0; 2740 else 2741 slot = PCI_SLOT(dev->devfn); 2742 2743 return (((pin - 1) + slot) % 4) + 1; 2744 } 2745 2746 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge) 2747 { 2748 u8 pin; 2749 2750 pin = dev->pin; 2751 if (!pin) 2752 return -1; 2753 2754 while (!pci_is_root_bus(dev->bus)) { 2755 pin = pci_swizzle_interrupt_pin(dev, pin); 2756 dev = dev->bus->self; 2757 } 2758 *bridge = dev; 2759 return pin; 2760 } 2761 2762 /** 2763 * pci_common_swizzle - swizzle INTx all the way to root bridge 2764 * @dev: the PCI device 2765 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD) 2766 * 2767 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI 2768 * bridges all the way up to a PCI root bus. 2769 */ 2770 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp) 2771 { 2772 u8 pin = *pinp; 2773 2774 while (!pci_is_root_bus(dev->bus)) { 2775 pin = pci_swizzle_interrupt_pin(dev, pin); 2776 dev = dev->bus->self; 2777 } 2778 *pinp = pin; 2779 return PCI_SLOT(dev->devfn); 2780 } 2781 EXPORT_SYMBOL_GPL(pci_common_swizzle); 2782 2783 /** 2784 * pci_release_region - Release a PCI bar 2785 * @pdev: PCI device whose resources were previously reserved by pci_request_region 2786 * @bar: BAR to release 2787 * 2788 * Releases the PCI I/O and memory resources previously reserved by a 2789 * successful call to pci_request_region. Call this function only 2790 * after all use of the PCI regions has ceased. 2791 */ 2792 void pci_release_region(struct pci_dev *pdev, int bar) 2793 { 2794 struct pci_devres *dr; 2795 2796 if (pci_resource_len(pdev, bar) == 0) 2797 return; 2798 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) 2799 release_region(pci_resource_start(pdev, bar), 2800 pci_resource_len(pdev, bar)); 2801 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) 2802 release_mem_region(pci_resource_start(pdev, bar), 2803 pci_resource_len(pdev, bar)); 2804 2805 dr = find_pci_dr(pdev); 2806 if (dr) 2807 dr->region_mask &= ~(1 << bar); 2808 } 2809 EXPORT_SYMBOL(pci_release_region); 2810 2811 /** 2812 * __pci_request_region - Reserved PCI I/O and memory resource 2813 * @pdev: PCI device whose resources are to be reserved 2814 * @bar: BAR to be reserved 2815 * @res_name: Name to be associated with resource. 2816 * @exclusive: whether the region access is exclusive or not 2817 * 2818 * Mark the PCI region associated with PCI device @pdev BR @bar as 2819 * being reserved by owner @res_name. Do not access any 2820 * address inside the PCI regions unless this call returns 2821 * successfully. 2822 * 2823 * If @exclusive is set, then the region is marked so that userspace 2824 * is explicitly not allowed to map the resource via /dev/mem or 2825 * sysfs MMIO access. 2826 * 2827 * Returns 0 on success, or %EBUSY on error. A warning 2828 * message is also printed on failure. 2829 */ 2830 static int __pci_request_region(struct pci_dev *pdev, int bar, 2831 const char *res_name, int exclusive) 2832 { 2833 struct pci_devres *dr; 2834 2835 if (pci_resource_len(pdev, bar) == 0) 2836 return 0; 2837 2838 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) { 2839 if (!request_region(pci_resource_start(pdev, bar), 2840 pci_resource_len(pdev, bar), res_name)) 2841 goto err_out; 2842 } else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) { 2843 if (!__request_mem_region(pci_resource_start(pdev, bar), 2844 pci_resource_len(pdev, bar), res_name, 2845 exclusive)) 2846 goto err_out; 2847 } 2848 2849 dr = find_pci_dr(pdev); 2850 if (dr) 2851 dr->region_mask |= 1 << bar; 2852 2853 return 0; 2854 2855 err_out: 2856 dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar, 2857 &pdev->resource[bar]); 2858 return -EBUSY; 2859 } 2860 2861 /** 2862 * pci_request_region - Reserve PCI I/O and memory resource 2863 * @pdev: PCI device whose resources are to be reserved 2864 * @bar: BAR to be reserved 2865 * @res_name: Name to be associated with resource 2866 * 2867 * Mark the PCI region associated with PCI device @pdev BAR @bar as 2868 * being reserved by owner @res_name. Do not access any 2869 * address inside the PCI regions unless this call returns 2870 * successfully. 2871 * 2872 * Returns 0 on success, or %EBUSY on error. A warning 2873 * message is also printed on failure. 2874 */ 2875 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) 2876 { 2877 return __pci_request_region(pdev, bar, res_name, 0); 2878 } 2879 EXPORT_SYMBOL(pci_request_region); 2880 2881 /** 2882 * pci_request_region_exclusive - Reserved PCI I/O and memory resource 2883 * @pdev: PCI device whose resources are to be reserved 2884 * @bar: BAR to be reserved 2885 * @res_name: Name to be associated with resource. 2886 * 2887 * Mark the PCI region associated with PCI device @pdev BR @bar as 2888 * being reserved by owner @res_name. Do not access any 2889 * address inside the PCI regions unless this call returns 2890 * successfully. 2891 * 2892 * Returns 0 on success, or %EBUSY on error. A warning 2893 * message is also printed on failure. 2894 * 2895 * The key difference that _exclusive makes it that userspace is 2896 * explicitly not allowed to map the resource via /dev/mem or 2897 * sysfs. 2898 */ 2899 int pci_request_region_exclusive(struct pci_dev *pdev, int bar, 2900 const char *res_name) 2901 { 2902 return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE); 2903 } 2904 EXPORT_SYMBOL(pci_request_region_exclusive); 2905 2906 /** 2907 * pci_release_selected_regions - Release selected PCI I/O and memory resources 2908 * @pdev: PCI device whose resources were previously reserved 2909 * @bars: Bitmask of BARs to be released 2910 * 2911 * Release selected PCI I/O and memory resources previously reserved. 2912 * Call this function only after all use of the PCI regions has ceased. 2913 */ 2914 void pci_release_selected_regions(struct pci_dev *pdev, int bars) 2915 { 2916 int i; 2917 2918 for (i = 0; i < 6; i++) 2919 if (bars & (1 << i)) 2920 pci_release_region(pdev, i); 2921 } 2922 EXPORT_SYMBOL(pci_release_selected_regions); 2923 2924 static int __pci_request_selected_regions(struct pci_dev *pdev, int bars, 2925 const char *res_name, int excl) 2926 { 2927 int i; 2928 2929 for (i = 0; i < 6; i++) 2930 if (bars & (1 << i)) 2931 if (__pci_request_region(pdev, i, res_name, excl)) 2932 goto err_out; 2933 return 0; 2934 2935 err_out: 2936 while (--i >= 0) 2937 if (bars & (1 << i)) 2938 pci_release_region(pdev, i); 2939 2940 return -EBUSY; 2941 } 2942 2943 2944 /** 2945 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources 2946 * @pdev: PCI device whose resources are to be reserved 2947 * @bars: Bitmask of BARs to be requested 2948 * @res_name: Name to be associated with resource 2949 */ 2950 int pci_request_selected_regions(struct pci_dev *pdev, int bars, 2951 const char *res_name) 2952 { 2953 return __pci_request_selected_regions(pdev, bars, res_name, 0); 2954 } 2955 EXPORT_SYMBOL(pci_request_selected_regions); 2956 2957 int pci_request_selected_regions_exclusive(struct pci_dev *pdev, int bars, 2958 const char *res_name) 2959 { 2960 return __pci_request_selected_regions(pdev, bars, res_name, 2961 IORESOURCE_EXCLUSIVE); 2962 } 2963 EXPORT_SYMBOL(pci_request_selected_regions_exclusive); 2964 2965 /** 2966 * pci_release_regions - Release reserved PCI I/O and memory resources 2967 * @pdev: PCI device whose resources were previously reserved by pci_request_regions 2968 * 2969 * Releases all PCI I/O and memory resources previously reserved by a 2970 * successful call to pci_request_regions. Call this function only 2971 * after all use of the PCI regions has ceased. 2972 */ 2973 2974 void pci_release_regions(struct pci_dev *pdev) 2975 { 2976 pci_release_selected_regions(pdev, (1 << 6) - 1); 2977 } 2978 EXPORT_SYMBOL(pci_release_regions); 2979 2980 /** 2981 * pci_request_regions - Reserved PCI I/O and memory resources 2982 * @pdev: PCI device whose resources are to be reserved 2983 * @res_name: Name to be associated with resource. 2984 * 2985 * Mark all PCI regions associated with PCI device @pdev as 2986 * being reserved by owner @res_name. Do not access any 2987 * address inside the PCI regions unless this call returns 2988 * successfully. 2989 * 2990 * Returns 0 on success, or %EBUSY on error. A warning 2991 * message is also printed on failure. 2992 */ 2993 int pci_request_regions(struct pci_dev *pdev, const char *res_name) 2994 { 2995 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name); 2996 } 2997 EXPORT_SYMBOL(pci_request_regions); 2998 2999 /** 3000 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources 3001 * @pdev: PCI device whose resources are to be reserved 3002 * @res_name: Name to be associated with resource. 3003 * 3004 * Mark all PCI regions associated with PCI device @pdev as 3005 * being reserved by owner @res_name. Do not access any 3006 * address inside the PCI regions unless this call returns 3007 * successfully. 3008 * 3009 * pci_request_regions_exclusive() will mark the region so that 3010 * /dev/mem and the sysfs MMIO access will not be allowed. 3011 * 3012 * Returns 0 on success, or %EBUSY on error. A warning 3013 * message is also printed on failure. 3014 */ 3015 int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name) 3016 { 3017 return pci_request_selected_regions_exclusive(pdev, 3018 ((1 << 6) - 1), res_name); 3019 } 3020 EXPORT_SYMBOL(pci_request_regions_exclusive); 3021 3022 #ifdef PCI_IOBASE 3023 struct io_range { 3024 struct list_head list; 3025 phys_addr_t start; 3026 resource_size_t size; 3027 }; 3028 3029 static LIST_HEAD(io_range_list); 3030 static DEFINE_SPINLOCK(io_range_lock); 3031 #endif 3032 3033 /* 3034 * Record the PCI IO range (expressed as CPU physical address + size). 3035 * Return a negative value if an error has occured, zero otherwise 3036 */ 3037 int __weak pci_register_io_range(phys_addr_t addr, resource_size_t size) 3038 { 3039 int err = 0; 3040 3041 #ifdef PCI_IOBASE 3042 struct io_range *range; 3043 resource_size_t allocated_size = 0; 3044 3045 /* check if the range hasn't been previously recorded */ 3046 spin_lock(&io_range_lock); 3047 list_for_each_entry(range, &io_range_list, list) { 3048 if (addr >= range->start && addr + size <= range->start + size) { 3049 /* range already registered, bail out */ 3050 goto end_register; 3051 } 3052 allocated_size += range->size; 3053 } 3054 3055 /* range not registed yet, check for available space */ 3056 if (allocated_size + size - 1 > IO_SPACE_LIMIT) { 3057 /* if it's too big check if 64K space can be reserved */ 3058 if (allocated_size + SZ_64K - 1 > IO_SPACE_LIMIT) { 3059 err = -E2BIG; 3060 goto end_register; 3061 } 3062 3063 size = SZ_64K; 3064 pr_warn("Requested IO range too big, new size set to 64K\n"); 3065 } 3066 3067 /* add the range to the list */ 3068 range = kzalloc(sizeof(*range), GFP_ATOMIC); 3069 if (!range) { 3070 err = -ENOMEM; 3071 goto end_register; 3072 } 3073 3074 range->start = addr; 3075 range->size = size; 3076 3077 list_add_tail(&range->list, &io_range_list); 3078 3079 end_register: 3080 spin_unlock(&io_range_lock); 3081 #endif 3082 3083 return err; 3084 } 3085 3086 phys_addr_t pci_pio_to_address(unsigned long pio) 3087 { 3088 phys_addr_t address = (phys_addr_t)OF_BAD_ADDR; 3089 3090 #ifdef PCI_IOBASE 3091 struct io_range *range; 3092 resource_size_t allocated_size = 0; 3093 3094 if (pio > IO_SPACE_LIMIT) 3095 return address; 3096 3097 spin_lock(&io_range_lock); 3098 list_for_each_entry(range, &io_range_list, list) { 3099 if (pio >= allocated_size && pio < allocated_size + range->size) { 3100 address = range->start + pio - allocated_size; 3101 break; 3102 } 3103 allocated_size += range->size; 3104 } 3105 spin_unlock(&io_range_lock); 3106 #endif 3107 3108 return address; 3109 } 3110 3111 unsigned long __weak pci_address_to_pio(phys_addr_t address) 3112 { 3113 #ifdef PCI_IOBASE 3114 struct io_range *res; 3115 resource_size_t offset = 0; 3116 unsigned long addr = -1; 3117 3118 spin_lock(&io_range_lock); 3119 list_for_each_entry(res, &io_range_list, list) { 3120 if (address >= res->start && address < res->start + res->size) { 3121 addr = address - res->start + offset; 3122 break; 3123 } 3124 offset += res->size; 3125 } 3126 spin_unlock(&io_range_lock); 3127 3128 return addr; 3129 #else 3130 if (address > IO_SPACE_LIMIT) 3131 return (unsigned long)-1; 3132 3133 return (unsigned long) address; 3134 #endif 3135 } 3136 3137 /** 3138 * pci_remap_iospace - Remap the memory mapped I/O space 3139 * @res: Resource describing the I/O space 3140 * @phys_addr: physical address of range to be mapped 3141 * 3142 * Remap the memory mapped I/O space described by the @res 3143 * and the CPU physical address @phys_addr into virtual address space. 3144 * Only architectures that have memory mapped IO functions defined 3145 * (and the PCI_IOBASE value defined) should call this function. 3146 */ 3147 int __weak pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr) 3148 { 3149 #if defined(PCI_IOBASE) && defined(CONFIG_MMU) 3150 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start; 3151 3152 if (!(res->flags & IORESOURCE_IO)) 3153 return -EINVAL; 3154 3155 if (res->end > IO_SPACE_LIMIT) 3156 return -EINVAL; 3157 3158 return ioremap_page_range(vaddr, vaddr + resource_size(res), phys_addr, 3159 pgprot_device(PAGE_KERNEL)); 3160 #else 3161 /* this architecture does not have memory mapped I/O space, 3162 so this function should never be called */ 3163 WARN_ONCE(1, "This architecture does not support memory mapped I/O\n"); 3164 return -ENODEV; 3165 #endif 3166 } 3167 3168 static void __pci_set_master(struct pci_dev *dev, bool enable) 3169 { 3170 u16 old_cmd, cmd; 3171 3172 pci_read_config_word(dev, PCI_COMMAND, &old_cmd); 3173 if (enable) 3174 cmd = old_cmd | PCI_COMMAND_MASTER; 3175 else 3176 cmd = old_cmd & ~PCI_COMMAND_MASTER; 3177 if (cmd != old_cmd) { 3178 dev_dbg(&dev->dev, "%s bus mastering\n", 3179 enable ? "enabling" : "disabling"); 3180 pci_write_config_word(dev, PCI_COMMAND, cmd); 3181 } 3182 dev->is_busmaster = enable; 3183 } 3184 3185 /** 3186 * pcibios_setup - process "pci=" kernel boot arguments 3187 * @str: string used to pass in "pci=" kernel boot arguments 3188 * 3189 * Process kernel boot arguments. This is the default implementation. 3190 * Architecture specific implementations can override this as necessary. 3191 */ 3192 char * __weak __init pcibios_setup(char *str) 3193 { 3194 return str; 3195 } 3196 3197 /** 3198 * pcibios_set_master - enable PCI bus-mastering for device dev 3199 * @dev: the PCI device to enable 3200 * 3201 * Enables PCI bus-mastering for the device. This is the default 3202 * implementation. Architecture specific implementations can override 3203 * this if necessary. 3204 */ 3205 void __weak pcibios_set_master(struct pci_dev *dev) 3206 { 3207 u8 lat; 3208 3209 /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */ 3210 if (pci_is_pcie(dev)) 3211 return; 3212 3213 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat); 3214 if (lat < 16) 3215 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency; 3216 else if (lat > pcibios_max_latency) 3217 lat = pcibios_max_latency; 3218 else 3219 return; 3220 3221 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat); 3222 } 3223 3224 /** 3225 * pci_set_master - enables bus-mastering for device dev 3226 * @dev: the PCI device to enable 3227 * 3228 * Enables bus-mastering on the device and calls pcibios_set_master() 3229 * to do the needed arch specific settings. 3230 */ 3231 void pci_set_master(struct pci_dev *dev) 3232 { 3233 __pci_set_master(dev, true); 3234 pcibios_set_master(dev); 3235 } 3236 EXPORT_SYMBOL(pci_set_master); 3237 3238 /** 3239 * pci_clear_master - disables bus-mastering for device dev 3240 * @dev: the PCI device to disable 3241 */ 3242 void pci_clear_master(struct pci_dev *dev) 3243 { 3244 __pci_set_master(dev, false); 3245 } 3246 EXPORT_SYMBOL(pci_clear_master); 3247 3248 /** 3249 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed 3250 * @dev: the PCI device for which MWI is to be enabled 3251 * 3252 * Helper function for pci_set_mwi. 3253 * Originally copied from drivers/net/acenic.c. 3254 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. 3255 * 3256 * RETURNS: An appropriate -ERRNO error value on error, or zero for success. 3257 */ 3258 int pci_set_cacheline_size(struct pci_dev *dev) 3259 { 3260 u8 cacheline_size; 3261 3262 if (!pci_cache_line_size) 3263 return -EINVAL; 3264 3265 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be 3266 equal to or multiple of the right value. */ 3267 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); 3268 if (cacheline_size >= pci_cache_line_size && 3269 (cacheline_size % pci_cache_line_size) == 0) 3270 return 0; 3271 3272 /* Write the correct value. */ 3273 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size); 3274 /* Read it back. */ 3275 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); 3276 if (cacheline_size == pci_cache_line_size) 3277 return 0; 3278 3279 dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not supported\n", 3280 pci_cache_line_size << 2); 3281 3282 return -EINVAL; 3283 } 3284 EXPORT_SYMBOL_GPL(pci_set_cacheline_size); 3285 3286 /** 3287 * pci_set_mwi - enables memory-write-invalidate PCI transaction 3288 * @dev: the PCI device for which MWI is enabled 3289 * 3290 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. 3291 * 3292 * RETURNS: An appropriate -ERRNO error value on error, or zero for success. 3293 */ 3294 int pci_set_mwi(struct pci_dev *dev) 3295 { 3296 #ifdef PCI_DISABLE_MWI 3297 return 0; 3298 #else 3299 int rc; 3300 u16 cmd; 3301 3302 rc = pci_set_cacheline_size(dev); 3303 if (rc) 3304 return rc; 3305 3306 pci_read_config_word(dev, PCI_COMMAND, &cmd); 3307 if (!(cmd & PCI_COMMAND_INVALIDATE)) { 3308 dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n"); 3309 cmd |= PCI_COMMAND_INVALIDATE; 3310 pci_write_config_word(dev, PCI_COMMAND, cmd); 3311 } 3312 return 0; 3313 #endif 3314 } 3315 EXPORT_SYMBOL(pci_set_mwi); 3316 3317 /** 3318 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction 3319 * @dev: the PCI device for which MWI is enabled 3320 * 3321 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. 3322 * Callers are not required to check the return value. 3323 * 3324 * RETURNS: An appropriate -ERRNO error value on error, or zero for success. 3325 */ 3326 int pci_try_set_mwi(struct pci_dev *dev) 3327 { 3328 #ifdef PCI_DISABLE_MWI 3329 return 0; 3330 #else 3331 return pci_set_mwi(dev); 3332 #endif 3333 } 3334 EXPORT_SYMBOL(pci_try_set_mwi); 3335 3336 /** 3337 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev 3338 * @dev: the PCI device to disable 3339 * 3340 * Disables PCI Memory-Write-Invalidate transaction on the device 3341 */ 3342 void pci_clear_mwi(struct pci_dev *dev) 3343 { 3344 #ifndef PCI_DISABLE_MWI 3345 u16 cmd; 3346 3347 pci_read_config_word(dev, PCI_COMMAND, &cmd); 3348 if (cmd & PCI_COMMAND_INVALIDATE) { 3349 cmd &= ~PCI_COMMAND_INVALIDATE; 3350 pci_write_config_word(dev, PCI_COMMAND, cmd); 3351 } 3352 #endif 3353 } 3354 EXPORT_SYMBOL(pci_clear_mwi); 3355 3356 /** 3357 * pci_intx - enables/disables PCI INTx for device dev 3358 * @pdev: the PCI device to operate on 3359 * @enable: boolean: whether to enable or disable PCI INTx 3360 * 3361 * Enables/disables PCI INTx for device dev 3362 */ 3363 void pci_intx(struct pci_dev *pdev, int enable) 3364 { 3365 u16 pci_command, new; 3366 3367 pci_read_config_word(pdev, PCI_COMMAND, &pci_command); 3368 3369 if (enable) 3370 new = pci_command & ~PCI_COMMAND_INTX_DISABLE; 3371 else 3372 new = pci_command | PCI_COMMAND_INTX_DISABLE; 3373 3374 if (new != pci_command) { 3375 struct pci_devres *dr; 3376 3377 pci_write_config_word(pdev, PCI_COMMAND, new); 3378 3379 dr = find_pci_dr(pdev); 3380 if (dr && !dr->restore_intx) { 3381 dr->restore_intx = 1; 3382 dr->orig_intx = !enable; 3383 } 3384 } 3385 } 3386 EXPORT_SYMBOL_GPL(pci_intx); 3387 3388 /** 3389 * pci_intx_mask_supported - probe for INTx masking support 3390 * @dev: the PCI device to operate on 3391 * 3392 * Check if the device dev support INTx masking via the config space 3393 * command word. 3394 */ 3395 bool pci_intx_mask_supported(struct pci_dev *dev) 3396 { 3397 bool mask_supported = false; 3398 u16 orig, new; 3399 3400 if (dev->broken_intx_masking) 3401 return false; 3402 3403 pci_cfg_access_lock(dev); 3404 3405 pci_read_config_word(dev, PCI_COMMAND, &orig); 3406 pci_write_config_word(dev, PCI_COMMAND, 3407 orig ^ PCI_COMMAND_INTX_DISABLE); 3408 pci_read_config_word(dev, PCI_COMMAND, &new); 3409 3410 /* 3411 * There's no way to protect against hardware bugs or detect them 3412 * reliably, but as long as we know what the value should be, let's 3413 * go ahead and check it. 3414 */ 3415 if ((new ^ orig) & ~PCI_COMMAND_INTX_DISABLE) { 3416 dev_err(&dev->dev, "Command register changed from 0x%x to 0x%x: driver or hardware bug?\n", 3417 orig, new); 3418 } else if ((new ^ orig) & PCI_COMMAND_INTX_DISABLE) { 3419 mask_supported = true; 3420 pci_write_config_word(dev, PCI_COMMAND, orig); 3421 } 3422 3423 pci_cfg_access_unlock(dev); 3424 return mask_supported; 3425 } 3426 EXPORT_SYMBOL_GPL(pci_intx_mask_supported); 3427 3428 static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask) 3429 { 3430 struct pci_bus *bus = dev->bus; 3431 bool mask_updated = true; 3432 u32 cmd_status_dword; 3433 u16 origcmd, newcmd; 3434 unsigned long flags; 3435 bool irq_pending; 3436 3437 /* 3438 * We do a single dword read to retrieve both command and status. 3439 * Document assumptions that make this possible. 3440 */ 3441 BUILD_BUG_ON(PCI_COMMAND % 4); 3442 BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS); 3443 3444 raw_spin_lock_irqsave(&pci_lock, flags); 3445 3446 bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword); 3447 3448 irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT; 3449 3450 /* 3451 * Check interrupt status register to see whether our device 3452 * triggered the interrupt (when masking) or the next IRQ is 3453 * already pending (when unmasking). 3454 */ 3455 if (mask != irq_pending) { 3456 mask_updated = false; 3457 goto done; 3458 } 3459 3460 origcmd = cmd_status_dword; 3461 newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE; 3462 if (mask) 3463 newcmd |= PCI_COMMAND_INTX_DISABLE; 3464 if (newcmd != origcmd) 3465 bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd); 3466 3467 done: 3468 raw_spin_unlock_irqrestore(&pci_lock, flags); 3469 3470 return mask_updated; 3471 } 3472 3473 /** 3474 * pci_check_and_mask_intx - mask INTx on pending interrupt 3475 * @dev: the PCI device to operate on 3476 * 3477 * Check if the device dev has its INTx line asserted, mask it and 3478 * return true in that case. False is returned if not interrupt was 3479 * pending. 3480 */ 3481 bool pci_check_and_mask_intx(struct pci_dev *dev) 3482 { 3483 return pci_check_and_set_intx_mask(dev, true); 3484 } 3485 EXPORT_SYMBOL_GPL(pci_check_and_mask_intx); 3486 3487 /** 3488 * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending 3489 * @dev: the PCI device to operate on 3490 * 3491 * Check if the device dev has its INTx line asserted, unmask it if not 3492 * and return true. False is returned and the mask remains active if 3493 * there was still an interrupt pending. 3494 */ 3495 bool pci_check_and_unmask_intx(struct pci_dev *dev) 3496 { 3497 return pci_check_and_set_intx_mask(dev, false); 3498 } 3499 EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx); 3500 3501 /** 3502 * pci_wait_for_pending_transaction - waits for pending transaction 3503 * @dev: the PCI device to operate on 3504 * 3505 * Return 0 if transaction is pending 1 otherwise. 3506 */ 3507 int pci_wait_for_pending_transaction(struct pci_dev *dev) 3508 { 3509 if (!pci_is_pcie(dev)) 3510 return 1; 3511 3512 return pci_wait_for_pending(dev, pci_pcie_cap(dev) + PCI_EXP_DEVSTA, 3513 PCI_EXP_DEVSTA_TRPND); 3514 } 3515 EXPORT_SYMBOL(pci_wait_for_pending_transaction); 3516 3517 /* 3518 * We should only need to wait 100ms after FLR, but some devices take longer. 3519 * Wait for up to 1000ms for config space to return something other than -1. 3520 * Intel IGD requires this when an LCD panel is attached. We read the 2nd 3521 * dword because VFs don't implement the 1st dword. 3522 */ 3523 static void pci_flr_wait(struct pci_dev *dev) 3524 { 3525 int i = 0; 3526 u32 id; 3527 3528 do { 3529 msleep(100); 3530 pci_read_config_dword(dev, PCI_COMMAND, &id); 3531 } while (i++ < 10 && id == ~0); 3532 3533 if (id == ~0) 3534 dev_warn(&dev->dev, "Failed to return from FLR\n"); 3535 else if (i > 1) 3536 dev_info(&dev->dev, "Required additional %dms to return from FLR\n", 3537 (i - 1) * 100); 3538 } 3539 3540 static int pcie_flr(struct pci_dev *dev, int probe) 3541 { 3542 u32 cap; 3543 3544 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap); 3545 if (!(cap & PCI_EXP_DEVCAP_FLR)) 3546 return -ENOTTY; 3547 3548 if (probe) 3549 return 0; 3550 3551 if (!pci_wait_for_pending_transaction(dev)) 3552 dev_err(&dev->dev, "timed out waiting for pending transaction; performing function level reset anyway\n"); 3553 3554 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR); 3555 pci_flr_wait(dev); 3556 return 0; 3557 } 3558 3559 static int pci_af_flr(struct pci_dev *dev, int probe) 3560 { 3561 int pos; 3562 u8 cap; 3563 3564 pos = pci_find_capability(dev, PCI_CAP_ID_AF); 3565 if (!pos) 3566 return -ENOTTY; 3567 3568 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap); 3569 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR)) 3570 return -ENOTTY; 3571 3572 if (probe) 3573 return 0; 3574 3575 /* 3576 * Wait for Transaction Pending bit to clear. A word-aligned test 3577 * is used, so we use the conrol offset rather than status and shift 3578 * the test bit to match. 3579 */ 3580 if (!pci_wait_for_pending(dev, pos + PCI_AF_CTRL, 3581 PCI_AF_STATUS_TP << 8)) 3582 dev_err(&dev->dev, "timed out waiting for pending transaction; performing AF function level reset anyway\n"); 3583 3584 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR); 3585 pci_flr_wait(dev); 3586 return 0; 3587 } 3588 3589 /** 3590 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0. 3591 * @dev: Device to reset. 3592 * @probe: If set, only check if the device can be reset this way. 3593 * 3594 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is 3595 * unset, it will be reinitialized internally when going from PCI_D3hot to 3596 * PCI_D0. If that's the case and the device is not in a low-power state 3597 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset. 3598 * 3599 * NOTE: This causes the caller to sleep for twice the device power transition 3600 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms 3601 * by default (i.e. unless the @dev's d3_delay field has a different value). 3602 * Moreover, only devices in D0 can be reset by this function. 3603 */ 3604 static int pci_pm_reset(struct pci_dev *dev, int probe) 3605 { 3606 u16 csr; 3607 3608 if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET) 3609 return -ENOTTY; 3610 3611 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr); 3612 if (csr & PCI_PM_CTRL_NO_SOFT_RESET) 3613 return -ENOTTY; 3614 3615 if (probe) 3616 return 0; 3617 3618 if (dev->current_state != PCI_D0) 3619 return -EINVAL; 3620 3621 csr &= ~PCI_PM_CTRL_STATE_MASK; 3622 csr |= PCI_D3hot; 3623 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); 3624 pci_dev_d3_sleep(dev); 3625 3626 csr &= ~PCI_PM_CTRL_STATE_MASK; 3627 csr |= PCI_D0; 3628 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); 3629 pci_dev_d3_sleep(dev); 3630 3631 return 0; 3632 } 3633 3634 void pci_reset_secondary_bus(struct pci_dev *dev) 3635 { 3636 u16 ctrl; 3637 3638 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl); 3639 ctrl |= PCI_BRIDGE_CTL_BUS_RESET; 3640 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl); 3641 /* 3642 * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double 3643 * this to 2ms to ensure that we meet the minimum requirement. 3644 */ 3645 msleep(2); 3646 3647 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET; 3648 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl); 3649 3650 /* 3651 * Trhfa for conventional PCI is 2^25 clock cycles. 3652 * Assuming a minimum 33MHz clock this results in a 1s 3653 * delay before we can consider subordinate devices to 3654 * be re-initialized. PCIe has some ways to shorten this, 3655 * but we don't make use of them yet. 3656 */ 3657 ssleep(1); 3658 } 3659 3660 void __weak pcibios_reset_secondary_bus(struct pci_dev *dev) 3661 { 3662 pci_reset_secondary_bus(dev); 3663 } 3664 3665 /** 3666 * pci_reset_bridge_secondary_bus - Reset the secondary bus on a PCI bridge. 3667 * @dev: Bridge device 3668 * 3669 * Use the bridge control register to assert reset on the secondary bus. 3670 * Devices on the secondary bus are left in power-on state. 3671 */ 3672 void pci_reset_bridge_secondary_bus(struct pci_dev *dev) 3673 { 3674 pcibios_reset_secondary_bus(dev); 3675 } 3676 EXPORT_SYMBOL_GPL(pci_reset_bridge_secondary_bus); 3677 3678 static int pci_parent_bus_reset(struct pci_dev *dev, int probe) 3679 { 3680 struct pci_dev *pdev; 3681 3682 if (pci_is_root_bus(dev->bus) || dev->subordinate || 3683 !dev->bus->self || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET) 3684 return -ENOTTY; 3685 3686 list_for_each_entry(pdev, &dev->bus->devices, bus_list) 3687 if (pdev != dev) 3688 return -ENOTTY; 3689 3690 if (probe) 3691 return 0; 3692 3693 pci_reset_bridge_secondary_bus(dev->bus->self); 3694 3695 return 0; 3696 } 3697 3698 static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, int probe) 3699 { 3700 int rc = -ENOTTY; 3701 3702 if (!hotplug || !try_module_get(hotplug->ops->owner)) 3703 return rc; 3704 3705 if (hotplug->ops->reset_slot) 3706 rc = hotplug->ops->reset_slot(hotplug, probe); 3707 3708 module_put(hotplug->ops->owner); 3709 3710 return rc; 3711 } 3712 3713 static int pci_dev_reset_slot_function(struct pci_dev *dev, int probe) 3714 { 3715 struct pci_dev *pdev; 3716 3717 if (dev->subordinate || !dev->slot || 3718 dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET) 3719 return -ENOTTY; 3720 3721 list_for_each_entry(pdev, &dev->bus->devices, bus_list) 3722 if (pdev != dev && pdev->slot == dev->slot) 3723 return -ENOTTY; 3724 3725 return pci_reset_hotplug_slot(dev->slot->hotplug, probe); 3726 } 3727 3728 static int __pci_dev_reset(struct pci_dev *dev, int probe) 3729 { 3730 int rc; 3731 3732 might_sleep(); 3733 3734 rc = pci_dev_specific_reset(dev, probe); 3735 if (rc != -ENOTTY) 3736 goto done; 3737 3738 rc = pcie_flr(dev, probe); 3739 if (rc != -ENOTTY) 3740 goto done; 3741 3742 rc = pci_af_flr(dev, probe); 3743 if (rc != -ENOTTY) 3744 goto done; 3745 3746 rc = pci_pm_reset(dev, probe); 3747 if (rc != -ENOTTY) 3748 goto done; 3749 3750 rc = pci_dev_reset_slot_function(dev, probe); 3751 if (rc != -ENOTTY) 3752 goto done; 3753 3754 rc = pci_parent_bus_reset(dev, probe); 3755 done: 3756 return rc; 3757 } 3758 3759 static void pci_dev_lock(struct pci_dev *dev) 3760 { 3761 pci_cfg_access_lock(dev); 3762 /* block PM suspend, driver probe, etc. */ 3763 device_lock(&dev->dev); 3764 } 3765 3766 /* Return 1 on successful lock, 0 on contention */ 3767 static int pci_dev_trylock(struct pci_dev *dev) 3768 { 3769 if (pci_cfg_access_trylock(dev)) { 3770 if (device_trylock(&dev->dev)) 3771 return 1; 3772 pci_cfg_access_unlock(dev); 3773 } 3774 3775 return 0; 3776 } 3777 3778 static void pci_dev_unlock(struct pci_dev *dev) 3779 { 3780 device_unlock(&dev->dev); 3781 pci_cfg_access_unlock(dev); 3782 } 3783 3784 /** 3785 * pci_reset_notify - notify device driver of reset 3786 * @dev: device to be notified of reset 3787 * @prepare: 'true' if device is about to be reset; 'false' if reset attempt 3788 * completed 3789 * 3790 * Must be called prior to device access being disabled and after device 3791 * access is restored. 3792 */ 3793 static void pci_reset_notify(struct pci_dev *dev, bool prepare) 3794 { 3795 const struct pci_error_handlers *err_handler = 3796 dev->driver ? dev->driver->err_handler : NULL; 3797 if (err_handler && err_handler->reset_notify) 3798 err_handler->reset_notify(dev, prepare); 3799 } 3800 3801 static void pci_dev_save_and_disable(struct pci_dev *dev) 3802 { 3803 pci_reset_notify(dev, true); 3804 3805 /* 3806 * Wake-up device prior to save. PM registers default to D0 after 3807 * reset and a simple register restore doesn't reliably return 3808 * to a non-D0 state anyway. 3809 */ 3810 pci_set_power_state(dev, PCI_D0); 3811 3812 pci_save_state(dev); 3813 /* 3814 * Disable the device by clearing the Command register, except for 3815 * INTx-disable which is set. This not only disables MMIO and I/O port 3816 * BARs, but also prevents the device from being Bus Master, preventing 3817 * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3 3818 * compliant devices, INTx-disable prevents legacy interrupts. 3819 */ 3820 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE); 3821 } 3822 3823 static void pci_dev_restore(struct pci_dev *dev) 3824 { 3825 pci_restore_state(dev); 3826 pci_reset_notify(dev, false); 3827 } 3828 3829 static int pci_dev_reset(struct pci_dev *dev, int probe) 3830 { 3831 int rc; 3832 3833 if (!probe) 3834 pci_dev_lock(dev); 3835 3836 rc = __pci_dev_reset(dev, probe); 3837 3838 if (!probe) 3839 pci_dev_unlock(dev); 3840 3841 return rc; 3842 } 3843 3844 /** 3845 * __pci_reset_function - reset a PCI device function 3846 * @dev: PCI device to reset 3847 * 3848 * Some devices allow an individual function to be reset without affecting 3849 * other functions in the same device. The PCI device must be responsive 3850 * to PCI config space in order to use this function. 3851 * 3852 * The device function is presumed to be unused when this function is called. 3853 * Resetting the device will make the contents of PCI configuration space 3854 * random, so any caller of this must be prepared to reinitialise the 3855 * device including MSI, bus mastering, BARs, decoding IO and memory spaces, 3856 * etc. 3857 * 3858 * Returns 0 if the device function was successfully reset or negative if the 3859 * device doesn't support resetting a single function. 3860 */ 3861 int __pci_reset_function(struct pci_dev *dev) 3862 { 3863 return pci_dev_reset(dev, 0); 3864 } 3865 EXPORT_SYMBOL_GPL(__pci_reset_function); 3866 3867 /** 3868 * __pci_reset_function_locked - reset a PCI device function while holding 3869 * the @dev mutex lock. 3870 * @dev: PCI device to reset 3871 * 3872 * Some devices allow an individual function to be reset without affecting 3873 * other functions in the same device. The PCI device must be responsive 3874 * to PCI config space in order to use this function. 3875 * 3876 * The device function is presumed to be unused and the caller is holding 3877 * the device mutex lock when this function is called. 3878 * Resetting the device will make the contents of PCI configuration space 3879 * random, so any caller of this must be prepared to reinitialise the 3880 * device including MSI, bus mastering, BARs, decoding IO and memory spaces, 3881 * etc. 3882 * 3883 * Returns 0 if the device function was successfully reset or negative if the 3884 * device doesn't support resetting a single function. 3885 */ 3886 int __pci_reset_function_locked(struct pci_dev *dev) 3887 { 3888 return __pci_dev_reset(dev, 0); 3889 } 3890 EXPORT_SYMBOL_GPL(__pci_reset_function_locked); 3891 3892 /** 3893 * pci_probe_reset_function - check whether the device can be safely reset 3894 * @dev: PCI device to reset 3895 * 3896 * Some devices allow an individual function to be reset without affecting 3897 * other functions in the same device. The PCI device must be responsive 3898 * to PCI config space in order to use this function. 3899 * 3900 * Returns 0 if the device function can be reset or negative if the 3901 * device doesn't support resetting a single function. 3902 */ 3903 int pci_probe_reset_function(struct pci_dev *dev) 3904 { 3905 return pci_dev_reset(dev, 1); 3906 } 3907 3908 /** 3909 * pci_reset_function - quiesce and reset a PCI device function 3910 * @dev: PCI device to reset 3911 * 3912 * Some devices allow an individual function to be reset without affecting 3913 * other functions in the same device. The PCI device must be responsive 3914 * to PCI config space in order to use this function. 3915 * 3916 * This function does not just reset the PCI portion of a device, but 3917 * clears all the state associated with the device. This function differs 3918 * from __pci_reset_function in that it saves and restores device state 3919 * over the reset. 3920 * 3921 * Returns 0 if the device function was successfully reset or negative if the 3922 * device doesn't support resetting a single function. 3923 */ 3924 int pci_reset_function(struct pci_dev *dev) 3925 { 3926 int rc; 3927 3928 rc = pci_dev_reset(dev, 1); 3929 if (rc) 3930 return rc; 3931 3932 pci_dev_save_and_disable(dev); 3933 3934 rc = pci_dev_reset(dev, 0); 3935 3936 pci_dev_restore(dev); 3937 3938 return rc; 3939 } 3940 EXPORT_SYMBOL_GPL(pci_reset_function); 3941 3942 /** 3943 * pci_try_reset_function - quiesce and reset a PCI device function 3944 * @dev: PCI device to reset 3945 * 3946 * Same as above, except return -EAGAIN if unable to lock device. 3947 */ 3948 int pci_try_reset_function(struct pci_dev *dev) 3949 { 3950 int rc; 3951 3952 rc = pci_dev_reset(dev, 1); 3953 if (rc) 3954 return rc; 3955 3956 pci_dev_save_and_disable(dev); 3957 3958 if (pci_dev_trylock(dev)) { 3959 rc = __pci_dev_reset(dev, 0); 3960 pci_dev_unlock(dev); 3961 } else 3962 rc = -EAGAIN; 3963 3964 pci_dev_restore(dev); 3965 3966 return rc; 3967 } 3968 EXPORT_SYMBOL_GPL(pci_try_reset_function); 3969 3970 /* Do any devices on or below this bus prevent a bus reset? */ 3971 static bool pci_bus_resetable(struct pci_bus *bus) 3972 { 3973 struct pci_dev *dev; 3974 3975 list_for_each_entry(dev, &bus->devices, bus_list) { 3976 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET || 3977 (dev->subordinate && !pci_bus_resetable(dev->subordinate))) 3978 return false; 3979 } 3980 3981 return true; 3982 } 3983 3984 /* Lock devices from the top of the tree down */ 3985 static void pci_bus_lock(struct pci_bus *bus) 3986 { 3987 struct pci_dev *dev; 3988 3989 list_for_each_entry(dev, &bus->devices, bus_list) { 3990 pci_dev_lock(dev); 3991 if (dev->subordinate) 3992 pci_bus_lock(dev->subordinate); 3993 } 3994 } 3995 3996 /* Unlock devices from the bottom of the tree up */ 3997 static void pci_bus_unlock(struct pci_bus *bus) 3998 { 3999 struct pci_dev *dev; 4000 4001 list_for_each_entry(dev, &bus->devices, bus_list) { 4002 if (dev->subordinate) 4003 pci_bus_unlock(dev->subordinate); 4004 pci_dev_unlock(dev); 4005 } 4006 } 4007 4008 /* Return 1 on successful lock, 0 on contention */ 4009 static int pci_bus_trylock(struct pci_bus *bus) 4010 { 4011 struct pci_dev *dev; 4012 4013 list_for_each_entry(dev, &bus->devices, bus_list) { 4014 if (!pci_dev_trylock(dev)) 4015 goto unlock; 4016 if (dev->subordinate) { 4017 if (!pci_bus_trylock(dev->subordinate)) { 4018 pci_dev_unlock(dev); 4019 goto unlock; 4020 } 4021 } 4022 } 4023 return 1; 4024 4025 unlock: 4026 list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) { 4027 if (dev->subordinate) 4028 pci_bus_unlock(dev->subordinate); 4029 pci_dev_unlock(dev); 4030 } 4031 return 0; 4032 } 4033 4034 /* Do any devices on or below this slot prevent a bus reset? */ 4035 static bool pci_slot_resetable(struct pci_slot *slot) 4036 { 4037 struct pci_dev *dev; 4038 4039 list_for_each_entry(dev, &slot->bus->devices, bus_list) { 4040 if (!dev->slot || dev->slot != slot) 4041 continue; 4042 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET || 4043 (dev->subordinate && !pci_bus_resetable(dev->subordinate))) 4044 return false; 4045 } 4046 4047 return true; 4048 } 4049 4050 /* Lock devices from the top of the tree down */ 4051 static void pci_slot_lock(struct pci_slot *slot) 4052 { 4053 struct pci_dev *dev; 4054 4055 list_for_each_entry(dev, &slot->bus->devices, bus_list) { 4056 if (!dev->slot || dev->slot != slot) 4057 continue; 4058 pci_dev_lock(dev); 4059 if (dev->subordinate) 4060 pci_bus_lock(dev->subordinate); 4061 } 4062 } 4063 4064 /* Unlock devices from the bottom of the tree up */ 4065 static void pci_slot_unlock(struct pci_slot *slot) 4066 { 4067 struct pci_dev *dev; 4068 4069 list_for_each_entry(dev, &slot->bus->devices, bus_list) { 4070 if (!dev->slot || dev->slot != slot) 4071 continue; 4072 if (dev->subordinate) 4073 pci_bus_unlock(dev->subordinate); 4074 pci_dev_unlock(dev); 4075 } 4076 } 4077 4078 /* Return 1 on successful lock, 0 on contention */ 4079 static int pci_slot_trylock(struct pci_slot *slot) 4080 { 4081 struct pci_dev *dev; 4082 4083 list_for_each_entry(dev, &slot->bus->devices, bus_list) { 4084 if (!dev->slot || dev->slot != slot) 4085 continue; 4086 if (!pci_dev_trylock(dev)) 4087 goto unlock; 4088 if (dev->subordinate) { 4089 if (!pci_bus_trylock(dev->subordinate)) { 4090 pci_dev_unlock(dev); 4091 goto unlock; 4092 } 4093 } 4094 } 4095 return 1; 4096 4097 unlock: 4098 list_for_each_entry_continue_reverse(dev, 4099 &slot->bus->devices, bus_list) { 4100 if (!dev->slot || dev->slot != slot) 4101 continue; 4102 if (dev->subordinate) 4103 pci_bus_unlock(dev->subordinate); 4104 pci_dev_unlock(dev); 4105 } 4106 return 0; 4107 } 4108 4109 /* Save and disable devices from the top of the tree down */ 4110 static void pci_bus_save_and_disable(struct pci_bus *bus) 4111 { 4112 struct pci_dev *dev; 4113 4114 list_for_each_entry(dev, &bus->devices, bus_list) { 4115 pci_dev_save_and_disable(dev); 4116 if (dev->subordinate) 4117 pci_bus_save_and_disable(dev->subordinate); 4118 } 4119 } 4120 4121 /* 4122 * Restore devices from top of the tree down - parent bridges need to be 4123 * restored before we can get to subordinate devices. 4124 */ 4125 static void pci_bus_restore(struct pci_bus *bus) 4126 { 4127 struct pci_dev *dev; 4128 4129 list_for_each_entry(dev, &bus->devices, bus_list) { 4130 pci_dev_restore(dev); 4131 if (dev->subordinate) 4132 pci_bus_restore(dev->subordinate); 4133 } 4134 } 4135 4136 /* Save and disable devices from the top of the tree down */ 4137 static void pci_slot_save_and_disable(struct pci_slot *slot) 4138 { 4139 struct pci_dev *dev; 4140 4141 list_for_each_entry(dev, &slot->bus->devices, bus_list) { 4142 if (!dev->slot || dev->slot != slot) 4143 continue; 4144 pci_dev_save_and_disable(dev); 4145 if (dev->subordinate) 4146 pci_bus_save_and_disable(dev->subordinate); 4147 } 4148 } 4149 4150 /* 4151 * Restore devices from top of the tree down - parent bridges need to be 4152 * restored before we can get to subordinate devices. 4153 */ 4154 static void pci_slot_restore(struct pci_slot *slot) 4155 { 4156 struct pci_dev *dev; 4157 4158 list_for_each_entry(dev, &slot->bus->devices, bus_list) { 4159 if (!dev->slot || dev->slot != slot) 4160 continue; 4161 pci_dev_restore(dev); 4162 if (dev->subordinate) 4163 pci_bus_restore(dev->subordinate); 4164 } 4165 } 4166 4167 static int pci_slot_reset(struct pci_slot *slot, int probe) 4168 { 4169 int rc; 4170 4171 if (!slot || !pci_slot_resetable(slot)) 4172 return -ENOTTY; 4173 4174 if (!probe) 4175 pci_slot_lock(slot); 4176 4177 might_sleep(); 4178 4179 rc = pci_reset_hotplug_slot(slot->hotplug, probe); 4180 4181 if (!probe) 4182 pci_slot_unlock(slot); 4183 4184 return rc; 4185 } 4186 4187 /** 4188 * pci_probe_reset_slot - probe whether a PCI slot can be reset 4189 * @slot: PCI slot to probe 4190 * 4191 * Return 0 if slot can be reset, negative if a slot reset is not supported. 4192 */ 4193 int pci_probe_reset_slot(struct pci_slot *slot) 4194 { 4195 return pci_slot_reset(slot, 1); 4196 } 4197 EXPORT_SYMBOL_GPL(pci_probe_reset_slot); 4198 4199 /** 4200 * pci_reset_slot - reset a PCI slot 4201 * @slot: PCI slot to reset 4202 * 4203 * A PCI bus may host multiple slots, each slot may support a reset mechanism 4204 * independent of other slots. For instance, some slots may support slot power 4205 * control. In the case of a 1:1 bus to slot architecture, this function may 4206 * wrap the bus reset to avoid spurious slot related events such as hotplug. 4207 * Generally a slot reset should be attempted before a bus reset. All of the 4208 * function of the slot and any subordinate buses behind the slot are reset 4209 * through this function. PCI config space of all devices in the slot and 4210 * behind the slot is saved before and restored after reset. 4211 * 4212 * Return 0 on success, non-zero on error. 4213 */ 4214 int pci_reset_slot(struct pci_slot *slot) 4215 { 4216 int rc; 4217 4218 rc = pci_slot_reset(slot, 1); 4219 if (rc) 4220 return rc; 4221 4222 pci_slot_save_and_disable(slot); 4223 4224 rc = pci_slot_reset(slot, 0); 4225 4226 pci_slot_restore(slot); 4227 4228 return rc; 4229 } 4230 EXPORT_SYMBOL_GPL(pci_reset_slot); 4231 4232 /** 4233 * pci_try_reset_slot - Try to reset a PCI slot 4234 * @slot: PCI slot to reset 4235 * 4236 * Same as above except return -EAGAIN if the slot cannot be locked 4237 */ 4238 int pci_try_reset_slot(struct pci_slot *slot) 4239 { 4240 int rc; 4241 4242 rc = pci_slot_reset(slot, 1); 4243 if (rc) 4244 return rc; 4245 4246 pci_slot_save_and_disable(slot); 4247 4248 if (pci_slot_trylock(slot)) { 4249 might_sleep(); 4250 rc = pci_reset_hotplug_slot(slot->hotplug, 0); 4251 pci_slot_unlock(slot); 4252 } else 4253 rc = -EAGAIN; 4254 4255 pci_slot_restore(slot); 4256 4257 return rc; 4258 } 4259 EXPORT_SYMBOL_GPL(pci_try_reset_slot); 4260 4261 static int pci_bus_reset(struct pci_bus *bus, int probe) 4262 { 4263 if (!bus->self || !pci_bus_resetable(bus)) 4264 return -ENOTTY; 4265 4266 if (probe) 4267 return 0; 4268 4269 pci_bus_lock(bus); 4270 4271 might_sleep(); 4272 4273 pci_reset_bridge_secondary_bus(bus->self); 4274 4275 pci_bus_unlock(bus); 4276 4277 return 0; 4278 } 4279 4280 /** 4281 * pci_probe_reset_bus - probe whether a PCI bus can be reset 4282 * @bus: PCI bus to probe 4283 * 4284 * Return 0 if bus can be reset, negative if a bus reset is not supported. 4285 */ 4286 int pci_probe_reset_bus(struct pci_bus *bus) 4287 { 4288 return pci_bus_reset(bus, 1); 4289 } 4290 EXPORT_SYMBOL_GPL(pci_probe_reset_bus); 4291 4292 /** 4293 * pci_reset_bus - reset a PCI bus 4294 * @bus: top level PCI bus to reset 4295 * 4296 * Do a bus reset on the given bus and any subordinate buses, saving 4297 * and restoring state of all devices. 4298 * 4299 * Return 0 on success, non-zero on error. 4300 */ 4301 int pci_reset_bus(struct pci_bus *bus) 4302 { 4303 int rc; 4304 4305 rc = pci_bus_reset(bus, 1); 4306 if (rc) 4307 return rc; 4308 4309 pci_bus_save_and_disable(bus); 4310 4311 rc = pci_bus_reset(bus, 0); 4312 4313 pci_bus_restore(bus); 4314 4315 return rc; 4316 } 4317 EXPORT_SYMBOL_GPL(pci_reset_bus); 4318 4319 /** 4320 * pci_try_reset_bus - Try to reset a PCI bus 4321 * @bus: top level PCI bus to reset 4322 * 4323 * Same as above except return -EAGAIN if the bus cannot be locked 4324 */ 4325 int pci_try_reset_bus(struct pci_bus *bus) 4326 { 4327 int rc; 4328 4329 rc = pci_bus_reset(bus, 1); 4330 if (rc) 4331 return rc; 4332 4333 pci_bus_save_and_disable(bus); 4334 4335 if (pci_bus_trylock(bus)) { 4336 might_sleep(); 4337 pci_reset_bridge_secondary_bus(bus->self); 4338 pci_bus_unlock(bus); 4339 } else 4340 rc = -EAGAIN; 4341 4342 pci_bus_restore(bus); 4343 4344 return rc; 4345 } 4346 EXPORT_SYMBOL_GPL(pci_try_reset_bus); 4347 4348 /** 4349 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count 4350 * @dev: PCI device to query 4351 * 4352 * Returns mmrbc: maximum designed memory read count in bytes 4353 * or appropriate error value. 4354 */ 4355 int pcix_get_max_mmrbc(struct pci_dev *dev) 4356 { 4357 int cap; 4358 u32 stat; 4359 4360 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); 4361 if (!cap) 4362 return -EINVAL; 4363 4364 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat)) 4365 return -EINVAL; 4366 4367 return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21); 4368 } 4369 EXPORT_SYMBOL(pcix_get_max_mmrbc); 4370 4371 /** 4372 * pcix_get_mmrbc - get PCI-X maximum memory read byte count 4373 * @dev: PCI device to query 4374 * 4375 * Returns mmrbc: maximum memory read count in bytes 4376 * or appropriate error value. 4377 */ 4378 int pcix_get_mmrbc(struct pci_dev *dev) 4379 { 4380 int cap; 4381 u16 cmd; 4382 4383 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); 4384 if (!cap) 4385 return -EINVAL; 4386 4387 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd)) 4388 return -EINVAL; 4389 4390 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2); 4391 } 4392 EXPORT_SYMBOL(pcix_get_mmrbc); 4393 4394 /** 4395 * pcix_set_mmrbc - set PCI-X maximum memory read byte count 4396 * @dev: PCI device to query 4397 * @mmrbc: maximum memory read count in bytes 4398 * valid values are 512, 1024, 2048, 4096 4399 * 4400 * If possible sets maximum memory read byte count, some bridges have erratas 4401 * that prevent this. 4402 */ 4403 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc) 4404 { 4405 int cap; 4406 u32 stat, v, o; 4407 u16 cmd; 4408 4409 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc)) 4410 return -EINVAL; 4411 4412 v = ffs(mmrbc) - 10; 4413 4414 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); 4415 if (!cap) 4416 return -EINVAL; 4417 4418 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat)) 4419 return -EINVAL; 4420 4421 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21) 4422 return -E2BIG; 4423 4424 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd)) 4425 return -EINVAL; 4426 4427 o = (cmd & PCI_X_CMD_MAX_READ) >> 2; 4428 if (o != v) { 4429 if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC)) 4430 return -EIO; 4431 4432 cmd &= ~PCI_X_CMD_MAX_READ; 4433 cmd |= v << 2; 4434 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd)) 4435 return -EIO; 4436 } 4437 return 0; 4438 } 4439 EXPORT_SYMBOL(pcix_set_mmrbc); 4440 4441 /** 4442 * pcie_get_readrq - get PCI Express read request size 4443 * @dev: PCI device to query 4444 * 4445 * Returns maximum memory read request in bytes 4446 * or appropriate error value. 4447 */ 4448 int pcie_get_readrq(struct pci_dev *dev) 4449 { 4450 u16 ctl; 4451 4452 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl); 4453 4454 return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12); 4455 } 4456 EXPORT_SYMBOL(pcie_get_readrq); 4457 4458 /** 4459 * pcie_set_readrq - set PCI Express maximum memory read request 4460 * @dev: PCI device to query 4461 * @rq: maximum memory read count in bytes 4462 * valid values are 128, 256, 512, 1024, 2048, 4096 4463 * 4464 * If possible sets maximum memory read request in bytes 4465 */ 4466 int pcie_set_readrq(struct pci_dev *dev, int rq) 4467 { 4468 u16 v; 4469 4470 if (rq < 128 || rq > 4096 || !is_power_of_2(rq)) 4471 return -EINVAL; 4472 4473 /* 4474 * If using the "performance" PCIe config, we clamp the 4475 * read rq size to the max packet size to prevent the 4476 * host bridge generating requests larger than we can 4477 * cope with 4478 */ 4479 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) { 4480 int mps = pcie_get_mps(dev); 4481 4482 if (mps < rq) 4483 rq = mps; 4484 } 4485 4486 v = (ffs(rq) - 8) << 12; 4487 4488 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL, 4489 PCI_EXP_DEVCTL_READRQ, v); 4490 } 4491 EXPORT_SYMBOL(pcie_set_readrq); 4492 4493 /** 4494 * pcie_get_mps - get PCI Express maximum payload size 4495 * @dev: PCI device to query 4496 * 4497 * Returns maximum payload size in bytes 4498 */ 4499 int pcie_get_mps(struct pci_dev *dev) 4500 { 4501 u16 ctl; 4502 4503 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl); 4504 4505 return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5); 4506 } 4507 EXPORT_SYMBOL(pcie_get_mps); 4508 4509 /** 4510 * pcie_set_mps - set PCI Express maximum payload size 4511 * @dev: PCI device to query 4512 * @mps: maximum payload size in bytes 4513 * valid values are 128, 256, 512, 1024, 2048, 4096 4514 * 4515 * If possible sets maximum payload size 4516 */ 4517 int pcie_set_mps(struct pci_dev *dev, int mps) 4518 { 4519 u16 v; 4520 4521 if (mps < 128 || mps > 4096 || !is_power_of_2(mps)) 4522 return -EINVAL; 4523 4524 v = ffs(mps) - 8; 4525 if (v > dev->pcie_mpss) 4526 return -EINVAL; 4527 v <<= 5; 4528 4529 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL, 4530 PCI_EXP_DEVCTL_PAYLOAD, v); 4531 } 4532 EXPORT_SYMBOL(pcie_set_mps); 4533 4534 /** 4535 * pcie_get_minimum_link - determine minimum link settings of a PCI device 4536 * @dev: PCI device to query 4537 * @speed: storage for minimum speed 4538 * @width: storage for minimum width 4539 * 4540 * This function will walk up the PCI device chain and determine the minimum 4541 * link width and speed of the device. 4542 */ 4543 int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed, 4544 enum pcie_link_width *width) 4545 { 4546 int ret; 4547 4548 *speed = PCI_SPEED_UNKNOWN; 4549 *width = PCIE_LNK_WIDTH_UNKNOWN; 4550 4551 while (dev) { 4552 u16 lnksta; 4553 enum pci_bus_speed next_speed; 4554 enum pcie_link_width next_width; 4555 4556 ret = pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta); 4557 if (ret) 4558 return ret; 4559 4560 next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS]; 4561 next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >> 4562 PCI_EXP_LNKSTA_NLW_SHIFT; 4563 4564 if (next_speed < *speed) 4565 *speed = next_speed; 4566 4567 if (next_width < *width) 4568 *width = next_width; 4569 4570 dev = dev->bus->self; 4571 } 4572 4573 return 0; 4574 } 4575 EXPORT_SYMBOL(pcie_get_minimum_link); 4576 4577 /** 4578 * pci_select_bars - Make BAR mask from the type of resource 4579 * @dev: the PCI device for which BAR mask is made 4580 * @flags: resource type mask to be selected 4581 * 4582 * This helper routine makes bar mask from the type of resource. 4583 */ 4584 int pci_select_bars(struct pci_dev *dev, unsigned long flags) 4585 { 4586 int i, bars = 0; 4587 for (i = 0; i < PCI_NUM_RESOURCES; i++) 4588 if (pci_resource_flags(dev, i) & flags) 4589 bars |= (1 << i); 4590 return bars; 4591 } 4592 EXPORT_SYMBOL(pci_select_bars); 4593 4594 /** 4595 * pci_resource_bar - get position of the BAR associated with a resource 4596 * @dev: the PCI device 4597 * @resno: the resource number 4598 * @type: the BAR type to be filled in 4599 * 4600 * Returns BAR position in config space, or 0 if the BAR is invalid. 4601 */ 4602 int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type) 4603 { 4604 int reg; 4605 4606 if (resno < PCI_ROM_RESOURCE) { 4607 *type = pci_bar_unknown; 4608 return PCI_BASE_ADDRESS_0 + 4 * resno; 4609 } else if (resno == PCI_ROM_RESOURCE) { 4610 *type = pci_bar_mem32; 4611 return dev->rom_base_reg; 4612 } else if (resno < PCI_BRIDGE_RESOURCES) { 4613 /* device specific resource */ 4614 *type = pci_bar_unknown; 4615 reg = pci_iov_resource_bar(dev, resno); 4616 if (reg) 4617 return reg; 4618 } 4619 4620 dev_err(&dev->dev, "BAR %d: invalid resource\n", resno); 4621 return 0; 4622 } 4623 4624 /* Some architectures require additional programming to enable VGA */ 4625 static arch_set_vga_state_t arch_set_vga_state; 4626 4627 void __init pci_register_set_vga_state(arch_set_vga_state_t func) 4628 { 4629 arch_set_vga_state = func; /* NULL disables */ 4630 } 4631 4632 static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode, 4633 unsigned int command_bits, u32 flags) 4634 { 4635 if (arch_set_vga_state) 4636 return arch_set_vga_state(dev, decode, command_bits, 4637 flags); 4638 return 0; 4639 } 4640 4641 /** 4642 * pci_set_vga_state - set VGA decode state on device and parents if requested 4643 * @dev: the PCI device 4644 * @decode: true = enable decoding, false = disable decoding 4645 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY 4646 * @flags: traverse ancestors and change bridges 4647 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE 4648 */ 4649 int pci_set_vga_state(struct pci_dev *dev, bool decode, 4650 unsigned int command_bits, u32 flags) 4651 { 4652 struct pci_bus *bus; 4653 struct pci_dev *bridge; 4654 u16 cmd; 4655 int rc; 4656 4657 WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) && (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY))); 4658 4659 /* ARCH specific VGA enables */ 4660 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags); 4661 if (rc) 4662 return rc; 4663 4664 if (flags & PCI_VGA_STATE_CHANGE_DECODES) { 4665 pci_read_config_word(dev, PCI_COMMAND, &cmd); 4666 if (decode == true) 4667 cmd |= command_bits; 4668 else 4669 cmd &= ~command_bits; 4670 pci_write_config_word(dev, PCI_COMMAND, cmd); 4671 } 4672 4673 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE)) 4674 return 0; 4675 4676 bus = dev->bus; 4677 while (bus) { 4678 bridge = bus->self; 4679 if (bridge) { 4680 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL, 4681 &cmd); 4682 if (decode == true) 4683 cmd |= PCI_BRIDGE_CTL_VGA; 4684 else 4685 cmd &= ~PCI_BRIDGE_CTL_VGA; 4686 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, 4687 cmd); 4688 } 4689 bus = bus->parent; 4690 } 4691 return 0; 4692 } 4693 4694 /** 4695 * pci_add_dma_alias - Add a DMA devfn alias for a device 4696 * @dev: the PCI device for which alias is added 4697 * @devfn: alias slot and function 4698 * 4699 * This helper encodes 8-bit devfn as bit number in dma_alias_mask. 4700 * It should be called early, preferably as PCI fixup header quirk. 4701 */ 4702 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn) 4703 { 4704 if (!dev->dma_alias_mask) 4705 dev->dma_alias_mask = kcalloc(BITS_TO_LONGS(U8_MAX), 4706 sizeof(long), GFP_KERNEL); 4707 if (!dev->dma_alias_mask) { 4708 dev_warn(&dev->dev, "Unable to allocate DMA alias mask\n"); 4709 return; 4710 } 4711 4712 set_bit(devfn, dev->dma_alias_mask); 4713 dev_info(&dev->dev, "Enabling fixed DMA alias to %02x.%d\n", 4714 PCI_SLOT(devfn), PCI_FUNC(devfn)); 4715 } 4716 4717 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2) 4718 { 4719 return (dev1->dma_alias_mask && 4720 test_bit(dev2->devfn, dev1->dma_alias_mask)) || 4721 (dev2->dma_alias_mask && 4722 test_bit(dev1->devfn, dev2->dma_alias_mask)); 4723 } 4724 4725 bool pci_device_is_present(struct pci_dev *pdev) 4726 { 4727 u32 v; 4728 4729 return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0); 4730 } 4731 EXPORT_SYMBOL_GPL(pci_device_is_present); 4732 4733 void pci_ignore_hotplug(struct pci_dev *dev) 4734 { 4735 struct pci_dev *bridge = dev->bus->self; 4736 4737 dev->ignore_hotplug = 1; 4738 /* Propagate the "ignore hotplug" setting to the parent bridge. */ 4739 if (bridge) 4740 bridge->ignore_hotplug = 1; 4741 } 4742 EXPORT_SYMBOL_GPL(pci_ignore_hotplug); 4743 4744 #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE 4745 static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0}; 4746 static DEFINE_SPINLOCK(resource_alignment_lock); 4747 4748 /** 4749 * pci_specified_resource_alignment - get resource alignment specified by user. 4750 * @dev: the PCI device to get 4751 * 4752 * RETURNS: Resource alignment if it is specified. 4753 * Zero if it is not specified. 4754 */ 4755 static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev) 4756 { 4757 int seg, bus, slot, func, align_order, count; 4758 resource_size_t align = 0; 4759 char *p; 4760 4761 spin_lock(&resource_alignment_lock); 4762 p = resource_alignment_param; 4763 while (*p) { 4764 count = 0; 4765 if (sscanf(p, "%d%n", &align_order, &count) == 1 && 4766 p[count] == '@') { 4767 p += count + 1; 4768 } else { 4769 align_order = -1; 4770 } 4771 if (sscanf(p, "%x:%x:%x.%x%n", 4772 &seg, &bus, &slot, &func, &count) != 4) { 4773 seg = 0; 4774 if (sscanf(p, "%x:%x.%x%n", 4775 &bus, &slot, &func, &count) != 3) { 4776 /* Invalid format */ 4777 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n", 4778 p); 4779 break; 4780 } 4781 } 4782 p += count; 4783 if (seg == pci_domain_nr(dev->bus) && 4784 bus == dev->bus->number && 4785 slot == PCI_SLOT(dev->devfn) && 4786 func == PCI_FUNC(dev->devfn)) { 4787 if (align_order == -1) 4788 align = PAGE_SIZE; 4789 else 4790 align = 1 << align_order; 4791 /* Found */ 4792 break; 4793 } 4794 if (*p != ';' && *p != ',') { 4795 /* End of param or invalid format */ 4796 break; 4797 } 4798 p++; 4799 } 4800 spin_unlock(&resource_alignment_lock); 4801 return align; 4802 } 4803 4804 /* 4805 * This function disables memory decoding and releases memory resources 4806 * of the device specified by kernel's boot parameter 'pci=resource_alignment='. 4807 * It also rounds up size to specified alignment. 4808 * Later on, the kernel will assign page-aligned memory resource back 4809 * to the device. 4810 */ 4811 void pci_reassigndev_resource_alignment(struct pci_dev *dev) 4812 { 4813 int i; 4814 struct resource *r; 4815 resource_size_t align, size; 4816 u16 command; 4817 4818 /* check if specified PCI is target device to reassign */ 4819 align = pci_specified_resource_alignment(dev); 4820 if (!align) 4821 return; 4822 4823 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL && 4824 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) { 4825 dev_warn(&dev->dev, 4826 "Can't reassign resources to host bridge.\n"); 4827 return; 4828 } 4829 4830 dev_info(&dev->dev, 4831 "Disabling memory decoding and releasing memory resources.\n"); 4832 pci_read_config_word(dev, PCI_COMMAND, &command); 4833 command &= ~PCI_COMMAND_MEMORY; 4834 pci_write_config_word(dev, PCI_COMMAND, command); 4835 4836 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) { 4837 r = &dev->resource[i]; 4838 if (!(r->flags & IORESOURCE_MEM)) 4839 continue; 4840 size = resource_size(r); 4841 if (size < align) { 4842 size = align; 4843 dev_info(&dev->dev, 4844 "Rounding up size of resource #%d to %#llx.\n", 4845 i, (unsigned long long)size); 4846 } 4847 r->flags |= IORESOURCE_UNSET; 4848 r->end = size - 1; 4849 r->start = 0; 4850 } 4851 /* Need to disable bridge's resource window, 4852 * to enable the kernel to reassign new resource 4853 * window later on. 4854 */ 4855 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE && 4856 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { 4857 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) { 4858 r = &dev->resource[i]; 4859 if (!(r->flags & IORESOURCE_MEM)) 4860 continue; 4861 r->flags |= IORESOURCE_UNSET; 4862 r->end = resource_size(r) - 1; 4863 r->start = 0; 4864 } 4865 pci_disable_bridge_window(dev); 4866 } 4867 } 4868 4869 static ssize_t pci_set_resource_alignment_param(const char *buf, size_t count) 4870 { 4871 if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1) 4872 count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1; 4873 spin_lock(&resource_alignment_lock); 4874 strncpy(resource_alignment_param, buf, count); 4875 resource_alignment_param[count] = '\0'; 4876 spin_unlock(&resource_alignment_lock); 4877 return count; 4878 } 4879 4880 static ssize_t pci_get_resource_alignment_param(char *buf, size_t size) 4881 { 4882 size_t count; 4883 spin_lock(&resource_alignment_lock); 4884 count = snprintf(buf, size, "%s", resource_alignment_param); 4885 spin_unlock(&resource_alignment_lock); 4886 return count; 4887 } 4888 4889 static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf) 4890 { 4891 return pci_get_resource_alignment_param(buf, PAGE_SIZE); 4892 } 4893 4894 static ssize_t pci_resource_alignment_store(struct bus_type *bus, 4895 const char *buf, size_t count) 4896 { 4897 return pci_set_resource_alignment_param(buf, count); 4898 } 4899 4900 BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show, 4901 pci_resource_alignment_store); 4902 4903 static int __init pci_resource_alignment_sysfs_init(void) 4904 { 4905 return bus_create_file(&pci_bus_type, 4906 &bus_attr_resource_alignment); 4907 } 4908 late_initcall(pci_resource_alignment_sysfs_init); 4909 4910 static void pci_no_domains(void) 4911 { 4912 #ifdef CONFIG_PCI_DOMAINS 4913 pci_domains_supported = 0; 4914 #endif 4915 } 4916 4917 #ifdef CONFIG_PCI_DOMAINS 4918 static atomic_t __domain_nr = ATOMIC_INIT(-1); 4919 4920 int pci_get_new_domain_nr(void) 4921 { 4922 return atomic_inc_return(&__domain_nr); 4923 } 4924 4925 #ifdef CONFIG_PCI_DOMAINS_GENERIC 4926 void pci_bus_assign_domain_nr(struct pci_bus *bus, struct device *parent) 4927 { 4928 static int use_dt_domains = -1; 4929 int domain = -1; 4930 4931 if (parent) 4932 domain = of_get_pci_domain_nr(parent->of_node); 4933 /* 4934 * Check DT domain and use_dt_domains values. 4935 * 4936 * If DT domain property is valid (domain >= 0) and 4937 * use_dt_domains != 0, the DT assignment is valid since this means 4938 * we have not previously allocated a domain number by using 4939 * pci_get_new_domain_nr(); we should also update use_dt_domains to 4940 * 1, to indicate that we have just assigned a domain number from 4941 * DT. 4942 * 4943 * If DT domain property value is not valid (ie domain < 0), and we 4944 * have not previously assigned a domain number from DT 4945 * (use_dt_domains != 1) we should assign a domain number by 4946 * using the: 4947 * 4948 * pci_get_new_domain_nr() 4949 * 4950 * API and update the use_dt_domains value to keep track of method we 4951 * are using to assign domain numbers (use_dt_domains = 0). 4952 * 4953 * All other combinations imply we have a platform that is trying 4954 * to mix domain numbers obtained from DT and pci_get_new_domain_nr(), 4955 * which is a recipe for domain mishandling and it is prevented by 4956 * invalidating the domain value (domain = -1) and printing a 4957 * corresponding error. 4958 */ 4959 if (domain >= 0 && use_dt_domains) { 4960 use_dt_domains = 1; 4961 } else if (domain < 0 && use_dt_domains != 1) { 4962 use_dt_domains = 0; 4963 domain = pci_get_new_domain_nr(); 4964 } else { 4965 dev_err(parent, "Node %s has inconsistent \"linux,pci-domain\" property in DT\n", 4966 parent->of_node->full_name); 4967 domain = -1; 4968 } 4969 4970 bus->domain_nr = domain; 4971 } 4972 #endif 4973 #endif 4974 4975 /** 4976 * pci_ext_cfg_avail - can we access extended PCI config space? 4977 * 4978 * Returns 1 if we can access PCI extended config space (offsets 4979 * greater than 0xff). This is the default implementation. Architecture 4980 * implementations can override this. 4981 */ 4982 int __weak pci_ext_cfg_avail(void) 4983 { 4984 return 1; 4985 } 4986 4987 void __weak pci_fixup_cardbus(struct pci_bus *bus) 4988 { 4989 } 4990 EXPORT_SYMBOL(pci_fixup_cardbus); 4991 4992 static int __init pci_setup(char *str) 4993 { 4994 while (str) { 4995 char *k = strchr(str, ','); 4996 if (k) 4997 *k++ = 0; 4998 if (*str && (str = pcibios_setup(str)) && *str) { 4999 if (!strcmp(str, "nomsi")) { 5000 pci_no_msi(); 5001 } else if (!strcmp(str, "noaer")) { 5002 pci_no_aer(); 5003 } else if (!strncmp(str, "realloc=", 8)) { 5004 pci_realloc_get_opt(str + 8); 5005 } else if (!strncmp(str, "realloc", 7)) { 5006 pci_realloc_get_opt("on"); 5007 } else if (!strcmp(str, "nodomains")) { 5008 pci_no_domains(); 5009 } else if (!strncmp(str, "noari", 5)) { 5010 pcie_ari_disabled = true; 5011 } else if (!strncmp(str, "cbiosize=", 9)) { 5012 pci_cardbus_io_size = memparse(str + 9, &str); 5013 } else if (!strncmp(str, "cbmemsize=", 10)) { 5014 pci_cardbus_mem_size = memparse(str + 10, &str); 5015 } else if (!strncmp(str, "resource_alignment=", 19)) { 5016 pci_set_resource_alignment_param(str + 19, 5017 strlen(str + 19)); 5018 } else if (!strncmp(str, "ecrc=", 5)) { 5019 pcie_ecrc_get_policy(str + 5); 5020 } else if (!strncmp(str, "hpiosize=", 9)) { 5021 pci_hotplug_io_size = memparse(str + 9, &str); 5022 } else if (!strncmp(str, "hpmemsize=", 10)) { 5023 pci_hotplug_mem_size = memparse(str + 10, &str); 5024 } else if (!strncmp(str, "pcie_bus_tune_off", 17)) { 5025 pcie_bus_config = PCIE_BUS_TUNE_OFF; 5026 } else if (!strncmp(str, "pcie_bus_safe", 13)) { 5027 pcie_bus_config = PCIE_BUS_SAFE; 5028 } else if (!strncmp(str, "pcie_bus_perf", 13)) { 5029 pcie_bus_config = PCIE_BUS_PERFORMANCE; 5030 } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) { 5031 pcie_bus_config = PCIE_BUS_PEER2PEER; 5032 } else if (!strncmp(str, "pcie_scan_all", 13)) { 5033 pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS); 5034 } else { 5035 printk(KERN_ERR "PCI: Unknown option `%s'\n", 5036 str); 5037 } 5038 } 5039 str = k; 5040 } 5041 return 0; 5042 } 5043 early_param("pci", pci_setup); 5044