1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2018 Marvell 4 * 5 * Author: Thomas Petazzoni <thomas.petazzoni@bootlin.com> 6 * 7 * This file helps PCI controller drivers implement a fake root port 8 * PCI bridge when the HW doesn't provide such a root port PCI 9 * bridge. 10 * 11 * It emulates a PCI bridge by providing a fake PCI configuration 12 * space (and optionally a PCIe capability configuration space) in 13 * memory. By default the read/write operations simply read and update 14 * this fake configuration space in memory. However, PCI controller 15 * drivers can provide through the 'struct pci_sw_bridge_ops' 16 * structure a set of operations to override or complement this 17 * default behavior. 18 */ 19 20 #include <linux/pci.h> 21 #include "pci-bridge-emul.h" 22 23 #define PCI_BRIDGE_CONF_END PCI_STD_HEADER_SIZEOF 24 #define PCI_CAP_PCIE_SIZEOF (PCI_EXP_SLTSTA2 + 2) 25 #define PCI_CAP_PCIE_START PCI_BRIDGE_CONF_END 26 #define PCI_CAP_PCIE_END (PCI_CAP_PCIE_START + PCI_CAP_PCIE_SIZEOF) 27 28 /** 29 * struct pci_bridge_reg_behavior - register bits behaviors 30 * @ro: Read-Only bits 31 * @rw: Read-Write bits 32 * @w1c: Write-1-to-Clear bits 33 * 34 * Reads and Writes will be filtered by specified behavior. All other bits not 35 * declared are assumed 'Reserved' and will return 0 on reads, per PCIe 5.0: 36 * "Reserved register fields must be read only and must return 0 (all 0's for 37 * multi-bit fields) when read". 38 */ 39 struct pci_bridge_reg_behavior { 40 /* Read-only bits */ 41 u32 ro; 42 43 /* Read-write bits */ 44 u32 rw; 45 46 /* Write-1-to-clear bits */ 47 u32 w1c; 48 }; 49 50 static const 51 struct pci_bridge_reg_behavior pci_regs_behavior[PCI_STD_HEADER_SIZEOF / 4] = { 52 [PCI_VENDOR_ID / 4] = { .ro = ~0 }, 53 [PCI_COMMAND / 4] = { 54 .rw = (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | 55 PCI_COMMAND_MASTER | PCI_COMMAND_PARITY | 56 PCI_COMMAND_SERR), 57 .ro = ((PCI_COMMAND_SPECIAL | PCI_COMMAND_INVALIDATE | 58 PCI_COMMAND_VGA_PALETTE | PCI_COMMAND_WAIT | 59 PCI_COMMAND_FAST_BACK) | 60 (PCI_STATUS_CAP_LIST | PCI_STATUS_66MHZ | 61 PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MASK) << 16), 62 .w1c = PCI_STATUS_ERROR_BITS << 16, 63 }, 64 [PCI_CLASS_REVISION / 4] = { .ro = ~0 }, 65 66 /* 67 * Cache Line Size register: implement as read-only, we do not 68 * pretend implementing "Memory Write and Invalidate" 69 * transactions" 70 * 71 * Latency Timer Register: implemented as read-only, as "A 72 * bridge that is not capable of a burst transfer of more than 73 * two data phases on its primary interface is permitted to 74 * hardwire the Latency Timer to a value of 16 or less" 75 * 76 * Header Type: always read-only 77 * 78 * BIST register: implemented as read-only, as "A bridge that 79 * does not support BIST must implement this register as a 80 * read-only register that returns 0 when read" 81 */ 82 [PCI_CACHE_LINE_SIZE / 4] = { .ro = ~0 }, 83 84 /* 85 * Base Address registers not used must be implemented as 86 * read-only registers that return 0 when read. 87 */ 88 [PCI_BASE_ADDRESS_0 / 4] = { .ro = ~0 }, 89 [PCI_BASE_ADDRESS_1 / 4] = { .ro = ~0 }, 90 91 [PCI_PRIMARY_BUS / 4] = { 92 /* Primary, secondary and subordinate bus are RW */ 93 .rw = GENMASK(24, 0), 94 /* Secondary latency is read-only */ 95 .ro = GENMASK(31, 24), 96 }, 97 98 [PCI_IO_BASE / 4] = { 99 /* The high four bits of I/O base/limit are RW */ 100 .rw = (GENMASK(15, 12) | GENMASK(7, 4)), 101 102 /* The low four bits of I/O base/limit are RO */ 103 .ro = (((PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK | 104 PCI_STATUS_DEVSEL_MASK) << 16) | 105 GENMASK(11, 8) | GENMASK(3, 0)), 106 107 .w1c = PCI_STATUS_ERROR_BITS << 16, 108 }, 109 110 [PCI_MEMORY_BASE / 4] = { 111 /* The high 12-bits of mem base/limit are RW */ 112 .rw = GENMASK(31, 20) | GENMASK(15, 4), 113 114 /* The low four bits of mem base/limit are RO */ 115 .ro = GENMASK(19, 16) | GENMASK(3, 0), 116 }, 117 118 [PCI_PREF_MEMORY_BASE / 4] = { 119 /* The high 12-bits of pref mem base/limit are RW */ 120 .rw = GENMASK(31, 20) | GENMASK(15, 4), 121 122 /* The low four bits of pref mem base/limit are RO */ 123 .ro = GENMASK(19, 16) | GENMASK(3, 0), 124 }, 125 126 [PCI_PREF_BASE_UPPER32 / 4] = { 127 .rw = ~0, 128 }, 129 130 [PCI_PREF_LIMIT_UPPER32 / 4] = { 131 .rw = ~0, 132 }, 133 134 [PCI_IO_BASE_UPPER16 / 4] = { 135 .rw = ~0, 136 }, 137 138 [PCI_CAPABILITY_LIST / 4] = { 139 .ro = GENMASK(7, 0), 140 }, 141 142 /* 143 * If expansion ROM is unsupported then ROM Base Address register must 144 * be implemented as read-only register that return 0 when read, same 145 * as for unused Base Address registers. 146 */ 147 [PCI_ROM_ADDRESS1 / 4] = { 148 .ro = ~0, 149 }, 150 151 /* 152 * Interrupt line (bits 7:0) are RW, interrupt pin (bits 15:8) 153 * are RO, and bridge control (31:16) are a mix of RW, RO, 154 * reserved and W1C bits 155 */ 156 [PCI_INTERRUPT_LINE / 4] = { 157 /* Interrupt line is RW */ 158 .rw = (GENMASK(7, 0) | 159 ((PCI_BRIDGE_CTL_PARITY | 160 PCI_BRIDGE_CTL_SERR | 161 PCI_BRIDGE_CTL_ISA | 162 PCI_BRIDGE_CTL_VGA | 163 PCI_BRIDGE_CTL_MASTER_ABORT | 164 PCI_BRIDGE_CTL_BUS_RESET | 165 BIT(8) | BIT(9) | BIT(11)) << 16)), 166 167 /* Interrupt pin is RO */ 168 .ro = (GENMASK(15, 8) | ((PCI_BRIDGE_CTL_FAST_BACK) << 16)), 169 170 .w1c = BIT(10) << 16, 171 }, 172 }; 173 174 static const 175 struct pci_bridge_reg_behavior pcie_cap_regs_behavior[PCI_CAP_PCIE_SIZEOF / 4] = { 176 [PCI_CAP_LIST_ID / 4] = { 177 /* 178 * Capability ID, Next Capability Pointer and 179 * bits [14:0] of Capabilities register are all read-only. 180 * Bit 15 of Capabilities register is reserved. 181 */ 182 .ro = GENMASK(30, 0), 183 }, 184 185 [PCI_EXP_DEVCAP / 4] = { 186 /* 187 * Bits [31:29] and [17:16] are reserved. 188 * Bits [27:18] are reserved for non-upstream ports. 189 * Bits 28 and [14:6] are reserved for non-endpoint devices. 190 * Other bits are read-only. 191 */ 192 .ro = BIT(15) | GENMASK(5, 0), 193 }, 194 195 [PCI_EXP_DEVCTL / 4] = { 196 /* 197 * Device control register is RW, except bit 15 which is 198 * reserved for non-endpoints or non-PCIe-to-PCI/X bridges. 199 */ 200 .rw = GENMASK(14, 0), 201 202 /* 203 * Device status register has bits 6 and [3:0] W1C, [5:4] RO, 204 * the rest is reserved. Also bit 6 is reserved for non-upstream 205 * ports. 206 */ 207 .w1c = GENMASK(3, 0) << 16, 208 .ro = GENMASK(5, 4) << 16, 209 }, 210 211 [PCI_EXP_LNKCAP / 4] = { 212 /* 213 * All bits are RO, except bit 23 which is reserved and 214 * bit 18 which is reserved for non-upstream ports. 215 */ 216 .ro = lower_32_bits(~(BIT(23) | PCI_EXP_LNKCAP_CLKPM)), 217 }, 218 219 [PCI_EXP_LNKCTL / 4] = { 220 /* 221 * Link control has bits [15:14], [11:3] and [1:0] RW, the 222 * rest is reserved. Bit 8 is reserved for non-upstream ports. 223 * 224 * Link status has bits [13:0] RO, and bits [15:14] 225 * W1C. 226 */ 227 .rw = GENMASK(15, 14) | GENMASK(11, 9) | GENMASK(7, 3) | GENMASK(1, 0), 228 .ro = GENMASK(13, 0) << 16, 229 .w1c = GENMASK(15, 14) << 16, 230 }, 231 232 [PCI_EXP_SLTCAP / 4] = { 233 .ro = ~0, 234 }, 235 236 [PCI_EXP_SLTCTL / 4] = { 237 /* 238 * Slot control has bits [14:0] RW, the rest is 239 * reserved. 240 * 241 * Slot status has bits 8 and [4:0] W1C, bits [7:5] RO, the 242 * rest is reserved. 243 */ 244 .rw = GENMASK(14, 0), 245 .w1c = (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD | 246 PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC | 247 PCI_EXP_SLTSTA_CC | PCI_EXP_SLTSTA_DLLSC) << 16, 248 .ro = (PCI_EXP_SLTSTA_MRLSS | PCI_EXP_SLTSTA_PDS | 249 PCI_EXP_SLTSTA_EIS) << 16, 250 }, 251 252 [PCI_EXP_RTCTL / 4] = { 253 /* 254 * Root control has bits [4:0] RW, the rest is 255 * reserved. 256 * 257 * Root capabilities has bit 0 RO, the rest is reserved. 258 */ 259 .rw = (PCI_EXP_RTCTL_SECEE | PCI_EXP_RTCTL_SENFEE | 260 PCI_EXP_RTCTL_SEFEE | PCI_EXP_RTCTL_PMEIE | 261 PCI_EXP_RTCTL_CRSSVE), 262 .ro = PCI_EXP_RTCAP_CRSVIS << 16, 263 }, 264 265 [PCI_EXP_RTSTA / 4] = { 266 /* 267 * Root status has bits 17 and [15:0] RO, bit 16 W1C, the rest 268 * is reserved. 269 */ 270 .ro = GENMASK(15, 0) | PCI_EXP_RTSTA_PENDING, 271 .w1c = PCI_EXP_RTSTA_PME, 272 }, 273 274 [PCI_EXP_DEVCAP2 / 4] = { 275 /* 276 * Device capabilities 2 register has reserved bits [30:27]. 277 * Also bits [26:24] are reserved for non-upstream ports. 278 */ 279 .ro = BIT(31) | GENMASK(23, 0), 280 }, 281 282 [PCI_EXP_DEVCTL2 / 4] = { 283 /* 284 * Device control 2 register is RW. Bit 11 is reserved for 285 * non-upstream ports. 286 * 287 * Device status 2 register is reserved. 288 */ 289 .rw = GENMASK(15, 12) | GENMASK(10, 0), 290 }, 291 292 [PCI_EXP_LNKCAP2 / 4] = { 293 /* Link capabilities 2 register has reserved bits [30:25] and 0. */ 294 .ro = BIT(31) | GENMASK(24, 1), 295 }, 296 297 [PCI_EXP_LNKCTL2 / 4] = { 298 /* 299 * Link control 2 register is RW. 300 * 301 * Link status 2 register has bits 5, 15 W1C; 302 * bits 10, 11 reserved and others are RO. 303 */ 304 .rw = GENMASK(15, 0), 305 .w1c = (BIT(15) | BIT(5)) << 16, 306 .ro = (GENMASK(14, 12) | GENMASK(9, 6) | GENMASK(4, 0)) << 16, 307 }, 308 309 [PCI_EXP_SLTCAP2 / 4] = { 310 /* Slot capabilities 2 register is reserved. */ 311 }, 312 313 [PCI_EXP_SLTCTL2 / 4] = { 314 /* Both Slot control 2 and Slot status 2 registers are reserved. */ 315 }, 316 }; 317 318 /* 319 * Initialize a pci_bridge_emul structure to represent a fake PCI 320 * bridge configuration space. The caller needs to have initialized 321 * the PCI configuration space with whatever values make sense 322 * (typically at least vendor, device, revision), the ->ops pointer, 323 * and optionally ->data and ->has_pcie. 324 */ 325 int pci_bridge_emul_init(struct pci_bridge_emul *bridge, 326 unsigned int flags) 327 { 328 BUILD_BUG_ON(sizeof(bridge->conf) != PCI_BRIDGE_CONF_END); 329 330 /* 331 * class_revision: Class is high 24 bits and revision is low 8 bit of this member, 332 * while class for PCI Bridge Normal Decode has the 24-bit value: PCI_CLASS_BRIDGE_PCI << 8 333 */ 334 bridge->conf.class_revision |= cpu_to_le32((PCI_CLASS_BRIDGE_PCI << 8) << 8); 335 bridge->conf.header_type = PCI_HEADER_TYPE_BRIDGE; 336 bridge->conf.cache_line_size = 0x10; 337 bridge->conf.status = cpu_to_le16(PCI_STATUS_CAP_LIST); 338 bridge->pci_regs_behavior = kmemdup(pci_regs_behavior, 339 sizeof(pci_regs_behavior), 340 GFP_KERNEL); 341 if (!bridge->pci_regs_behavior) 342 return -ENOMEM; 343 344 if (bridge->has_pcie) { 345 bridge->conf.capabilities_pointer = PCI_CAP_PCIE_START; 346 bridge->conf.status |= cpu_to_le16(PCI_STATUS_CAP_LIST); 347 bridge->pcie_conf.cap_id = PCI_CAP_ID_EXP; 348 bridge->pcie_conf.cap |= cpu_to_le16(PCI_EXP_TYPE_ROOT_PORT << 4); 349 bridge->pcie_cap_regs_behavior = 350 kmemdup(pcie_cap_regs_behavior, 351 sizeof(pcie_cap_regs_behavior), 352 GFP_KERNEL); 353 if (!bridge->pcie_cap_regs_behavior) { 354 kfree(bridge->pci_regs_behavior); 355 return -ENOMEM; 356 } 357 /* These bits are applicable only for PCI and reserved on PCIe */ 358 bridge->pci_regs_behavior[PCI_CACHE_LINE_SIZE / 4].ro &= 359 ~GENMASK(15, 8); 360 bridge->pci_regs_behavior[PCI_COMMAND / 4].ro &= 361 ~((PCI_COMMAND_SPECIAL | PCI_COMMAND_INVALIDATE | 362 PCI_COMMAND_VGA_PALETTE | PCI_COMMAND_WAIT | 363 PCI_COMMAND_FAST_BACK) | 364 (PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK | 365 PCI_STATUS_DEVSEL_MASK) << 16); 366 bridge->pci_regs_behavior[PCI_PRIMARY_BUS / 4].ro &= 367 ~GENMASK(31, 24); 368 bridge->pci_regs_behavior[PCI_IO_BASE / 4].ro &= 369 ~((PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK | 370 PCI_STATUS_DEVSEL_MASK) << 16); 371 bridge->pci_regs_behavior[PCI_INTERRUPT_LINE / 4].rw &= 372 ~((PCI_BRIDGE_CTL_MASTER_ABORT | 373 BIT(8) | BIT(9) | BIT(11)) << 16); 374 bridge->pci_regs_behavior[PCI_INTERRUPT_LINE / 4].ro &= 375 ~((PCI_BRIDGE_CTL_FAST_BACK) << 16); 376 bridge->pci_regs_behavior[PCI_INTERRUPT_LINE / 4].w1c &= 377 ~(BIT(10) << 16); 378 } 379 380 if (flags & PCI_BRIDGE_EMUL_NO_PREFETCHABLE_BAR) { 381 bridge->pci_regs_behavior[PCI_PREF_MEMORY_BASE / 4].ro = ~0; 382 bridge->pci_regs_behavior[PCI_PREF_MEMORY_BASE / 4].rw = 0; 383 } 384 385 return 0; 386 } 387 EXPORT_SYMBOL_GPL(pci_bridge_emul_init); 388 389 /* 390 * Cleanup a pci_bridge_emul structure that was previously initialized 391 * using pci_bridge_emul_init(). 392 */ 393 void pci_bridge_emul_cleanup(struct pci_bridge_emul *bridge) 394 { 395 if (bridge->has_pcie) 396 kfree(bridge->pcie_cap_regs_behavior); 397 kfree(bridge->pci_regs_behavior); 398 } 399 EXPORT_SYMBOL_GPL(pci_bridge_emul_cleanup); 400 401 /* 402 * Should be called by the PCI controller driver when reading the PCI 403 * configuration space of the fake bridge. It will call back the 404 * ->ops->read_base or ->ops->read_pcie operations. 405 */ 406 int pci_bridge_emul_conf_read(struct pci_bridge_emul *bridge, int where, 407 int size, u32 *value) 408 { 409 int ret; 410 int reg = where & ~3; 411 pci_bridge_emul_read_status_t (*read_op)(struct pci_bridge_emul *bridge, 412 int reg, u32 *value); 413 __le32 *cfgspace; 414 const struct pci_bridge_reg_behavior *behavior; 415 416 if (bridge->has_pcie && reg >= PCI_CAP_PCIE_END) { 417 *value = 0; 418 return PCIBIOS_SUCCESSFUL; 419 } 420 421 if (!bridge->has_pcie && reg >= PCI_BRIDGE_CONF_END) { 422 *value = 0; 423 return PCIBIOS_SUCCESSFUL; 424 } 425 426 if (bridge->has_pcie && reg >= PCI_CAP_PCIE_START) { 427 reg -= PCI_CAP_PCIE_START; 428 read_op = bridge->ops->read_pcie; 429 cfgspace = (__le32 *) &bridge->pcie_conf; 430 behavior = bridge->pcie_cap_regs_behavior; 431 } else { 432 read_op = bridge->ops->read_base; 433 cfgspace = (__le32 *) &bridge->conf; 434 behavior = bridge->pci_regs_behavior; 435 } 436 437 if (read_op) 438 ret = read_op(bridge, reg, value); 439 else 440 ret = PCI_BRIDGE_EMUL_NOT_HANDLED; 441 442 if (ret == PCI_BRIDGE_EMUL_NOT_HANDLED) 443 *value = le32_to_cpu(cfgspace[reg / 4]); 444 445 /* 446 * Make sure we never return any reserved bit with a value 447 * different from 0. 448 */ 449 *value &= behavior[reg / 4].ro | behavior[reg / 4].rw | 450 behavior[reg / 4].w1c; 451 452 if (size == 1) 453 *value = (*value >> (8 * (where & 3))) & 0xff; 454 else if (size == 2) 455 *value = (*value >> (8 * (where & 3))) & 0xffff; 456 else if (size != 4) 457 return PCIBIOS_BAD_REGISTER_NUMBER; 458 459 return PCIBIOS_SUCCESSFUL; 460 } 461 EXPORT_SYMBOL_GPL(pci_bridge_emul_conf_read); 462 463 /* 464 * Should be called by the PCI controller driver when writing the PCI 465 * configuration space of the fake bridge. It will call back the 466 * ->ops->write_base or ->ops->write_pcie operations. 467 */ 468 int pci_bridge_emul_conf_write(struct pci_bridge_emul *bridge, int where, 469 int size, u32 value) 470 { 471 int reg = where & ~3; 472 int mask, ret, old, new, shift; 473 void (*write_op)(struct pci_bridge_emul *bridge, int reg, 474 u32 old, u32 new, u32 mask); 475 __le32 *cfgspace; 476 const struct pci_bridge_reg_behavior *behavior; 477 478 if (bridge->has_pcie && reg >= PCI_CAP_PCIE_END) 479 return PCIBIOS_SUCCESSFUL; 480 481 if (!bridge->has_pcie && reg >= PCI_BRIDGE_CONF_END) 482 return PCIBIOS_SUCCESSFUL; 483 484 shift = (where & 0x3) * 8; 485 486 if (size == 4) 487 mask = 0xffffffff; 488 else if (size == 2) 489 mask = 0xffff << shift; 490 else if (size == 1) 491 mask = 0xff << shift; 492 else 493 return PCIBIOS_BAD_REGISTER_NUMBER; 494 495 ret = pci_bridge_emul_conf_read(bridge, reg, 4, &old); 496 if (ret != PCIBIOS_SUCCESSFUL) 497 return ret; 498 499 if (bridge->has_pcie && reg >= PCI_CAP_PCIE_START) { 500 reg -= PCI_CAP_PCIE_START; 501 write_op = bridge->ops->write_pcie; 502 cfgspace = (__le32 *) &bridge->pcie_conf; 503 behavior = bridge->pcie_cap_regs_behavior; 504 } else { 505 write_op = bridge->ops->write_base; 506 cfgspace = (__le32 *) &bridge->conf; 507 behavior = bridge->pci_regs_behavior; 508 } 509 510 /* Keep all bits, except the RW bits */ 511 new = old & (~mask | ~behavior[reg / 4].rw); 512 513 /* Update the value of the RW bits */ 514 new |= (value << shift) & (behavior[reg / 4].rw & mask); 515 516 /* Clear the W1C bits */ 517 new &= ~((value << shift) & (behavior[reg / 4].w1c & mask)); 518 519 /* Save the new value with the cleared W1C bits into the cfgspace */ 520 cfgspace[reg / 4] = cpu_to_le32(new); 521 522 /* 523 * Clear the W1C bits not specified by the write mask, so that the 524 * write_op() does not clear them. 525 */ 526 new &= ~(behavior[reg / 4].w1c & ~mask); 527 528 /* 529 * Set the W1C bits specified by the write mask, so that write_op() 530 * knows about that they are to be cleared. 531 */ 532 new |= (value << shift) & (behavior[reg / 4].w1c & mask); 533 534 if (write_op) 535 write_op(bridge, reg, old, new, mask); 536 537 return PCIBIOS_SUCCESSFUL; 538 } 539 EXPORT_SYMBOL_GPL(pci_bridge_emul_conf_write); 540