1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2018 Marvell 4 * 5 * Author: Thomas Petazzoni <thomas.petazzoni@bootlin.com> 6 * 7 * This file helps PCI controller drivers implement a fake root port 8 * PCI bridge when the HW doesn't provide such a root port PCI 9 * bridge. 10 * 11 * It emulates a PCI bridge by providing a fake PCI configuration 12 * space (and optionally a PCIe capability configuration space) in 13 * memory. By default the read/write operations simply read and update 14 * this fake configuration space in memory. However, PCI controller 15 * drivers can provide through the 'struct pci_sw_bridge_ops' 16 * structure a set of operations to override or complement this 17 * default behavior. 18 */ 19 20 #include <linux/pci.h> 21 #include "pci-bridge-emul.h" 22 23 #define PCI_BRIDGE_CONF_END PCI_STD_HEADER_SIZEOF 24 #define PCI_CAP_PCIE_START PCI_BRIDGE_CONF_END 25 #define PCI_CAP_PCIE_END (PCI_CAP_PCIE_START + PCI_EXP_SLTSTA2 + 2) 26 27 struct pci_bridge_reg_behavior { 28 /* Read-only bits */ 29 u32 ro; 30 31 /* Read-write bits */ 32 u32 rw; 33 34 /* Write-1-to-clear bits */ 35 u32 w1c; 36 37 /* Reserved bits (hardwired to 0) */ 38 u32 rsvd; 39 }; 40 41 static const struct pci_bridge_reg_behavior pci_regs_behavior[] = { 42 [PCI_VENDOR_ID / 4] = { .ro = ~0 }, 43 [PCI_COMMAND / 4] = { 44 .rw = (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | 45 PCI_COMMAND_MASTER | PCI_COMMAND_PARITY | 46 PCI_COMMAND_SERR), 47 .ro = ((PCI_COMMAND_SPECIAL | PCI_COMMAND_INVALIDATE | 48 PCI_COMMAND_VGA_PALETTE | PCI_COMMAND_WAIT | 49 PCI_COMMAND_FAST_BACK) | 50 (PCI_STATUS_CAP_LIST | PCI_STATUS_66MHZ | 51 PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MASK) << 16), 52 .rsvd = GENMASK(15, 10) | ((BIT(6) | GENMASK(3, 0)) << 16), 53 .w1c = PCI_STATUS_ERROR_BITS << 16, 54 }, 55 [PCI_CLASS_REVISION / 4] = { .ro = ~0 }, 56 57 /* 58 * Cache Line Size register: implement as read-only, we do not 59 * pretend implementing "Memory Write and Invalidate" 60 * transactions" 61 * 62 * Latency Timer Register: implemented as read-only, as "A 63 * bridge that is not capable of a burst transfer of more than 64 * two data phases on its primary interface is permitted to 65 * hardwire the Latency Timer to a value of 16 or less" 66 * 67 * Header Type: always read-only 68 * 69 * BIST register: implemented as read-only, as "A bridge that 70 * does not support BIST must implement this register as a 71 * read-only register that returns 0 when read" 72 */ 73 [PCI_CACHE_LINE_SIZE / 4] = { .ro = ~0 }, 74 75 /* 76 * Base Address registers not used must be implemented as 77 * read-only registers that return 0 when read. 78 */ 79 [PCI_BASE_ADDRESS_0 / 4] = { .ro = ~0 }, 80 [PCI_BASE_ADDRESS_1 / 4] = { .ro = ~0 }, 81 82 [PCI_PRIMARY_BUS / 4] = { 83 /* Primary, secondary and subordinate bus are RW */ 84 .rw = GENMASK(24, 0), 85 /* Secondary latency is read-only */ 86 .ro = GENMASK(31, 24), 87 }, 88 89 [PCI_IO_BASE / 4] = { 90 /* The high four bits of I/O base/limit are RW */ 91 .rw = (GENMASK(15, 12) | GENMASK(7, 4)), 92 93 /* The low four bits of I/O base/limit are RO */ 94 .ro = (((PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK | 95 PCI_STATUS_DEVSEL_MASK) << 16) | 96 GENMASK(11, 8) | GENMASK(3, 0)), 97 98 .w1c = PCI_STATUS_ERROR_BITS << 16, 99 100 .rsvd = ((BIT(6) | GENMASK(4, 0)) << 16), 101 }, 102 103 [PCI_MEMORY_BASE / 4] = { 104 /* The high 12-bits of mem base/limit are RW */ 105 .rw = GENMASK(31, 20) | GENMASK(15, 4), 106 107 /* The low four bits of mem base/limit are RO */ 108 .ro = GENMASK(19, 16) | GENMASK(3, 0), 109 }, 110 111 [PCI_PREF_MEMORY_BASE / 4] = { 112 /* The high 12-bits of pref mem base/limit are RW */ 113 .rw = GENMASK(31, 20) | GENMASK(15, 4), 114 115 /* The low four bits of pref mem base/limit are RO */ 116 .ro = GENMASK(19, 16) | GENMASK(3, 0), 117 }, 118 119 [PCI_PREF_BASE_UPPER32 / 4] = { 120 .rw = ~0, 121 }, 122 123 [PCI_PREF_LIMIT_UPPER32 / 4] = { 124 .rw = ~0, 125 }, 126 127 [PCI_IO_BASE_UPPER16 / 4] = { 128 .rw = ~0, 129 }, 130 131 [PCI_CAPABILITY_LIST / 4] = { 132 .ro = GENMASK(7, 0), 133 .rsvd = GENMASK(31, 8), 134 }, 135 136 [PCI_ROM_ADDRESS1 / 4] = { 137 .rw = GENMASK(31, 11) | BIT(0), 138 .rsvd = GENMASK(10, 1), 139 }, 140 141 /* 142 * Interrupt line (bits 7:0) are RW, interrupt pin (bits 15:8) 143 * are RO, and bridge control (31:16) are a mix of RW, RO, 144 * reserved and W1C bits 145 */ 146 [PCI_INTERRUPT_LINE / 4] = { 147 /* Interrupt line is RW */ 148 .rw = (GENMASK(7, 0) | 149 ((PCI_BRIDGE_CTL_PARITY | 150 PCI_BRIDGE_CTL_SERR | 151 PCI_BRIDGE_CTL_ISA | 152 PCI_BRIDGE_CTL_VGA | 153 PCI_BRIDGE_CTL_MASTER_ABORT | 154 PCI_BRIDGE_CTL_BUS_RESET | 155 BIT(8) | BIT(9) | BIT(11)) << 16)), 156 157 /* Interrupt pin is RO */ 158 .ro = (GENMASK(15, 8) | ((PCI_BRIDGE_CTL_FAST_BACK) << 16)), 159 160 .w1c = BIT(10) << 16, 161 162 .rsvd = (GENMASK(15, 12) | BIT(4)) << 16, 163 }, 164 }; 165 166 static const struct pci_bridge_reg_behavior pcie_cap_regs_behavior[] = { 167 [PCI_CAP_LIST_ID / 4] = { 168 /* 169 * Capability ID, Next Capability Pointer and 170 * Capabilities register are all read-only. 171 */ 172 .ro = ~0, 173 }, 174 175 [PCI_EXP_DEVCAP / 4] = { 176 .ro = ~0, 177 }, 178 179 [PCI_EXP_DEVCTL / 4] = { 180 /* Device control register is RW */ 181 .rw = GENMASK(15, 0), 182 183 /* 184 * Device status register has 4 bits W1C, then 2 bits 185 * RO, the rest is reserved 186 */ 187 .w1c = GENMASK(19, 16), 188 .ro = GENMASK(20, 19), 189 .rsvd = GENMASK(31, 21), 190 }, 191 192 [PCI_EXP_LNKCAP / 4] = { 193 /* All bits are RO, except bit 23 which is reserved */ 194 .ro = lower_32_bits(~BIT(23)), 195 .rsvd = BIT(23), 196 }, 197 198 [PCI_EXP_LNKCTL / 4] = { 199 /* 200 * Link control has bits [1:0] and [11:3] RW, the 201 * other bits are reserved. 202 * Link status has bits [13:0] RO, and bits [14:15] 203 * W1C. 204 */ 205 .rw = GENMASK(11, 3) | GENMASK(1, 0), 206 .ro = GENMASK(13, 0) << 16, 207 .w1c = GENMASK(15, 14) << 16, 208 .rsvd = GENMASK(15, 12) | BIT(2), 209 }, 210 211 [PCI_EXP_SLTCAP / 4] = { 212 .ro = ~0, 213 }, 214 215 [PCI_EXP_SLTCTL / 4] = { 216 /* 217 * Slot control has bits [12:0] RW, the rest is 218 * reserved. 219 * 220 * Slot status has a mix of W1C and RO bits, as well 221 * as reserved bits. 222 */ 223 .rw = GENMASK(12, 0), 224 .w1c = (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD | 225 PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC | 226 PCI_EXP_SLTSTA_CC | PCI_EXP_SLTSTA_DLLSC) << 16, 227 .ro = (PCI_EXP_SLTSTA_MRLSS | PCI_EXP_SLTSTA_PDS | 228 PCI_EXP_SLTSTA_EIS) << 16, 229 .rsvd = GENMASK(15, 12) | (GENMASK(15, 9) << 16), 230 }, 231 232 [PCI_EXP_RTCTL / 4] = { 233 /* 234 * Root control has bits [4:0] RW, the rest is 235 * reserved. 236 * 237 * Root status has bit 0 RO, the rest is reserved. 238 */ 239 .rw = (PCI_EXP_RTCTL_SECEE | PCI_EXP_RTCTL_SENFEE | 240 PCI_EXP_RTCTL_SEFEE | PCI_EXP_RTCTL_PMEIE | 241 PCI_EXP_RTCTL_CRSSVE), 242 .ro = PCI_EXP_RTCAP_CRSVIS << 16, 243 .rsvd = GENMASK(15, 5) | (GENMASK(15, 1) << 16), 244 }, 245 246 [PCI_EXP_RTSTA / 4] = { 247 .ro = GENMASK(15, 0) | PCI_EXP_RTSTA_PENDING, 248 .w1c = PCI_EXP_RTSTA_PME, 249 .rsvd = GENMASK(31, 18), 250 }, 251 }; 252 253 /* 254 * Initialize a pci_bridge_emul structure to represent a fake PCI 255 * bridge configuration space. The caller needs to have initialized 256 * the PCI configuration space with whatever values make sense 257 * (typically at least vendor, device, revision), the ->ops pointer, 258 * and optionally ->data and ->has_pcie. 259 */ 260 int pci_bridge_emul_init(struct pci_bridge_emul *bridge, 261 unsigned int flags) 262 { 263 bridge->conf.class_revision |= cpu_to_le32(PCI_CLASS_BRIDGE_PCI << 16); 264 bridge->conf.header_type = PCI_HEADER_TYPE_BRIDGE; 265 bridge->conf.cache_line_size = 0x10; 266 bridge->conf.status = cpu_to_le16(PCI_STATUS_CAP_LIST); 267 bridge->pci_regs_behavior = kmemdup(pci_regs_behavior, 268 sizeof(pci_regs_behavior), 269 GFP_KERNEL); 270 if (!bridge->pci_regs_behavior) 271 return -ENOMEM; 272 273 if (bridge->has_pcie) { 274 bridge->conf.capabilities_pointer = PCI_CAP_PCIE_START; 275 bridge->pcie_conf.cap_id = PCI_CAP_ID_EXP; 276 /* Set PCIe v2, root port, slot support */ 277 bridge->pcie_conf.cap = 278 cpu_to_le16(PCI_EXP_TYPE_ROOT_PORT << 4 | 2 | 279 PCI_EXP_FLAGS_SLOT); 280 bridge->pcie_cap_regs_behavior = 281 kmemdup(pcie_cap_regs_behavior, 282 sizeof(pcie_cap_regs_behavior), 283 GFP_KERNEL); 284 if (!bridge->pcie_cap_regs_behavior) { 285 kfree(bridge->pci_regs_behavior); 286 return -ENOMEM; 287 } 288 } 289 290 if (flags & PCI_BRIDGE_EMUL_NO_PREFETCHABLE_BAR) { 291 bridge->pci_regs_behavior[PCI_PREF_MEMORY_BASE / 4].ro = ~0; 292 bridge->pci_regs_behavior[PCI_PREF_MEMORY_BASE / 4].rw = 0; 293 } 294 295 return 0; 296 } 297 298 /* 299 * Cleanup a pci_bridge_emul structure that was previously initialized 300 * using pci_bridge_emul_init(). 301 */ 302 void pci_bridge_emul_cleanup(struct pci_bridge_emul *bridge) 303 { 304 if (bridge->has_pcie) 305 kfree(bridge->pcie_cap_regs_behavior); 306 kfree(bridge->pci_regs_behavior); 307 } 308 309 /* 310 * Should be called by the PCI controller driver when reading the PCI 311 * configuration space of the fake bridge. It will call back the 312 * ->ops->read_base or ->ops->read_pcie operations. 313 */ 314 int pci_bridge_emul_conf_read(struct pci_bridge_emul *bridge, int where, 315 int size, u32 *value) 316 { 317 int ret; 318 int reg = where & ~3; 319 pci_bridge_emul_read_status_t (*read_op)(struct pci_bridge_emul *bridge, 320 int reg, u32 *value); 321 __le32 *cfgspace; 322 const struct pci_bridge_reg_behavior *behavior; 323 324 if (bridge->has_pcie && reg >= PCI_CAP_PCIE_END) { 325 *value = 0; 326 return PCIBIOS_SUCCESSFUL; 327 } 328 329 if (!bridge->has_pcie && reg >= PCI_BRIDGE_CONF_END) { 330 *value = 0; 331 return PCIBIOS_SUCCESSFUL; 332 } 333 334 if (bridge->has_pcie && reg >= PCI_CAP_PCIE_START) { 335 reg -= PCI_CAP_PCIE_START; 336 read_op = bridge->ops->read_pcie; 337 cfgspace = (__le32 *) &bridge->pcie_conf; 338 behavior = bridge->pcie_cap_regs_behavior; 339 } else { 340 read_op = bridge->ops->read_base; 341 cfgspace = (__le32 *) &bridge->conf; 342 behavior = bridge->pci_regs_behavior; 343 } 344 345 if (read_op) 346 ret = read_op(bridge, reg, value); 347 else 348 ret = PCI_BRIDGE_EMUL_NOT_HANDLED; 349 350 if (ret == PCI_BRIDGE_EMUL_NOT_HANDLED) 351 *value = le32_to_cpu(cfgspace[reg / 4]); 352 353 /* 354 * Make sure we never return any reserved bit with a value 355 * different from 0. 356 */ 357 *value &= ~behavior[reg / 4].rsvd; 358 359 if (size == 1) 360 *value = (*value >> (8 * (where & 3))) & 0xff; 361 else if (size == 2) 362 *value = (*value >> (8 * (where & 3))) & 0xffff; 363 else if (size != 4) 364 return PCIBIOS_BAD_REGISTER_NUMBER; 365 366 return PCIBIOS_SUCCESSFUL; 367 } 368 369 /* 370 * Should be called by the PCI controller driver when writing the PCI 371 * configuration space of the fake bridge. It will call back the 372 * ->ops->write_base or ->ops->write_pcie operations. 373 */ 374 int pci_bridge_emul_conf_write(struct pci_bridge_emul *bridge, int where, 375 int size, u32 value) 376 { 377 int reg = where & ~3; 378 int mask, ret, old, new, shift; 379 void (*write_op)(struct pci_bridge_emul *bridge, int reg, 380 u32 old, u32 new, u32 mask); 381 __le32 *cfgspace; 382 const struct pci_bridge_reg_behavior *behavior; 383 384 if (bridge->has_pcie && reg >= PCI_CAP_PCIE_END) 385 return PCIBIOS_SUCCESSFUL; 386 387 if (!bridge->has_pcie && reg >= PCI_BRIDGE_CONF_END) 388 return PCIBIOS_SUCCESSFUL; 389 390 shift = (where & 0x3) * 8; 391 392 if (size == 4) 393 mask = 0xffffffff; 394 else if (size == 2) 395 mask = 0xffff << shift; 396 else if (size == 1) 397 mask = 0xff << shift; 398 else 399 return PCIBIOS_BAD_REGISTER_NUMBER; 400 401 ret = pci_bridge_emul_conf_read(bridge, reg, 4, &old); 402 if (ret != PCIBIOS_SUCCESSFUL) 403 return ret; 404 405 if (bridge->has_pcie && reg >= PCI_CAP_PCIE_START) { 406 reg -= PCI_CAP_PCIE_START; 407 write_op = bridge->ops->write_pcie; 408 cfgspace = (__le32 *) &bridge->pcie_conf; 409 behavior = bridge->pcie_cap_regs_behavior; 410 } else { 411 write_op = bridge->ops->write_base; 412 cfgspace = (__le32 *) &bridge->conf; 413 behavior = bridge->pci_regs_behavior; 414 } 415 416 /* Keep all bits, except the RW bits */ 417 new = old & (~mask | ~behavior[reg / 4].rw); 418 419 /* Update the value of the RW bits */ 420 new |= (value << shift) & (behavior[reg / 4].rw & mask); 421 422 /* Clear the W1C bits */ 423 new &= ~((value << shift) & (behavior[reg / 4].w1c & mask)); 424 425 cfgspace[reg / 4] = cpu_to_le32(new); 426 427 if (write_op) 428 write_op(bridge, reg, old, new, mask); 429 430 return PCIBIOS_SUCCESSFUL; 431 } 432