1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2018 Marvell 4 * 5 * Author: Thomas Petazzoni <thomas.petazzoni@bootlin.com> 6 * 7 * This file helps PCI controller drivers implement a fake root port 8 * PCI bridge when the HW doesn't provide such a root port PCI 9 * bridge. 10 * 11 * It emulates a PCI bridge by providing a fake PCI configuration 12 * space (and optionally a PCIe capability configuration space) in 13 * memory. By default the read/write operations simply read and update 14 * this fake configuration space in memory. However, PCI controller 15 * drivers can provide through the 'struct pci_sw_bridge_ops' 16 * structure a set of operations to override or complement this 17 * default behavior. 18 */ 19 20 #include <linux/pci.h> 21 #include "pci-bridge-emul.h" 22 23 #define PCI_BRIDGE_CONF_END PCI_STD_HEADER_SIZEOF 24 #define PCI_CAP_PCIE_START PCI_BRIDGE_CONF_END 25 #define PCI_CAP_PCIE_END (PCI_CAP_PCIE_START + PCI_EXP_SLTSTA2 + 2) 26 27 struct pci_bridge_reg_behavior { 28 /* Read-only bits */ 29 u32 ro; 30 31 /* Read-write bits */ 32 u32 rw; 33 34 /* Write-1-to-clear bits */ 35 u32 w1c; 36 37 /* Reserved bits (hardwired to 0) */ 38 u32 rsvd; 39 }; 40 41 const static struct pci_bridge_reg_behavior pci_regs_behavior[] = { 42 [PCI_VENDOR_ID / 4] = { .ro = ~0 }, 43 [PCI_COMMAND / 4] = { 44 .rw = (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | 45 PCI_COMMAND_MASTER | PCI_COMMAND_PARITY | 46 PCI_COMMAND_SERR), 47 .ro = ((PCI_COMMAND_SPECIAL | PCI_COMMAND_INVALIDATE | 48 PCI_COMMAND_VGA_PALETTE | PCI_COMMAND_WAIT | 49 PCI_COMMAND_FAST_BACK) | 50 (PCI_STATUS_CAP_LIST | PCI_STATUS_66MHZ | 51 PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MASK) << 16), 52 .rsvd = GENMASK(15, 10) | ((BIT(6) | GENMASK(3, 0)) << 16), 53 .w1c = (PCI_STATUS_PARITY | 54 PCI_STATUS_SIG_TARGET_ABORT | 55 PCI_STATUS_REC_TARGET_ABORT | 56 PCI_STATUS_REC_MASTER_ABORT | 57 PCI_STATUS_SIG_SYSTEM_ERROR | 58 PCI_STATUS_DETECTED_PARITY) << 16, 59 }, 60 [PCI_CLASS_REVISION / 4] = { .ro = ~0 }, 61 62 /* 63 * Cache Line Size register: implement as read-only, we do not 64 * pretend implementing "Memory Write and Invalidate" 65 * transactions" 66 * 67 * Latency Timer Register: implemented as read-only, as "A 68 * bridge that is not capable of a burst transfer of more than 69 * two data phases on its primary interface is permitted to 70 * hardwire the Latency Timer to a value of 16 or less" 71 * 72 * Header Type: always read-only 73 * 74 * BIST register: implemented as read-only, as "A bridge that 75 * does not support BIST must implement this register as a 76 * read-only register that returns 0 when read" 77 */ 78 [PCI_CACHE_LINE_SIZE / 4] = { .ro = ~0 }, 79 80 /* 81 * Base Address registers not used must be implemented as 82 * read-only registers that return 0 when read. 83 */ 84 [PCI_BASE_ADDRESS_0 / 4] = { .ro = ~0 }, 85 [PCI_BASE_ADDRESS_1 / 4] = { .ro = ~0 }, 86 87 [PCI_PRIMARY_BUS / 4] = { 88 /* Primary, secondary and subordinate bus are RW */ 89 .rw = GENMASK(24, 0), 90 /* Secondary latency is read-only */ 91 .ro = GENMASK(31, 24), 92 }, 93 94 [PCI_IO_BASE / 4] = { 95 /* The high four bits of I/O base/limit are RW */ 96 .rw = (GENMASK(15, 12) | GENMASK(7, 4)), 97 98 /* The low four bits of I/O base/limit are RO */ 99 .ro = (((PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK | 100 PCI_STATUS_DEVSEL_MASK) << 16) | 101 GENMASK(11, 8) | GENMASK(3, 0)), 102 103 .w1c = (PCI_STATUS_PARITY | 104 PCI_STATUS_SIG_TARGET_ABORT | 105 PCI_STATUS_REC_TARGET_ABORT | 106 PCI_STATUS_REC_MASTER_ABORT | 107 PCI_STATUS_SIG_SYSTEM_ERROR | 108 PCI_STATUS_DETECTED_PARITY) << 16, 109 110 .rsvd = ((BIT(6) | GENMASK(4, 0)) << 16), 111 }, 112 113 [PCI_MEMORY_BASE / 4] = { 114 /* The high 12-bits of mem base/limit are RW */ 115 .rw = GENMASK(31, 20) | GENMASK(15, 4), 116 117 /* The low four bits of mem base/limit are RO */ 118 .ro = GENMASK(19, 16) | GENMASK(3, 0), 119 }, 120 121 [PCI_PREF_MEMORY_BASE / 4] = { 122 /* The high 12-bits of pref mem base/limit are RW */ 123 .rw = GENMASK(31, 20) | GENMASK(15, 4), 124 125 /* The low four bits of pref mem base/limit are RO */ 126 .ro = GENMASK(19, 16) | GENMASK(3, 0), 127 }, 128 129 [PCI_PREF_BASE_UPPER32 / 4] = { 130 .rw = ~0, 131 }, 132 133 [PCI_PREF_LIMIT_UPPER32 / 4] = { 134 .rw = ~0, 135 }, 136 137 [PCI_IO_BASE_UPPER16 / 4] = { 138 .rw = ~0, 139 }, 140 141 [PCI_CAPABILITY_LIST / 4] = { 142 .ro = GENMASK(7, 0), 143 .rsvd = GENMASK(31, 8), 144 }, 145 146 [PCI_ROM_ADDRESS1 / 4] = { 147 .rw = GENMASK(31, 11) | BIT(0), 148 .rsvd = GENMASK(10, 1), 149 }, 150 151 /* 152 * Interrupt line (bits 7:0) are RW, interrupt pin (bits 15:8) 153 * are RO, and bridge control (31:16) are a mix of RW, RO, 154 * reserved and W1C bits 155 */ 156 [PCI_INTERRUPT_LINE / 4] = { 157 /* Interrupt line is RW */ 158 .rw = (GENMASK(7, 0) | 159 ((PCI_BRIDGE_CTL_PARITY | 160 PCI_BRIDGE_CTL_SERR | 161 PCI_BRIDGE_CTL_ISA | 162 PCI_BRIDGE_CTL_VGA | 163 PCI_BRIDGE_CTL_MASTER_ABORT | 164 PCI_BRIDGE_CTL_BUS_RESET | 165 BIT(8) | BIT(9) | BIT(11)) << 16)), 166 167 /* Interrupt pin is RO */ 168 .ro = (GENMASK(15, 8) | ((PCI_BRIDGE_CTL_FAST_BACK) << 16)), 169 170 .w1c = BIT(10) << 16, 171 172 .rsvd = (GENMASK(15, 12) | BIT(4)) << 16, 173 }, 174 }; 175 176 const static struct pci_bridge_reg_behavior pcie_cap_regs_behavior[] = { 177 [PCI_CAP_LIST_ID / 4] = { 178 /* 179 * Capability ID, Next Capability Pointer and 180 * Capabilities register are all read-only. 181 */ 182 .ro = ~0, 183 }, 184 185 [PCI_EXP_DEVCAP / 4] = { 186 .ro = ~0, 187 }, 188 189 [PCI_EXP_DEVCTL / 4] = { 190 /* Device control register is RW */ 191 .rw = GENMASK(15, 0), 192 193 /* 194 * Device status register has 4 bits W1C, then 2 bits 195 * RO, the rest is reserved 196 */ 197 .w1c = GENMASK(19, 16), 198 .ro = GENMASK(20, 19), 199 .rsvd = GENMASK(31, 21), 200 }, 201 202 [PCI_EXP_LNKCAP / 4] = { 203 /* All bits are RO, except bit 23 which is reserved */ 204 .ro = lower_32_bits(~BIT(23)), 205 .rsvd = BIT(23), 206 }, 207 208 [PCI_EXP_LNKCTL / 4] = { 209 /* 210 * Link control has bits [1:0] and [11:3] RW, the 211 * other bits are reserved. 212 * Link status has bits [13:0] RO, and bits [14:15] 213 * W1C. 214 */ 215 .rw = GENMASK(11, 3) | GENMASK(1, 0), 216 .ro = GENMASK(13, 0) << 16, 217 .w1c = GENMASK(15, 14) << 16, 218 .rsvd = GENMASK(15, 12) | BIT(2), 219 }, 220 221 [PCI_EXP_SLTCAP / 4] = { 222 .ro = ~0, 223 }, 224 225 [PCI_EXP_SLTCTL / 4] = { 226 /* 227 * Slot control has bits [12:0] RW, the rest is 228 * reserved. 229 * 230 * Slot status has a mix of W1C and RO bits, as well 231 * as reserved bits. 232 */ 233 .rw = GENMASK(12, 0), 234 .w1c = (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD | 235 PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC | 236 PCI_EXP_SLTSTA_CC | PCI_EXP_SLTSTA_DLLSC) << 16, 237 .ro = (PCI_EXP_SLTSTA_MRLSS | PCI_EXP_SLTSTA_PDS | 238 PCI_EXP_SLTSTA_EIS) << 16, 239 .rsvd = GENMASK(15, 12) | (GENMASK(15, 9) << 16), 240 }, 241 242 [PCI_EXP_RTCTL / 4] = { 243 /* 244 * Root control has bits [4:0] RW, the rest is 245 * reserved. 246 * 247 * Root status has bit 0 RO, the rest is reserved. 248 */ 249 .rw = (PCI_EXP_RTCTL_SECEE | PCI_EXP_RTCTL_SENFEE | 250 PCI_EXP_RTCTL_SEFEE | PCI_EXP_RTCTL_PMEIE | 251 PCI_EXP_RTCTL_CRSSVE), 252 .ro = PCI_EXP_RTCAP_CRSVIS << 16, 253 .rsvd = GENMASK(15, 5) | (GENMASK(15, 1) << 16), 254 }, 255 256 [PCI_EXP_RTSTA / 4] = { 257 .ro = GENMASK(15, 0) | PCI_EXP_RTSTA_PENDING, 258 .w1c = PCI_EXP_RTSTA_PME, 259 .rsvd = GENMASK(31, 18), 260 }, 261 }; 262 263 /* 264 * Initialize a pci_bridge_emul structure to represent a fake PCI 265 * bridge configuration space. The caller needs to have initialized 266 * the PCI configuration space with whatever values make sense 267 * (typically at least vendor, device, revision), the ->ops pointer, 268 * and optionally ->data and ->has_pcie. 269 */ 270 int pci_bridge_emul_init(struct pci_bridge_emul *bridge, 271 unsigned int flags) 272 { 273 bridge->conf.class_revision |= PCI_CLASS_BRIDGE_PCI << 16; 274 bridge->conf.header_type = PCI_HEADER_TYPE_BRIDGE; 275 bridge->conf.cache_line_size = 0x10; 276 bridge->conf.status = PCI_STATUS_CAP_LIST; 277 bridge->pci_regs_behavior = kmemdup(pci_regs_behavior, 278 sizeof(pci_regs_behavior), 279 GFP_KERNEL); 280 if (!bridge->pci_regs_behavior) 281 return -ENOMEM; 282 283 if (bridge->has_pcie) { 284 bridge->conf.capabilities_pointer = PCI_CAP_PCIE_START; 285 bridge->pcie_conf.cap_id = PCI_CAP_ID_EXP; 286 /* Set PCIe v2, root port, slot support */ 287 bridge->pcie_conf.cap = PCI_EXP_TYPE_ROOT_PORT << 4 | 2 | 288 PCI_EXP_FLAGS_SLOT; 289 bridge->pcie_cap_regs_behavior = 290 kmemdup(pcie_cap_regs_behavior, 291 sizeof(pcie_cap_regs_behavior), 292 GFP_KERNEL); 293 if (!bridge->pcie_cap_regs_behavior) { 294 kfree(bridge->pci_regs_behavior); 295 return -ENOMEM; 296 } 297 } 298 299 if (flags & PCI_BRIDGE_EMUL_NO_PREFETCHABLE_BAR) { 300 bridge->pci_regs_behavior[PCI_PREF_MEMORY_BASE / 4].ro = ~0; 301 bridge->pci_regs_behavior[PCI_PREF_MEMORY_BASE / 4].rw = 0; 302 } 303 304 return 0; 305 } 306 307 /* 308 * Cleanup a pci_bridge_emul structure that was previously initilized 309 * using pci_bridge_emul_init(). 310 */ 311 void pci_bridge_emul_cleanup(struct pci_bridge_emul *bridge) 312 { 313 if (bridge->has_pcie) 314 kfree(bridge->pcie_cap_regs_behavior); 315 kfree(bridge->pci_regs_behavior); 316 } 317 318 /* 319 * Should be called by the PCI controller driver when reading the PCI 320 * configuration space of the fake bridge. It will call back the 321 * ->ops->read_base or ->ops->read_pcie operations. 322 */ 323 int pci_bridge_emul_conf_read(struct pci_bridge_emul *bridge, int where, 324 int size, u32 *value) 325 { 326 int ret; 327 int reg = where & ~3; 328 pci_bridge_emul_read_status_t (*read_op)(struct pci_bridge_emul *bridge, 329 int reg, u32 *value); 330 u32 *cfgspace; 331 const struct pci_bridge_reg_behavior *behavior; 332 333 if (bridge->has_pcie && reg >= PCI_CAP_PCIE_END) { 334 *value = 0; 335 return PCIBIOS_SUCCESSFUL; 336 } 337 338 if (!bridge->has_pcie && reg >= PCI_BRIDGE_CONF_END) { 339 *value = 0; 340 return PCIBIOS_SUCCESSFUL; 341 } 342 343 if (bridge->has_pcie && reg >= PCI_CAP_PCIE_START) { 344 reg -= PCI_CAP_PCIE_START; 345 read_op = bridge->ops->read_pcie; 346 cfgspace = (u32 *) &bridge->pcie_conf; 347 behavior = bridge->pcie_cap_regs_behavior; 348 } else { 349 read_op = bridge->ops->read_base; 350 cfgspace = (u32 *) &bridge->conf; 351 behavior = bridge->pci_regs_behavior; 352 } 353 354 if (read_op) 355 ret = read_op(bridge, reg, value); 356 else 357 ret = PCI_BRIDGE_EMUL_NOT_HANDLED; 358 359 if (ret == PCI_BRIDGE_EMUL_NOT_HANDLED) 360 *value = cfgspace[reg / 4]; 361 362 /* 363 * Make sure we never return any reserved bit with a value 364 * different from 0. 365 */ 366 *value &= ~behavior[reg / 4].rsvd; 367 368 if (size == 1) 369 *value = (*value >> (8 * (where & 3))) & 0xff; 370 else if (size == 2) 371 *value = (*value >> (8 * (where & 3))) & 0xffff; 372 else if (size != 4) 373 return PCIBIOS_BAD_REGISTER_NUMBER; 374 375 return PCIBIOS_SUCCESSFUL; 376 } 377 378 /* 379 * Should be called by the PCI controller driver when writing the PCI 380 * configuration space of the fake bridge. It will call back the 381 * ->ops->write_base or ->ops->write_pcie operations. 382 */ 383 int pci_bridge_emul_conf_write(struct pci_bridge_emul *bridge, int where, 384 int size, u32 value) 385 { 386 int reg = where & ~3; 387 int mask, ret, old, new, shift; 388 void (*write_op)(struct pci_bridge_emul *bridge, int reg, 389 u32 old, u32 new, u32 mask); 390 u32 *cfgspace; 391 const struct pci_bridge_reg_behavior *behavior; 392 393 if (bridge->has_pcie && reg >= PCI_CAP_PCIE_END) 394 return PCIBIOS_SUCCESSFUL; 395 396 if (!bridge->has_pcie && reg >= PCI_BRIDGE_CONF_END) 397 return PCIBIOS_SUCCESSFUL; 398 399 shift = (where & 0x3) * 8; 400 401 if (size == 4) 402 mask = 0xffffffff; 403 else if (size == 2) 404 mask = 0xffff << shift; 405 else if (size == 1) 406 mask = 0xff << shift; 407 else 408 return PCIBIOS_BAD_REGISTER_NUMBER; 409 410 ret = pci_bridge_emul_conf_read(bridge, reg, 4, &old); 411 if (ret != PCIBIOS_SUCCESSFUL) 412 return ret; 413 414 if (bridge->has_pcie && reg >= PCI_CAP_PCIE_START) { 415 reg -= PCI_CAP_PCIE_START; 416 write_op = bridge->ops->write_pcie; 417 cfgspace = (u32 *) &bridge->pcie_conf; 418 behavior = bridge->pcie_cap_regs_behavior; 419 } else { 420 write_op = bridge->ops->write_base; 421 cfgspace = (u32 *) &bridge->conf; 422 behavior = bridge->pci_regs_behavior; 423 } 424 425 /* Keep all bits, except the RW bits */ 426 new = old & (~mask | ~behavior[reg / 4].rw); 427 428 /* Update the value of the RW bits */ 429 new |= (value << shift) & (behavior[reg / 4].rw & mask); 430 431 /* Clear the W1C bits */ 432 new &= ~((value << shift) & (behavior[reg / 4].w1c & mask)); 433 434 cfgspace[reg / 4] = new; 435 436 if (write_op) 437 write_op(bridge, reg, old, new, mask); 438 439 return PCIBIOS_SUCCESSFUL; 440 } 441