1 /* 2 * Standard PCI Hot Plug Driver 3 * 4 * Copyright (C) 1995,2001 Compaq Computer Corporation 5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com) 6 * Copyright (C) 2001 IBM Corp. 7 * Copyright (C) 2003-2004 Intel Corporation 8 * 9 * All rights reserved. 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or (at 14 * your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 19 * NON INFRINGEMENT. See the GNU General Public License for more 20 * details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 25 * 26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com> 27 * 28 */ 29 30 #include <linux/kernel.h> 31 #include <linux/module.h> 32 #include <linux/types.h> 33 #include <linux/pci.h> 34 #include <linux/interrupt.h> 35 36 #include "shpchp.h" 37 38 /* Slot Available Register I field definition */ 39 #define SLOT_33MHZ 0x0000001f 40 #define SLOT_66MHZ_PCIX 0x00001f00 41 #define SLOT_100MHZ_PCIX 0x001f0000 42 #define SLOT_133MHZ_PCIX 0x1f000000 43 44 /* Slot Available Register II field definition */ 45 #define SLOT_66MHZ 0x0000001f 46 #define SLOT_66MHZ_PCIX_266 0x00000f00 47 #define SLOT_100MHZ_PCIX_266 0x0000f000 48 #define SLOT_133MHZ_PCIX_266 0x000f0000 49 #define SLOT_66MHZ_PCIX_533 0x00f00000 50 #define SLOT_100MHZ_PCIX_533 0x0f000000 51 #define SLOT_133MHZ_PCIX_533 0xf0000000 52 53 /* Slot Configuration */ 54 #define SLOT_NUM 0x0000001F 55 #define FIRST_DEV_NUM 0x00001F00 56 #define PSN 0x07FF0000 57 #define UPDOWN 0x20000000 58 #define MRLSENSOR 0x40000000 59 #define ATTN_BUTTON 0x80000000 60 61 /* 62 * Interrupt Locator Register definitions 63 */ 64 #define CMD_INTR_PENDING (1 << 0) 65 #define SLOT_INTR_PENDING(i) (1 << (i + 1)) 66 67 /* 68 * Controller SERR-INT Register 69 */ 70 #define GLOBAL_INTR_MASK (1 << 0) 71 #define GLOBAL_SERR_MASK (1 << 1) 72 #define COMMAND_INTR_MASK (1 << 2) 73 #define ARBITER_SERR_MASK (1 << 3) 74 #define COMMAND_DETECTED (1 << 16) 75 #define ARBITER_DETECTED (1 << 17) 76 #define SERR_INTR_RSVDZ_MASK 0xfffc0000 77 78 /* 79 * Logical Slot Register definitions 80 */ 81 #define SLOT_REG(i) (SLOT1 + (4 * i)) 82 83 #define SLOT_STATE_SHIFT (0) 84 #define SLOT_STATE_MASK (3 << 0) 85 #define SLOT_STATE_PWRONLY (1) 86 #define SLOT_STATE_ENABLED (2) 87 #define SLOT_STATE_DISABLED (3) 88 #define PWR_LED_STATE_SHIFT (2) 89 #define PWR_LED_STATE_MASK (3 << 2) 90 #define ATN_LED_STATE_SHIFT (4) 91 #define ATN_LED_STATE_MASK (3 << 4) 92 #define ATN_LED_STATE_ON (1) 93 #define ATN_LED_STATE_BLINK (2) 94 #define ATN_LED_STATE_OFF (3) 95 #define POWER_FAULT (1 << 6) 96 #define ATN_BUTTON (1 << 7) 97 #define MRL_SENSOR (1 << 8) 98 #define MHZ66_CAP (1 << 9) 99 #define PRSNT_SHIFT (10) 100 #define PRSNT_MASK (3 << 10) 101 #define PCIX_CAP_SHIFT (12) 102 #define PCIX_CAP_MASK_PI1 (3 << 12) 103 #define PCIX_CAP_MASK_PI2 (7 << 12) 104 #define PRSNT_CHANGE_DETECTED (1 << 16) 105 #define ISO_PFAULT_DETECTED (1 << 17) 106 #define BUTTON_PRESS_DETECTED (1 << 18) 107 #define MRL_CHANGE_DETECTED (1 << 19) 108 #define CON_PFAULT_DETECTED (1 << 20) 109 #define PRSNT_CHANGE_INTR_MASK (1 << 24) 110 #define ISO_PFAULT_INTR_MASK (1 << 25) 111 #define BUTTON_PRESS_INTR_MASK (1 << 26) 112 #define MRL_CHANGE_INTR_MASK (1 << 27) 113 #define CON_PFAULT_INTR_MASK (1 << 28) 114 #define MRL_CHANGE_SERR_MASK (1 << 29) 115 #define CON_PFAULT_SERR_MASK (1 << 30) 116 #define SLOT_REG_RSVDZ_MASK ((1 << 15) | (7 << 21)) 117 118 /* 119 * SHPC Command Code definitions 120 * 121 * Slot Operation 00h - 3Fh 122 * Set Bus Segment Speed/Mode A 40h - 47h 123 * Power-Only All Slots 48h 124 * Enable All Slots 49h 125 * Set Bus Segment Speed/Mode B (PI=2) 50h - 5Fh 126 * Reserved Command Codes 60h - BFh 127 * Vendor Specific Commands C0h - FFh 128 */ 129 #define SET_SLOT_PWR 0x01 /* Slot Operation */ 130 #define SET_SLOT_ENABLE 0x02 131 #define SET_SLOT_DISABLE 0x03 132 #define SET_PWR_ON 0x04 133 #define SET_PWR_BLINK 0x08 134 #define SET_PWR_OFF 0x0c 135 #define SET_ATTN_ON 0x10 136 #define SET_ATTN_BLINK 0x20 137 #define SET_ATTN_OFF 0x30 138 #define SETA_PCI_33MHZ 0x40 /* Set Bus Segment Speed/Mode A */ 139 #define SETA_PCI_66MHZ 0x41 140 #define SETA_PCIX_66MHZ 0x42 141 #define SETA_PCIX_100MHZ 0x43 142 #define SETA_PCIX_133MHZ 0x44 143 #define SETA_RESERVED1 0x45 144 #define SETA_RESERVED2 0x46 145 #define SETA_RESERVED3 0x47 146 #define SET_PWR_ONLY_ALL 0x48 /* Power-Only All Slots */ 147 #define SET_ENABLE_ALL 0x49 /* Enable All Slots */ 148 #define SETB_PCI_33MHZ 0x50 /* Set Bus Segment Speed/Mode B */ 149 #define SETB_PCI_66MHZ 0x51 150 #define SETB_PCIX_66MHZ_PM 0x52 151 #define SETB_PCIX_100MHZ_PM 0x53 152 #define SETB_PCIX_133MHZ_PM 0x54 153 #define SETB_PCIX_66MHZ_EM 0x55 154 #define SETB_PCIX_100MHZ_EM 0x56 155 #define SETB_PCIX_133MHZ_EM 0x57 156 #define SETB_PCIX_66MHZ_266 0x58 157 #define SETB_PCIX_100MHZ_266 0x59 158 #define SETB_PCIX_133MHZ_266 0x5a 159 #define SETB_PCIX_66MHZ_533 0x5b 160 #define SETB_PCIX_100MHZ_533 0x5c 161 #define SETB_PCIX_133MHZ_533 0x5d 162 #define SETB_RESERVED1 0x5e 163 #define SETB_RESERVED2 0x5f 164 165 /* 166 * SHPC controller command error code 167 */ 168 #define SWITCH_OPEN 0x1 169 #define INVALID_CMD 0x2 170 #define INVALID_SPEED_MODE 0x4 171 172 /* 173 * For accessing SHPC Working Register Set via PCI Configuration Space 174 */ 175 #define DWORD_SELECT 0x2 176 #define DWORD_DATA 0x4 177 178 /* Field Offset in Logical Slot Register - byte boundary */ 179 #define SLOT_EVENT_LATCH 0x2 180 #define SLOT_SERR_INT_MASK 0x3 181 182 static irqreturn_t shpc_isr(int irq, void *dev_id); 183 static void start_int_poll_timer(struct controller *ctrl, int sec); 184 static int hpc_check_cmd_status(struct controller *ctrl); 185 186 static inline u8 shpc_readb(struct controller *ctrl, int reg) 187 { 188 return readb(ctrl->creg + reg); 189 } 190 191 static inline void shpc_writeb(struct controller *ctrl, int reg, u8 val) 192 { 193 writeb(val, ctrl->creg + reg); 194 } 195 196 static inline u16 shpc_readw(struct controller *ctrl, int reg) 197 { 198 return readw(ctrl->creg + reg); 199 } 200 201 static inline void shpc_writew(struct controller *ctrl, int reg, u16 val) 202 { 203 writew(val, ctrl->creg + reg); 204 } 205 206 static inline u32 shpc_readl(struct controller *ctrl, int reg) 207 { 208 return readl(ctrl->creg + reg); 209 } 210 211 static inline void shpc_writel(struct controller *ctrl, int reg, u32 val) 212 { 213 writel(val, ctrl->creg + reg); 214 } 215 216 static inline int shpc_indirect_read(struct controller *ctrl, int index, 217 u32 *value) 218 { 219 int rc; 220 u32 cap_offset = ctrl->cap_offset; 221 struct pci_dev *pdev = ctrl->pci_dev; 222 223 rc = pci_write_config_byte(pdev, cap_offset + DWORD_SELECT, index); 224 if (rc) 225 return rc; 226 return pci_read_config_dword(pdev, cap_offset + DWORD_DATA, value); 227 } 228 229 /* 230 * This is the interrupt polling timeout function. 231 */ 232 static void int_poll_timeout(struct timer_list *t) 233 { 234 struct controller *ctrl = from_timer(ctrl, t, poll_timer); 235 236 /* Poll for interrupt events. regs == NULL => polling */ 237 shpc_isr(0, ctrl); 238 239 if (!shpchp_poll_time) 240 shpchp_poll_time = 2; /* default polling interval is 2 sec */ 241 242 start_int_poll_timer(ctrl, shpchp_poll_time); 243 } 244 245 /* 246 * This function starts the interrupt polling timer. 247 */ 248 static void start_int_poll_timer(struct controller *ctrl, int sec) 249 { 250 /* Clamp to sane value */ 251 if ((sec <= 0) || (sec > 60)) 252 sec = 2; 253 254 ctrl->poll_timer.expires = jiffies + sec * HZ; 255 add_timer(&ctrl->poll_timer); 256 } 257 258 static inline int is_ctrl_busy(struct controller *ctrl) 259 { 260 u16 cmd_status = shpc_readw(ctrl, CMD_STATUS); 261 return cmd_status & 0x1; 262 } 263 264 /* 265 * Returns 1 if SHPC finishes executing a command within 1 sec, 266 * otherwise returns 0. 267 */ 268 static inline int shpc_poll_ctrl_busy(struct controller *ctrl) 269 { 270 int i; 271 272 if (!is_ctrl_busy(ctrl)) 273 return 1; 274 275 /* Check every 0.1 sec for a total of 1 sec */ 276 for (i = 0; i < 10; i++) { 277 msleep(100); 278 if (!is_ctrl_busy(ctrl)) 279 return 1; 280 } 281 282 return 0; 283 } 284 285 static inline int shpc_wait_cmd(struct controller *ctrl) 286 { 287 int retval = 0; 288 unsigned long timeout = msecs_to_jiffies(1000); 289 int rc; 290 291 if (shpchp_poll_mode) 292 rc = shpc_poll_ctrl_busy(ctrl); 293 else 294 rc = wait_event_interruptible_timeout(ctrl->queue, 295 !is_ctrl_busy(ctrl), timeout); 296 if (!rc && is_ctrl_busy(ctrl)) { 297 retval = -EIO; 298 ctrl_err(ctrl, "Command not completed in 1000 msec\n"); 299 } else if (rc < 0) { 300 retval = -EINTR; 301 ctrl_info(ctrl, "Command was interrupted by a signal\n"); 302 } 303 304 return retval; 305 } 306 307 static int shpc_write_cmd(struct slot *slot, u8 t_slot, u8 cmd) 308 { 309 struct controller *ctrl = slot->ctrl; 310 u16 cmd_status; 311 int retval = 0; 312 u16 temp_word; 313 314 mutex_lock(&slot->ctrl->cmd_lock); 315 316 if (!shpc_poll_ctrl_busy(ctrl)) { 317 /* After 1 sec and and the controller is still busy */ 318 ctrl_err(ctrl, "Controller is still busy after 1 sec\n"); 319 retval = -EBUSY; 320 goto out; 321 } 322 323 ++t_slot; 324 temp_word = (t_slot << 8) | (cmd & 0xFF); 325 ctrl_dbg(ctrl, "%s: t_slot %x cmd %x\n", __func__, t_slot, cmd); 326 327 /* To make sure the Controller Busy bit is 0 before we send out the 328 * command. 329 */ 330 shpc_writew(ctrl, CMD, temp_word); 331 332 /* 333 * Wait for command completion. 334 */ 335 retval = shpc_wait_cmd(slot->ctrl); 336 if (retval) 337 goto out; 338 339 cmd_status = hpc_check_cmd_status(slot->ctrl); 340 if (cmd_status) { 341 ctrl_err(ctrl, "Failed to issued command 0x%x (error code = %d)\n", 342 cmd, cmd_status); 343 retval = -EIO; 344 } 345 out: 346 mutex_unlock(&slot->ctrl->cmd_lock); 347 return retval; 348 } 349 350 static int hpc_check_cmd_status(struct controller *ctrl) 351 { 352 int retval = 0; 353 u16 cmd_status = shpc_readw(ctrl, CMD_STATUS) & 0x000F; 354 355 switch (cmd_status >> 1) { 356 case 0: 357 retval = 0; 358 break; 359 case 1: 360 retval = SWITCH_OPEN; 361 ctrl_err(ctrl, "Switch opened!\n"); 362 break; 363 case 2: 364 retval = INVALID_CMD; 365 ctrl_err(ctrl, "Invalid HPC command!\n"); 366 break; 367 case 4: 368 retval = INVALID_SPEED_MODE; 369 ctrl_err(ctrl, "Invalid bus speed/mode!\n"); 370 break; 371 default: 372 retval = cmd_status; 373 } 374 375 return retval; 376 } 377 378 379 static int hpc_get_attention_status(struct slot *slot, u8 *status) 380 { 381 struct controller *ctrl = slot->ctrl; 382 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); 383 u8 state = (slot_reg & ATN_LED_STATE_MASK) >> ATN_LED_STATE_SHIFT; 384 385 switch (state) { 386 case ATN_LED_STATE_ON: 387 *status = 1; /* On */ 388 break; 389 case ATN_LED_STATE_BLINK: 390 *status = 2; /* Blink */ 391 break; 392 case ATN_LED_STATE_OFF: 393 *status = 0; /* Off */ 394 break; 395 default: 396 *status = 0xFF; /* Reserved */ 397 break; 398 } 399 400 return 0; 401 } 402 403 static int hpc_get_power_status(struct slot *slot, u8 *status) 404 { 405 struct controller *ctrl = slot->ctrl; 406 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); 407 u8 state = (slot_reg & SLOT_STATE_MASK) >> SLOT_STATE_SHIFT; 408 409 switch (state) { 410 case SLOT_STATE_PWRONLY: 411 *status = 2; /* Powered only */ 412 break; 413 case SLOT_STATE_ENABLED: 414 *status = 1; /* Enabled */ 415 break; 416 case SLOT_STATE_DISABLED: 417 *status = 0; /* Disabled */ 418 break; 419 default: 420 *status = 0xFF; /* Reserved */ 421 break; 422 } 423 424 return 0; 425 } 426 427 428 static int hpc_get_latch_status(struct slot *slot, u8 *status) 429 { 430 struct controller *ctrl = slot->ctrl; 431 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); 432 433 *status = !!(slot_reg & MRL_SENSOR); /* 0 -> close; 1 -> open */ 434 435 return 0; 436 } 437 438 static int hpc_get_adapter_status(struct slot *slot, u8 *status) 439 { 440 struct controller *ctrl = slot->ctrl; 441 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); 442 u8 state = (slot_reg & PRSNT_MASK) >> PRSNT_SHIFT; 443 444 *status = (state != 0x3) ? 1 : 0; 445 446 return 0; 447 } 448 449 static int hpc_get_prog_int(struct slot *slot, u8 *prog_int) 450 { 451 struct controller *ctrl = slot->ctrl; 452 453 *prog_int = shpc_readb(ctrl, PROG_INTERFACE); 454 455 return 0; 456 } 457 458 static int hpc_get_adapter_speed(struct slot *slot, enum pci_bus_speed *value) 459 { 460 int retval = 0; 461 struct controller *ctrl = slot->ctrl; 462 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); 463 u8 m66_cap = !!(slot_reg & MHZ66_CAP); 464 u8 pi, pcix_cap; 465 466 retval = hpc_get_prog_int(slot, &pi); 467 if (retval) 468 return retval; 469 470 switch (pi) { 471 case 1: 472 pcix_cap = (slot_reg & PCIX_CAP_MASK_PI1) >> PCIX_CAP_SHIFT; 473 break; 474 case 2: 475 pcix_cap = (slot_reg & PCIX_CAP_MASK_PI2) >> PCIX_CAP_SHIFT; 476 break; 477 default: 478 return -ENODEV; 479 } 480 481 ctrl_dbg(ctrl, "%s: slot_reg = %x, pcix_cap = %x, m66_cap = %x\n", 482 __func__, slot_reg, pcix_cap, m66_cap); 483 484 switch (pcix_cap) { 485 case 0x0: 486 *value = m66_cap ? PCI_SPEED_66MHz : PCI_SPEED_33MHz; 487 break; 488 case 0x1: 489 *value = PCI_SPEED_66MHz_PCIX; 490 break; 491 case 0x3: 492 *value = PCI_SPEED_133MHz_PCIX; 493 break; 494 case 0x4: 495 *value = PCI_SPEED_133MHz_PCIX_266; 496 break; 497 case 0x5: 498 *value = PCI_SPEED_133MHz_PCIX_533; 499 break; 500 case 0x2: 501 default: 502 *value = PCI_SPEED_UNKNOWN; 503 retval = -ENODEV; 504 break; 505 } 506 507 ctrl_dbg(ctrl, "Adapter speed = %d\n", *value); 508 return retval; 509 } 510 511 static int hpc_get_mode1_ECC_cap(struct slot *slot, u8 *mode) 512 { 513 int retval = 0; 514 struct controller *ctrl = slot->ctrl; 515 u16 sec_bus_status = shpc_readw(ctrl, SEC_BUS_CONFIG); 516 u8 pi = shpc_readb(ctrl, PROG_INTERFACE); 517 518 if (pi == 2) { 519 *mode = (sec_bus_status & 0x0100) >> 8; 520 } else { 521 retval = -1; 522 } 523 524 ctrl_dbg(ctrl, "Mode 1 ECC cap = %d\n", *mode); 525 return retval; 526 } 527 528 static int hpc_query_power_fault(struct slot *slot) 529 { 530 struct controller *ctrl = slot->ctrl; 531 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); 532 533 /* Note: Logic 0 => fault */ 534 return !(slot_reg & POWER_FAULT); 535 } 536 537 static int hpc_set_attention_status(struct slot *slot, u8 value) 538 { 539 u8 slot_cmd = 0; 540 541 switch (value) { 542 case 0: 543 slot_cmd = SET_ATTN_OFF; /* OFF */ 544 break; 545 case 1: 546 slot_cmd = SET_ATTN_ON; /* ON */ 547 break; 548 case 2: 549 slot_cmd = SET_ATTN_BLINK; /* BLINK */ 550 break; 551 default: 552 return -1; 553 } 554 555 return shpc_write_cmd(slot, slot->hp_slot, slot_cmd); 556 } 557 558 559 static void hpc_set_green_led_on(struct slot *slot) 560 { 561 shpc_write_cmd(slot, slot->hp_slot, SET_PWR_ON); 562 } 563 564 static void hpc_set_green_led_off(struct slot *slot) 565 { 566 shpc_write_cmd(slot, slot->hp_slot, SET_PWR_OFF); 567 } 568 569 static void hpc_set_green_led_blink(struct slot *slot) 570 { 571 shpc_write_cmd(slot, slot->hp_slot, SET_PWR_BLINK); 572 } 573 574 static void hpc_release_ctlr(struct controller *ctrl) 575 { 576 int i; 577 u32 slot_reg, serr_int; 578 579 /* 580 * Mask event interrupts and SERRs of all slots 581 */ 582 for (i = 0; i < ctrl->num_slots; i++) { 583 slot_reg = shpc_readl(ctrl, SLOT_REG(i)); 584 slot_reg |= (PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK | 585 BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK | 586 CON_PFAULT_INTR_MASK | MRL_CHANGE_SERR_MASK | 587 CON_PFAULT_SERR_MASK); 588 slot_reg &= ~SLOT_REG_RSVDZ_MASK; 589 shpc_writel(ctrl, SLOT_REG(i), slot_reg); 590 } 591 592 cleanup_slots(ctrl); 593 594 /* 595 * Mask SERR and System Interrupt generation 596 */ 597 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE); 598 serr_int |= (GLOBAL_INTR_MASK | GLOBAL_SERR_MASK | 599 COMMAND_INTR_MASK | ARBITER_SERR_MASK); 600 serr_int &= ~SERR_INTR_RSVDZ_MASK; 601 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int); 602 603 if (shpchp_poll_mode) 604 del_timer(&ctrl->poll_timer); 605 else { 606 free_irq(ctrl->pci_dev->irq, ctrl); 607 pci_disable_msi(ctrl->pci_dev); 608 } 609 610 iounmap(ctrl->creg); 611 release_mem_region(ctrl->mmio_base, ctrl->mmio_size); 612 } 613 614 static int hpc_power_on_slot(struct slot *slot) 615 { 616 int retval; 617 618 retval = shpc_write_cmd(slot, slot->hp_slot, SET_SLOT_PWR); 619 if (retval) 620 ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__); 621 622 return retval; 623 } 624 625 static int hpc_slot_enable(struct slot *slot) 626 { 627 int retval; 628 629 /* Slot - Enable, Power Indicator - Blink, Attention Indicator - Off */ 630 retval = shpc_write_cmd(slot, slot->hp_slot, 631 SET_SLOT_ENABLE | SET_PWR_BLINK | SET_ATTN_OFF); 632 if (retval) 633 ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__); 634 635 return retval; 636 } 637 638 static int hpc_slot_disable(struct slot *slot) 639 { 640 int retval; 641 642 /* Slot - Disable, Power Indicator - Off, Attention Indicator - On */ 643 retval = shpc_write_cmd(slot, slot->hp_slot, 644 SET_SLOT_DISABLE | SET_PWR_OFF | SET_ATTN_ON); 645 if (retval) 646 ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__); 647 648 return retval; 649 } 650 651 static int shpc_get_cur_bus_speed(struct controller *ctrl) 652 { 653 int retval = 0; 654 struct pci_bus *bus = ctrl->pci_dev->subordinate; 655 enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN; 656 u16 sec_bus_reg = shpc_readw(ctrl, SEC_BUS_CONFIG); 657 u8 pi = shpc_readb(ctrl, PROG_INTERFACE); 658 u8 speed_mode = (pi == 2) ? (sec_bus_reg & 0xF) : (sec_bus_reg & 0x7); 659 660 if ((pi == 1) && (speed_mode > 4)) { 661 retval = -ENODEV; 662 goto out; 663 } 664 665 switch (speed_mode) { 666 case 0x0: 667 bus_speed = PCI_SPEED_33MHz; 668 break; 669 case 0x1: 670 bus_speed = PCI_SPEED_66MHz; 671 break; 672 case 0x2: 673 bus_speed = PCI_SPEED_66MHz_PCIX; 674 break; 675 case 0x3: 676 bus_speed = PCI_SPEED_100MHz_PCIX; 677 break; 678 case 0x4: 679 bus_speed = PCI_SPEED_133MHz_PCIX; 680 break; 681 case 0x5: 682 bus_speed = PCI_SPEED_66MHz_PCIX_ECC; 683 break; 684 case 0x6: 685 bus_speed = PCI_SPEED_100MHz_PCIX_ECC; 686 break; 687 case 0x7: 688 bus_speed = PCI_SPEED_133MHz_PCIX_ECC; 689 break; 690 case 0x8: 691 bus_speed = PCI_SPEED_66MHz_PCIX_266; 692 break; 693 case 0x9: 694 bus_speed = PCI_SPEED_100MHz_PCIX_266; 695 break; 696 case 0xa: 697 bus_speed = PCI_SPEED_133MHz_PCIX_266; 698 break; 699 case 0xb: 700 bus_speed = PCI_SPEED_66MHz_PCIX_533; 701 break; 702 case 0xc: 703 bus_speed = PCI_SPEED_100MHz_PCIX_533; 704 break; 705 case 0xd: 706 bus_speed = PCI_SPEED_133MHz_PCIX_533; 707 break; 708 default: 709 retval = -ENODEV; 710 break; 711 } 712 713 out: 714 bus->cur_bus_speed = bus_speed; 715 dbg("Current bus speed = %d\n", bus_speed); 716 return retval; 717 } 718 719 720 static int hpc_set_bus_speed_mode(struct slot *slot, enum pci_bus_speed value) 721 { 722 int retval; 723 struct controller *ctrl = slot->ctrl; 724 u8 pi, cmd; 725 726 pi = shpc_readb(ctrl, PROG_INTERFACE); 727 if ((pi == 1) && (value > PCI_SPEED_133MHz_PCIX)) 728 return -EINVAL; 729 730 switch (value) { 731 case PCI_SPEED_33MHz: 732 cmd = SETA_PCI_33MHZ; 733 break; 734 case PCI_SPEED_66MHz: 735 cmd = SETA_PCI_66MHZ; 736 break; 737 case PCI_SPEED_66MHz_PCIX: 738 cmd = SETA_PCIX_66MHZ; 739 break; 740 case PCI_SPEED_100MHz_PCIX: 741 cmd = SETA_PCIX_100MHZ; 742 break; 743 case PCI_SPEED_133MHz_PCIX: 744 cmd = SETA_PCIX_133MHZ; 745 break; 746 case PCI_SPEED_66MHz_PCIX_ECC: 747 cmd = SETB_PCIX_66MHZ_EM; 748 break; 749 case PCI_SPEED_100MHz_PCIX_ECC: 750 cmd = SETB_PCIX_100MHZ_EM; 751 break; 752 case PCI_SPEED_133MHz_PCIX_ECC: 753 cmd = SETB_PCIX_133MHZ_EM; 754 break; 755 case PCI_SPEED_66MHz_PCIX_266: 756 cmd = SETB_PCIX_66MHZ_266; 757 break; 758 case PCI_SPEED_100MHz_PCIX_266: 759 cmd = SETB_PCIX_100MHZ_266; 760 break; 761 case PCI_SPEED_133MHz_PCIX_266: 762 cmd = SETB_PCIX_133MHZ_266; 763 break; 764 case PCI_SPEED_66MHz_PCIX_533: 765 cmd = SETB_PCIX_66MHZ_533; 766 break; 767 case PCI_SPEED_100MHz_PCIX_533: 768 cmd = SETB_PCIX_100MHZ_533; 769 break; 770 case PCI_SPEED_133MHz_PCIX_533: 771 cmd = SETB_PCIX_133MHZ_533; 772 break; 773 default: 774 return -EINVAL; 775 } 776 777 retval = shpc_write_cmd(slot, 0, cmd); 778 if (retval) 779 ctrl_err(ctrl, "%s: Write command failed!\n", __func__); 780 else 781 shpc_get_cur_bus_speed(ctrl); 782 783 return retval; 784 } 785 786 static irqreturn_t shpc_isr(int irq, void *dev_id) 787 { 788 struct controller *ctrl = (struct controller *)dev_id; 789 u32 serr_int, slot_reg, intr_loc, intr_loc2; 790 int hp_slot; 791 792 /* Check to see if it was our interrupt */ 793 intr_loc = shpc_readl(ctrl, INTR_LOC); 794 if (!intr_loc) 795 return IRQ_NONE; 796 797 ctrl_dbg(ctrl, "%s: intr_loc = %x\n", __func__, intr_loc); 798 799 if (!shpchp_poll_mode) { 800 /* 801 * Mask Global Interrupt Mask - see implementation 802 * note on p. 139 of SHPC spec rev 1.0 803 */ 804 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE); 805 serr_int |= GLOBAL_INTR_MASK; 806 serr_int &= ~SERR_INTR_RSVDZ_MASK; 807 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int); 808 809 intr_loc2 = shpc_readl(ctrl, INTR_LOC); 810 ctrl_dbg(ctrl, "%s: intr_loc2 = %x\n", __func__, intr_loc2); 811 } 812 813 if (intr_loc & CMD_INTR_PENDING) { 814 /* 815 * Command Complete Interrupt Pending 816 * RO only - clear by writing 1 to the Command Completion 817 * Detect bit in Controller SERR-INT register 818 */ 819 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE); 820 serr_int &= ~SERR_INTR_RSVDZ_MASK; 821 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int); 822 823 wake_up_interruptible(&ctrl->queue); 824 } 825 826 if (!(intr_loc & ~CMD_INTR_PENDING)) 827 goto out; 828 829 for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) { 830 /* To find out which slot has interrupt pending */ 831 if (!(intr_loc & SLOT_INTR_PENDING(hp_slot))) 832 continue; 833 834 slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot)); 835 ctrl_dbg(ctrl, "Slot %x with intr, slot register = %x\n", 836 hp_slot, slot_reg); 837 838 if (slot_reg & MRL_CHANGE_DETECTED) 839 shpchp_handle_switch_change(hp_slot, ctrl); 840 841 if (slot_reg & BUTTON_PRESS_DETECTED) 842 shpchp_handle_attention_button(hp_slot, ctrl); 843 844 if (slot_reg & PRSNT_CHANGE_DETECTED) 845 shpchp_handle_presence_change(hp_slot, ctrl); 846 847 if (slot_reg & (ISO_PFAULT_DETECTED | CON_PFAULT_DETECTED)) 848 shpchp_handle_power_fault(hp_slot, ctrl); 849 850 /* Clear all slot events */ 851 slot_reg &= ~SLOT_REG_RSVDZ_MASK; 852 shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg); 853 } 854 out: 855 if (!shpchp_poll_mode) { 856 /* Unmask Global Interrupt Mask */ 857 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE); 858 serr_int &= ~(GLOBAL_INTR_MASK | SERR_INTR_RSVDZ_MASK); 859 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int); 860 } 861 862 return IRQ_HANDLED; 863 } 864 865 static int shpc_get_max_bus_speed(struct controller *ctrl) 866 { 867 int retval = 0; 868 struct pci_bus *bus = ctrl->pci_dev->subordinate; 869 enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN; 870 u8 pi = shpc_readb(ctrl, PROG_INTERFACE); 871 u32 slot_avail1 = shpc_readl(ctrl, SLOT_AVAIL1); 872 u32 slot_avail2 = shpc_readl(ctrl, SLOT_AVAIL2); 873 874 if (pi == 2) { 875 if (slot_avail2 & SLOT_133MHZ_PCIX_533) 876 bus_speed = PCI_SPEED_133MHz_PCIX_533; 877 else if (slot_avail2 & SLOT_100MHZ_PCIX_533) 878 bus_speed = PCI_SPEED_100MHz_PCIX_533; 879 else if (slot_avail2 & SLOT_66MHZ_PCIX_533) 880 bus_speed = PCI_SPEED_66MHz_PCIX_533; 881 else if (slot_avail2 & SLOT_133MHZ_PCIX_266) 882 bus_speed = PCI_SPEED_133MHz_PCIX_266; 883 else if (slot_avail2 & SLOT_100MHZ_PCIX_266) 884 bus_speed = PCI_SPEED_100MHz_PCIX_266; 885 else if (slot_avail2 & SLOT_66MHZ_PCIX_266) 886 bus_speed = PCI_SPEED_66MHz_PCIX_266; 887 } 888 889 if (bus_speed == PCI_SPEED_UNKNOWN) { 890 if (slot_avail1 & SLOT_133MHZ_PCIX) 891 bus_speed = PCI_SPEED_133MHz_PCIX; 892 else if (slot_avail1 & SLOT_100MHZ_PCIX) 893 bus_speed = PCI_SPEED_100MHz_PCIX; 894 else if (slot_avail1 & SLOT_66MHZ_PCIX) 895 bus_speed = PCI_SPEED_66MHz_PCIX; 896 else if (slot_avail2 & SLOT_66MHZ) 897 bus_speed = PCI_SPEED_66MHz; 898 else if (slot_avail1 & SLOT_33MHZ) 899 bus_speed = PCI_SPEED_33MHz; 900 else 901 retval = -ENODEV; 902 } 903 904 bus->max_bus_speed = bus_speed; 905 ctrl_dbg(ctrl, "Max bus speed = %d\n", bus_speed); 906 907 return retval; 908 } 909 910 static const struct hpc_ops shpchp_hpc_ops = { 911 .power_on_slot = hpc_power_on_slot, 912 .slot_enable = hpc_slot_enable, 913 .slot_disable = hpc_slot_disable, 914 .set_bus_speed_mode = hpc_set_bus_speed_mode, 915 .set_attention_status = hpc_set_attention_status, 916 .get_power_status = hpc_get_power_status, 917 .get_attention_status = hpc_get_attention_status, 918 .get_latch_status = hpc_get_latch_status, 919 .get_adapter_status = hpc_get_adapter_status, 920 921 .get_adapter_speed = hpc_get_adapter_speed, 922 .get_mode1_ECC_cap = hpc_get_mode1_ECC_cap, 923 .get_prog_int = hpc_get_prog_int, 924 925 .query_power_fault = hpc_query_power_fault, 926 .green_led_on = hpc_set_green_led_on, 927 .green_led_off = hpc_set_green_led_off, 928 .green_led_blink = hpc_set_green_led_blink, 929 930 .release_ctlr = hpc_release_ctlr, 931 }; 932 933 int shpc_init(struct controller *ctrl, struct pci_dev *pdev) 934 { 935 int rc = -1, num_slots = 0; 936 u8 hp_slot; 937 u32 shpc_base_offset; 938 u32 tempdword, slot_reg, slot_config; 939 u8 i; 940 941 ctrl->pci_dev = pdev; /* pci_dev of the P2P bridge */ 942 ctrl_dbg(ctrl, "Hotplug Controller:\n"); 943 944 if (pdev->vendor == PCI_VENDOR_ID_AMD && 945 pdev->device == PCI_DEVICE_ID_AMD_GOLAM_7450) { 946 /* amd shpc driver doesn't use Base Offset; assume 0 */ 947 ctrl->mmio_base = pci_resource_start(pdev, 0); 948 ctrl->mmio_size = pci_resource_len(pdev, 0); 949 } else { 950 ctrl->cap_offset = pci_find_capability(pdev, PCI_CAP_ID_SHPC); 951 if (!ctrl->cap_offset) { 952 ctrl_err(ctrl, "Cannot find PCI capability\n"); 953 goto abort; 954 } 955 ctrl_dbg(ctrl, " cap_offset = %x\n", ctrl->cap_offset); 956 957 rc = shpc_indirect_read(ctrl, 0, &shpc_base_offset); 958 if (rc) { 959 ctrl_err(ctrl, "Cannot read base_offset\n"); 960 goto abort; 961 } 962 963 rc = shpc_indirect_read(ctrl, 3, &tempdword); 964 if (rc) { 965 ctrl_err(ctrl, "Cannot read slot config\n"); 966 goto abort; 967 } 968 num_slots = tempdword & SLOT_NUM; 969 ctrl_dbg(ctrl, " num_slots (indirect) %x\n", num_slots); 970 971 for (i = 0; i < 9 + num_slots; i++) { 972 rc = shpc_indirect_read(ctrl, i, &tempdword); 973 if (rc) { 974 ctrl_err(ctrl, "Cannot read creg (index = %d)\n", 975 i); 976 goto abort; 977 } 978 ctrl_dbg(ctrl, " offset %d: value %x\n", i, tempdword); 979 } 980 981 ctrl->mmio_base = 982 pci_resource_start(pdev, 0) + shpc_base_offset; 983 ctrl->mmio_size = 0x24 + 0x4 * num_slots; 984 } 985 986 ctrl_info(ctrl, "HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", 987 pdev->vendor, pdev->device, pdev->subsystem_vendor, 988 pdev->subsystem_device); 989 990 rc = pci_enable_device(pdev); 991 if (rc) { 992 ctrl_err(ctrl, "pci_enable_device failed\n"); 993 goto abort; 994 } 995 996 if (!request_mem_region(ctrl->mmio_base, ctrl->mmio_size, MY_NAME)) { 997 ctrl_err(ctrl, "Cannot reserve MMIO region\n"); 998 rc = -1; 999 goto abort; 1000 } 1001 1002 ctrl->creg = ioremap(ctrl->mmio_base, ctrl->mmio_size); 1003 if (!ctrl->creg) { 1004 ctrl_err(ctrl, "Cannot remap MMIO region %lx @ %lx\n", 1005 ctrl->mmio_size, ctrl->mmio_base); 1006 release_mem_region(ctrl->mmio_base, ctrl->mmio_size); 1007 rc = -1; 1008 goto abort; 1009 } 1010 ctrl_dbg(ctrl, "ctrl->creg %p\n", ctrl->creg); 1011 1012 mutex_init(&ctrl->crit_sect); 1013 mutex_init(&ctrl->cmd_lock); 1014 1015 /* Setup wait queue */ 1016 init_waitqueue_head(&ctrl->queue); 1017 1018 ctrl->hpc_ops = &shpchp_hpc_ops; 1019 1020 /* Return PCI Controller Info */ 1021 slot_config = shpc_readl(ctrl, SLOT_CONFIG); 1022 ctrl->slot_device_offset = (slot_config & FIRST_DEV_NUM) >> 8; 1023 ctrl->num_slots = slot_config & SLOT_NUM; 1024 ctrl->first_slot = (slot_config & PSN) >> 16; 1025 ctrl->slot_num_inc = ((slot_config & UPDOWN) >> 29) ? 1 : -1; 1026 1027 /* Mask Global Interrupt Mask & Command Complete Interrupt Mask */ 1028 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); 1029 ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword); 1030 tempdword |= (GLOBAL_INTR_MASK | GLOBAL_SERR_MASK | 1031 COMMAND_INTR_MASK | ARBITER_SERR_MASK); 1032 tempdword &= ~SERR_INTR_RSVDZ_MASK; 1033 shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword); 1034 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); 1035 ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword); 1036 1037 /* Mask the MRL sensor SERR Mask of individual slot in 1038 * Slot SERR-INT Mask & clear all the existing event if any 1039 */ 1040 for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) { 1041 slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot)); 1042 ctrl_dbg(ctrl, "Default Logical Slot Register %d value %x\n", 1043 hp_slot, slot_reg); 1044 slot_reg |= (PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK | 1045 BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK | 1046 CON_PFAULT_INTR_MASK | MRL_CHANGE_SERR_MASK | 1047 CON_PFAULT_SERR_MASK); 1048 slot_reg &= ~SLOT_REG_RSVDZ_MASK; 1049 shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg); 1050 } 1051 1052 if (shpchp_poll_mode) { 1053 /* Install interrupt polling timer. Start with 10 sec delay */ 1054 timer_setup(&ctrl->poll_timer, int_poll_timeout, 0); 1055 start_int_poll_timer(ctrl, 10); 1056 } else { 1057 /* Installs the interrupt handler */ 1058 rc = pci_enable_msi(pdev); 1059 if (rc) { 1060 ctrl_info(ctrl, "Can't get msi for the hotplug controller\n"); 1061 ctrl_info(ctrl, "Use INTx for the hotplug controller\n"); 1062 } else { 1063 pci_set_master(pdev); 1064 } 1065 1066 rc = request_irq(ctrl->pci_dev->irq, shpc_isr, IRQF_SHARED, 1067 MY_NAME, (void *)ctrl); 1068 ctrl_dbg(ctrl, "request_irq %d (returns %d)\n", 1069 ctrl->pci_dev->irq, rc); 1070 if (rc) { 1071 ctrl_err(ctrl, "Can't get irq %d for the hotplug controller\n", 1072 ctrl->pci_dev->irq); 1073 goto abort_iounmap; 1074 } 1075 } 1076 ctrl_dbg(ctrl, "HPC at %s irq=%x\n", pci_name(pdev), pdev->irq); 1077 1078 shpc_get_max_bus_speed(ctrl); 1079 shpc_get_cur_bus_speed(ctrl); 1080 1081 /* 1082 * Unmask all event interrupts of all slots 1083 */ 1084 for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) { 1085 slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot)); 1086 ctrl_dbg(ctrl, "Default Logical Slot Register %d value %x\n", 1087 hp_slot, slot_reg); 1088 slot_reg &= ~(PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK | 1089 BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK | 1090 CON_PFAULT_INTR_MASK | SLOT_REG_RSVDZ_MASK); 1091 shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg); 1092 } 1093 if (!shpchp_poll_mode) { 1094 /* Unmask all general input interrupts and SERR */ 1095 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); 1096 tempdword &= ~(GLOBAL_INTR_MASK | COMMAND_INTR_MASK | 1097 SERR_INTR_RSVDZ_MASK); 1098 shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword); 1099 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); 1100 ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword); 1101 } 1102 1103 return 0; 1104 1105 /* We end up here for the many possible ways to fail this API. */ 1106 abort_iounmap: 1107 iounmap(ctrl->creg); 1108 abort: 1109 return rc; 1110 } 1111