11da177e4SLinus Torvalds /* 21da177e4SLinus Torvalds * Standard PCI Hot Plug Driver 31da177e4SLinus Torvalds * 41da177e4SLinus Torvalds * Copyright (C) 1995,2001 Compaq Computer Corporation 51da177e4SLinus Torvalds * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com) 61da177e4SLinus Torvalds * Copyright (C) 2001 IBM Corp. 71da177e4SLinus Torvalds * Copyright (C) 2003-2004 Intel Corporation 81da177e4SLinus Torvalds * 91da177e4SLinus Torvalds * All rights reserved. 101da177e4SLinus Torvalds * 111da177e4SLinus Torvalds * This program is free software; you can redistribute it and/or modify 121da177e4SLinus Torvalds * it under the terms of the GNU General Public License as published by 131da177e4SLinus Torvalds * the Free Software Foundation; either version 2 of the License, or (at 141da177e4SLinus Torvalds * your option) any later version. 151da177e4SLinus Torvalds * 161da177e4SLinus Torvalds * This program is distributed in the hope that it will be useful, but 171da177e4SLinus Torvalds * WITHOUT ANY WARRANTY; without even the implied warranty of 181da177e4SLinus Torvalds * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 191da177e4SLinus Torvalds * NON INFRINGEMENT. See the GNU General Public License for more 201da177e4SLinus Torvalds * details. 211da177e4SLinus Torvalds * 221da177e4SLinus Torvalds * You should have received a copy of the GNU General Public License 231da177e4SLinus Torvalds * along with this program; if not, write to the Free Software 241da177e4SLinus Torvalds * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 251da177e4SLinus Torvalds * 268cf4c195SKristen Accardi * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com> 271da177e4SLinus Torvalds * 281da177e4SLinus Torvalds */ 291da177e4SLinus Torvalds 301da177e4SLinus Torvalds #include <linux/kernel.h> 311da177e4SLinus Torvalds #include <linux/module.h> 321da177e4SLinus Torvalds #include <linux/types.h> 331da177e4SLinus Torvalds #include <linux/pci.h> 34d4d28dd4SAndrew Morton #include <linux/interrupt.h> 35d4d28dd4SAndrew Morton 361da177e4SLinus Torvalds #include "shpchp.h" 371da177e4SLinus Torvalds 381da177e4SLinus Torvalds /* Slot Available Register I field definition */ 391da177e4SLinus Torvalds #define SLOT_33MHZ 0x0000001f 401da177e4SLinus Torvalds #define SLOT_66MHZ_PCIX 0x00001f00 411da177e4SLinus Torvalds #define SLOT_100MHZ_PCIX 0x001f0000 421da177e4SLinus Torvalds #define SLOT_133MHZ_PCIX 0x1f000000 431da177e4SLinus Torvalds 441da177e4SLinus Torvalds /* Slot Available Register II field definition */ 451da177e4SLinus Torvalds #define SLOT_66MHZ 0x0000001f 461da177e4SLinus Torvalds #define SLOT_66MHZ_PCIX_266 0x00000f00 471da177e4SLinus Torvalds #define SLOT_100MHZ_PCIX_266 0x0000f000 481da177e4SLinus Torvalds #define SLOT_133MHZ_PCIX_266 0x000f0000 491da177e4SLinus Torvalds #define SLOT_66MHZ_PCIX_533 0x00f00000 501da177e4SLinus Torvalds #define SLOT_100MHZ_PCIX_533 0x0f000000 511da177e4SLinus Torvalds #define SLOT_133MHZ_PCIX_533 0xf0000000 521da177e4SLinus Torvalds 531da177e4SLinus Torvalds /* Slot Configuration */ 541da177e4SLinus Torvalds #define SLOT_NUM 0x0000001F 551da177e4SLinus Torvalds #define FIRST_DEV_NUM 0x00001F00 561da177e4SLinus Torvalds #define PSN 0x07FF0000 571da177e4SLinus Torvalds #define UPDOWN 0x20000000 581da177e4SLinus Torvalds #define MRLSENSOR 0x40000000 591da177e4SLinus Torvalds #define ATTN_BUTTON 0x80000000 601da177e4SLinus Torvalds 612b34da7eSKenji Kaneshige /* 62c4cecc19SKenji Kaneshige * Interrupt Locator Register definitions 63c4cecc19SKenji Kaneshige */ 64c4cecc19SKenji Kaneshige #define CMD_INTR_PENDING (1 << 0) 65c4cecc19SKenji Kaneshige #define SLOT_INTR_PENDING(i) (1 << (i + 1)) 66c4cecc19SKenji Kaneshige 67c4cecc19SKenji Kaneshige /* 68e7138723SKenji Kaneshige * Controller SERR-INT Register 69e7138723SKenji Kaneshige */ 70e7138723SKenji Kaneshige #define GLOBAL_INTR_MASK (1 << 0) 71e7138723SKenji Kaneshige #define GLOBAL_SERR_MASK (1 << 1) 72e7138723SKenji Kaneshige #define COMMAND_INTR_MASK (1 << 2) 73e7138723SKenji Kaneshige #define ARBITER_SERR_MASK (1 << 3) 74e7138723SKenji Kaneshige #define COMMAND_DETECTED (1 << 16) 75e7138723SKenji Kaneshige #define ARBITER_DETECTED (1 << 17) 76e7138723SKenji Kaneshige #define SERR_INTR_RSVDZ_MASK 0xfffc0000 77e7138723SKenji Kaneshige 78e7138723SKenji Kaneshige /* 792b34da7eSKenji Kaneshige * Logical Slot Register definitions 802b34da7eSKenji Kaneshige */ 812b34da7eSKenji Kaneshige #define SLOT_REG(i) (SLOT1 + (4 * i)) 822b34da7eSKenji Kaneshige 835858759cSKenji Kaneshige #define SLOT_STATE_SHIFT (0) 845858759cSKenji Kaneshige #define SLOT_STATE_MASK (3 << 0) 855858759cSKenji Kaneshige #define SLOT_STATE_PWRONLY (1) 865858759cSKenji Kaneshige #define SLOT_STATE_ENABLED (2) 875858759cSKenji Kaneshige #define SLOT_STATE_DISABLED (3) 885858759cSKenji Kaneshige #define PWR_LED_STATE_SHIFT (2) 895858759cSKenji Kaneshige #define PWR_LED_STATE_MASK (3 << 2) 905858759cSKenji Kaneshige #define ATN_LED_STATE_SHIFT (4) 915858759cSKenji Kaneshige #define ATN_LED_STATE_MASK (3 << 4) 925858759cSKenji Kaneshige #define ATN_LED_STATE_ON (1) 935858759cSKenji Kaneshige #define ATN_LED_STATE_BLINK (2) 945858759cSKenji Kaneshige #define ATN_LED_STATE_OFF (3) 955858759cSKenji Kaneshige #define POWER_FAULT (1 << 6) 965858759cSKenji Kaneshige #define ATN_BUTTON (1 << 7) 975858759cSKenji Kaneshige #define MRL_SENSOR (1 << 8) 985858759cSKenji Kaneshige #define MHZ66_CAP (1 << 9) 995858759cSKenji Kaneshige #define PRSNT_SHIFT (10) 1005858759cSKenji Kaneshige #define PRSNT_MASK (3 << 10) 1015858759cSKenji Kaneshige #define PCIX_CAP_SHIFT (12) 1025858759cSKenji Kaneshige #define PCIX_CAP_MASK_PI1 (3 << 12) 1035858759cSKenji Kaneshige #define PCIX_CAP_MASK_PI2 (7 << 12) 1045858759cSKenji Kaneshige #define PRSNT_CHANGE_DETECTED (1 << 16) 1055858759cSKenji Kaneshige #define ISO_PFAULT_DETECTED (1 << 17) 1065858759cSKenji Kaneshige #define BUTTON_PRESS_DETECTED (1 << 18) 1075858759cSKenji Kaneshige #define MRL_CHANGE_DETECTED (1 << 19) 1085858759cSKenji Kaneshige #define CON_PFAULT_DETECTED (1 << 20) 1095858759cSKenji Kaneshige #define PRSNT_CHANGE_INTR_MASK (1 << 24) 1105858759cSKenji Kaneshige #define ISO_PFAULT_INTR_MASK (1 << 25) 1115858759cSKenji Kaneshige #define BUTTON_PRESS_INTR_MASK (1 << 26) 1125858759cSKenji Kaneshige #define MRL_CHANGE_INTR_MASK (1 << 27) 1135858759cSKenji Kaneshige #define CON_PFAULT_INTR_MASK (1 << 28) 1145858759cSKenji Kaneshige #define MRL_CHANGE_SERR_MASK (1 << 29) 1155858759cSKenji Kaneshige #define CON_PFAULT_SERR_MASK (1 << 30) 1163b8fdb75SDan Carpenter #define SLOT_REG_RSVDZ_MASK ((1 << 15) | (7 << 21)) 1171da177e4SLinus Torvalds 1184085399dSKenji Kaneshige /* 1194085399dSKenji Kaneshige * SHPC Command Code definitnions 1204085399dSKenji Kaneshige * 1214085399dSKenji Kaneshige * Slot Operation 00h - 3Fh 1224085399dSKenji Kaneshige * Set Bus Segment Speed/Mode A 40h - 47h 1234085399dSKenji Kaneshige * Power-Only All Slots 48h 1244085399dSKenji Kaneshige * Enable All Slots 49h 1254085399dSKenji Kaneshige * Set Bus Segment Speed/Mode B (PI=2) 50h - 5Fh 1264085399dSKenji Kaneshige * Reserved Command Codes 60h - BFh 1274085399dSKenji Kaneshige * Vendor Specific Commands C0h - FFh 1284085399dSKenji Kaneshige */ 1294085399dSKenji Kaneshige #define SET_SLOT_PWR 0x01 /* Slot Operation */ 1301da177e4SLinus Torvalds #define SET_SLOT_ENABLE 0x02 1311da177e4SLinus Torvalds #define SET_SLOT_DISABLE 0x03 1321da177e4SLinus Torvalds #define SET_PWR_ON 0x04 1331da177e4SLinus Torvalds #define SET_PWR_BLINK 0x08 1344085399dSKenji Kaneshige #define SET_PWR_OFF 0x0c 1354085399dSKenji Kaneshige #define SET_ATTN_ON 0x10 1364085399dSKenji Kaneshige #define SET_ATTN_BLINK 0x20 1374085399dSKenji Kaneshige #define SET_ATTN_OFF 0x30 1384085399dSKenji Kaneshige #define SETA_PCI_33MHZ 0x40 /* Set Bus Segment Speed/Mode A */ 1391da177e4SLinus Torvalds #define SETA_PCI_66MHZ 0x41 1401da177e4SLinus Torvalds #define SETA_PCIX_66MHZ 0x42 1411da177e4SLinus Torvalds #define SETA_PCIX_100MHZ 0x43 1421da177e4SLinus Torvalds #define SETA_PCIX_133MHZ 0x44 1434085399dSKenji Kaneshige #define SETA_RESERVED1 0x45 1444085399dSKenji Kaneshige #define SETA_RESERVED2 0x46 1454085399dSKenji Kaneshige #define SETA_RESERVED3 0x47 1464085399dSKenji Kaneshige #define SET_PWR_ONLY_ALL 0x48 /* Power-Only All Slots */ 1474085399dSKenji Kaneshige #define SET_ENABLE_ALL 0x49 /* Enable All Slots */ 1484085399dSKenji Kaneshige #define SETB_PCI_33MHZ 0x50 /* Set Bus Segment Speed/Mode B */ 1491da177e4SLinus Torvalds #define SETB_PCI_66MHZ 0x51 1501da177e4SLinus Torvalds #define SETB_PCIX_66MHZ_PM 0x52 1511da177e4SLinus Torvalds #define SETB_PCIX_100MHZ_PM 0x53 1521da177e4SLinus Torvalds #define SETB_PCIX_133MHZ_PM 0x54 1531da177e4SLinus Torvalds #define SETB_PCIX_66MHZ_EM 0x55 1541da177e4SLinus Torvalds #define SETB_PCIX_100MHZ_EM 0x56 1551da177e4SLinus Torvalds #define SETB_PCIX_133MHZ_EM 0x57 1561da177e4SLinus Torvalds #define SETB_PCIX_66MHZ_266 0x58 1571da177e4SLinus Torvalds #define SETB_PCIX_100MHZ_266 0x59 1581da177e4SLinus Torvalds #define SETB_PCIX_133MHZ_266 0x5a 1591da177e4SLinus Torvalds #define SETB_PCIX_66MHZ_533 0x5b 1601da177e4SLinus Torvalds #define SETB_PCIX_100MHZ_533 0x5c 1611da177e4SLinus Torvalds #define SETB_PCIX_133MHZ_533 0x5d 1624085399dSKenji Kaneshige #define SETB_RESERVED1 0x5e 1634085399dSKenji Kaneshige #define SETB_RESERVED2 0x5f 1641da177e4SLinus Torvalds 1654085399dSKenji Kaneshige /* 1664085399dSKenji Kaneshige * SHPC controller command error code 1674085399dSKenji Kaneshige */ 1681da177e4SLinus Torvalds #define SWITCH_OPEN 0x1 1691da177e4SLinus Torvalds #define INVALID_CMD 0x2 1701da177e4SLinus Torvalds #define INVALID_SPEED_MODE 0x4 1711da177e4SLinus Torvalds 1724085399dSKenji Kaneshige /* 1734085399dSKenji Kaneshige * For accessing SHPC Working Register Set via PCI Configuration Space 1744085399dSKenji Kaneshige */ 1751da177e4SLinus Torvalds #define DWORD_SELECT 0x2 1761da177e4SLinus Torvalds #define DWORD_DATA 0x4 1771da177e4SLinus Torvalds 1781da177e4SLinus Torvalds /* Field Offset in Logical Slot Register - byte boundary */ 1791da177e4SLinus Torvalds #define SLOT_EVENT_LATCH 0x2 1801da177e4SLinus Torvalds #define SLOT_SERR_INT_MASK 0x3 1811da177e4SLinus Torvalds 1827d12e780SDavid Howells static irqreturn_t shpc_isr(int irq, void *dev_id); 1830abe68ceSKenji Kaneshige static void start_int_poll_timer(struct controller *ctrl, int sec); 184d29aaddaSKenji Kaneshige static int hpc_check_cmd_status(struct controller *ctrl); 1851da177e4SLinus Torvalds 18675d97c59SKenji Kaneshige static inline u8 shpc_readb(struct controller *ctrl, int reg) 18775d97c59SKenji Kaneshige { 1880abe68ceSKenji Kaneshige return readb(ctrl->creg + reg); 18975d97c59SKenji Kaneshige } 19075d97c59SKenji Kaneshige 19175d97c59SKenji Kaneshige static inline void shpc_writeb(struct controller *ctrl, int reg, u8 val) 19275d97c59SKenji Kaneshige { 1930abe68ceSKenji Kaneshige writeb(val, ctrl->creg + reg); 19475d97c59SKenji Kaneshige } 19575d97c59SKenji Kaneshige 19675d97c59SKenji Kaneshige static inline u16 shpc_readw(struct controller *ctrl, int reg) 19775d97c59SKenji Kaneshige { 1980abe68ceSKenji Kaneshige return readw(ctrl->creg + reg); 19975d97c59SKenji Kaneshige } 20075d97c59SKenji Kaneshige 20175d97c59SKenji Kaneshige static inline void shpc_writew(struct controller *ctrl, int reg, u16 val) 20275d97c59SKenji Kaneshige { 2030abe68ceSKenji Kaneshige writew(val, ctrl->creg + reg); 20475d97c59SKenji Kaneshige } 20575d97c59SKenji Kaneshige 20675d97c59SKenji Kaneshige static inline u32 shpc_readl(struct controller *ctrl, int reg) 20775d97c59SKenji Kaneshige { 2080abe68ceSKenji Kaneshige return readl(ctrl->creg + reg); 20975d97c59SKenji Kaneshige } 21075d97c59SKenji Kaneshige 21175d97c59SKenji Kaneshige static inline void shpc_writel(struct controller *ctrl, int reg, u32 val) 21275d97c59SKenji Kaneshige { 2130abe68ceSKenji Kaneshige writel(val, ctrl->creg + reg); 21475d97c59SKenji Kaneshige } 21575d97c59SKenji Kaneshige 21675d97c59SKenji Kaneshige static inline int shpc_indirect_read(struct controller *ctrl, int index, 21775d97c59SKenji Kaneshige u32 *value) 21875d97c59SKenji Kaneshige { 21975d97c59SKenji Kaneshige int rc; 22075d97c59SKenji Kaneshige u32 cap_offset = ctrl->cap_offset; 22175d97c59SKenji Kaneshige struct pci_dev *pdev = ctrl->pci_dev; 22275d97c59SKenji Kaneshige 22375d97c59SKenji Kaneshige rc = pci_write_config_byte(pdev, cap_offset + DWORD_SELECT, index); 22475d97c59SKenji Kaneshige if (rc) 22575d97c59SKenji Kaneshige return rc; 22675d97c59SKenji Kaneshige return pci_read_config_dword(pdev, cap_offset + DWORD_DATA, value); 22775d97c59SKenji Kaneshige } 22875d97c59SKenji Kaneshige 229f4263957SKenji Kaneshige /* 230f4263957SKenji Kaneshige * This is the interrupt polling timeout function. 231f4263957SKenji Kaneshige */ 2320abe68ceSKenji Kaneshige static void int_poll_timeout(unsigned long data) 2331da177e4SLinus Torvalds { 2340abe68ceSKenji Kaneshige struct controller *ctrl = (struct controller *)data; 2351da177e4SLinus Torvalds 2361da177e4SLinus Torvalds /* Poll for interrupt events. regs == NULL => polling */ 2370abe68ceSKenji Kaneshige shpc_isr(0, ctrl); 2381da177e4SLinus Torvalds 2390abe68ceSKenji Kaneshige init_timer(&ctrl->poll_timer); 2401da177e4SLinus Torvalds if (!shpchp_poll_time) 241f4263957SKenji Kaneshige shpchp_poll_time = 2; /* default polling interval is 2 sec */ 2421da177e4SLinus Torvalds 2430abe68ceSKenji Kaneshige start_int_poll_timer(ctrl, shpchp_poll_time); 2441da177e4SLinus Torvalds } 2451da177e4SLinus Torvalds 246f4263957SKenji Kaneshige /* 247f4263957SKenji Kaneshige * This function starts the interrupt polling timer. 248f4263957SKenji Kaneshige */ 2490abe68ceSKenji Kaneshige static void start_int_poll_timer(struct controller *ctrl, int sec) 2501da177e4SLinus Torvalds { 251f4263957SKenji Kaneshige /* Clamp to sane value */ 252f4263957SKenji Kaneshige if ((sec <= 0) || (sec > 60)) 253f4263957SKenji Kaneshige sec = 2; 2541da177e4SLinus Torvalds 2550abe68ceSKenji Kaneshige ctrl->poll_timer.function = &int_poll_timeout; 2560abe68ceSKenji Kaneshige ctrl->poll_timer.data = (unsigned long)ctrl; 2570abe68ceSKenji Kaneshige ctrl->poll_timer.expires = jiffies + sec * HZ; 2580abe68ceSKenji Kaneshige add_timer(&ctrl->poll_timer); 2591da177e4SLinus Torvalds } 2601da177e4SLinus Torvalds 261d1729cceSKenji Kaneshige static inline int is_ctrl_busy(struct controller *ctrl) 262d1729cceSKenji Kaneshige { 263d1729cceSKenji Kaneshige u16 cmd_status = shpc_readw(ctrl, CMD_STATUS); 264d1729cceSKenji Kaneshige return cmd_status & 0x1; 265d1729cceSKenji Kaneshige } 266d1729cceSKenji Kaneshige 267b4a1efffSKenji Kaneshige /* 268b4a1efffSKenji Kaneshige * Returns 1 if SHPC finishes executing a command within 1 sec, 269b4a1efffSKenji Kaneshige * otherwise returns 0. 270b4a1efffSKenji Kaneshige */ 271b4a1efffSKenji Kaneshige static inline int shpc_poll_ctrl_busy(struct controller *ctrl) 272b4a1efffSKenji Kaneshige { 273b4a1efffSKenji Kaneshige int i; 274b4a1efffSKenji Kaneshige 275d1729cceSKenji Kaneshige if (!is_ctrl_busy(ctrl)) 276b4a1efffSKenji Kaneshige return 1; 277b4a1efffSKenji Kaneshige 278b4a1efffSKenji Kaneshige /* Check every 0.1 sec for a total of 1 sec */ 279b4a1efffSKenji Kaneshige for (i = 0; i < 10; i++) { 280b4a1efffSKenji Kaneshige msleep(100); 281d1729cceSKenji Kaneshige if (!is_ctrl_busy(ctrl)) 282b4a1efffSKenji Kaneshige return 1; 283b4a1efffSKenji Kaneshige } 284b4a1efffSKenji Kaneshige 285b4a1efffSKenji Kaneshige return 0; 286b4a1efffSKenji Kaneshige } 287b4a1efffSKenji Kaneshige 288bd62e271SKenji Kaneshige static inline int shpc_wait_cmd(struct controller *ctrl) 289bd62e271SKenji Kaneshige { 290bd62e271SKenji Kaneshige int retval = 0; 291b4a1efffSKenji Kaneshige unsigned long timeout = msecs_to_jiffies(1000); 292b4a1efffSKenji Kaneshige int rc; 293b4a1efffSKenji Kaneshige 294b4a1efffSKenji Kaneshige if (shpchp_poll_mode) 295b4a1efffSKenji Kaneshige rc = shpc_poll_ctrl_busy(ctrl); 296b4a1efffSKenji Kaneshige else 297b4a1efffSKenji Kaneshige rc = wait_event_interruptible_timeout(ctrl->queue, 2986aa562c2SKenji Kaneshige !is_ctrl_busy(ctrl), timeout); 299d1729cceSKenji Kaneshige if (!rc && is_ctrl_busy(ctrl)) { 300bd62e271SKenji Kaneshige retval = -EIO; 301f98ca311STaku Izumi ctrl_err(ctrl, "Command not completed in 1000 msec\n"); 302bd62e271SKenji Kaneshige } else if (rc < 0) { 303bd62e271SKenji Kaneshige retval = -EINTR; 304f98ca311STaku Izumi ctrl_info(ctrl, "Command was interrupted by a signal\n"); 305bd62e271SKenji Kaneshige } 306bd62e271SKenji Kaneshige 307bd62e271SKenji Kaneshige return retval; 308bd62e271SKenji Kaneshige } 309bd62e271SKenji Kaneshige 3101da177e4SLinus Torvalds static int shpc_write_cmd(struct slot *slot, u8 t_slot, u8 cmd) 3111da177e4SLinus Torvalds { 31275d97c59SKenji Kaneshige struct controller *ctrl = slot->ctrl; 3131da177e4SLinus Torvalds u16 cmd_status; 3141da177e4SLinus Torvalds int retval = 0; 3151da177e4SLinus Torvalds u16 temp_word; 3161da177e4SLinus Torvalds 317d29aaddaSKenji Kaneshige mutex_lock(&slot->ctrl->cmd_lock); 318d29aaddaSKenji Kaneshige 319b4a1efffSKenji Kaneshige if (!shpc_poll_ctrl_busy(ctrl)) { 3201da177e4SLinus Torvalds /* After 1 sec and and the controller is still busy */ 321be7bce25STaku Izumi ctrl_err(ctrl, "Controller is still busy after 1 sec\n"); 322d29aaddaSKenji Kaneshige retval = -EBUSY; 323d29aaddaSKenji Kaneshige goto out; 3241da177e4SLinus Torvalds } 3251da177e4SLinus Torvalds 3261da177e4SLinus Torvalds ++t_slot; 3271da177e4SLinus Torvalds temp_word = (t_slot << 8) | (cmd & 0xFF); 328f98ca311STaku Izumi ctrl_dbg(ctrl, "%s: t_slot %x cmd %x\n", __func__, t_slot, cmd); 3291da177e4SLinus Torvalds 3301da177e4SLinus Torvalds /* To make sure the Controller Busy bit is 0 before we send out the 3311da177e4SLinus Torvalds * command. 3321da177e4SLinus Torvalds */ 33375d97c59SKenji Kaneshige shpc_writew(ctrl, CMD, temp_word); 3341da177e4SLinus Torvalds 335bd62e271SKenji Kaneshige /* 336bd62e271SKenji Kaneshige * Wait for command completion. 337bd62e271SKenji Kaneshige */ 338bd62e271SKenji Kaneshige retval = shpc_wait_cmd(slot->ctrl); 339d29aaddaSKenji Kaneshige if (retval) 340d29aaddaSKenji Kaneshige goto out; 341d29aaddaSKenji Kaneshige 342d29aaddaSKenji Kaneshige cmd_status = hpc_check_cmd_status(slot->ctrl); 343d29aaddaSKenji Kaneshige if (cmd_status) { 344be7bce25STaku Izumi ctrl_err(ctrl, 345be7bce25STaku Izumi "Failed to issued command 0x%x (error code = %d)\n", 346be7bce25STaku Izumi cmd, cmd_status); 347d29aaddaSKenji Kaneshige retval = -EIO; 348d29aaddaSKenji Kaneshige } 349d29aaddaSKenji Kaneshige out: 350d29aaddaSKenji Kaneshige mutex_unlock(&slot->ctrl->cmd_lock); 3511da177e4SLinus Torvalds return retval; 3521da177e4SLinus Torvalds } 3531da177e4SLinus Torvalds 3541da177e4SLinus Torvalds static int hpc_check_cmd_status(struct controller *ctrl) 3551da177e4SLinus Torvalds { 3561da177e4SLinus Torvalds int retval = 0; 3571555b33dSKenji Kaneshige u16 cmd_status = shpc_readw(ctrl, CMD_STATUS) & 0x000F; 3581da177e4SLinus Torvalds 3591da177e4SLinus Torvalds switch (cmd_status >> 1) { 3601da177e4SLinus Torvalds case 0: 3611da177e4SLinus Torvalds retval = 0; 3621da177e4SLinus Torvalds break; 3631da177e4SLinus Torvalds case 1: 3641da177e4SLinus Torvalds retval = SWITCH_OPEN; 365be7bce25STaku Izumi ctrl_err(ctrl, "Switch opened!\n"); 3661da177e4SLinus Torvalds break; 3671da177e4SLinus Torvalds case 2: 3681da177e4SLinus Torvalds retval = INVALID_CMD; 369be7bce25STaku Izumi ctrl_err(ctrl, "Invalid HPC command!\n"); 3701da177e4SLinus Torvalds break; 3711da177e4SLinus Torvalds case 4: 3721da177e4SLinus Torvalds retval = INVALID_SPEED_MODE; 373be7bce25STaku Izumi ctrl_err(ctrl, "Invalid bus speed/mode!\n"); 3741da177e4SLinus Torvalds break; 3751da177e4SLinus Torvalds default: 3761da177e4SLinus Torvalds retval = cmd_status; 3771da177e4SLinus Torvalds } 3781da177e4SLinus Torvalds 3791da177e4SLinus Torvalds return retval; 3801da177e4SLinus Torvalds } 3811da177e4SLinus Torvalds 3821da177e4SLinus Torvalds 3831da177e4SLinus Torvalds static int hpc_get_attention_status(struct slot *slot, u8 *status) 3841da177e4SLinus Torvalds { 38575d97c59SKenji Kaneshige struct controller *ctrl = slot->ctrl; 3861555b33dSKenji Kaneshige u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); 3871555b33dSKenji Kaneshige u8 state = (slot_reg & ATN_LED_STATE_MASK) >> ATN_LED_STATE_SHIFT; 3881da177e4SLinus Torvalds 3895858759cSKenji Kaneshige switch (state) { 3905858759cSKenji Kaneshige case ATN_LED_STATE_ON: 3911da177e4SLinus Torvalds *status = 1; /* On */ 3921da177e4SLinus Torvalds break; 3935858759cSKenji Kaneshige case ATN_LED_STATE_BLINK: 3941da177e4SLinus Torvalds *status = 2; /* Blink */ 3951da177e4SLinus Torvalds break; 3965858759cSKenji Kaneshige case ATN_LED_STATE_OFF: 3971da177e4SLinus Torvalds *status = 0; /* Off */ 3981da177e4SLinus Torvalds break; 3991da177e4SLinus Torvalds default: 4005858759cSKenji Kaneshige *status = 0xFF; /* Reserved */ 4011da177e4SLinus Torvalds break; 4021da177e4SLinus Torvalds } 4031da177e4SLinus Torvalds 4041da177e4SLinus Torvalds return 0; 4051da177e4SLinus Torvalds } 4061da177e4SLinus Torvalds 4071da177e4SLinus Torvalds static int hpc_get_power_status(struct slot * slot, u8 *status) 4081da177e4SLinus Torvalds { 40975d97c59SKenji Kaneshige struct controller *ctrl = slot->ctrl; 4101555b33dSKenji Kaneshige u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); 4111555b33dSKenji Kaneshige u8 state = (slot_reg & SLOT_STATE_MASK) >> SLOT_STATE_SHIFT; 4121da177e4SLinus Torvalds 4135858759cSKenji Kaneshige switch (state) { 4145858759cSKenji Kaneshige case SLOT_STATE_PWRONLY: 4151da177e4SLinus Torvalds *status = 2; /* Powered only */ 4161da177e4SLinus Torvalds break; 4175858759cSKenji Kaneshige case SLOT_STATE_ENABLED: 4181da177e4SLinus Torvalds *status = 1; /* Enabled */ 4191da177e4SLinus Torvalds break; 4205858759cSKenji Kaneshige case SLOT_STATE_DISABLED: 4211da177e4SLinus Torvalds *status = 0; /* Disabled */ 4221da177e4SLinus Torvalds break; 4231da177e4SLinus Torvalds default: 4245858759cSKenji Kaneshige *status = 0xFF; /* Reserved */ 4251da177e4SLinus Torvalds break; 4261da177e4SLinus Torvalds } 4271da177e4SLinus Torvalds 4285858759cSKenji Kaneshige return 0; 4291da177e4SLinus Torvalds } 4301da177e4SLinus Torvalds 4311da177e4SLinus Torvalds 4321da177e4SLinus Torvalds static int hpc_get_latch_status(struct slot *slot, u8 *status) 4331da177e4SLinus Torvalds { 43475d97c59SKenji Kaneshige struct controller *ctrl = slot->ctrl; 4351555b33dSKenji Kaneshige u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); 4361da177e4SLinus Torvalds 4375858759cSKenji Kaneshige *status = !!(slot_reg & MRL_SENSOR); /* 0 -> close; 1 -> open */ 4381da177e4SLinus Torvalds 4391da177e4SLinus Torvalds return 0; 4401da177e4SLinus Torvalds } 4411da177e4SLinus Torvalds 4421da177e4SLinus Torvalds static int hpc_get_adapter_status(struct slot *slot, u8 *status) 4431da177e4SLinus Torvalds { 44475d97c59SKenji Kaneshige struct controller *ctrl = slot->ctrl; 4451555b33dSKenji Kaneshige u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); 4461555b33dSKenji Kaneshige u8 state = (slot_reg & PRSNT_MASK) >> PRSNT_SHIFT; 4471da177e4SLinus Torvalds 4485858759cSKenji Kaneshige *status = (state != 0x3) ? 1 : 0; 4491da177e4SLinus Torvalds 4501da177e4SLinus Torvalds return 0; 4511da177e4SLinus Torvalds } 4521da177e4SLinus Torvalds 4531da177e4SLinus Torvalds static int hpc_get_prog_int(struct slot *slot, u8 *prog_int) 4541da177e4SLinus Torvalds { 45575d97c59SKenji Kaneshige struct controller *ctrl = slot->ctrl; 4561da177e4SLinus Torvalds 45775d97c59SKenji Kaneshige *prog_int = shpc_readb(ctrl, PROG_INTERFACE); 4581da177e4SLinus Torvalds 4591da177e4SLinus Torvalds return 0; 4601da177e4SLinus Torvalds } 4611da177e4SLinus Torvalds 4621da177e4SLinus Torvalds static int hpc_get_adapter_speed(struct slot *slot, enum pci_bus_speed *value) 4631da177e4SLinus Torvalds { 4641da177e4SLinus Torvalds int retval = 0; 46575d97c59SKenji Kaneshige struct controller *ctrl = slot->ctrl; 4662b34da7eSKenji Kaneshige u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); 4675858759cSKenji Kaneshige u8 m66_cap = !!(slot_reg & MHZ66_CAP); 468795eb5c4SKenji Kaneshige u8 pi, pcix_cap; 4691da177e4SLinus Torvalds 470795eb5c4SKenji Kaneshige if ((retval = hpc_get_prog_int(slot, &pi))) 471795eb5c4SKenji Kaneshige return retval; 472795eb5c4SKenji Kaneshige 473795eb5c4SKenji Kaneshige switch (pi) { 474795eb5c4SKenji Kaneshige case 1: 475795eb5c4SKenji Kaneshige pcix_cap = (slot_reg & PCIX_CAP_MASK_PI1) >> PCIX_CAP_SHIFT; 476795eb5c4SKenji Kaneshige break; 477795eb5c4SKenji Kaneshige case 2: 478795eb5c4SKenji Kaneshige pcix_cap = (slot_reg & PCIX_CAP_MASK_PI2) >> PCIX_CAP_SHIFT; 479795eb5c4SKenji Kaneshige break; 480795eb5c4SKenji Kaneshige default: 481795eb5c4SKenji Kaneshige return -ENODEV; 482795eb5c4SKenji Kaneshige } 483795eb5c4SKenji Kaneshige 484f98ca311STaku Izumi ctrl_dbg(ctrl, "%s: slot_reg = %x, pcix_cap = %x, m66_cap = %x\n", 48566bef8c0SHarvey Harrison __func__, slot_reg, pcix_cap, m66_cap); 4861da177e4SLinus Torvalds 4871da177e4SLinus Torvalds switch (pcix_cap) { 4880afabe90SKenji Kaneshige case 0x0: 4891da177e4SLinus Torvalds *value = m66_cap ? PCI_SPEED_66MHz : PCI_SPEED_33MHz; 4901da177e4SLinus Torvalds break; 4910afabe90SKenji Kaneshige case 0x1: 4921da177e4SLinus Torvalds *value = PCI_SPEED_66MHz_PCIX; 4931da177e4SLinus Torvalds break; 4940afabe90SKenji Kaneshige case 0x3: 4951da177e4SLinus Torvalds *value = PCI_SPEED_133MHz_PCIX; 4961da177e4SLinus Torvalds break; 4970afabe90SKenji Kaneshige case 0x4: 4981da177e4SLinus Torvalds *value = PCI_SPEED_133MHz_PCIX_266; 4991da177e4SLinus Torvalds break; 5000afabe90SKenji Kaneshige case 0x5: 5011da177e4SLinus Torvalds *value = PCI_SPEED_133MHz_PCIX_533; 5021da177e4SLinus Torvalds break; 5030afabe90SKenji Kaneshige case 0x2: 5041da177e4SLinus Torvalds default: 5051da177e4SLinus Torvalds *value = PCI_SPEED_UNKNOWN; 5061da177e4SLinus Torvalds retval = -ENODEV; 5071da177e4SLinus Torvalds break; 5081da177e4SLinus Torvalds } 5091da177e4SLinus Torvalds 510f98ca311STaku Izumi ctrl_dbg(ctrl, "Adapter speed = %d\n", *value); 5111da177e4SLinus Torvalds return retval; 5121da177e4SLinus Torvalds } 5131da177e4SLinus Torvalds 5141da177e4SLinus Torvalds static int hpc_get_mode1_ECC_cap(struct slot *slot, u8 *mode) 5151da177e4SLinus Torvalds { 5161da177e4SLinus Torvalds int retval = 0; 5171555b33dSKenji Kaneshige struct controller *ctrl = slot->ctrl; 5181555b33dSKenji Kaneshige u16 sec_bus_status = shpc_readw(ctrl, SEC_BUS_CONFIG); 5191555b33dSKenji Kaneshige u8 pi = shpc_readb(ctrl, PROG_INTERFACE); 5201da177e4SLinus Torvalds 5211da177e4SLinus Torvalds if (pi == 2) { 52287d6c559SKenji Kaneshige *mode = (sec_bus_status & 0x0100) >> 8; 5231da177e4SLinus Torvalds } else { 5241da177e4SLinus Torvalds retval = -1; 5251da177e4SLinus Torvalds } 5261da177e4SLinus Torvalds 527f98ca311STaku Izumi ctrl_dbg(ctrl, "Mode 1 ECC cap = %d\n", *mode); 5281da177e4SLinus Torvalds return retval; 5291da177e4SLinus Torvalds } 5301da177e4SLinus Torvalds 5311da177e4SLinus Torvalds static int hpc_query_power_fault(struct slot * slot) 5321da177e4SLinus Torvalds { 53375d97c59SKenji Kaneshige struct controller *ctrl = slot->ctrl; 5341555b33dSKenji Kaneshige u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); 5351da177e4SLinus Torvalds 5361da177e4SLinus Torvalds /* Note: Logic 0 => fault */ 5375858759cSKenji Kaneshige return !(slot_reg & POWER_FAULT); 5381da177e4SLinus Torvalds } 5391da177e4SLinus Torvalds 5401da177e4SLinus Torvalds static int hpc_set_attention_status(struct slot *slot, u8 value) 5411da177e4SLinus Torvalds { 5421da177e4SLinus Torvalds u8 slot_cmd = 0; 5431da177e4SLinus Torvalds 5441da177e4SLinus Torvalds switch (value) { 5451da177e4SLinus Torvalds case 0 : 5464085399dSKenji Kaneshige slot_cmd = SET_ATTN_OFF; /* OFF */ 5471da177e4SLinus Torvalds break; 5481da177e4SLinus Torvalds case 1: 5494085399dSKenji Kaneshige slot_cmd = SET_ATTN_ON; /* ON */ 5501da177e4SLinus Torvalds break; 5511da177e4SLinus Torvalds case 2: 5524085399dSKenji Kaneshige slot_cmd = SET_ATTN_BLINK; /* BLINK */ 5531da177e4SLinus Torvalds break; 5541da177e4SLinus Torvalds default: 5551da177e4SLinus Torvalds return -1; 5561da177e4SLinus Torvalds } 5571da177e4SLinus Torvalds 558d4fbf600SKenji Kaneshige return shpc_write_cmd(slot, slot->hp_slot, slot_cmd); 5591da177e4SLinus Torvalds } 5601da177e4SLinus Torvalds 5611da177e4SLinus Torvalds 5621da177e4SLinus Torvalds static void hpc_set_green_led_on(struct slot *slot) 5631da177e4SLinus Torvalds { 5644085399dSKenji Kaneshige shpc_write_cmd(slot, slot->hp_slot, SET_PWR_ON); 5651da177e4SLinus Torvalds } 5661da177e4SLinus Torvalds 5671da177e4SLinus Torvalds static void hpc_set_green_led_off(struct slot *slot) 5681da177e4SLinus Torvalds { 5694085399dSKenji Kaneshige shpc_write_cmd(slot, slot->hp_slot, SET_PWR_OFF); 5701da177e4SLinus Torvalds } 5711da177e4SLinus Torvalds 5721da177e4SLinus Torvalds static void hpc_set_green_led_blink(struct slot *slot) 5731da177e4SLinus Torvalds { 5744085399dSKenji Kaneshige shpc_write_cmd(slot, slot->hp_slot, SET_PWR_BLINK); 5751da177e4SLinus Torvalds } 5761da177e4SLinus Torvalds 5771da177e4SLinus Torvalds static void hpc_release_ctlr(struct controller *ctrl) 5781da177e4SLinus Torvalds { 579f7391f53SKenji Kaneshige int i; 580d49f2c49SKenji Kaneshige u32 slot_reg, serr_int; 5811da177e4SLinus Torvalds 582f7391f53SKenji Kaneshige /* 583795eb5c4SKenji Kaneshige * Mask event interrupts and SERRs of all slots 584f7391f53SKenji Kaneshige */ 585795eb5c4SKenji Kaneshige for (i = 0; i < ctrl->num_slots; i++) { 586795eb5c4SKenji Kaneshige slot_reg = shpc_readl(ctrl, SLOT_REG(i)); 587795eb5c4SKenji Kaneshige slot_reg |= (PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK | 588795eb5c4SKenji Kaneshige BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK | 589795eb5c4SKenji Kaneshige CON_PFAULT_INTR_MASK | MRL_CHANGE_SERR_MASK | 590795eb5c4SKenji Kaneshige CON_PFAULT_SERR_MASK); 591795eb5c4SKenji Kaneshige slot_reg &= ~SLOT_REG_RSVDZ_MASK; 592795eb5c4SKenji Kaneshige shpc_writel(ctrl, SLOT_REG(i), slot_reg); 593795eb5c4SKenji Kaneshige } 594f7391f53SKenji Kaneshige 595f7391f53SKenji Kaneshige cleanup_slots(ctrl); 596f7391f53SKenji Kaneshige 597d49f2c49SKenji Kaneshige /* 5983609801eSJoe Perches * Mask SERR and System Interrupt generation 599d49f2c49SKenji Kaneshige */ 600d49f2c49SKenji Kaneshige serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE); 601d49f2c49SKenji Kaneshige serr_int |= (GLOBAL_INTR_MASK | GLOBAL_SERR_MASK | 602d49f2c49SKenji Kaneshige COMMAND_INTR_MASK | ARBITER_SERR_MASK); 603d49f2c49SKenji Kaneshige serr_int &= ~SERR_INTR_RSVDZ_MASK; 604d49f2c49SKenji Kaneshige shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int); 605d49f2c49SKenji Kaneshige 6060abe68ceSKenji Kaneshige if (shpchp_poll_mode) 6070abe68ceSKenji Kaneshige del_timer(&ctrl->poll_timer); 6080abe68ceSKenji Kaneshige else { 6090abe68ceSKenji Kaneshige free_irq(ctrl->pci_dev->irq, ctrl); 6100abe68ceSKenji Kaneshige pci_disable_msi(ctrl->pci_dev); 6111da177e4SLinus Torvalds } 612f7391f53SKenji Kaneshige 6130abe68ceSKenji Kaneshige iounmap(ctrl->creg); 6140455986cSKenji Kaneshige release_mem_region(ctrl->mmio_base, ctrl->mmio_size); 6151da177e4SLinus Torvalds } 6161da177e4SLinus Torvalds 6171da177e4SLinus Torvalds static int hpc_power_on_slot(struct slot * slot) 6181da177e4SLinus Torvalds { 619d4fbf600SKenji Kaneshige int retval; 6201da177e4SLinus Torvalds 6214085399dSKenji Kaneshige retval = shpc_write_cmd(slot, slot->hp_slot, SET_SLOT_PWR); 6221555b33dSKenji Kaneshige if (retval) 623f98ca311STaku Izumi ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__); 6241555b33dSKenji Kaneshige 625d4fbf600SKenji Kaneshige return retval; 6261da177e4SLinus Torvalds } 6271da177e4SLinus Torvalds 6281da177e4SLinus Torvalds static int hpc_slot_enable(struct slot * slot) 6291da177e4SLinus Torvalds { 630d4fbf600SKenji Kaneshige int retval; 6311da177e4SLinus Torvalds 6324085399dSKenji Kaneshige /* Slot - Enable, Power Indicator - Blink, Attention Indicator - Off */ 6334085399dSKenji Kaneshige retval = shpc_write_cmd(slot, slot->hp_slot, 6344085399dSKenji Kaneshige SET_SLOT_ENABLE | SET_PWR_BLINK | SET_ATTN_OFF); 6351555b33dSKenji Kaneshige if (retval) 636f98ca311STaku Izumi ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__); 6371da177e4SLinus Torvalds 6381555b33dSKenji Kaneshige return retval; 6391da177e4SLinus Torvalds } 6401da177e4SLinus Torvalds 6411da177e4SLinus Torvalds static int hpc_slot_disable(struct slot * slot) 6421da177e4SLinus Torvalds { 643d4fbf600SKenji Kaneshige int retval; 6441da177e4SLinus Torvalds 6454085399dSKenji Kaneshige /* Slot - Disable, Power Indicator - Off, Attention Indicator - On */ 6464085399dSKenji Kaneshige retval = shpc_write_cmd(slot, slot->hp_slot, 6474085399dSKenji Kaneshige SET_SLOT_DISABLE | SET_PWR_OFF | SET_ATTN_ON); 6481555b33dSKenji Kaneshige if (retval) 649f98ca311STaku Izumi ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__); 6501da177e4SLinus Torvalds 6511555b33dSKenji Kaneshige return retval; 6521da177e4SLinus Torvalds } 6531da177e4SLinus Torvalds 6543749c51aSMatthew Wilcox static int shpc_get_cur_bus_speed(struct controller *ctrl) 6553749c51aSMatthew Wilcox { 6563749c51aSMatthew Wilcox int retval = 0; 6573749c51aSMatthew Wilcox struct pci_bus *bus = ctrl->pci_dev->subordinate; 6583749c51aSMatthew Wilcox enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN; 6593749c51aSMatthew Wilcox u16 sec_bus_reg = shpc_readw(ctrl, SEC_BUS_CONFIG); 6603749c51aSMatthew Wilcox u8 pi = shpc_readb(ctrl, PROG_INTERFACE); 6613749c51aSMatthew Wilcox u8 speed_mode = (pi == 2) ? (sec_bus_reg & 0xF) : (sec_bus_reg & 0x7); 6623749c51aSMatthew Wilcox 6633749c51aSMatthew Wilcox if ((pi == 1) && (speed_mode > 4)) { 6643749c51aSMatthew Wilcox retval = -ENODEV; 6653749c51aSMatthew Wilcox goto out; 6663749c51aSMatthew Wilcox } 6673749c51aSMatthew Wilcox 6683749c51aSMatthew Wilcox switch (speed_mode) { 6693749c51aSMatthew Wilcox case 0x0: 6703749c51aSMatthew Wilcox bus_speed = PCI_SPEED_33MHz; 6713749c51aSMatthew Wilcox break; 6723749c51aSMatthew Wilcox case 0x1: 6733749c51aSMatthew Wilcox bus_speed = PCI_SPEED_66MHz; 6743749c51aSMatthew Wilcox break; 6753749c51aSMatthew Wilcox case 0x2: 6763749c51aSMatthew Wilcox bus_speed = PCI_SPEED_66MHz_PCIX; 6773749c51aSMatthew Wilcox break; 6783749c51aSMatthew Wilcox case 0x3: 6793749c51aSMatthew Wilcox bus_speed = PCI_SPEED_100MHz_PCIX; 6803749c51aSMatthew Wilcox break; 6813749c51aSMatthew Wilcox case 0x4: 6823749c51aSMatthew Wilcox bus_speed = PCI_SPEED_133MHz_PCIX; 6833749c51aSMatthew Wilcox break; 6843749c51aSMatthew Wilcox case 0x5: 6853749c51aSMatthew Wilcox bus_speed = PCI_SPEED_66MHz_PCIX_ECC; 6863749c51aSMatthew Wilcox break; 6873749c51aSMatthew Wilcox case 0x6: 6883749c51aSMatthew Wilcox bus_speed = PCI_SPEED_100MHz_PCIX_ECC; 6893749c51aSMatthew Wilcox break; 6903749c51aSMatthew Wilcox case 0x7: 6913749c51aSMatthew Wilcox bus_speed = PCI_SPEED_133MHz_PCIX_ECC; 6923749c51aSMatthew Wilcox break; 6933749c51aSMatthew Wilcox case 0x8: 6943749c51aSMatthew Wilcox bus_speed = PCI_SPEED_66MHz_PCIX_266; 6953749c51aSMatthew Wilcox break; 6963749c51aSMatthew Wilcox case 0x9: 6973749c51aSMatthew Wilcox bus_speed = PCI_SPEED_100MHz_PCIX_266; 6983749c51aSMatthew Wilcox break; 6993749c51aSMatthew Wilcox case 0xa: 7003749c51aSMatthew Wilcox bus_speed = PCI_SPEED_133MHz_PCIX_266; 7013749c51aSMatthew Wilcox break; 7023749c51aSMatthew Wilcox case 0xb: 7033749c51aSMatthew Wilcox bus_speed = PCI_SPEED_66MHz_PCIX_533; 7043749c51aSMatthew Wilcox break; 7053749c51aSMatthew Wilcox case 0xc: 7063749c51aSMatthew Wilcox bus_speed = PCI_SPEED_100MHz_PCIX_533; 7073749c51aSMatthew Wilcox break; 7083749c51aSMatthew Wilcox case 0xd: 7093749c51aSMatthew Wilcox bus_speed = PCI_SPEED_133MHz_PCIX_533; 7103749c51aSMatthew Wilcox break; 7113749c51aSMatthew Wilcox default: 7123749c51aSMatthew Wilcox retval = -ENODEV; 7133749c51aSMatthew Wilcox break; 7143749c51aSMatthew Wilcox } 7153749c51aSMatthew Wilcox 7163749c51aSMatthew Wilcox out: 7173749c51aSMatthew Wilcox bus->cur_bus_speed = bus_speed; 7183749c51aSMatthew Wilcox dbg("Current bus speed = %d\n", bus_speed); 7193749c51aSMatthew Wilcox return retval; 7203749c51aSMatthew Wilcox } 7213749c51aSMatthew Wilcox 7223749c51aSMatthew Wilcox 7231da177e4SLinus Torvalds static int hpc_set_bus_speed_mode(struct slot * slot, enum pci_bus_speed value) 7241da177e4SLinus Torvalds { 7250afabe90SKenji Kaneshige int retval; 72675d97c59SKenji Kaneshige struct controller *ctrl = slot->ctrl; 7270afabe90SKenji Kaneshige u8 pi, cmd; 7281da177e4SLinus Torvalds 72975d97c59SKenji Kaneshige pi = shpc_readb(ctrl, PROG_INTERFACE); 7300afabe90SKenji Kaneshige if ((pi == 1) && (value > PCI_SPEED_133MHz_PCIX)) 7310afabe90SKenji Kaneshige return -EINVAL; 7321da177e4SLinus Torvalds 7331da177e4SLinus Torvalds switch (value) { 7340afabe90SKenji Kaneshige case PCI_SPEED_33MHz: 7350afabe90SKenji Kaneshige cmd = SETA_PCI_33MHZ; 7361da177e4SLinus Torvalds break; 7370afabe90SKenji Kaneshige case PCI_SPEED_66MHz: 7380afabe90SKenji Kaneshige cmd = SETA_PCI_66MHZ; 7391da177e4SLinus Torvalds break; 7400afabe90SKenji Kaneshige case PCI_SPEED_66MHz_PCIX: 7410afabe90SKenji Kaneshige cmd = SETA_PCIX_66MHZ; 7421da177e4SLinus Torvalds break; 7430afabe90SKenji Kaneshige case PCI_SPEED_100MHz_PCIX: 7440afabe90SKenji Kaneshige cmd = SETA_PCIX_100MHZ; 7451da177e4SLinus Torvalds break; 7460afabe90SKenji Kaneshige case PCI_SPEED_133MHz_PCIX: 7470afabe90SKenji Kaneshige cmd = SETA_PCIX_133MHZ; 7480afabe90SKenji Kaneshige break; 7490afabe90SKenji Kaneshige case PCI_SPEED_66MHz_PCIX_ECC: 7500afabe90SKenji Kaneshige cmd = SETB_PCIX_66MHZ_EM; 7510afabe90SKenji Kaneshige break; 7520afabe90SKenji Kaneshige case PCI_SPEED_100MHz_PCIX_ECC: 7530afabe90SKenji Kaneshige cmd = SETB_PCIX_100MHZ_EM; 7540afabe90SKenji Kaneshige break; 7550afabe90SKenji Kaneshige case PCI_SPEED_133MHz_PCIX_ECC: 7560afabe90SKenji Kaneshige cmd = SETB_PCIX_133MHZ_EM; 7570afabe90SKenji Kaneshige break; 7580afabe90SKenji Kaneshige case PCI_SPEED_66MHz_PCIX_266: 7590afabe90SKenji Kaneshige cmd = SETB_PCIX_66MHZ_266; 7600afabe90SKenji Kaneshige break; 7610afabe90SKenji Kaneshige case PCI_SPEED_100MHz_PCIX_266: 7620afabe90SKenji Kaneshige cmd = SETB_PCIX_100MHZ_266; 7630afabe90SKenji Kaneshige break; 7640afabe90SKenji Kaneshige case PCI_SPEED_133MHz_PCIX_266: 7650afabe90SKenji Kaneshige cmd = SETB_PCIX_133MHZ_266; 7660afabe90SKenji Kaneshige break; 7670afabe90SKenji Kaneshige case PCI_SPEED_66MHz_PCIX_533: 7680afabe90SKenji Kaneshige cmd = SETB_PCIX_66MHZ_533; 7690afabe90SKenji Kaneshige break; 7700afabe90SKenji Kaneshige case PCI_SPEED_100MHz_PCIX_533: 7710afabe90SKenji Kaneshige cmd = SETB_PCIX_100MHZ_533; 7720afabe90SKenji Kaneshige break; 7730afabe90SKenji Kaneshige case PCI_SPEED_133MHz_PCIX_533: 7740afabe90SKenji Kaneshige cmd = SETB_PCIX_133MHZ_533; 7751da177e4SLinus Torvalds break; 7761da177e4SLinus Torvalds default: 7770afabe90SKenji Kaneshige return -EINVAL; 7781da177e4SLinus Torvalds } 7791da177e4SLinus Torvalds 7800afabe90SKenji Kaneshige retval = shpc_write_cmd(slot, 0, cmd); 7810afabe90SKenji Kaneshige if (retval) 782f98ca311STaku Izumi ctrl_err(ctrl, "%s: Write command failed!\n", __func__); 7833749c51aSMatthew Wilcox else 7843749c51aSMatthew Wilcox shpc_get_cur_bus_speed(ctrl); 7851da177e4SLinus Torvalds 7861da177e4SLinus Torvalds return retval; 7871da177e4SLinus Torvalds } 7881da177e4SLinus Torvalds 7897d12e780SDavid Howells static irqreturn_t shpc_isr(int irq, void *dev_id) 7901da177e4SLinus Torvalds { 791c4cecc19SKenji Kaneshige struct controller *ctrl = (struct controller *)dev_id; 792c4cecc19SKenji Kaneshige u32 serr_int, slot_reg, intr_loc, intr_loc2; 7931da177e4SLinus Torvalds int hp_slot; 7941da177e4SLinus Torvalds 7951da177e4SLinus Torvalds /* Check to see if it was our interrupt */ 79675d97c59SKenji Kaneshige intr_loc = shpc_readl(ctrl, INTR_LOC); 7971da177e4SLinus Torvalds if (!intr_loc) 7981da177e4SLinus Torvalds return IRQ_NONE; 799c4cecc19SKenji Kaneshige 800f98ca311STaku Izumi ctrl_dbg(ctrl, "%s: intr_loc = %x\n", __func__, intr_loc); 8011da177e4SLinus Torvalds 8021da177e4SLinus Torvalds if(!shpchp_poll_mode) { 803c4cecc19SKenji Kaneshige /* 804c4cecc19SKenji Kaneshige * Mask Global Interrupt Mask - see implementation 805c4cecc19SKenji Kaneshige * note on p. 139 of SHPC spec rev 1.0 806c4cecc19SKenji Kaneshige */ 807c4cecc19SKenji Kaneshige serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE); 808c4cecc19SKenji Kaneshige serr_int |= GLOBAL_INTR_MASK; 809c4cecc19SKenji Kaneshige serr_int &= ~SERR_INTR_RSVDZ_MASK; 810c4cecc19SKenji Kaneshige shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int); 8111da177e4SLinus Torvalds 81275d97c59SKenji Kaneshige intr_loc2 = shpc_readl(ctrl, INTR_LOC); 813f98ca311STaku Izumi ctrl_dbg(ctrl, "%s: intr_loc2 = %x\n", __func__, intr_loc2); 8141da177e4SLinus Torvalds } 8151da177e4SLinus Torvalds 816c4cecc19SKenji Kaneshige if (intr_loc & CMD_INTR_PENDING) { 8171da177e4SLinus Torvalds /* 8181da177e4SLinus Torvalds * Command Complete Interrupt Pending 819f467f618SKenji Kaneshige * RO only - clear by writing 1 to the Command Completion 8201da177e4SLinus Torvalds * Detect bit in Controller SERR-INT register 8211da177e4SLinus Torvalds */ 822c4cecc19SKenji Kaneshige serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE); 823c4cecc19SKenji Kaneshige serr_int &= ~SERR_INTR_RSVDZ_MASK; 824c4cecc19SKenji Kaneshige shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int); 825c4cecc19SKenji Kaneshige 8261da177e4SLinus Torvalds wake_up_interruptible(&ctrl->queue); 8271da177e4SLinus Torvalds } 8281da177e4SLinus Torvalds 829c4cecc19SKenji Kaneshige if (!(intr_loc & ~CMD_INTR_PENDING)) 830e4e73041SKenji Kaneshige goto out; 8311da177e4SLinus Torvalds 8321da177e4SLinus Torvalds for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) { 8331da177e4SLinus Torvalds /* To find out which slot has interrupt pending */ 834c4cecc19SKenji Kaneshige if (!(intr_loc & SLOT_INTR_PENDING(hp_slot))) 835c4cecc19SKenji Kaneshige continue; 836c4cecc19SKenji Kaneshige 837c4cecc19SKenji Kaneshige slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot)); 838be7bce25STaku Izumi ctrl_dbg(ctrl, "Slot %x with intr, slot register = %x\n", 839be7bce25STaku Izumi hp_slot, slot_reg); 840c4cecc19SKenji Kaneshige 841c4cecc19SKenji Kaneshige if (slot_reg & MRL_CHANGE_DETECTED) 8420abe68ceSKenji Kaneshige shpchp_handle_switch_change(hp_slot, ctrl); 843c4cecc19SKenji Kaneshige 844c4cecc19SKenji Kaneshige if (slot_reg & BUTTON_PRESS_DETECTED) 8450abe68ceSKenji Kaneshige shpchp_handle_attention_button(hp_slot, ctrl); 846c4cecc19SKenji Kaneshige 847c4cecc19SKenji Kaneshige if (slot_reg & PRSNT_CHANGE_DETECTED) 8480abe68ceSKenji Kaneshige shpchp_handle_presence_change(hp_slot, ctrl); 849c4cecc19SKenji Kaneshige 850c4cecc19SKenji Kaneshige if (slot_reg & (ISO_PFAULT_DETECTED | CON_PFAULT_DETECTED)) 8510abe68ceSKenji Kaneshige shpchp_handle_power_fault(hp_slot, ctrl); 8521da177e4SLinus Torvalds 8531da177e4SLinus Torvalds /* Clear all slot events */ 854c4cecc19SKenji Kaneshige slot_reg &= ~SLOT_REG_RSVDZ_MASK; 855c4cecc19SKenji Kaneshige shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg); 8561da177e4SLinus Torvalds } 857e4e73041SKenji Kaneshige out: 8581da177e4SLinus Torvalds if (!shpchp_poll_mode) { 8591da177e4SLinus Torvalds /* Unmask Global Interrupt Mask */ 860c4cecc19SKenji Kaneshige serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE); 861c4cecc19SKenji Kaneshige serr_int &= ~(GLOBAL_INTR_MASK | SERR_INTR_RSVDZ_MASK); 862c4cecc19SKenji Kaneshige shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int); 8631da177e4SLinus Torvalds } 8641da177e4SLinus Torvalds 8651da177e4SLinus Torvalds return IRQ_HANDLED; 8661da177e4SLinus Torvalds } 8671da177e4SLinus Torvalds 8683749c51aSMatthew Wilcox static int shpc_get_max_bus_speed(struct controller *ctrl) 8691da177e4SLinus Torvalds { 8700afabe90SKenji Kaneshige int retval = 0; 8713749c51aSMatthew Wilcox struct pci_bus *bus = ctrl->pci_dev->subordinate; 8721da177e4SLinus Torvalds enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN; 87375d97c59SKenji Kaneshige u8 pi = shpc_readb(ctrl, PROG_INTERFACE); 87475d97c59SKenji Kaneshige u32 slot_avail1 = shpc_readl(ctrl, SLOT_AVAIL1); 87575d97c59SKenji Kaneshige u32 slot_avail2 = shpc_readl(ctrl, SLOT_AVAIL2); 8761da177e4SLinus Torvalds 8771da177e4SLinus Torvalds if (pi == 2) { 8786558b6abSKenji Kaneshige if (slot_avail2 & SLOT_133MHZ_PCIX_533) 8790afabe90SKenji Kaneshige bus_speed = PCI_SPEED_133MHz_PCIX_533; 8806558b6abSKenji Kaneshige else if (slot_avail2 & SLOT_100MHZ_PCIX_533) 8810afabe90SKenji Kaneshige bus_speed = PCI_SPEED_100MHz_PCIX_533; 8826558b6abSKenji Kaneshige else if (slot_avail2 & SLOT_66MHZ_PCIX_533) 8830afabe90SKenji Kaneshige bus_speed = PCI_SPEED_66MHz_PCIX_533; 8846558b6abSKenji Kaneshige else if (slot_avail2 & SLOT_133MHZ_PCIX_266) 8850afabe90SKenji Kaneshige bus_speed = PCI_SPEED_133MHz_PCIX_266; 8866558b6abSKenji Kaneshige else if (slot_avail2 & SLOT_100MHZ_PCIX_266) 8870afabe90SKenji Kaneshige bus_speed = PCI_SPEED_100MHz_PCIX_266; 8886558b6abSKenji Kaneshige else if (slot_avail2 & SLOT_66MHZ_PCIX_266) 8890afabe90SKenji Kaneshige bus_speed = PCI_SPEED_66MHz_PCIX_266; 8900afabe90SKenji Kaneshige } 8910afabe90SKenji Kaneshige 8920afabe90SKenji Kaneshige if (bus_speed == PCI_SPEED_UNKNOWN) { 8936558b6abSKenji Kaneshige if (slot_avail1 & SLOT_133MHZ_PCIX) 8940afabe90SKenji Kaneshige bus_speed = PCI_SPEED_133MHz_PCIX; 8956558b6abSKenji Kaneshige else if (slot_avail1 & SLOT_100MHZ_PCIX) 8960afabe90SKenji Kaneshige bus_speed = PCI_SPEED_100MHz_PCIX; 8976558b6abSKenji Kaneshige else if (slot_avail1 & SLOT_66MHZ_PCIX) 8980afabe90SKenji Kaneshige bus_speed = PCI_SPEED_66MHz_PCIX; 8996558b6abSKenji Kaneshige else if (slot_avail2 & SLOT_66MHZ) 9000afabe90SKenji Kaneshige bus_speed = PCI_SPEED_66MHz; 9016558b6abSKenji Kaneshige else if (slot_avail1 & SLOT_33MHZ) 9020afabe90SKenji Kaneshige bus_speed = PCI_SPEED_33MHz; 9030afabe90SKenji Kaneshige else 9040afabe90SKenji Kaneshige retval = -ENODEV; 9051da177e4SLinus Torvalds } 9061da177e4SLinus Torvalds 9073749c51aSMatthew Wilcox bus->max_bus_speed = bus_speed; 908f98ca311STaku Izumi ctrl_dbg(ctrl, "Max bus speed = %d\n", bus_speed); 9091555b33dSKenji Kaneshige 9101da177e4SLinus Torvalds return retval; 9111da177e4SLinus Torvalds } 9121da177e4SLinus Torvalds 9131da177e4SLinus Torvalds static struct hpc_ops shpchp_hpc_ops = { 9141da177e4SLinus Torvalds .power_on_slot = hpc_power_on_slot, 9151da177e4SLinus Torvalds .slot_enable = hpc_slot_enable, 9161da177e4SLinus Torvalds .slot_disable = hpc_slot_disable, 9171da177e4SLinus Torvalds .set_bus_speed_mode = hpc_set_bus_speed_mode, 9181da177e4SLinus Torvalds .set_attention_status = hpc_set_attention_status, 9191da177e4SLinus Torvalds .get_power_status = hpc_get_power_status, 9201da177e4SLinus Torvalds .get_attention_status = hpc_get_attention_status, 9211da177e4SLinus Torvalds .get_latch_status = hpc_get_latch_status, 9221da177e4SLinus Torvalds .get_adapter_status = hpc_get_adapter_status, 9231da177e4SLinus Torvalds 9241da177e4SLinus Torvalds .get_adapter_speed = hpc_get_adapter_speed, 9251da177e4SLinus Torvalds .get_mode1_ECC_cap = hpc_get_mode1_ECC_cap, 9261da177e4SLinus Torvalds .get_prog_int = hpc_get_prog_int, 9271da177e4SLinus Torvalds 9281da177e4SLinus Torvalds .query_power_fault = hpc_query_power_fault, 9291da177e4SLinus Torvalds .green_led_on = hpc_set_green_led_on, 9301da177e4SLinus Torvalds .green_led_off = hpc_set_green_led_off, 9311da177e4SLinus Torvalds .green_led_blink = hpc_set_green_led_blink, 9321da177e4SLinus Torvalds 9331da177e4SLinus Torvalds .release_ctlr = hpc_release_ctlr, 9341da177e4SLinus Torvalds }; 9351da177e4SLinus Torvalds 936ee138334Srajesh.shah@intel.com int shpc_init(struct controller *ctrl, struct pci_dev *pdev) 9371da177e4SLinus Torvalds { 938662a98fbSAmol Lad int rc = -1, num_slots = 0; 9391da177e4SLinus Torvalds u8 hp_slot; 9400455986cSKenji Kaneshige u32 shpc_base_offset; 94175d97c59SKenji Kaneshige u32 tempdword, slot_reg, slot_config; 9421da177e4SLinus Torvalds u8 i; 9431da177e4SLinus Torvalds 9440455986cSKenji Kaneshige ctrl->pci_dev = pdev; /* pci_dev of the P2P bridge */ 945be7bce25STaku Izumi ctrl_dbg(ctrl, "Hotplug Controller:\n"); 9460455986cSKenji Kaneshige 947ee138334Srajesh.shah@intel.com if ((pdev->vendor == PCI_VENDOR_ID_AMD) || (pdev->device == 948ee138334Srajesh.shah@intel.com PCI_DEVICE_ID_AMD_GOLAM_7450)) { 9490455986cSKenji Kaneshige /* amd shpc driver doesn't use Base Offset; assume 0 */ 9500455986cSKenji Kaneshige ctrl->mmio_base = pci_resource_start(pdev, 0); 9510455986cSKenji Kaneshige ctrl->mmio_size = pci_resource_len(pdev, 0); 9521da177e4SLinus Torvalds } else { 9530455986cSKenji Kaneshige ctrl->cap_offset = pci_find_capability(pdev, PCI_CAP_ID_SHPC); 9540455986cSKenji Kaneshige if (!ctrl->cap_offset) { 955be7bce25STaku Izumi ctrl_err(ctrl, "Cannot find PCI capability\n"); 9560abe68ceSKenji Kaneshige goto abort; 9571da177e4SLinus Torvalds } 958be7bce25STaku Izumi ctrl_dbg(ctrl, " cap_offset = %x\n", ctrl->cap_offset); 9591da177e4SLinus Torvalds 96075d97c59SKenji Kaneshige rc = shpc_indirect_read(ctrl, 0, &shpc_base_offset); 9611da177e4SLinus Torvalds if (rc) { 962be7bce25STaku Izumi ctrl_err(ctrl, "Cannot read base_offset\n"); 9630abe68ceSKenji Kaneshige goto abort; 9641da177e4SLinus Torvalds } 9651da177e4SLinus Torvalds 96675d97c59SKenji Kaneshige rc = shpc_indirect_read(ctrl, 3, &tempdword); 9671da177e4SLinus Torvalds if (rc) { 968be7bce25STaku Izumi ctrl_err(ctrl, "Cannot read slot config\n"); 9690abe68ceSKenji Kaneshige goto abort; 9701da177e4SLinus Torvalds } 9710455986cSKenji Kaneshige num_slots = tempdword & SLOT_NUM; 972be7bce25STaku Izumi ctrl_dbg(ctrl, " num_slots (indirect) %x\n", num_slots); 9731da177e4SLinus Torvalds 9740455986cSKenji Kaneshige for (i = 0; i < 9 + num_slots; i++) { 97575d97c59SKenji Kaneshige rc = shpc_indirect_read(ctrl, i, &tempdword); 9761da177e4SLinus Torvalds if (rc) { 977be7bce25STaku Izumi ctrl_err(ctrl, 978be7bce25STaku Izumi "Cannot read creg (index = %d)\n", i); 9790abe68ceSKenji Kaneshige goto abort; 9801da177e4SLinus Torvalds } 981be7bce25STaku Izumi ctrl_dbg(ctrl, " offset %d: value %x\n", i, tempdword); 9821da177e4SLinus Torvalds } 9830455986cSKenji Kaneshige 9840455986cSKenji Kaneshige ctrl->mmio_base = 9850455986cSKenji Kaneshige pci_resource_start(pdev, 0) + shpc_base_offset; 9860455986cSKenji Kaneshige ctrl->mmio_size = 0x24 + 0x4 * num_slots; 9871da177e4SLinus Torvalds } 9881da177e4SLinus Torvalds 989f98ca311STaku Izumi ctrl_info(ctrl, "HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", 990f98ca311STaku Izumi pdev->vendor, pdev->device, pdev->subsystem_vendor, 9911da177e4SLinus Torvalds pdev->subsystem_device); 9921da177e4SLinus Torvalds 993662a98fbSAmol Lad rc = pci_enable_device(pdev); 994662a98fbSAmol Lad if (rc) { 995be7bce25STaku Izumi ctrl_err(ctrl, "pci_enable_device failed\n"); 9960abe68ceSKenji Kaneshige goto abort; 997662a98fbSAmol Lad } 9981da177e4SLinus Torvalds 9990455986cSKenji Kaneshige if (!request_mem_region(ctrl->mmio_base, ctrl->mmio_size, MY_NAME)) { 1000be7bce25STaku Izumi ctrl_err(ctrl, "Cannot reserve MMIO region\n"); 1001662a98fbSAmol Lad rc = -1; 10020abe68ceSKenji Kaneshige goto abort; 10031da177e4SLinus Torvalds } 10041da177e4SLinus Torvalds 10050abe68ceSKenji Kaneshige ctrl->creg = ioremap(ctrl->mmio_base, ctrl->mmio_size); 10060abe68ceSKenji Kaneshige if (!ctrl->creg) { 1007be7bce25STaku Izumi ctrl_err(ctrl, "Cannot remap MMIO region %lx @ %lx\n", 1008be7bce25STaku Izumi ctrl->mmio_size, ctrl->mmio_base); 10090455986cSKenji Kaneshige release_mem_region(ctrl->mmio_base, ctrl->mmio_size); 1010662a98fbSAmol Lad rc = -1; 10110abe68ceSKenji Kaneshige goto abort; 10121da177e4SLinus Torvalds } 1013be7bce25STaku Izumi ctrl_dbg(ctrl, "ctrl->creg %p\n", ctrl->creg); 10141da177e4SLinus Torvalds 10156aa4cdd0SIngo Molnar mutex_init(&ctrl->crit_sect); 1016d29aaddaSKenji Kaneshige mutex_init(&ctrl->cmd_lock); 1017d29aaddaSKenji Kaneshige 10181da177e4SLinus Torvalds /* Setup wait queue */ 10191da177e4SLinus Torvalds init_waitqueue_head(&ctrl->queue); 10201da177e4SLinus Torvalds 102175d97c59SKenji Kaneshige ctrl->hpc_ops = &shpchp_hpc_ops; 102275d97c59SKenji Kaneshige 10231da177e4SLinus Torvalds /* Return PCI Controller Info */ 102475d97c59SKenji Kaneshige slot_config = shpc_readl(ctrl, SLOT_CONFIG); 10250abe68ceSKenji Kaneshige ctrl->slot_device_offset = (slot_config & FIRST_DEV_NUM) >> 8; 10260abe68ceSKenji Kaneshige ctrl->num_slots = slot_config & SLOT_NUM; 10270abe68ceSKenji Kaneshige ctrl->first_slot = (slot_config & PSN) >> 16; 10280abe68ceSKenji Kaneshige ctrl->slot_num_inc = ((slot_config & UPDOWN) >> 29) ? 1 : -1; 10291da177e4SLinus Torvalds 10301da177e4SLinus Torvalds /* Mask Global Interrupt Mask & Command Complete Interrupt Mask */ 103175d97c59SKenji Kaneshige tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); 1032be7bce25STaku Izumi ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword); 1033e7138723SKenji Kaneshige tempdword |= (GLOBAL_INTR_MASK | GLOBAL_SERR_MASK | 1034e7138723SKenji Kaneshige COMMAND_INTR_MASK | ARBITER_SERR_MASK); 1035e7138723SKenji Kaneshige tempdword &= ~SERR_INTR_RSVDZ_MASK; 103675d97c59SKenji Kaneshige shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword); 103775d97c59SKenji Kaneshige tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); 1038be7bce25STaku Izumi ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword); 10391da177e4SLinus Torvalds 10401da177e4SLinus Torvalds /* Mask the MRL sensor SERR Mask of individual slot in 10411da177e4SLinus Torvalds * Slot SERR-INT Mask & clear all the existing event if any 10421da177e4SLinus Torvalds */ 10430abe68ceSKenji Kaneshige for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) { 10442b34da7eSKenji Kaneshige slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot)); 1045be7bce25STaku Izumi ctrl_dbg(ctrl, "Default Logical Slot Register %d value %x\n", 1046be7bce25STaku Izumi hp_slot, slot_reg); 1047795eb5c4SKenji Kaneshige slot_reg |= (PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK | 1048795eb5c4SKenji Kaneshige BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK | 1049795eb5c4SKenji Kaneshige CON_PFAULT_INTR_MASK | MRL_CHANGE_SERR_MASK | 1050795eb5c4SKenji Kaneshige CON_PFAULT_SERR_MASK); 1051795eb5c4SKenji Kaneshige slot_reg &= ~SLOT_REG_RSVDZ_MASK; 1052795eb5c4SKenji Kaneshige shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg); 10531da177e4SLinus Torvalds } 10541da177e4SLinus Torvalds 10550abe68ceSKenji Kaneshige if (shpchp_poll_mode) { 10560abe68ceSKenji Kaneshige /* Install interrupt polling timer. Start with 10 sec delay */ 10570abe68ceSKenji Kaneshige init_timer(&ctrl->poll_timer); 10580abe68ceSKenji Kaneshige start_int_poll_timer(ctrl, 10); 10591da177e4SLinus Torvalds } else { 10601da177e4SLinus Torvalds /* Installs the interrupt handler */ 10611da177e4SLinus Torvalds rc = pci_enable_msi(pdev); 10621da177e4SLinus Torvalds if (rc) { 1063f98ca311STaku Izumi ctrl_info(ctrl, 1064f98ca311STaku Izumi "Can't get msi for the hotplug controller\n"); 1065f98ca311STaku Izumi ctrl_info(ctrl, 1066f98ca311STaku Izumi "Use INTx for the hotplug controller\n"); 10670abe68ceSKenji Kaneshige } 10681da177e4SLinus Torvalds 10690abe68ceSKenji Kaneshige rc = request_irq(ctrl->pci_dev->irq, shpc_isr, IRQF_SHARED, 10700abe68ceSKenji Kaneshige MY_NAME, (void *)ctrl); 1071e24dcbefSTejun Heo ctrl_dbg(ctrl, "request_irq %d (returns %d)\n", 1072e24dcbefSTejun Heo ctrl->pci_dev->irq, rc); 10731da177e4SLinus Torvalds if (rc) { 1074f98ca311STaku Izumi ctrl_err(ctrl, "Can't get irq %d for the hotplug " 1075f98ca311STaku Izumi "controller\n", ctrl->pci_dev->irq); 10760abe68ceSKenji Kaneshige goto abort_iounmap; 10771da177e4SLinus Torvalds } 10781da177e4SLinus Torvalds } 1079be7bce25STaku Izumi ctrl_dbg(ctrl, "HPC at %s irq=%x\n", pci_name(pdev), pdev->irq); 10801da177e4SLinus Torvalds 10813749c51aSMatthew Wilcox shpc_get_max_bus_speed(ctrl); 10823749c51aSMatthew Wilcox shpc_get_cur_bus_speed(ctrl); 10833749c51aSMatthew Wilcox 1084795eb5c4SKenji Kaneshige /* 1085795eb5c4SKenji Kaneshige * Unmask all event interrupts of all slots 1086795eb5c4SKenji Kaneshige */ 10870abe68ceSKenji Kaneshige for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) { 10882b34da7eSKenji Kaneshige slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot)); 1089be7bce25STaku Izumi ctrl_dbg(ctrl, "Default Logical Slot Register %d value %x\n", 1090be7bce25STaku Izumi hp_slot, slot_reg); 1091795eb5c4SKenji Kaneshige slot_reg &= ~(PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK | 1092795eb5c4SKenji Kaneshige BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK | 1093795eb5c4SKenji Kaneshige CON_PFAULT_INTR_MASK | SLOT_REG_RSVDZ_MASK); 1094795eb5c4SKenji Kaneshige shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg); 10951da177e4SLinus Torvalds } 10961da177e4SLinus Torvalds if (!shpchp_poll_mode) { 10971da177e4SLinus Torvalds /* Unmask all general input interrupts and SERR */ 109875d97c59SKenji Kaneshige tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); 1099e7138723SKenji Kaneshige tempdword &= ~(GLOBAL_INTR_MASK | COMMAND_INTR_MASK | 1100e7138723SKenji Kaneshige SERR_INTR_RSVDZ_MASK); 110175d97c59SKenji Kaneshige shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword); 110275d97c59SKenji Kaneshige tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); 1103be7bce25STaku Izumi ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword); 11041da177e4SLinus Torvalds } 11051da177e4SLinus Torvalds 11061da177e4SLinus Torvalds return 0; 11071da177e4SLinus Torvalds 11081da177e4SLinus Torvalds /* We end up here for the many possible ways to fail this API. */ 11090abe68ceSKenji Kaneshige abort_iounmap: 11100abe68ceSKenji Kaneshige iounmap(ctrl->creg); 11111da177e4SLinus Torvalds abort: 1112662a98fbSAmol Lad return rc; 11131da177e4SLinus Torvalds } 1114