11da177e4SLinus Torvalds /* 21da177e4SLinus Torvalds * Standard PCI Hot Plug Driver 31da177e4SLinus Torvalds * 41da177e4SLinus Torvalds * Copyright (C) 1995,2001 Compaq Computer Corporation 51da177e4SLinus Torvalds * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com) 61da177e4SLinus Torvalds * Copyright (C) 2001 IBM Corp. 71da177e4SLinus Torvalds * Copyright (C) 2003-2004 Intel Corporation 81da177e4SLinus Torvalds * 91da177e4SLinus Torvalds * All rights reserved. 101da177e4SLinus Torvalds * 111da177e4SLinus Torvalds * This program is free software; you can redistribute it and/or modify 121da177e4SLinus Torvalds * it under the terms of the GNU General Public License as published by 131da177e4SLinus Torvalds * the Free Software Foundation; either version 2 of the License, or (at 141da177e4SLinus Torvalds * your option) any later version. 151da177e4SLinus Torvalds * 161da177e4SLinus Torvalds * This program is distributed in the hope that it will be useful, but 171da177e4SLinus Torvalds * WITHOUT ANY WARRANTY; without even the implied warranty of 181da177e4SLinus Torvalds * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 191da177e4SLinus Torvalds * NON INFRINGEMENT. See the GNU General Public License for more 201da177e4SLinus Torvalds * details. 211da177e4SLinus Torvalds * 221da177e4SLinus Torvalds * You should have received a copy of the GNU General Public License 231da177e4SLinus Torvalds * along with this program; if not, write to the Free Software 241da177e4SLinus Torvalds * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 251da177e4SLinus Torvalds * 268cf4c195SKristen Accardi * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com> 271da177e4SLinus Torvalds * 281da177e4SLinus Torvalds */ 291da177e4SLinus Torvalds 301da177e4SLinus Torvalds #include <linux/kernel.h> 311da177e4SLinus Torvalds #include <linux/module.h> 321da177e4SLinus Torvalds #include <linux/types.h> 331da177e4SLinus Torvalds #include <linux/pci.h> 34d4d28dd4SAndrew Morton #include <linux/interrupt.h> 35d4d28dd4SAndrew Morton 361da177e4SLinus Torvalds #include "shpchp.h" 371da177e4SLinus Torvalds 381da177e4SLinus Torvalds #ifdef DEBUG 391da177e4SLinus Torvalds #define DBG_K_TRACE_ENTRY ((unsigned int)0x00000001) /* On function entry */ 401da177e4SLinus Torvalds #define DBG_K_TRACE_EXIT ((unsigned int)0x00000002) /* On function exit */ 411da177e4SLinus Torvalds #define DBG_K_INFO ((unsigned int)0x00000004) /* Info messages */ 421da177e4SLinus Torvalds #define DBG_K_ERROR ((unsigned int)0x00000008) /* Error messages */ 431da177e4SLinus Torvalds #define DBG_K_TRACE (DBG_K_TRACE_ENTRY|DBG_K_TRACE_EXIT) 441da177e4SLinus Torvalds #define DBG_K_STANDARD (DBG_K_INFO|DBG_K_ERROR|DBG_K_TRACE) 451da177e4SLinus Torvalds /* Redefine this flagword to set debug level */ 461da177e4SLinus Torvalds #define DEBUG_LEVEL DBG_K_STANDARD 471da177e4SLinus Torvalds 481da177e4SLinus Torvalds #define DEFINE_DBG_BUFFER char __dbg_str_buf[256]; 491da177e4SLinus Torvalds 501da177e4SLinus Torvalds #define DBG_PRINT( dbg_flags, args... ) \ 511da177e4SLinus Torvalds do { \ 521da177e4SLinus Torvalds if ( DEBUG_LEVEL & ( dbg_flags ) ) \ 531da177e4SLinus Torvalds { \ 541da177e4SLinus Torvalds int len; \ 551da177e4SLinus Torvalds len = sprintf( __dbg_str_buf, "%s:%d: %s: ", \ 561da177e4SLinus Torvalds __FILE__, __LINE__, __FUNCTION__ ); \ 571da177e4SLinus Torvalds sprintf( __dbg_str_buf + len, args ); \ 581da177e4SLinus Torvalds printk( KERN_NOTICE "%s\n", __dbg_str_buf ); \ 591da177e4SLinus Torvalds } \ 601da177e4SLinus Torvalds } while (0) 611da177e4SLinus Torvalds 621da177e4SLinus Torvalds #define DBG_ENTER_ROUTINE DBG_PRINT (DBG_K_TRACE_ENTRY, "%s", "[Entry]"); 631da177e4SLinus Torvalds #define DBG_LEAVE_ROUTINE DBG_PRINT (DBG_K_TRACE_EXIT, "%s", "[Exit]"); 641da177e4SLinus Torvalds #else 651da177e4SLinus Torvalds #define DEFINE_DBG_BUFFER 661da177e4SLinus Torvalds #define DBG_ENTER_ROUTINE 671da177e4SLinus Torvalds #define DBG_LEAVE_ROUTINE 681da177e4SLinus Torvalds #endif /* DEBUG */ 691da177e4SLinus Torvalds 701da177e4SLinus Torvalds /* Slot Available Register I field definition */ 711da177e4SLinus Torvalds #define SLOT_33MHZ 0x0000001f 721da177e4SLinus Torvalds #define SLOT_66MHZ_PCIX 0x00001f00 731da177e4SLinus Torvalds #define SLOT_100MHZ_PCIX 0x001f0000 741da177e4SLinus Torvalds #define SLOT_133MHZ_PCIX 0x1f000000 751da177e4SLinus Torvalds 761da177e4SLinus Torvalds /* Slot Available Register II field definition */ 771da177e4SLinus Torvalds #define SLOT_66MHZ 0x0000001f 781da177e4SLinus Torvalds #define SLOT_66MHZ_PCIX_266 0x00000f00 791da177e4SLinus Torvalds #define SLOT_100MHZ_PCIX_266 0x0000f000 801da177e4SLinus Torvalds #define SLOT_133MHZ_PCIX_266 0x000f0000 811da177e4SLinus Torvalds #define SLOT_66MHZ_PCIX_533 0x00f00000 821da177e4SLinus Torvalds #define SLOT_100MHZ_PCIX_533 0x0f000000 831da177e4SLinus Torvalds #define SLOT_133MHZ_PCIX_533 0xf0000000 841da177e4SLinus Torvalds 851da177e4SLinus Torvalds /* Slot Configuration */ 861da177e4SLinus Torvalds #define SLOT_NUM 0x0000001F 871da177e4SLinus Torvalds #define FIRST_DEV_NUM 0x00001F00 881da177e4SLinus Torvalds #define PSN 0x07FF0000 891da177e4SLinus Torvalds #define UPDOWN 0x20000000 901da177e4SLinus Torvalds #define MRLSENSOR 0x40000000 911da177e4SLinus Torvalds #define ATTN_BUTTON 0x80000000 921da177e4SLinus Torvalds 932b34da7eSKenji Kaneshige /* 94c4cecc19SKenji Kaneshige * Interrupt Locator Register definitions 95c4cecc19SKenji Kaneshige */ 96c4cecc19SKenji Kaneshige #define CMD_INTR_PENDING (1 << 0) 97c4cecc19SKenji Kaneshige #define SLOT_INTR_PENDING(i) (1 << (i + 1)) 98c4cecc19SKenji Kaneshige 99c4cecc19SKenji Kaneshige /* 100e7138723SKenji Kaneshige * Controller SERR-INT Register 101e7138723SKenji Kaneshige */ 102e7138723SKenji Kaneshige #define GLOBAL_INTR_MASK (1 << 0) 103e7138723SKenji Kaneshige #define GLOBAL_SERR_MASK (1 << 1) 104e7138723SKenji Kaneshige #define COMMAND_INTR_MASK (1 << 2) 105e7138723SKenji Kaneshige #define ARBITER_SERR_MASK (1 << 3) 106e7138723SKenji Kaneshige #define COMMAND_DETECTED (1 << 16) 107e7138723SKenji Kaneshige #define ARBITER_DETECTED (1 << 17) 108e7138723SKenji Kaneshige #define SERR_INTR_RSVDZ_MASK 0xfffc0000 109e7138723SKenji Kaneshige 110e7138723SKenji Kaneshige /* 1112b34da7eSKenji Kaneshige * Logical Slot Register definitions 1122b34da7eSKenji Kaneshige */ 1132b34da7eSKenji Kaneshige #define SLOT_REG(i) (SLOT1 + (4 * i)) 1142b34da7eSKenji Kaneshige 1155858759cSKenji Kaneshige #define SLOT_STATE_SHIFT (0) 1165858759cSKenji Kaneshige #define SLOT_STATE_MASK (3 << 0) 1175858759cSKenji Kaneshige #define SLOT_STATE_PWRONLY (1) 1185858759cSKenji Kaneshige #define SLOT_STATE_ENABLED (2) 1195858759cSKenji Kaneshige #define SLOT_STATE_DISABLED (3) 1205858759cSKenji Kaneshige #define PWR_LED_STATE_SHIFT (2) 1215858759cSKenji Kaneshige #define PWR_LED_STATE_MASK (3 << 2) 1225858759cSKenji Kaneshige #define ATN_LED_STATE_SHIFT (4) 1235858759cSKenji Kaneshige #define ATN_LED_STATE_MASK (3 << 4) 1245858759cSKenji Kaneshige #define ATN_LED_STATE_ON (1) 1255858759cSKenji Kaneshige #define ATN_LED_STATE_BLINK (2) 1265858759cSKenji Kaneshige #define ATN_LED_STATE_OFF (3) 1275858759cSKenji Kaneshige #define POWER_FAULT (1 << 6) 1285858759cSKenji Kaneshige #define ATN_BUTTON (1 << 7) 1295858759cSKenji Kaneshige #define MRL_SENSOR (1 << 8) 1305858759cSKenji Kaneshige #define MHZ66_CAP (1 << 9) 1315858759cSKenji Kaneshige #define PRSNT_SHIFT (10) 1325858759cSKenji Kaneshige #define PRSNT_MASK (3 << 10) 1335858759cSKenji Kaneshige #define PCIX_CAP_SHIFT (12) 1345858759cSKenji Kaneshige #define PCIX_CAP_MASK_PI1 (3 << 12) 1355858759cSKenji Kaneshige #define PCIX_CAP_MASK_PI2 (7 << 12) 1365858759cSKenji Kaneshige #define PRSNT_CHANGE_DETECTED (1 << 16) 1375858759cSKenji Kaneshige #define ISO_PFAULT_DETECTED (1 << 17) 1385858759cSKenji Kaneshige #define BUTTON_PRESS_DETECTED (1 << 18) 1395858759cSKenji Kaneshige #define MRL_CHANGE_DETECTED (1 << 19) 1405858759cSKenji Kaneshige #define CON_PFAULT_DETECTED (1 << 20) 1415858759cSKenji Kaneshige #define PRSNT_CHANGE_INTR_MASK (1 << 24) 1425858759cSKenji Kaneshige #define ISO_PFAULT_INTR_MASK (1 << 25) 1435858759cSKenji Kaneshige #define BUTTON_PRESS_INTR_MASK (1 << 26) 1445858759cSKenji Kaneshige #define MRL_CHANGE_INTR_MASK (1 << 27) 1455858759cSKenji Kaneshige #define CON_PFAULT_INTR_MASK (1 << 28) 1465858759cSKenji Kaneshige #define MRL_CHANGE_SERR_MASK (1 << 29) 1475858759cSKenji Kaneshige #define CON_PFAULT_SERR_MASK (1 << 30) 1485858759cSKenji Kaneshige #define SLOT_REG_RSVDZ_MASK (1 << 15) | (7 << 21) 1491da177e4SLinus Torvalds 1504085399dSKenji Kaneshige /* 1514085399dSKenji Kaneshige * SHPC Command Code definitnions 1524085399dSKenji Kaneshige * 1534085399dSKenji Kaneshige * Slot Operation 00h - 3Fh 1544085399dSKenji Kaneshige * Set Bus Segment Speed/Mode A 40h - 47h 1554085399dSKenji Kaneshige * Power-Only All Slots 48h 1564085399dSKenji Kaneshige * Enable All Slots 49h 1574085399dSKenji Kaneshige * Set Bus Segment Speed/Mode B (PI=2) 50h - 5Fh 1584085399dSKenji Kaneshige * Reserved Command Codes 60h - BFh 1594085399dSKenji Kaneshige * Vendor Specific Commands C0h - FFh 1604085399dSKenji Kaneshige */ 1614085399dSKenji Kaneshige #define SET_SLOT_PWR 0x01 /* Slot Operation */ 1621da177e4SLinus Torvalds #define SET_SLOT_ENABLE 0x02 1631da177e4SLinus Torvalds #define SET_SLOT_DISABLE 0x03 1641da177e4SLinus Torvalds #define SET_PWR_ON 0x04 1651da177e4SLinus Torvalds #define SET_PWR_BLINK 0x08 1664085399dSKenji Kaneshige #define SET_PWR_OFF 0x0c 1674085399dSKenji Kaneshige #define SET_ATTN_ON 0x10 1684085399dSKenji Kaneshige #define SET_ATTN_BLINK 0x20 1694085399dSKenji Kaneshige #define SET_ATTN_OFF 0x30 1704085399dSKenji Kaneshige #define SETA_PCI_33MHZ 0x40 /* Set Bus Segment Speed/Mode A */ 1711da177e4SLinus Torvalds #define SETA_PCI_66MHZ 0x41 1721da177e4SLinus Torvalds #define SETA_PCIX_66MHZ 0x42 1731da177e4SLinus Torvalds #define SETA_PCIX_100MHZ 0x43 1741da177e4SLinus Torvalds #define SETA_PCIX_133MHZ 0x44 1754085399dSKenji Kaneshige #define SETA_RESERVED1 0x45 1764085399dSKenji Kaneshige #define SETA_RESERVED2 0x46 1774085399dSKenji Kaneshige #define SETA_RESERVED3 0x47 1784085399dSKenji Kaneshige #define SET_PWR_ONLY_ALL 0x48 /* Power-Only All Slots */ 1794085399dSKenji Kaneshige #define SET_ENABLE_ALL 0x49 /* Enable All Slots */ 1804085399dSKenji Kaneshige #define SETB_PCI_33MHZ 0x50 /* Set Bus Segment Speed/Mode B */ 1811da177e4SLinus Torvalds #define SETB_PCI_66MHZ 0x51 1821da177e4SLinus Torvalds #define SETB_PCIX_66MHZ_PM 0x52 1831da177e4SLinus Torvalds #define SETB_PCIX_100MHZ_PM 0x53 1841da177e4SLinus Torvalds #define SETB_PCIX_133MHZ_PM 0x54 1851da177e4SLinus Torvalds #define SETB_PCIX_66MHZ_EM 0x55 1861da177e4SLinus Torvalds #define SETB_PCIX_100MHZ_EM 0x56 1871da177e4SLinus Torvalds #define SETB_PCIX_133MHZ_EM 0x57 1881da177e4SLinus Torvalds #define SETB_PCIX_66MHZ_266 0x58 1891da177e4SLinus Torvalds #define SETB_PCIX_100MHZ_266 0x59 1901da177e4SLinus Torvalds #define SETB_PCIX_133MHZ_266 0x5a 1911da177e4SLinus Torvalds #define SETB_PCIX_66MHZ_533 0x5b 1921da177e4SLinus Torvalds #define SETB_PCIX_100MHZ_533 0x5c 1931da177e4SLinus Torvalds #define SETB_PCIX_133MHZ_533 0x5d 1944085399dSKenji Kaneshige #define SETB_RESERVED1 0x5e 1954085399dSKenji Kaneshige #define SETB_RESERVED2 0x5f 1961da177e4SLinus Torvalds 1974085399dSKenji Kaneshige /* 1984085399dSKenji Kaneshige * SHPC controller command error code 1994085399dSKenji Kaneshige */ 2001da177e4SLinus Torvalds #define SWITCH_OPEN 0x1 2011da177e4SLinus Torvalds #define INVALID_CMD 0x2 2021da177e4SLinus Torvalds #define INVALID_SPEED_MODE 0x4 2031da177e4SLinus Torvalds 2044085399dSKenji Kaneshige /* 2054085399dSKenji Kaneshige * For accessing SHPC Working Register Set via PCI Configuration Space 2064085399dSKenji Kaneshige */ 2071da177e4SLinus Torvalds #define DWORD_SELECT 0x2 2081da177e4SLinus Torvalds #define DWORD_DATA 0x4 2091da177e4SLinus Torvalds 2101da177e4SLinus Torvalds /* Field Offset in Logical Slot Register - byte boundary */ 2111da177e4SLinus Torvalds #define SLOT_EVENT_LATCH 0x2 2121da177e4SLinus Torvalds #define SLOT_SERR_INT_MASK 0x3 2131da177e4SLinus Torvalds 2141da177e4SLinus Torvalds DEFINE_DBG_BUFFER /* Debug string buffer for entire HPC defined here */ 2151da177e4SLinus Torvalds static struct php_ctlr_state_s *php_ctlr_list_head; /* HPC state linked list */ 2161da177e4SLinus Torvalds static int ctlr_seq_num = 0; /* Controller sequenc # */ 2171da177e4SLinus Torvalds static spinlock_t list_lock; 2181da177e4SLinus Torvalds 21982d5f4aaSKenji Kaneshige static atomic_t shpchp_num_controllers = ATOMIC_INIT(0); 22082d5f4aaSKenji Kaneshige 221c4cecc19SKenji Kaneshige static irqreturn_t shpc_isr(int irq, void *dev_id, struct pt_regs *regs); 222f4263957SKenji Kaneshige static void start_int_poll_timer(struct php_ctlr_state_s *php_ctlr, int sec); 223d29aaddaSKenji Kaneshige static int hpc_check_cmd_status(struct controller *ctrl); 2241da177e4SLinus Torvalds 22575d97c59SKenji Kaneshige static inline u8 shpc_readb(struct controller *ctrl, int reg) 22675d97c59SKenji Kaneshige { 22775d97c59SKenji Kaneshige return readb(ctrl->hpc_ctlr_handle->creg + reg); 22875d97c59SKenji Kaneshige } 22975d97c59SKenji Kaneshige 23075d97c59SKenji Kaneshige static inline void shpc_writeb(struct controller *ctrl, int reg, u8 val) 23175d97c59SKenji Kaneshige { 23275d97c59SKenji Kaneshige writeb(val, ctrl->hpc_ctlr_handle->creg + reg); 23375d97c59SKenji Kaneshige } 23475d97c59SKenji Kaneshige 23575d97c59SKenji Kaneshige static inline u16 shpc_readw(struct controller *ctrl, int reg) 23675d97c59SKenji Kaneshige { 23775d97c59SKenji Kaneshige return readw(ctrl->hpc_ctlr_handle->creg + reg); 23875d97c59SKenji Kaneshige } 23975d97c59SKenji Kaneshige 24075d97c59SKenji Kaneshige static inline void shpc_writew(struct controller *ctrl, int reg, u16 val) 24175d97c59SKenji Kaneshige { 24275d97c59SKenji Kaneshige writew(val, ctrl->hpc_ctlr_handle->creg + reg); 24375d97c59SKenji Kaneshige } 24475d97c59SKenji Kaneshige 24575d97c59SKenji Kaneshige static inline u32 shpc_readl(struct controller *ctrl, int reg) 24675d97c59SKenji Kaneshige { 24775d97c59SKenji Kaneshige return readl(ctrl->hpc_ctlr_handle->creg + reg); 24875d97c59SKenji Kaneshige } 24975d97c59SKenji Kaneshige 25075d97c59SKenji Kaneshige static inline void shpc_writel(struct controller *ctrl, int reg, u32 val) 25175d97c59SKenji Kaneshige { 25275d97c59SKenji Kaneshige writel(val, ctrl->hpc_ctlr_handle->creg + reg); 25375d97c59SKenji Kaneshige } 25475d97c59SKenji Kaneshige 25575d97c59SKenji Kaneshige static inline int shpc_indirect_read(struct controller *ctrl, int index, 25675d97c59SKenji Kaneshige u32 *value) 25775d97c59SKenji Kaneshige { 25875d97c59SKenji Kaneshige int rc; 25975d97c59SKenji Kaneshige u32 cap_offset = ctrl->cap_offset; 26075d97c59SKenji Kaneshige struct pci_dev *pdev = ctrl->pci_dev; 26175d97c59SKenji Kaneshige 26275d97c59SKenji Kaneshige rc = pci_write_config_byte(pdev, cap_offset + DWORD_SELECT, index); 26375d97c59SKenji Kaneshige if (rc) 26475d97c59SKenji Kaneshige return rc; 26575d97c59SKenji Kaneshige return pci_read_config_dword(pdev, cap_offset + DWORD_DATA, value); 26675d97c59SKenji Kaneshige } 26775d97c59SKenji Kaneshige 268f4263957SKenji Kaneshige /* 269f4263957SKenji Kaneshige * This is the interrupt polling timeout function. 270f4263957SKenji Kaneshige */ 2711da177e4SLinus Torvalds static void int_poll_timeout(unsigned long lphp_ctlr) 2721da177e4SLinus Torvalds { 273f4263957SKenji Kaneshige struct php_ctlr_state_s *php_ctlr = 274f4263957SKenji Kaneshige (struct php_ctlr_state_s *)lphp_ctlr; 2751da177e4SLinus Torvalds 2761da177e4SLinus Torvalds DBG_ENTER_ROUTINE 2771da177e4SLinus Torvalds 2781da177e4SLinus Torvalds /* Poll for interrupt events. regs == NULL => polling */ 279c4cecc19SKenji Kaneshige shpc_isr(0, php_ctlr->callback_instance_id, NULL); 2801da177e4SLinus Torvalds 2811da177e4SLinus Torvalds init_timer(&php_ctlr->int_poll_timer); 2821da177e4SLinus Torvalds if (!shpchp_poll_time) 283f4263957SKenji Kaneshige shpchp_poll_time = 2; /* default polling interval is 2 sec */ 2841da177e4SLinus Torvalds 2851da177e4SLinus Torvalds start_int_poll_timer(php_ctlr, shpchp_poll_time); 2861da177e4SLinus Torvalds 287f4263957SKenji Kaneshige DBG_LEAVE_ROUTINE 2881da177e4SLinus Torvalds } 2891da177e4SLinus Torvalds 290f4263957SKenji Kaneshige /* 291f4263957SKenji Kaneshige * This function starts the interrupt polling timer. 292f4263957SKenji Kaneshige */ 293f4263957SKenji Kaneshige static void start_int_poll_timer(struct php_ctlr_state_s *php_ctlr, int sec) 2941da177e4SLinus Torvalds { 295f4263957SKenji Kaneshige /* Clamp to sane value */ 296f4263957SKenji Kaneshige if ((sec <= 0) || (sec > 60)) 297f4263957SKenji Kaneshige sec = 2; 2981da177e4SLinus Torvalds 2991da177e4SLinus Torvalds php_ctlr->int_poll_timer.function = &int_poll_timeout; 300f4263957SKenji Kaneshige php_ctlr->int_poll_timer.data = (unsigned long)php_ctlr; 301f4263957SKenji Kaneshige php_ctlr->int_poll_timer.expires = jiffies + sec * HZ; 3021da177e4SLinus Torvalds add_timer(&php_ctlr->int_poll_timer); 3031da177e4SLinus Torvalds } 3041da177e4SLinus Torvalds 305bd62e271SKenji Kaneshige static inline int shpc_wait_cmd(struct controller *ctrl) 306bd62e271SKenji Kaneshige { 307bd62e271SKenji Kaneshige int retval = 0; 308bd62e271SKenji Kaneshige unsigned int timeout_msec = shpchp_poll_mode ? 2000 : 1000; 309bd62e271SKenji Kaneshige unsigned long timeout = msecs_to_jiffies(timeout_msec); 310bd62e271SKenji Kaneshige int rc = wait_event_interruptible_timeout(ctrl->queue, 311bd62e271SKenji Kaneshige !ctrl->cmd_busy, timeout); 312bd62e271SKenji Kaneshige if (!rc) { 313bd62e271SKenji Kaneshige retval = -EIO; 314bd62e271SKenji Kaneshige err("Command not completed in %d msec\n", timeout_msec); 315bd62e271SKenji Kaneshige } else if (rc < 0) { 316bd62e271SKenji Kaneshige retval = -EINTR; 317bd62e271SKenji Kaneshige info("Command was interrupted by a signal\n"); 318bd62e271SKenji Kaneshige } 319bd62e271SKenji Kaneshige ctrl->cmd_busy = 0; 320bd62e271SKenji Kaneshige 321bd62e271SKenji Kaneshige return retval; 322bd62e271SKenji Kaneshige } 323bd62e271SKenji Kaneshige 3241da177e4SLinus Torvalds static int shpc_write_cmd(struct slot *slot, u8 t_slot, u8 cmd) 3251da177e4SLinus Torvalds { 32675d97c59SKenji Kaneshige struct controller *ctrl = slot->ctrl; 3271da177e4SLinus Torvalds u16 cmd_status; 3281da177e4SLinus Torvalds int retval = 0; 3291da177e4SLinus Torvalds u16 temp_word; 3301da177e4SLinus Torvalds int i; 3311da177e4SLinus Torvalds 3321da177e4SLinus Torvalds DBG_ENTER_ROUTINE 3331da177e4SLinus Torvalds 334d29aaddaSKenji Kaneshige mutex_lock(&slot->ctrl->cmd_lock); 335d29aaddaSKenji Kaneshige 3361da177e4SLinus Torvalds for (i = 0; i < 10; i++) { 33775d97c59SKenji Kaneshige cmd_status = shpc_readw(ctrl, CMD_STATUS); 3381da177e4SLinus Torvalds 3391da177e4SLinus Torvalds if (!(cmd_status & 0x1)) 3401da177e4SLinus Torvalds break; 3411da177e4SLinus Torvalds /* Check every 0.1 sec for a total of 1 sec*/ 3421da177e4SLinus Torvalds msleep(100); 3431da177e4SLinus Torvalds } 3441da177e4SLinus Torvalds 34575d97c59SKenji Kaneshige cmd_status = shpc_readw(ctrl, CMD_STATUS); 3461da177e4SLinus Torvalds 3471da177e4SLinus Torvalds if (cmd_status & 0x1) { 3481da177e4SLinus Torvalds /* After 1 sec and and the controller is still busy */ 3491da177e4SLinus Torvalds err("%s : Controller is still busy after 1 sec.\n", __FUNCTION__); 350d29aaddaSKenji Kaneshige retval = -EBUSY; 351d29aaddaSKenji Kaneshige goto out; 3521da177e4SLinus Torvalds } 3531da177e4SLinus Torvalds 3541da177e4SLinus Torvalds ++t_slot; 3551da177e4SLinus Torvalds temp_word = (t_slot << 8) | (cmd & 0xFF); 3561da177e4SLinus Torvalds dbg("%s: t_slot %x cmd %x\n", __FUNCTION__, t_slot, cmd); 3571da177e4SLinus Torvalds 3581da177e4SLinus Torvalds /* To make sure the Controller Busy bit is 0 before we send out the 3591da177e4SLinus Torvalds * command. 3601da177e4SLinus Torvalds */ 361bd62e271SKenji Kaneshige slot->ctrl->cmd_busy = 1; 36275d97c59SKenji Kaneshige shpc_writew(ctrl, CMD, temp_word); 3631da177e4SLinus Torvalds 364bd62e271SKenji Kaneshige /* 365bd62e271SKenji Kaneshige * Wait for command completion. 366bd62e271SKenji Kaneshige */ 367bd62e271SKenji Kaneshige retval = shpc_wait_cmd(slot->ctrl); 368d29aaddaSKenji Kaneshige if (retval) 369d29aaddaSKenji Kaneshige goto out; 370d29aaddaSKenji Kaneshige 371d29aaddaSKenji Kaneshige cmd_status = hpc_check_cmd_status(slot->ctrl); 372d29aaddaSKenji Kaneshige if (cmd_status) { 373d29aaddaSKenji Kaneshige err("%s: Failed to issued command 0x%x (error code = %d)\n", 374d29aaddaSKenji Kaneshige __FUNCTION__, cmd, cmd_status); 375d29aaddaSKenji Kaneshige retval = -EIO; 376d29aaddaSKenji Kaneshige } 377d29aaddaSKenji Kaneshige out: 378d29aaddaSKenji Kaneshige mutex_unlock(&slot->ctrl->cmd_lock); 379bd62e271SKenji Kaneshige 3801da177e4SLinus Torvalds DBG_LEAVE_ROUTINE 3811da177e4SLinus Torvalds return retval; 3821da177e4SLinus Torvalds } 3831da177e4SLinus Torvalds 3841da177e4SLinus Torvalds static int hpc_check_cmd_status(struct controller *ctrl) 3851da177e4SLinus Torvalds { 3861da177e4SLinus Torvalds u16 cmd_status; 3871da177e4SLinus Torvalds int retval = 0; 3881da177e4SLinus Torvalds 3891da177e4SLinus Torvalds DBG_ENTER_ROUTINE 3901da177e4SLinus Torvalds 39175d97c59SKenji Kaneshige cmd_status = shpc_readw(ctrl, CMD_STATUS) & 0x000F; 3921da177e4SLinus Torvalds 3931da177e4SLinus Torvalds switch (cmd_status >> 1) { 3941da177e4SLinus Torvalds case 0: 3951da177e4SLinus Torvalds retval = 0; 3961da177e4SLinus Torvalds break; 3971da177e4SLinus Torvalds case 1: 3981da177e4SLinus Torvalds retval = SWITCH_OPEN; 3991da177e4SLinus Torvalds err("%s: Switch opened!\n", __FUNCTION__); 4001da177e4SLinus Torvalds break; 4011da177e4SLinus Torvalds case 2: 4021da177e4SLinus Torvalds retval = INVALID_CMD; 4031da177e4SLinus Torvalds err("%s: Invalid HPC command!\n", __FUNCTION__); 4041da177e4SLinus Torvalds break; 4051da177e4SLinus Torvalds case 4: 4061da177e4SLinus Torvalds retval = INVALID_SPEED_MODE; 4071da177e4SLinus Torvalds err("%s: Invalid bus speed/mode!\n", __FUNCTION__); 4081da177e4SLinus Torvalds break; 4091da177e4SLinus Torvalds default: 4101da177e4SLinus Torvalds retval = cmd_status; 4111da177e4SLinus Torvalds } 4121da177e4SLinus Torvalds 4131da177e4SLinus Torvalds DBG_LEAVE_ROUTINE 4141da177e4SLinus Torvalds return retval; 4151da177e4SLinus Torvalds } 4161da177e4SLinus Torvalds 4171da177e4SLinus Torvalds 4181da177e4SLinus Torvalds static int hpc_get_attention_status(struct slot *slot, u8 *status) 4191da177e4SLinus Torvalds { 42075d97c59SKenji Kaneshige struct controller *ctrl = slot->ctrl; 4211da177e4SLinus Torvalds u32 slot_reg; 4225858759cSKenji Kaneshige u8 state; 4231da177e4SLinus Torvalds 4241da177e4SLinus Torvalds DBG_ENTER_ROUTINE 4251da177e4SLinus Torvalds 4262b34da7eSKenji Kaneshige slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); 4275858759cSKenji Kaneshige state = (slot_reg & ATN_LED_STATE_MASK) >> ATN_LED_STATE_SHIFT; 4281da177e4SLinus Torvalds 4295858759cSKenji Kaneshige switch (state) { 4305858759cSKenji Kaneshige case ATN_LED_STATE_ON: 4311da177e4SLinus Torvalds *status = 1; /* On */ 4321da177e4SLinus Torvalds break; 4335858759cSKenji Kaneshige case ATN_LED_STATE_BLINK: 4341da177e4SLinus Torvalds *status = 2; /* Blink */ 4351da177e4SLinus Torvalds break; 4365858759cSKenji Kaneshige case ATN_LED_STATE_OFF: 4371da177e4SLinus Torvalds *status = 0; /* Off */ 4381da177e4SLinus Torvalds break; 4391da177e4SLinus Torvalds default: 4405858759cSKenji Kaneshige *status = 0xFF; /* Reserved */ 4411da177e4SLinus Torvalds break; 4421da177e4SLinus Torvalds } 4431da177e4SLinus Torvalds 4441da177e4SLinus Torvalds DBG_LEAVE_ROUTINE 4451da177e4SLinus Torvalds return 0; 4461da177e4SLinus Torvalds } 4471da177e4SLinus Torvalds 4481da177e4SLinus Torvalds static int hpc_get_power_status(struct slot * slot, u8 *status) 4491da177e4SLinus Torvalds { 45075d97c59SKenji Kaneshige struct controller *ctrl = slot->ctrl; 4511da177e4SLinus Torvalds u32 slot_reg; 4525858759cSKenji Kaneshige u8 state; 4531da177e4SLinus Torvalds 4541da177e4SLinus Torvalds DBG_ENTER_ROUTINE 4551da177e4SLinus Torvalds 4562b34da7eSKenji Kaneshige slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); 4575858759cSKenji Kaneshige state = (slot_reg & SLOT_STATE_MASK) >> SLOT_STATE_SHIFT; 4581da177e4SLinus Torvalds 4595858759cSKenji Kaneshige switch (state) { 4605858759cSKenji Kaneshige case SLOT_STATE_PWRONLY: 4611da177e4SLinus Torvalds *status = 2; /* Powered only */ 4621da177e4SLinus Torvalds break; 4635858759cSKenji Kaneshige case SLOT_STATE_ENABLED: 4641da177e4SLinus Torvalds *status = 1; /* Enabled */ 4651da177e4SLinus Torvalds break; 4665858759cSKenji Kaneshige case SLOT_STATE_DISABLED: 4671da177e4SLinus Torvalds *status = 0; /* Disabled */ 4681da177e4SLinus Torvalds break; 4691da177e4SLinus Torvalds default: 4705858759cSKenji Kaneshige *status = 0xFF; /* Reserved */ 4711da177e4SLinus Torvalds break; 4721da177e4SLinus Torvalds } 4731da177e4SLinus Torvalds 4741da177e4SLinus Torvalds DBG_LEAVE_ROUTINE 4755858759cSKenji Kaneshige return 0; 4761da177e4SLinus Torvalds } 4771da177e4SLinus Torvalds 4781da177e4SLinus Torvalds 4791da177e4SLinus Torvalds static int hpc_get_latch_status(struct slot *slot, u8 *status) 4801da177e4SLinus Torvalds { 48175d97c59SKenji Kaneshige struct controller *ctrl = slot->ctrl; 4821da177e4SLinus Torvalds u32 slot_reg; 4831da177e4SLinus Torvalds 4841da177e4SLinus Torvalds DBG_ENTER_ROUTINE 4851da177e4SLinus Torvalds 4862b34da7eSKenji Kaneshige slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); 4875858759cSKenji Kaneshige *status = !!(slot_reg & MRL_SENSOR); /* 0 -> close; 1 -> open */ 4881da177e4SLinus Torvalds 4891da177e4SLinus Torvalds DBG_LEAVE_ROUTINE 4901da177e4SLinus Torvalds return 0; 4911da177e4SLinus Torvalds } 4921da177e4SLinus Torvalds 4931da177e4SLinus Torvalds static int hpc_get_adapter_status(struct slot *slot, u8 *status) 4941da177e4SLinus Torvalds { 49575d97c59SKenji Kaneshige struct controller *ctrl = slot->ctrl; 4961da177e4SLinus Torvalds u32 slot_reg; 4975858759cSKenji Kaneshige u8 state; 4981da177e4SLinus Torvalds 4991da177e4SLinus Torvalds DBG_ENTER_ROUTINE 5001da177e4SLinus Torvalds 5012b34da7eSKenji Kaneshige slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); 5025858759cSKenji Kaneshige state = (slot_reg & PRSNT_MASK) >> PRSNT_SHIFT; 5035858759cSKenji Kaneshige *status = (state != 0x3) ? 1 : 0; 5041da177e4SLinus Torvalds 5051da177e4SLinus Torvalds DBG_LEAVE_ROUTINE 5061da177e4SLinus Torvalds return 0; 5071da177e4SLinus Torvalds } 5081da177e4SLinus Torvalds 5091da177e4SLinus Torvalds static int hpc_get_prog_int(struct slot *slot, u8 *prog_int) 5101da177e4SLinus Torvalds { 51175d97c59SKenji Kaneshige struct controller *ctrl = slot->ctrl; 5121da177e4SLinus Torvalds 5131da177e4SLinus Torvalds DBG_ENTER_ROUTINE 5141da177e4SLinus Torvalds 51575d97c59SKenji Kaneshige *prog_int = shpc_readb(ctrl, PROG_INTERFACE); 5161da177e4SLinus Torvalds 5171da177e4SLinus Torvalds DBG_LEAVE_ROUTINE 5181da177e4SLinus Torvalds return 0; 5191da177e4SLinus Torvalds } 5201da177e4SLinus Torvalds 5211da177e4SLinus Torvalds static int hpc_get_adapter_speed(struct slot *slot, enum pci_bus_speed *value) 5221da177e4SLinus Torvalds { 5231da177e4SLinus Torvalds int retval = 0; 52475d97c59SKenji Kaneshige struct controller *ctrl = slot->ctrl; 5252b34da7eSKenji Kaneshige u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); 5265858759cSKenji Kaneshige u8 m66_cap = !!(slot_reg & MHZ66_CAP); 527795eb5c4SKenji Kaneshige u8 pi, pcix_cap; 5281da177e4SLinus Torvalds 5291da177e4SLinus Torvalds DBG_ENTER_ROUTINE 5301da177e4SLinus Torvalds 531795eb5c4SKenji Kaneshige if ((retval = hpc_get_prog_int(slot, &pi))) 532795eb5c4SKenji Kaneshige return retval; 533795eb5c4SKenji Kaneshige 534795eb5c4SKenji Kaneshige switch (pi) { 535795eb5c4SKenji Kaneshige case 1: 536795eb5c4SKenji Kaneshige pcix_cap = (slot_reg & PCIX_CAP_MASK_PI1) >> PCIX_CAP_SHIFT; 537795eb5c4SKenji Kaneshige break; 538795eb5c4SKenji Kaneshige case 2: 539795eb5c4SKenji Kaneshige pcix_cap = (slot_reg & PCIX_CAP_MASK_PI2) >> PCIX_CAP_SHIFT; 540795eb5c4SKenji Kaneshige break; 541795eb5c4SKenji Kaneshige default: 542795eb5c4SKenji Kaneshige return -ENODEV; 543795eb5c4SKenji Kaneshige } 544795eb5c4SKenji Kaneshige 5450afabe90SKenji Kaneshige dbg("%s: slot_reg = %x, pcix_cap = %x, m66_cap = %x\n", 5460afabe90SKenji Kaneshige __FUNCTION__, slot_reg, pcix_cap, m66_cap); 5471da177e4SLinus Torvalds 5481da177e4SLinus Torvalds switch (pcix_cap) { 5490afabe90SKenji Kaneshige case 0x0: 5501da177e4SLinus Torvalds *value = m66_cap ? PCI_SPEED_66MHz : PCI_SPEED_33MHz; 5511da177e4SLinus Torvalds break; 5520afabe90SKenji Kaneshige case 0x1: 5531da177e4SLinus Torvalds *value = PCI_SPEED_66MHz_PCIX; 5541da177e4SLinus Torvalds break; 5550afabe90SKenji Kaneshige case 0x3: 5561da177e4SLinus Torvalds *value = PCI_SPEED_133MHz_PCIX; 5571da177e4SLinus Torvalds break; 5580afabe90SKenji Kaneshige case 0x4: 5591da177e4SLinus Torvalds *value = PCI_SPEED_133MHz_PCIX_266; 5601da177e4SLinus Torvalds break; 5610afabe90SKenji Kaneshige case 0x5: 5621da177e4SLinus Torvalds *value = PCI_SPEED_133MHz_PCIX_533; 5631da177e4SLinus Torvalds break; 5640afabe90SKenji Kaneshige case 0x2: 5651da177e4SLinus Torvalds default: 5661da177e4SLinus Torvalds *value = PCI_SPEED_UNKNOWN; 5671da177e4SLinus Torvalds retval = -ENODEV; 5681da177e4SLinus Torvalds break; 5691da177e4SLinus Torvalds } 5701da177e4SLinus Torvalds 5711da177e4SLinus Torvalds dbg("Adapter speed = %d\n", *value); 5721da177e4SLinus Torvalds DBG_LEAVE_ROUTINE 5731da177e4SLinus Torvalds return retval; 5741da177e4SLinus Torvalds } 5751da177e4SLinus Torvalds 5761da177e4SLinus Torvalds static int hpc_get_mode1_ECC_cap(struct slot *slot, u8 *mode) 5771da177e4SLinus Torvalds { 57875d97c59SKenji Kaneshige struct controller *ctrl = slot->ctrl; 5791da177e4SLinus Torvalds u16 sec_bus_status; 5801da177e4SLinus Torvalds u8 pi; 5811da177e4SLinus Torvalds int retval = 0; 5821da177e4SLinus Torvalds 5831da177e4SLinus Torvalds DBG_ENTER_ROUTINE 5841da177e4SLinus Torvalds 58575d97c59SKenji Kaneshige pi = shpc_readb(ctrl, PROG_INTERFACE); 58675d97c59SKenji Kaneshige sec_bus_status = shpc_readw(ctrl, SEC_BUS_CONFIG); 5871da177e4SLinus Torvalds 5881da177e4SLinus Torvalds if (pi == 2) { 58987d6c559SKenji Kaneshige *mode = (sec_bus_status & 0x0100) >> 8; 5901da177e4SLinus Torvalds } else { 5911da177e4SLinus Torvalds retval = -1; 5921da177e4SLinus Torvalds } 5931da177e4SLinus Torvalds 5941da177e4SLinus Torvalds dbg("Mode 1 ECC cap = %d\n", *mode); 5951da177e4SLinus Torvalds 5961da177e4SLinus Torvalds DBG_LEAVE_ROUTINE 5971da177e4SLinus Torvalds return retval; 5981da177e4SLinus Torvalds } 5991da177e4SLinus Torvalds 6001da177e4SLinus Torvalds static int hpc_query_power_fault(struct slot * slot) 6011da177e4SLinus Torvalds { 60275d97c59SKenji Kaneshige struct controller *ctrl = slot->ctrl; 6031da177e4SLinus Torvalds u32 slot_reg; 6041da177e4SLinus Torvalds 6051da177e4SLinus Torvalds DBG_ENTER_ROUTINE 6061da177e4SLinus Torvalds 6072b34da7eSKenji Kaneshige slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); 6081da177e4SLinus Torvalds 6091da177e4SLinus Torvalds DBG_LEAVE_ROUTINE 6101da177e4SLinus Torvalds /* Note: Logic 0 => fault */ 6115858759cSKenji Kaneshige return !(slot_reg & POWER_FAULT); 6121da177e4SLinus Torvalds } 6131da177e4SLinus Torvalds 6141da177e4SLinus Torvalds static int hpc_set_attention_status(struct slot *slot, u8 value) 6151da177e4SLinus Torvalds { 6161da177e4SLinus Torvalds u8 slot_cmd = 0; 6171da177e4SLinus Torvalds 6181da177e4SLinus Torvalds switch (value) { 6191da177e4SLinus Torvalds case 0 : 6204085399dSKenji Kaneshige slot_cmd = SET_ATTN_OFF; /* OFF */ 6211da177e4SLinus Torvalds break; 6221da177e4SLinus Torvalds case 1: 6234085399dSKenji Kaneshige slot_cmd = SET_ATTN_ON; /* ON */ 6241da177e4SLinus Torvalds break; 6251da177e4SLinus Torvalds case 2: 6264085399dSKenji Kaneshige slot_cmd = SET_ATTN_BLINK; /* BLINK */ 6271da177e4SLinus Torvalds break; 6281da177e4SLinus Torvalds default: 6291da177e4SLinus Torvalds return -1; 6301da177e4SLinus Torvalds } 6311da177e4SLinus Torvalds 632d4fbf600SKenji Kaneshige return shpc_write_cmd(slot, slot->hp_slot, slot_cmd); 6331da177e4SLinus Torvalds } 6341da177e4SLinus Torvalds 6351da177e4SLinus Torvalds 6361da177e4SLinus Torvalds static void hpc_set_green_led_on(struct slot *slot) 6371da177e4SLinus Torvalds { 6384085399dSKenji Kaneshige shpc_write_cmd(slot, slot->hp_slot, SET_PWR_ON); 6391da177e4SLinus Torvalds } 6401da177e4SLinus Torvalds 6411da177e4SLinus Torvalds static void hpc_set_green_led_off(struct slot *slot) 6421da177e4SLinus Torvalds { 6434085399dSKenji Kaneshige shpc_write_cmd(slot, slot->hp_slot, SET_PWR_OFF); 6441da177e4SLinus Torvalds } 6451da177e4SLinus Torvalds 6461da177e4SLinus Torvalds static void hpc_set_green_led_blink(struct slot *slot) 6471da177e4SLinus Torvalds { 6484085399dSKenji Kaneshige shpc_write_cmd(slot, slot->hp_slot, SET_PWR_BLINK); 6491da177e4SLinus Torvalds } 6501da177e4SLinus Torvalds 6511da177e4SLinus Torvalds int shpc_get_ctlr_slot_config(struct controller *ctrl, 6521da177e4SLinus Torvalds int *num_ctlr_slots, /* number of slots in this HPC */ 6531da177e4SLinus Torvalds int *first_device_num, /* PCI dev num of the first slot in this SHPC */ 6541da177e4SLinus Torvalds int *physical_slot_num, /* phy slot num of the first slot in this SHPC */ 6551da177e4SLinus Torvalds int *updown, /* physical_slot_num increament: 1 or -1 */ 6561da177e4SLinus Torvalds int *flags) 6571da177e4SLinus Torvalds { 65875d97c59SKenji Kaneshige u32 slot_config; 6591da177e4SLinus Torvalds 6601da177e4SLinus Torvalds DBG_ENTER_ROUTINE 6611da177e4SLinus Torvalds 66275d97c59SKenji Kaneshige slot_config = shpc_readl(ctrl, SLOT_CONFIG); 66375d97c59SKenji Kaneshige *first_device_num = (slot_config & FIRST_DEV_NUM) >> 8; 66475d97c59SKenji Kaneshige *num_ctlr_slots = slot_config & SLOT_NUM; 66575d97c59SKenji Kaneshige *physical_slot_num = (slot_config & PSN) >> 16; 66675d97c59SKenji Kaneshige *updown = ((slot_config & UPDOWN) >> 29) ? 1 : -1; 6671da177e4SLinus Torvalds 6681da177e4SLinus Torvalds dbg("%s: physical_slot_num = %x\n", __FUNCTION__, *physical_slot_num); 6691da177e4SLinus Torvalds 6701da177e4SLinus Torvalds DBG_LEAVE_ROUTINE 6711da177e4SLinus Torvalds return 0; 6721da177e4SLinus Torvalds } 6731da177e4SLinus Torvalds 6741da177e4SLinus Torvalds static void hpc_release_ctlr(struct controller *ctrl) 6751da177e4SLinus Torvalds { 676ee138334Srajesh.shah@intel.com struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle; 6771da177e4SLinus Torvalds struct php_ctlr_state_s *p, *p_prev; 678f7391f53SKenji Kaneshige int i; 679d49f2c49SKenji Kaneshige u32 slot_reg, serr_int; 6801da177e4SLinus Torvalds 6811da177e4SLinus Torvalds DBG_ENTER_ROUTINE 6821da177e4SLinus Torvalds 683f7391f53SKenji Kaneshige /* 684795eb5c4SKenji Kaneshige * Mask event interrupts and SERRs of all slots 685f7391f53SKenji Kaneshige */ 686795eb5c4SKenji Kaneshige for (i = 0; i < ctrl->num_slots; i++) { 687795eb5c4SKenji Kaneshige slot_reg = shpc_readl(ctrl, SLOT_REG(i)); 688795eb5c4SKenji Kaneshige slot_reg |= (PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK | 689795eb5c4SKenji Kaneshige BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK | 690795eb5c4SKenji Kaneshige CON_PFAULT_INTR_MASK | MRL_CHANGE_SERR_MASK | 691795eb5c4SKenji Kaneshige CON_PFAULT_SERR_MASK); 692795eb5c4SKenji Kaneshige slot_reg &= ~SLOT_REG_RSVDZ_MASK; 693795eb5c4SKenji Kaneshige shpc_writel(ctrl, SLOT_REG(i), slot_reg); 694795eb5c4SKenji Kaneshige } 695f7391f53SKenji Kaneshige 696f7391f53SKenji Kaneshige cleanup_slots(ctrl); 697f7391f53SKenji Kaneshige 698d49f2c49SKenji Kaneshige /* 699d49f2c49SKenji Kaneshige * Mask SERR and System Interrut generation 700d49f2c49SKenji Kaneshige */ 701d49f2c49SKenji Kaneshige serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE); 702d49f2c49SKenji Kaneshige serr_int |= (GLOBAL_INTR_MASK | GLOBAL_SERR_MASK | 703d49f2c49SKenji Kaneshige COMMAND_INTR_MASK | ARBITER_SERR_MASK); 704d49f2c49SKenji Kaneshige serr_int &= ~SERR_INTR_RSVDZ_MASK; 705d49f2c49SKenji Kaneshige shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int); 706d49f2c49SKenji Kaneshige 7071da177e4SLinus Torvalds if (shpchp_poll_mode) { 7081da177e4SLinus Torvalds del_timer(&php_ctlr->int_poll_timer); 7091da177e4SLinus Torvalds } else { 7101da177e4SLinus Torvalds if (php_ctlr->irq) { 7111da177e4SLinus Torvalds free_irq(php_ctlr->irq, ctrl); 7121da177e4SLinus Torvalds php_ctlr->irq = 0; 7131da177e4SLinus Torvalds pci_disable_msi(php_ctlr->pci_dev); 7141da177e4SLinus Torvalds } 7151da177e4SLinus Torvalds } 716f7391f53SKenji Kaneshige 7171da177e4SLinus Torvalds if (php_ctlr->pci_dev) { 7181da177e4SLinus Torvalds iounmap(php_ctlr->creg); 7190455986cSKenji Kaneshige release_mem_region(ctrl->mmio_base, ctrl->mmio_size); 7201da177e4SLinus Torvalds php_ctlr->pci_dev = NULL; 7211da177e4SLinus Torvalds } 7221da177e4SLinus Torvalds 7231da177e4SLinus Torvalds spin_lock(&list_lock); 7241da177e4SLinus Torvalds p = php_ctlr_list_head; 7251da177e4SLinus Torvalds p_prev = NULL; 7261da177e4SLinus Torvalds while (p) { 7271da177e4SLinus Torvalds if (p == php_ctlr) { 7281da177e4SLinus Torvalds if (p_prev) 7291da177e4SLinus Torvalds p_prev->pnext = p->pnext; 7301da177e4SLinus Torvalds else 7311da177e4SLinus Torvalds php_ctlr_list_head = p->pnext; 7321da177e4SLinus Torvalds break; 7331da177e4SLinus Torvalds } else { 7341da177e4SLinus Torvalds p_prev = p; 7351da177e4SLinus Torvalds p = p->pnext; 7361da177e4SLinus Torvalds } 7371da177e4SLinus Torvalds } 7381da177e4SLinus Torvalds spin_unlock(&list_lock); 7391da177e4SLinus Torvalds 7401da177e4SLinus Torvalds kfree(php_ctlr); 7411da177e4SLinus Torvalds 74282d5f4aaSKenji Kaneshige /* 74382d5f4aaSKenji Kaneshige * If this is the last controller to be released, destroy the 74482d5f4aaSKenji Kaneshige * shpchpd work queue 74582d5f4aaSKenji Kaneshige */ 74682d5f4aaSKenji Kaneshige if (atomic_dec_and_test(&shpchp_num_controllers)) 74782d5f4aaSKenji Kaneshige destroy_workqueue(shpchp_wq); 74882d5f4aaSKenji Kaneshige 7491da177e4SLinus Torvalds DBG_LEAVE_ROUTINE 7501da177e4SLinus Torvalds 7511da177e4SLinus Torvalds } 7521da177e4SLinus Torvalds 7531da177e4SLinus Torvalds static int hpc_power_on_slot(struct slot * slot) 7541da177e4SLinus Torvalds { 755d4fbf600SKenji Kaneshige int retval; 7561da177e4SLinus Torvalds 7571da177e4SLinus Torvalds DBG_ENTER_ROUTINE 7581da177e4SLinus Torvalds 7594085399dSKenji Kaneshige retval = shpc_write_cmd(slot, slot->hp_slot, SET_SLOT_PWR); 7601da177e4SLinus Torvalds if (retval) { 7611da177e4SLinus Torvalds err("%s: Write command failed!\n", __FUNCTION__); 762d4fbf600SKenji Kaneshige return retval; 7631da177e4SLinus Torvalds } 7641da177e4SLinus Torvalds 7651da177e4SLinus Torvalds DBG_LEAVE_ROUTINE 7661da177e4SLinus Torvalds 767d4fbf600SKenji Kaneshige return 0; 7681da177e4SLinus Torvalds } 7691da177e4SLinus Torvalds 7701da177e4SLinus Torvalds static int hpc_slot_enable(struct slot * slot) 7711da177e4SLinus Torvalds { 772d4fbf600SKenji Kaneshige int retval; 7731da177e4SLinus Torvalds 7741da177e4SLinus Torvalds DBG_ENTER_ROUTINE 7751da177e4SLinus Torvalds 7764085399dSKenji Kaneshige /* Slot - Enable, Power Indicator - Blink, Attention Indicator - Off */ 7774085399dSKenji Kaneshige retval = shpc_write_cmd(slot, slot->hp_slot, 7784085399dSKenji Kaneshige SET_SLOT_ENABLE | SET_PWR_BLINK | SET_ATTN_OFF); 7791da177e4SLinus Torvalds if (retval) { 7801da177e4SLinus Torvalds err("%s: Write command failed!\n", __FUNCTION__); 781d4fbf600SKenji Kaneshige return retval; 7821da177e4SLinus Torvalds } 7831da177e4SLinus Torvalds 7841da177e4SLinus Torvalds DBG_LEAVE_ROUTINE 785d4fbf600SKenji Kaneshige return 0; 7861da177e4SLinus Torvalds } 7871da177e4SLinus Torvalds 7881da177e4SLinus Torvalds static int hpc_slot_disable(struct slot * slot) 7891da177e4SLinus Torvalds { 790d4fbf600SKenji Kaneshige int retval; 7911da177e4SLinus Torvalds 7921da177e4SLinus Torvalds DBG_ENTER_ROUTINE 7931da177e4SLinus Torvalds 7944085399dSKenji Kaneshige /* Slot - Disable, Power Indicator - Off, Attention Indicator - On */ 7954085399dSKenji Kaneshige retval = shpc_write_cmd(slot, slot->hp_slot, 7964085399dSKenji Kaneshige SET_SLOT_DISABLE | SET_PWR_OFF | SET_ATTN_ON); 7971da177e4SLinus Torvalds if (retval) { 7981da177e4SLinus Torvalds err("%s: Write command failed!\n", __FUNCTION__); 799d4fbf600SKenji Kaneshige return retval; 8001da177e4SLinus Torvalds } 8011da177e4SLinus Torvalds 8021da177e4SLinus Torvalds DBG_LEAVE_ROUTINE 803d4fbf600SKenji Kaneshige return 0; 8041da177e4SLinus Torvalds } 8051da177e4SLinus Torvalds 8061da177e4SLinus Torvalds static int hpc_set_bus_speed_mode(struct slot * slot, enum pci_bus_speed value) 8071da177e4SLinus Torvalds { 8080afabe90SKenji Kaneshige int retval; 80975d97c59SKenji Kaneshige struct controller *ctrl = slot->ctrl; 8100afabe90SKenji Kaneshige u8 pi, cmd; 8111da177e4SLinus Torvalds 8121da177e4SLinus Torvalds DBG_ENTER_ROUTINE 8131da177e4SLinus Torvalds 81475d97c59SKenji Kaneshige pi = shpc_readb(ctrl, PROG_INTERFACE); 8150afabe90SKenji Kaneshige if ((pi == 1) && (value > PCI_SPEED_133MHz_PCIX)) 8160afabe90SKenji Kaneshige return -EINVAL; 8171da177e4SLinus Torvalds 8181da177e4SLinus Torvalds switch (value) { 8190afabe90SKenji Kaneshige case PCI_SPEED_33MHz: 8200afabe90SKenji Kaneshige cmd = SETA_PCI_33MHZ; 8211da177e4SLinus Torvalds break; 8220afabe90SKenji Kaneshige case PCI_SPEED_66MHz: 8230afabe90SKenji Kaneshige cmd = SETA_PCI_66MHZ; 8241da177e4SLinus Torvalds break; 8250afabe90SKenji Kaneshige case PCI_SPEED_66MHz_PCIX: 8260afabe90SKenji Kaneshige cmd = SETA_PCIX_66MHZ; 8271da177e4SLinus Torvalds break; 8280afabe90SKenji Kaneshige case PCI_SPEED_100MHz_PCIX: 8290afabe90SKenji Kaneshige cmd = SETA_PCIX_100MHZ; 8301da177e4SLinus Torvalds break; 8310afabe90SKenji Kaneshige case PCI_SPEED_133MHz_PCIX: 8320afabe90SKenji Kaneshige cmd = SETA_PCIX_133MHZ; 8330afabe90SKenji Kaneshige break; 8340afabe90SKenji Kaneshige case PCI_SPEED_66MHz_PCIX_ECC: 8350afabe90SKenji Kaneshige cmd = SETB_PCIX_66MHZ_EM; 8360afabe90SKenji Kaneshige break; 8370afabe90SKenji Kaneshige case PCI_SPEED_100MHz_PCIX_ECC: 8380afabe90SKenji Kaneshige cmd = SETB_PCIX_100MHZ_EM; 8390afabe90SKenji Kaneshige break; 8400afabe90SKenji Kaneshige case PCI_SPEED_133MHz_PCIX_ECC: 8410afabe90SKenji Kaneshige cmd = SETB_PCIX_133MHZ_EM; 8420afabe90SKenji Kaneshige break; 8430afabe90SKenji Kaneshige case PCI_SPEED_66MHz_PCIX_266: 8440afabe90SKenji Kaneshige cmd = SETB_PCIX_66MHZ_266; 8450afabe90SKenji Kaneshige break; 8460afabe90SKenji Kaneshige case PCI_SPEED_100MHz_PCIX_266: 8470afabe90SKenji Kaneshige cmd = SETB_PCIX_100MHZ_266; 8480afabe90SKenji Kaneshige break; 8490afabe90SKenji Kaneshige case PCI_SPEED_133MHz_PCIX_266: 8500afabe90SKenji Kaneshige cmd = SETB_PCIX_133MHZ_266; 8510afabe90SKenji Kaneshige break; 8520afabe90SKenji Kaneshige case PCI_SPEED_66MHz_PCIX_533: 8530afabe90SKenji Kaneshige cmd = SETB_PCIX_66MHZ_533; 8540afabe90SKenji Kaneshige break; 8550afabe90SKenji Kaneshige case PCI_SPEED_100MHz_PCIX_533: 8560afabe90SKenji Kaneshige cmd = SETB_PCIX_100MHZ_533; 8570afabe90SKenji Kaneshige break; 8580afabe90SKenji Kaneshige case PCI_SPEED_133MHz_PCIX_533: 8590afabe90SKenji Kaneshige cmd = SETB_PCIX_133MHZ_533; 8601da177e4SLinus Torvalds break; 8611da177e4SLinus Torvalds default: 8620afabe90SKenji Kaneshige return -EINVAL; 8631da177e4SLinus Torvalds } 8641da177e4SLinus Torvalds 8650afabe90SKenji Kaneshige retval = shpc_write_cmd(slot, 0, cmd); 8660afabe90SKenji Kaneshige if (retval) 8671da177e4SLinus Torvalds err("%s: Write command failed!\n", __FUNCTION__); 8681da177e4SLinus Torvalds 8691da177e4SLinus Torvalds DBG_LEAVE_ROUTINE 8701da177e4SLinus Torvalds return retval; 8711da177e4SLinus Torvalds } 8721da177e4SLinus Torvalds 873c4cecc19SKenji Kaneshige static irqreturn_t shpc_isr(int irq, void *dev_id, struct pt_regs *regs) 8741da177e4SLinus Torvalds { 875c4cecc19SKenji Kaneshige struct controller *ctrl = (struct controller *)dev_id; 876c4cecc19SKenji Kaneshige struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle; 877c4cecc19SKenji Kaneshige u32 serr_int, slot_reg, intr_loc, intr_loc2; 8781da177e4SLinus Torvalds int hp_slot; 8791da177e4SLinus Torvalds 8801da177e4SLinus Torvalds /* Check to see if it was our interrupt */ 88175d97c59SKenji Kaneshige intr_loc = shpc_readl(ctrl, INTR_LOC); 8821da177e4SLinus Torvalds if (!intr_loc) 8831da177e4SLinus Torvalds return IRQ_NONE; 884c4cecc19SKenji Kaneshige 8851da177e4SLinus Torvalds dbg("%s: intr_loc = %x\n",__FUNCTION__, intr_loc); 8861da177e4SLinus Torvalds 8871da177e4SLinus Torvalds if(!shpchp_poll_mode) { 888c4cecc19SKenji Kaneshige /* 889c4cecc19SKenji Kaneshige * Mask Global Interrupt Mask - see implementation 890c4cecc19SKenji Kaneshige * note on p. 139 of SHPC spec rev 1.0 891c4cecc19SKenji Kaneshige */ 892c4cecc19SKenji Kaneshige serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE); 893c4cecc19SKenji Kaneshige serr_int |= GLOBAL_INTR_MASK; 894c4cecc19SKenji Kaneshige serr_int &= ~SERR_INTR_RSVDZ_MASK; 895c4cecc19SKenji Kaneshige shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int); 8961da177e4SLinus Torvalds 89775d97c59SKenji Kaneshige intr_loc2 = shpc_readl(ctrl, INTR_LOC); 8981da177e4SLinus Torvalds dbg("%s: intr_loc2 = %x\n",__FUNCTION__, intr_loc2); 8991da177e4SLinus Torvalds } 9001da177e4SLinus Torvalds 901c4cecc19SKenji Kaneshige if (intr_loc & CMD_INTR_PENDING) { 9021da177e4SLinus Torvalds /* 9031da177e4SLinus Torvalds * Command Complete Interrupt Pending 904f467f618SKenji Kaneshige * RO only - clear by writing 1 to the Command Completion 9051da177e4SLinus Torvalds * Detect bit in Controller SERR-INT register 9061da177e4SLinus Torvalds */ 907c4cecc19SKenji Kaneshige serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE); 908c4cecc19SKenji Kaneshige serr_int &= ~SERR_INTR_RSVDZ_MASK; 909c4cecc19SKenji Kaneshige shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int); 910c4cecc19SKenji Kaneshige 911bd62e271SKenji Kaneshige ctrl->cmd_busy = 0; 9121da177e4SLinus Torvalds wake_up_interruptible(&ctrl->queue); 9131da177e4SLinus Torvalds } 9141da177e4SLinus Torvalds 915c4cecc19SKenji Kaneshige if (!(intr_loc & ~CMD_INTR_PENDING)) 916e4e73041SKenji Kaneshige goto out; 9171da177e4SLinus Torvalds 9181da177e4SLinus Torvalds for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) { 9191da177e4SLinus Torvalds /* To find out which slot has interrupt pending */ 920c4cecc19SKenji Kaneshige if (!(intr_loc & SLOT_INTR_PENDING(hp_slot))) 921c4cecc19SKenji Kaneshige continue; 922c4cecc19SKenji Kaneshige 923c4cecc19SKenji Kaneshige slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot)); 9247c8942f9Srajesh.shah@intel.com dbg("%s: Slot %x with intr, slot register = %x\n", 925c4cecc19SKenji Kaneshige __FUNCTION__, hp_slot, slot_reg); 926c4cecc19SKenji Kaneshige 927c4cecc19SKenji Kaneshige if (slot_reg & MRL_CHANGE_DETECTED) 928c4cecc19SKenji Kaneshige php_ctlr->switch_change_callback( 9291da177e4SLinus Torvalds hp_slot, php_ctlr->callback_instance_id); 930c4cecc19SKenji Kaneshige 931c4cecc19SKenji Kaneshige if (slot_reg & BUTTON_PRESS_DETECTED) 932c4cecc19SKenji Kaneshige php_ctlr->attention_button_callback( 9331da177e4SLinus Torvalds hp_slot, php_ctlr->callback_instance_id); 934c4cecc19SKenji Kaneshige 935c4cecc19SKenji Kaneshige if (slot_reg & PRSNT_CHANGE_DETECTED) 936c4cecc19SKenji Kaneshige php_ctlr->presence_change_callback( 9371da177e4SLinus Torvalds hp_slot , php_ctlr->callback_instance_id); 938c4cecc19SKenji Kaneshige 939c4cecc19SKenji Kaneshige if (slot_reg & (ISO_PFAULT_DETECTED | CON_PFAULT_DETECTED)) 940c4cecc19SKenji Kaneshige php_ctlr->power_fault_callback( 9411da177e4SLinus Torvalds hp_slot, php_ctlr->callback_instance_id); 9421da177e4SLinus Torvalds 9431da177e4SLinus Torvalds /* Clear all slot events */ 944c4cecc19SKenji Kaneshige slot_reg &= ~SLOT_REG_RSVDZ_MASK; 945c4cecc19SKenji Kaneshige shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg); 9461da177e4SLinus Torvalds } 947e4e73041SKenji Kaneshige out: 9481da177e4SLinus Torvalds if (!shpchp_poll_mode) { 9491da177e4SLinus Torvalds /* Unmask Global Interrupt Mask */ 950c4cecc19SKenji Kaneshige serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE); 951c4cecc19SKenji Kaneshige serr_int &= ~(GLOBAL_INTR_MASK | SERR_INTR_RSVDZ_MASK); 952c4cecc19SKenji Kaneshige shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int); 9531da177e4SLinus Torvalds } 9541da177e4SLinus Torvalds 9551da177e4SLinus Torvalds return IRQ_HANDLED; 9561da177e4SLinus Torvalds } 9571da177e4SLinus Torvalds 9581da177e4SLinus Torvalds static int hpc_get_max_bus_speed (struct slot *slot, enum pci_bus_speed *value) 9591da177e4SLinus Torvalds { 9600afabe90SKenji Kaneshige int retval = 0; 96175d97c59SKenji Kaneshige struct controller *ctrl = slot->ctrl; 9621da177e4SLinus Torvalds enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN; 96375d97c59SKenji Kaneshige u8 pi = shpc_readb(ctrl, PROG_INTERFACE); 96475d97c59SKenji Kaneshige u32 slot_avail1 = shpc_readl(ctrl, SLOT_AVAIL1); 96575d97c59SKenji Kaneshige u32 slot_avail2 = shpc_readl(ctrl, SLOT_AVAIL2); 9661da177e4SLinus Torvalds 9671da177e4SLinus Torvalds DBG_ENTER_ROUTINE 9681da177e4SLinus Torvalds 9691da177e4SLinus Torvalds if (pi == 2) { 9706558b6abSKenji Kaneshige if (slot_avail2 & SLOT_133MHZ_PCIX_533) 9710afabe90SKenji Kaneshige bus_speed = PCI_SPEED_133MHz_PCIX_533; 9726558b6abSKenji Kaneshige else if (slot_avail2 & SLOT_100MHZ_PCIX_533) 9730afabe90SKenji Kaneshige bus_speed = PCI_SPEED_100MHz_PCIX_533; 9746558b6abSKenji Kaneshige else if (slot_avail2 & SLOT_66MHZ_PCIX_533) 9750afabe90SKenji Kaneshige bus_speed = PCI_SPEED_66MHz_PCIX_533; 9766558b6abSKenji Kaneshige else if (slot_avail2 & SLOT_133MHZ_PCIX_266) 9770afabe90SKenji Kaneshige bus_speed = PCI_SPEED_133MHz_PCIX_266; 9786558b6abSKenji Kaneshige else if (slot_avail2 & SLOT_100MHZ_PCIX_266) 9790afabe90SKenji Kaneshige bus_speed = PCI_SPEED_100MHz_PCIX_266; 9806558b6abSKenji Kaneshige else if (slot_avail2 & SLOT_66MHZ_PCIX_266) 9810afabe90SKenji Kaneshige bus_speed = PCI_SPEED_66MHz_PCIX_266; 9820afabe90SKenji Kaneshige } 9830afabe90SKenji Kaneshige 9840afabe90SKenji Kaneshige if (bus_speed == PCI_SPEED_UNKNOWN) { 9856558b6abSKenji Kaneshige if (slot_avail1 & SLOT_133MHZ_PCIX) 9860afabe90SKenji Kaneshige bus_speed = PCI_SPEED_133MHz_PCIX; 9876558b6abSKenji Kaneshige else if (slot_avail1 & SLOT_100MHZ_PCIX) 9880afabe90SKenji Kaneshige bus_speed = PCI_SPEED_100MHz_PCIX; 9896558b6abSKenji Kaneshige else if (slot_avail1 & SLOT_66MHZ_PCIX) 9900afabe90SKenji Kaneshige bus_speed = PCI_SPEED_66MHz_PCIX; 9916558b6abSKenji Kaneshige else if (slot_avail2 & SLOT_66MHZ) 9920afabe90SKenji Kaneshige bus_speed = PCI_SPEED_66MHz; 9936558b6abSKenji Kaneshige else if (slot_avail1 & SLOT_33MHZ) 9940afabe90SKenji Kaneshige bus_speed = PCI_SPEED_33MHz; 9950afabe90SKenji Kaneshige else 9960afabe90SKenji Kaneshige retval = -ENODEV; 9971da177e4SLinus Torvalds } 9981da177e4SLinus Torvalds 9991da177e4SLinus Torvalds *value = bus_speed; 10001da177e4SLinus Torvalds dbg("Max bus speed = %d\n", bus_speed); 10011da177e4SLinus Torvalds DBG_LEAVE_ROUTINE 10021da177e4SLinus Torvalds return retval; 10031da177e4SLinus Torvalds } 10041da177e4SLinus Torvalds 10051da177e4SLinus Torvalds static int hpc_get_cur_bus_speed (struct slot *slot, enum pci_bus_speed *value) 10061da177e4SLinus Torvalds { 10070afabe90SKenji Kaneshige int retval = 0; 100875d97c59SKenji Kaneshige struct controller *ctrl = slot->ctrl; 10091da177e4SLinus Torvalds enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN; 101075d97c59SKenji Kaneshige u16 sec_bus_reg = shpc_readw(ctrl, SEC_BUS_CONFIG); 101175d97c59SKenji Kaneshige u8 pi = shpc_readb(ctrl, PROG_INTERFACE); 10120afabe90SKenji Kaneshige u8 speed_mode = (pi == 2) ? (sec_bus_reg & 0xF) : (sec_bus_reg & 0x7); 10131da177e4SLinus Torvalds 10141da177e4SLinus Torvalds DBG_ENTER_ROUTINE 10151da177e4SLinus Torvalds 10160afabe90SKenji Kaneshige if ((pi == 1) && (speed_mode > 4)) { 10170afabe90SKenji Kaneshige *value = PCI_SPEED_UNKNOWN; 10180afabe90SKenji Kaneshige return -ENODEV; 10191da177e4SLinus Torvalds } 10201da177e4SLinus Torvalds 10210afabe90SKenji Kaneshige switch (speed_mode) { 10220afabe90SKenji Kaneshige case 0x0: 10230afabe90SKenji Kaneshige *value = PCI_SPEED_33MHz; 10241da177e4SLinus Torvalds break; 10250afabe90SKenji Kaneshige case 0x1: 10260afabe90SKenji Kaneshige *value = PCI_SPEED_66MHz; 10271da177e4SLinus Torvalds break; 10280afabe90SKenji Kaneshige case 0x2: 10290afabe90SKenji Kaneshige *value = PCI_SPEED_66MHz_PCIX; 10301da177e4SLinus Torvalds break; 10310afabe90SKenji Kaneshige case 0x3: 10320afabe90SKenji Kaneshige *value = PCI_SPEED_100MHz_PCIX; 10331da177e4SLinus Torvalds break; 10340afabe90SKenji Kaneshige case 0x4: 10350afabe90SKenji Kaneshige *value = PCI_SPEED_133MHz_PCIX; 10361da177e4SLinus Torvalds break; 10370afabe90SKenji Kaneshige case 0x5: 10380afabe90SKenji Kaneshige *value = PCI_SPEED_66MHz_PCIX_ECC; 10391da177e4SLinus Torvalds break; 10400afabe90SKenji Kaneshige case 0x6: 10410afabe90SKenji Kaneshige *value = PCI_SPEED_100MHz_PCIX_ECC; 10421da177e4SLinus Torvalds break; 10430afabe90SKenji Kaneshige case 0x7: 10440afabe90SKenji Kaneshige *value = PCI_SPEED_133MHz_PCIX_ECC; 10451da177e4SLinus Torvalds break; 10460afabe90SKenji Kaneshige case 0x8: 10470afabe90SKenji Kaneshige *value = PCI_SPEED_66MHz_PCIX_266; 10481da177e4SLinus Torvalds break; 10490afabe90SKenji Kaneshige case 0x9: 10500afabe90SKenji Kaneshige *value = PCI_SPEED_100MHz_PCIX_266; 10511da177e4SLinus Torvalds break; 10521da177e4SLinus Torvalds case 0xa: 10530afabe90SKenji Kaneshige *value = PCI_SPEED_133MHz_PCIX_266; 10541da177e4SLinus Torvalds break; 10551da177e4SLinus Torvalds case 0xb: 10560afabe90SKenji Kaneshige *value = PCI_SPEED_66MHz_PCIX_533; 10571da177e4SLinus Torvalds break; 10581da177e4SLinus Torvalds case 0xc: 10590afabe90SKenji Kaneshige *value = PCI_SPEED_100MHz_PCIX_533; 10601da177e4SLinus Torvalds break; 10611da177e4SLinus Torvalds case 0xd: 10620afabe90SKenji Kaneshige *value = PCI_SPEED_133MHz_PCIX_533; 10631da177e4SLinus Torvalds break; 10641da177e4SLinus Torvalds default: 10650afabe90SKenji Kaneshige *value = PCI_SPEED_UNKNOWN; 10660afabe90SKenji Kaneshige retval = -ENODEV; 10671da177e4SLinus Torvalds break; 10681da177e4SLinus Torvalds } 10691da177e4SLinus Torvalds 10701da177e4SLinus Torvalds dbg("Current bus speed = %d\n", bus_speed); 10711da177e4SLinus Torvalds DBG_LEAVE_ROUTINE 10721da177e4SLinus Torvalds return retval; 10731da177e4SLinus Torvalds } 10741da177e4SLinus Torvalds 10751da177e4SLinus Torvalds static struct hpc_ops shpchp_hpc_ops = { 10761da177e4SLinus Torvalds .power_on_slot = hpc_power_on_slot, 10771da177e4SLinus Torvalds .slot_enable = hpc_slot_enable, 10781da177e4SLinus Torvalds .slot_disable = hpc_slot_disable, 10791da177e4SLinus Torvalds .set_bus_speed_mode = hpc_set_bus_speed_mode, 10801da177e4SLinus Torvalds .set_attention_status = hpc_set_attention_status, 10811da177e4SLinus Torvalds .get_power_status = hpc_get_power_status, 10821da177e4SLinus Torvalds .get_attention_status = hpc_get_attention_status, 10831da177e4SLinus Torvalds .get_latch_status = hpc_get_latch_status, 10841da177e4SLinus Torvalds .get_adapter_status = hpc_get_adapter_status, 10851da177e4SLinus Torvalds 10861da177e4SLinus Torvalds .get_max_bus_speed = hpc_get_max_bus_speed, 10871da177e4SLinus Torvalds .get_cur_bus_speed = hpc_get_cur_bus_speed, 10881da177e4SLinus Torvalds .get_adapter_speed = hpc_get_adapter_speed, 10891da177e4SLinus Torvalds .get_mode1_ECC_cap = hpc_get_mode1_ECC_cap, 10901da177e4SLinus Torvalds .get_prog_int = hpc_get_prog_int, 10911da177e4SLinus Torvalds 10921da177e4SLinus Torvalds .query_power_fault = hpc_query_power_fault, 10931da177e4SLinus Torvalds .green_led_on = hpc_set_green_led_on, 10941da177e4SLinus Torvalds .green_led_off = hpc_set_green_led_off, 10951da177e4SLinus Torvalds .green_led_blink = hpc_set_green_led_blink, 10961da177e4SLinus Torvalds 10971da177e4SLinus Torvalds .release_ctlr = hpc_release_ctlr, 10981da177e4SLinus Torvalds }; 10991da177e4SLinus Torvalds 1100ee138334Srajesh.shah@intel.com int shpc_init(struct controller * ctrl, struct pci_dev * pdev) 11011da177e4SLinus Torvalds { 11021da177e4SLinus Torvalds struct php_ctlr_state_s *php_ctlr, *p; 11031da177e4SLinus Torvalds void *instance_id = ctrl; 11040455986cSKenji Kaneshige int rc, num_slots = 0; 11051da177e4SLinus Torvalds u8 hp_slot; 11060455986cSKenji Kaneshige u32 shpc_base_offset; 110775d97c59SKenji Kaneshige u32 tempdword, slot_reg, slot_config; 11081da177e4SLinus Torvalds u8 i; 11091da177e4SLinus Torvalds 11101da177e4SLinus Torvalds DBG_ENTER_ROUTINE 11111da177e4SLinus Torvalds 11120455986cSKenji Kaneshige ctrl->pci_dev = pdev; /* pci_dev of the P2P bridge */ 11130455986cSKenji Kaneshige 11141da177e4SLinus Torvalds spin_lock_init(&list_lock); 111557c95c0dSKenji Kaneshige php_ctlr = kzalloc(sizeof(*php_ctlr), GFP_KERNEL); 11161da177e4SLinus Torvalds 11171da177e4SLinus Torvalds if (!php_ctlr) { /* allocate controller state data */ 11181da177e4SLinus Torvalds err("%s: HPC controller memory allocation error!\n", __FUNCTION__); 11191da177e4SLinus Torvalds goto abort; 11201da177e4SLinus Torvalds } 11211da177e4SLinus Torvalds 11221da177e4SLinus Torvalds php_ctlr->pci_dev = pdev; /* save pci_dev in context */ 11231da177e4SLinus Torvalds 1124ee138334Srajesh.shah@intel.com if ((pdev->vendor == PCI_VENDOR_ID_AMD) || (pdev->device == 1125ee138334Srajesh.shah@intel.com PCI_DEVICE_ID_AMD_GOLAM_7450)) { 11260455986cSKenji Kaneshige /* amd shpc driver doesn't use Base Offset; assume 0 */ 11270455986cSKenji Kaneshige ctrl->mmio_base = pci_resource_start(pdev, 0); 11280455986cSKenji Kaneshige ctrl->mmio_size = pci_resource_len(pdev, 0); 11291da177e4SLinus Torvalds } else { 11300455986cSKenji Kaneshige ctrl->cap_offset = pci_find_capability(pdev, PCI_CAP_ID_SHPC); 11310455986cSKenji Kaneshige if (!ctrl->cap_offset) { 11320455986cSKenji Kaneshige err("%s : cap_offset == 0\n", __FUNCTION__); 11331da177e4SLinus Torvalds goto abort_free_ctlr; 11341da177e4SLinus Torvalds } 11350455986cSKenji Kaneshige dbg("%s: cap_offset = %x\n", __FUNCTION__, ctrl->cap_offset); 11361da177e4SLinus Torvalds 113775d97c59SKenji Kaneshige rc = shpc_indirect_read(ctrl, 0, &shpc_base_offset); 11381da177e4SLinus Torvalds if (rc) { 11390455986cSKenji Kaneshige err("%s: cannot read base_offset\n", __FUNCTION__); 11401da177e4SLinus Torvalds goto abort_free_ctlr; 11411da177e4SLinus Torvalds } 11421da177e4SLinus Torvalds 114375d97c59SKenji Kaneshige rc = shpc_indirect_read(ctrl, 3, &tempdword); 11441da177e4SLinus Torvalds if (rc) { 11450455986cSKenji Kaneshige err("%s: cannot read slot config\n", __FUNCTION__); 11461da177e4SLinus Torvalds goto abort_free_ctlr; 11471da177e4SLinus Torvalds } 11480455986cSKenji Kaneshige num_slots = tempdword & SLOT_NUM; 11490455986cSKenji Kaneshige dbg("%s: num_slots (indirect) %x\n", __FUNCTION__, num_slots); 11501da177e4SLinus Torvalds 11510455986cSKenji Kaneshige for (i = 0; i < 9 + num_slots; i++) { 115275d97c59SKenji Kaneshige rc = shpc_indirect_read(ctrl, i, &tempdword); 11531da177e4SLinus Torvalds if (rc) { 11540455986cSKenji Kaneshige err("%s: cannot read creg (index = %d)\n", 11550455986cSKenji Kaneshige __FUNCTION__, i); 11561da177e4SLinus Torvalds goto abort_free_ctlr; 11571da177e4SLinus Torvalds } 11587c8942f9Srajesh.shah@intel.com dbg("%s: offset %d: value %x\n", __FUNCTION__,i, 11597c8942f9Srajesh.shah@intel.com tempdword); 11601da177e4SLinus Torvalds } 11610455986cSKenji Kaneshige 11620455986cSKenji Kaneshige ctrl->mmio_base = 11630455986cSKenji Kaneshige pci_resource_start(pdev, 0) + shpc_base_offset; 11640455986cSKenji Kaneshige ctrl->mmio_size = 0x24 + 0x4 * num_slots; 11651da177e4SLinus Torvalds } 11661da177e4SLinus Torvalds 11671da177e4SLinus Torvalds info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", pdev->vendor, pdev->device, pdev->subsystem_vendor, 11681da177e4SLinus Torvalds pdev->subsystem_device); 11691da177e4SLinus Torvalds 11701da177e4SLinus Torvalds if (pci_enable_device(pdev)) 11711da177e4SLinus Torvalds goto abort_free_ctlr; 11721da177e4SLinus Torvalds 11730455986cSKenji Kaneshige if (!request_mem_region(ctrl->mmio_base, ctrl->mmio_size, MY_NAME)) { 11741da177e4SLinus Torvalds err("%s: cannot reserve MMIO region\n", __FUNCTION__); 11751da177e4SLinus Torvalds goto abort_free_ctlr; 11761da177e4SLinus Torvalds } 11771da177e4SLinus Torvalds 11780455986cSKenji Kaneshige php_ctlr->creg = ioremap(ctrl->mmio_base, ctrl->mmio_size); 11791da177e4SLinus Torvalds if (!php_ctlr->creg) { 11800455986cSKenji Kaneshige err("%s: cannot remap MMIO region %lx @ %lx\n", __FUNCTION__, 11810455986cSKenji Kaneshige ctrl->mmio_size, ctrl->mmio_base); 11820455986cSKenji Kaneshige release_mem_region(ctrl->mmio_base, ctrl->mmio_size); 11831da177e4SLinus Torvalds goto abort_free_ctlr; 11841da177e4SLinus Torvalds } 11851da177e4SLinus Torvalds dbg("%s: php_ctlr->creg %p\n", __FUNCTION__, php_ctlr->creg); 11861da177e4SLinus Torvalds 11876aa4cdd0SIngo Molnar mutex_init(&ctrl->crit_sect); 1188d29aaddaSKenji Kaneshige mutex_init(&ctrl->cmd_lock); 1189d29aaddaSKenji Kaneshige 11901da177e4SLinus Torvalds /* Setup wait queue */ 11911da177e4SLinus Torvalds init_waitqueue_head(&ctrl->queue); 11921da177e4SLinus Torvalds 11931da177e4SLinus Torvalds /* Find the IRQ */ 11941da177e4SLinus Torvalds php_ctlr->irq = pdev->irq; 1195ee138334Srajesh.shah@intel.com php_ctlr->attention_button_callback = shpchp_handle_attention_button, 1196ee138334Srajesh.shah@intel.com php_ctlr->switch_change_callback = shpchp_handle_switch_change; 1197ee138334Srajesh.shah@intel.com php_ctlr->presence_change_callback = shpchp_handle_presence_change; 1198ee138334Srajesh.shah@intel.com php_ctlr->power_fault_callback = shpchp_handle_power_fault; 11991da177e4SLinus Torvalds php_ctlr->callback_instance_id = instance_id; 12001da177e4SLinus Torvalds 120175d97c59SKenji Kaneshige ctrl->hpc_ctlr_handle = php_ctlr; 120275d97c59SKenji Kaneshige ctrl->hpc_ops = &shpchp_hpc_ops; 120375d97c59SKenji Kaneshige 12041da177e4SLinus Torvalds /* Return PCI Controller Info */ 120575d97c59SKenji Kaneshige slot_config = shpc_readl(ctrl, SLOT_CONFIG); 120675d97c59SKenji Kaneshige php_ctlr->slot_device_offset = (slot_config & FIRST_DEV_NUM) >> 8; 120775d97c59SKenji Kaneshige php_ctlr->num_slots = slot_config & SLOT_NUM; 12081da177e4SLinus Torvalds dbg("%s: slot_device_offset %x\n", __FUNCTION__, php_ctlr->slot_device_offset); 12091da177e4SLinus Torvalds dbg("%s: num_slots %x\n", __FUNCTION__, php_ctlr->num_slots); 12101da177e4SLinus Torvalds 12111da177e4SLinus Torvalds /* Mask Global Interrupt Mask & Command Complete Interrupt Mask */ 121275d97c59SKenji Kaneshige tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); 12131da177e4SLinus Torvalds dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword); 1214e7138723SKenji Kaneshige tempdword |= (GLOBAL_INTR_MASK | GLOBAL_SERR_MASK | 1215e7138723SKenji Kaneshige COMMAND_INTR_MASK | ARBITER_SERR_MASK); 1216e7138723SKenji Kaneshige tempdword &= ~SERR_INTR_RSVDZ_MASK; 121775d97c59SKenji Kaneshige shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword); 121875d97c59SKenji Kaneshige tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); 12191da177e4SLinus Torvalds dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword); 12201da177e4SLinus Torvalds 12211da177e4SLinus Torvalds /* Mask the MRL sensor SERR Mask of individual slot in 12221da177e4SLinus Torvalds * Slot SERR-INT Mask & clear all the existing event if any 12231da177e4SLinus Torvalds */ 12241da177e4SLinus Torvalds for (hp_slot = 0; hp_slot < php_ctlr->num_slots; hp_slot++) { 12252b34da7eSKenji Kaneshige slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot)); 12261da177e4SLinus Torvalds dbg("%s: Default Logical Slot Register %d value %x\n", __FUNCTION__, 12271da177e4SLinus Torvalds hp_slot, slot_reg); 1228795eb5c4SKenji Kaneshige slot_reg |= (PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK | 1229795eb5c4SKenji Kaneshige BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK | 1230795eb5c4SKenji Kaneshige CON_PFAULT_INTR_MASK | MRL_CHANGE_SERR_MASK | 1231795eb5c4SKenji Kaneshige CON_PFAULT_SERR_MASK); 1232795eb5c4SKenji Kaneshige slot_reg &= ~SLOT_REG_RSVDZ_MASK; 1233795eb5c4SKenji Kaneshige shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg); 12341da177e4SLinus Torvalds } 12351da177e4SLinus Torvalds 12361da177e4SLinus Torvalds if (shpchp_poll_mode) {/* Install interrupt polling code */ 12371da177e4SLinus Torvalds /* Install and start the interrupt polling timer */ 12381da177e4SLinus Torvalds init_timer(&php_ctlr->int_poll_timer); 12391da177e4SLinus Torvalds start_int_poll_timer( php_ctlr, 10 ); /* start with 10 second delay */ 12401da177e4SLinus Torvalds } else { 12411da177e4SLinus Torvalds /* Installs the interrupt handler */ 12421da177e4SLinus Torvalds rc = pci_enable_msi(pdev); 12431da177e4SLinus Torvalds if (rc) { 12441da177e4SLinus Torvalds info("Can't get msi for the hotplug controller\n"); 12451da177e4SLinus Torvalds info("Use INTx for the hotplug controller\n"); 12461da177e4SLinus Torvalds } else 12471da177e4SLinus Torvalds php_ctlr->irq = pdev->irq; 12481da177e4SLinus Torvalds 12496b4486e2SThomas Gleixner rc = request_irq(php_ctlr->irq, shpc_isr, IRQF_SHARED, MY_NAME, (void *) ctrl); 12501da177e4SLinus Torvalds dbg("%s: request_irq %d for hpc%d (returns %d)\n", __FUNCTION__, php_ctlr->irq, ctlr_seq_num, rc); 12511da177e4SLinus Torvalds if (rc) { 12521da177e4SLinus Torvalds err("Can't get irq %d for the hotplug controller\n", php_ctlr->irq); 12531da177e4SLinus Torvalds goto abort_free_ctlr; 12541da177e4SLinus Torvalds } 12551da177e4SLinus Torvalds } 12567c8942f9Srajesh.shah@intel.com dbg("%s: HPC at b:d:f:irq=0x%x:%x:%x:%x\n", __FUNCTION__, 12577c8942f9Srajesh.shah@intel.com pdev->bus->number, PCI_SLOT(pdev->devfn), 12587c8942f9Srajesh.shah@intel.com PCI_FUNC(pdev->devfn), pdev->irq); 1259424600f9Srajesh.shah@intel.com get_hp_hw_control_from_firmware(pdev); 12601da177e4SLinus Torvalds 12611da177e4SLinus Torvalds /* Add this HPC instance into the HPC list */ 12621da177e4SLinus Torvalds spin_lock(&list_lock); 12631da177e4SLinus Torvalds if (php_ctlr_list_head == 0) { 12641da177e4SLinus Torvalds php_ctlr_list_head = php_ctlr; 12651da177e4SLinus Torvalds p = php_ctlr_list_head; 12661da177e4SLinus Torvalds p->pnext = NULL; 12671da177e4SLinus Torvalds } else { 12681da177e4SLinus Torvalds p = php_ctlr_list_head; 12691da177e4SLinus Torvalds 12701da177e4SLinus Torvalds while (p->pnext) 12711da177e4SLinus Torvalds p = p->pnext; 12721da177e4SLinus Torvalds 12731da177e4SLinus Torvalds p->pnext = php_ctlr; 12741da177e4SLinus Torvalds } 12751da177e4SLinus Torvalds spin_unlock(&list_lock); 12761da177e4SLinus Torvalds 12771da177e4SLinus Torvalds ctlr_seq_num++; 12781da177e4SLinus Torvalds 1279795eb5c4SKenji Kaneshige /* 128082d5f4aaSKenji Kaneshige * If this is the first controller to be initialized, 128182d5f4aaSKenji Kaneshige * initialize the shpchpd work queue 128282d5f4aaSKenji Kaneshige */ 128382d5f4aaSKenji Kaneshige if (atomic_add_return(1, &shpchp_num_controllers) == 1) { 128482d5f4aaSKenji Kaneshige shpchp_wq = create_singlethread_workqueue("shpchpd"); 128582d5f4aaSKenji Kaneshige if (!shpchp_wq) 128682d5f4aaSKenji Kaneshige return -ENOMEM; 128782d5f4aaSKenji Kaneshige } 128882d5f4aaSKenji Kaneshige 128982d5f4aaSKenji Kaneshige /* 1290795eb5c4SKenji Kaneshige * Unmask all event interrupts of all slots 1291795eb5c4SKenji Kaneshige */ 12921da177e4SLinus Torvalds for (hp_slot = 0; hp_slot < php_ctlr->num_slots; hp_slot++) { 12932b34da7eSKenji Kaneshige slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot)); 12941da177e4SLinus Torvalds dbg("%s: Default Logical Slot Register %d value %x\n", __FUNCTION__, 12951da177e4SLinus Torvalds hp_slot, slot_reg); 1296795eb5c4SKenji Kaneshige slot_reg &= ~(PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK | 1297795eb5c4SKenji Kaneshige BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK | 1298795eb5c4SKenji Kaneshige CON_PFAULT_INTR_MASK | SLOT_REG_RSVDZ_MASK); 1299795eb5c4SKenji Kaneshige shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg); 13001da177e4SLinus Torvalds } 13011da177e4SLinus Torvalds if (!shpchp_poll_mode) { 13021da177e4SLinus Torvalds /* Unmask all general input interrupts and SERR */ 130375d97c59SKenji Kaneshige tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); 1304e7138723SKenji Kaneshige tempdword &= ~(GLOBAL_INTR_MASK | COMMAND_INTR_MASK | 1305e7138723SKenji Kaneshige SERR_INTR_RSVDZ_MASK); 130675d97c59SKenji Kaneshige shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword); 130775d97c59SKenji Kaneshige tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); 13081da177e4SLinus Torvalds dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword); 13091da177e4SLinus Torvalds } 13101da177e4SLinus Torvalds 13111da177e4SLinus Torvalds DBG_LEAVE_ROUTINE 13121da177e4SLinus Torvalds return 0; 13131da177e4SLinus Torvalds 13141da177e4SLinus Torvalds /* We end up here for the many possible ways to fail this API. */ 13151da177e4SLinus Torvalds abort_free_ctlr: 13161da177e4SLinus Torvalds kfree(php_ctlr); 13171da177e4SLinus Torvalds abort: 13181da177e4SLinus Torvalds DBG_LEAVE_ROUTINE 13191da177e4SLinus Torvalds return -1; 13201da177e4SLinus Torvalds } 1321