11da177e4SLinus Torvalds /* 21da177e4SLinus Torvalds * Standard PCI Hot Plug Driver 31da177e4SLinus Torvalds * 41da177e4SLinus Torvalds * Copyright (C) 1995,2001 Compaq Computer Corporation 51da177e4SLinus Torvalds * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com) 61da177e4SLinus Torvalds * Copyright (C) 2001 IBM Corp. 71da177e4SLinus Torvalds * Copyright (C) 2003-2004 Intel Corporation 81da177e4SLinus Torvalds * 91da177e4SLinus Torvalds * All rights reserved. 101da177e4SLinus Torvalds * 111da177e4SLinus Torvalds * This program is free software; you can redistribute it and/or modify 121da177e4SLinus Torvalds * it under the terms of the GNU General Public License as published by 131da177e4SLinus Torvalds * the Free Software Foundation; either version 2 of the License, or (at 141da177e4SLinus Torvalds * your option) any later version. 151da177e4SLinus Torvalds * 161da177e4SLinus Torvalds * This program is distributed in the hope that it will be useful, but 171da177e4SLinus Torvalds * WITHOUT ANY WARRANTY; without even the implied warranty of 181da177e4SLinus Torvalds * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 191da177e4SLinus Torvalds * NON INFRINGEMENT. See the GNU General Public License for more 201da177e4SLinus Torvalds * details. 211da177e4SLinus Torvalds * 221da177e4SLinus Torvalds * You should have received a copy of the GNU General Public License 231da177e4SLinus Torvalds * along with this program; if not, write to the Free Software 241da177e4SLinus Torvalds * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 251da177e4SLinus Torvalds * 268cf4c195SKristen Accardi * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com> 271da177e4SLinus Torvalds * 281da177e4SLinus Torvalds */ 291da177e4SLinus Torvalds 301da177e4SLinus Torvalds #include <linux/kernel.h> 311da177e4SLinus Torvalds #include <linux/module.h> 321da177e4SLinus Torvalds #include <linux/types.h> 331da177e4SLinus Torvalds #include <linux/pci.h> 34d4d28dd4SAndrew Morton #include <linux/interrupt.h> 35d4d28dd4SAndrew Morton 361da177e4SLinus Torvalds #include "shpchp.h" 371da177e4SLinus Torvalds 381da177e4SLinus Torvalds #ifdef DEBUG 391da177e4SLinus Torvalds #define DBG_K_TRACE_ENTRY ((unsigned int)0x00000001) /* On function entry */ 401da177e4SLinus Torvalds #define DBG_K_TRACE_EXIT ((unsigned int)0x00000002) /* On function exit */ 411da177e4SLinus Torvalds #define DBG_K_INFO ((unsigned int)0x00000004) /* Info messages */ 421da177e4SLinus Torvalds #define DBG_K_ERROR ((unsigned int)0x00000008) /* Error messages */ 431da177e4SLinus Torvalds #define DBG_K_TRACE (DBG_K_TRACE_ENTRY|DBG_K_TRACE_EXIT) 441da177e4SLinus Torvalds #define DBG_K_STANDARD (DBG_K_INFO|DBG_K_ERROR|DBG_K_TRACE) 451da177e4SLinus Torvalds /* Redefine this flagword to set debug level */ 461da177e4SLinus Torvalds #define DEBUG_LEVEL DBG_K_STANDARD 471da177e4SLinus Torvalds 481da177e4SLinus Torvalds #define DEFINE_DBG_BUFFER char __dbg_str_buf[256]; 491da177e4SLinus Torvalds 501da177e4SLinus Torvalds #define DBG_PRINT( dbg_flags, args... ) \ 511da177e4SLinus Torvalds do { \ 521da177e4SLinus Torvalds if ( DEBUG_LEVEL & ( dbg_flags ) ) \ 531da177e4SLinus Torvalds { \ 541da177e4SLinus Torvalds int len; \ 551da177e4SLinus Torvalds len = sprintf( __dbg_str_buf, "%s:%d: %s: ", \ 561da177e4SLinus Torvalds __FILE__, __LINE__, __FUNCTION__ ); \ 571da177e4SLinus Torvalds sprintf( __dbg_str_buf + len, args ); \ 581da177e4SLinus Torvalds printk( KERN_NOTICE "%s\n", __dbg_str_buf ); \ 591da177e4SLinus Torvalds } \ 601da177e4SLinus Torvalds } while (0) 611da177e4SLinus Torvalds 621da177e4SLinus Torvalds #define DBG_ENTER_ROUTINE DBG_PRINT (DBG_K_TRACE_ENTRY, "%s", "[Entry]"); 631da177e4SLinus Torvalds #define DBG_LEAVE_ROUTINE DBG_PRINT (DBG_K_TRACE_EXIT, "%s", "[Exit]"); 641da177e4SLinus Torvalds #else 651da177e4SLinus Torvalds #define DEFINE_DBG_BUFFER 661da177e4SLinus Torvalds #define DBG_ENTER_ROUTINE 671da177e4SLinus Torvalds #define DBG_LEAVE_ROUTINE 681da177e4SLinus Torvalds #endif /* DEBUG */ 691da177e4SLinus Torvalds 701da177e4SLinus Torvalds /* Slot Available Register I field definition */ 711da177e4SLinus Torvalds #define SLOT_33MHZ 0x0000001f 721da177e4SLinus Torvalds #define SLOT_66MHZ_PCIX 0x00001f00 731da177e4SLinus Torvalds #define SLOT_100MHZ_PCIX 0x001f0000 741da177e4SLinus Torvalds #define SLOT_133MHZ_PCIX 0x1f000000 751da177e4SLinus Torvalds 761da177e4SLinus Torvalds /* Slot Available Register II field definition */ 771da177e4SLinus Torvalds #define SLOT_66MHZ 0x0000001f 781da177e4SLinus Torvalds #define SLOT_66MHZ_PCIX_266 0x00000f00 791da177e4SLinus Torvalds #define SLOT_100MHZ_PCIX_266 0x0000f000 801da177e4SLinus Torvalds #define SLOT_133MHZ_PCIX_266 0x000f0000 811da177e4SLinus Torvalds #define SLOT_66MHZ_PCIX_533 0x00f00000 821da177e4SLinus Torvalds #define SLOT_100MHZ_PCIX_533 0x0f000000 831da177e4SLinus Torvalds #define SLOT_133MHZ_PCIX_533 0xf0000000 841da177e4SLinus Torvalds 851da177e4SLinus Torvalds /* Slot Configuration */ 861da177e4SLinus Torvalds #define SLOT_NUM 0x0000001F 871da177e4SLinus Torvalds #define FIRST_DEV_NUM 0x00001F00 881da177e4SLinus Torvalds #define PSN 0x07FF0000 891da177e4SLinus Torvalds #define UPDOWN 0x20000000 901da177e4SLinus Torvalds #define MRLSENSOR 0x40000000 911da177e4SLinus Torvalds #define ATTN_BUTTON 0x80000000 921da177e4SLinus Torvalds 932b34da7eSKenji Kaneshige /* 94c4cecc19SKenji Kaneshige * Interrupt Locator Register definitions 95c4cecc19SKenji Kaneshige */ 96c4cecc19SKenji Kaneshige #define CMD_INTR_PENDING (1 << 0) 97c4cecc19SKenji Kaneshige #define SLOT_INTR_PENDING(i) (1 << (i + 1)) 98c4cecc19SKenji Kaneshige 99c4cecc19SKenji Kaneshige /* 100e7138723SKenji Kaneshige * Controller SERR-INT Register 101e7138723SKenji Kaneshige */ 102e7138723SKenji Kaneshige #define GLOBAL_INTR_MASK (1 << 0) 103e7138723SKenji Kaneshige #define GLOBAL_SERR_MASK (1 << 1) 104e7138723SKenji Kaneshige #define COMMAND_INTR_MASK (1 << 2) 105e7138723SKenji Kaneshige #define ARBITER_SERR_MASK (1 << 3) 106e7138723SKenji Kaneshige #define COMMAND_DETECTED (1 << 16) 107e7138723SKenji Kaneshige #define ARBITER_DETECTED (1 << 17) 108e7138723SKenji Kaneshige #define SERR_INTR_RSVDZ_MASK 0xfffc0000 109e7138723SKenji Kaneshige 110e7138723SKenji Kaneshige /* 1112b34da7eSKenji Kaneshige * Logical Slot Register definitions 1122b34da7eSKenji Kaneshige */ 1132b34da7eSKenji Kaneshige #define SLOT_REG(i) (SLOT1 + (4 * i)) 1142b34da7eSKenji Kaneshige 1155858759cSKenji Kaneshige #define SLOT_STATE_SHIFT (0) 1165858759cSKenji Kaneshige #define SLOT_STATE_MASK (3 << 0) 1175858759cSKenji Kaneshige #define SLOT_STATE_PWRONLY (1) 1185858759cSKenji Kaneshige #define SLOT_STATE_ENABLED (2) 1195858759cSKenji Kaneshige #define SLOT_STATE_DISABLED (3) 1205858759cSKenji Kaneshige #define PWR_LED_STATE_SHIFT (2) 1215858759cSKenji Kaneshige #define PWR_LED_STATE_MASK (3 << 2) 1225858759cSKenji Kaneshige #define ATN_LED_STATE_SHIFT (4) 1235858759cSKenji Kaneshige #define ATN_LED_STATE_MASK (3 << 4) 1245858759cSKenji Kaneshige #define ATN_LED_STATE_ON (1) 1255858759cSKenji Kaneshige #define ATN_LED_STATE_BLINK (2) 1265858759cSKenji Kaneshige #define ATN_LED_STATE_OFF (3) 1275858759cSKenji Kaneshige #define POWER_FAULT (1 << 6) 1285858759cSKenji Kaneshige #define ATN_BUTTON (1 << 7) 1295858759cSKenji Kaneshige #define MRL_SENSOR (1 << 8) 1305858759cSKenji Kaneshige #define MHZ66_CAP (1 << 9) 1315858759cSKenji Kaneshige #define PRSNT_SHIFT (10) 1325858759cSKenji Kaneshige #define PRSNT_MASK (3 << 10) 1335858759cSKenji Kaneshige #define PCIX_CAP_SHIFT (12) 1345858759cSKenji Kaneshige #define PCIX_CAP_MASK_PI1 (3 << 12) 1355858759cSKenji Kaneshige #define PCIX_CAP_MASK_PI2 (7 << 12) 1365858759cSKenji Kaneshige #define PRSNT_CHANGE_DETECTED (1 << 16) 1375858759cSKenji Kaneshige #define ISO_PFAULT_DETECTED (1 << 17) 1385858759cSKenji Kaneshige #define BUTTON_PRESS_DETECTED (1 << 18) 1395858759cSKenji Kaneshige #define MRL_CHANGE_DETECTED (1 << 19) 1405858759cSKenji Kaneshige #define CON_PFAULT_DETECTED (1 << 20) 1415858759cSKenji Kaneshige #define PRSNT_CHANGE_INTR_MASK (1 << 24) 1425858759cSKenji Kaneshige #define ISO_PFAULT_INTR_MASK (1 << 25) 1435858759cSKenji Kaneshige #define BUTTON_PRESS_INTR_MASK (1 << 26) 1445858759cSKenji Kaneshige #define MRL_CHANGE_INTR_MASK (1 << 27) 1455858759cSKenji Kaneshige #define CON_PFAULT_INTR_MASK (1 << 28) 1465858759cSKenji Kaneshige #define MRL_CHANGE_SERR_MASK (1 << 29) 1475858759cSKenji Kaneshige #define CON_PFAULT_SERR_MASK (1 << 30) 1485858759cSKenji Kaneshige #define SLOT_REG_RSVDZ_MASK (1 << 15) | (7 << 21) 1491da177e4SLinus Torvalds 1504085399dSKenji Kaneshige /* 1514085399dSKenji Kaneshige * SHPC Command Code definitnions 1524085399dSKenji Kaneshige * 1534085399dSKenji Kaneshige * Slot Operation 00h - 3Fh 1544085399dSKenji Kaneshige * Set Bus Segment Speed/Mode A 40h - 47h 1554085399dSKenji Kaneshige * Power-Only All Slots 48h 1564085399dSKenji Kaneshige * Enable All Slots 49h 1574085399dSKenji Kaneshige * Set Bus Segment Speed/Mode B (PI=2) 50h - 5Fh 1584085399dSKenji Kaneshige * Reserved Command Codes 60h - BFh 1594085399dSKenji Kaneshige * Vendor Specific Commands C0h - FFh 1604085399dSKenji Kaneshige */ 1614085399dSKenji Kaneshige #define SET_SLOT_PWR 0x01 /* Slot Operation */ 1621da177e4SLinus Torvalds #define SET_SLOT_ENABLE 0x02 1631da177e4SLinus Torvalds #define SET_SLOT_DISABLE 0x03 1641da177e4SLinus Torvalds #define SET_PWR_ON 0x04 1651da177e4SLinus Torvalds #define SET_PWR_BLINK 0x08 1664085399dSKenji Kaneshige #define SET_PWR_OFF 0x0c 1674085399dSKenji Kaneshige #define SET_ATTN_ON 0x10 1684085399dSKenji Kaneshige #define SET_ATTN_BLINK 0x20 1694085399dSKenji Kaneshige #define SET_ATTN_OFF 0x30 1704085399dSKenji Kaneshige #define SETA_PCI_33MHZ 0x40 /* Set Bus Segment Speed/Mode A */ 1711da177e4SLinus Torvalds #define SETA_PCI_66MHZ 0x41 1721da177e4SLinus Torvalds #define SETA_PCIX_66MHZ 0x42 1731da177e4SLinus Torvalds #define SETA_PCIX_100MHZ 0x43 1741da177e4SLinus Torvalds #define SETA_PCIX_133MHZ 0x44 1754085399dSKenji Kaneshige #define SETA_RESERVED1 0x45 1764085399dSKenji Kaneshige #define SETA_RESERVED2 0x46 1774085399dSKenji Kaneshige #define SETA_RESERVED3 0x47 1784085399dSKenji Kaneshige #define SET_PWR_ONLY_ALL 0x48 /* Power-Only All Slots */ 1794085399dSKenji Kaneshige #define SET_ENABLE_ALL 0x49 /* Enable All Slots */ 1804085399dSKenji Kaneshige #define SETB_PCI_33MHZ 0x50 /* Set Bus Segment Speed/Mode B */ 1811da177e4SLinus Torvalds #define SETB_PCI_66MHZ 0x51 1821da177e4SLinus Torvalds #define SETB_PCIX_66MHZ_PM 0x52 1831da177e4SLinus Torvalds #define SETB_PCIX_100MHZ_PM 0x53 1841da177e4SLinus Torvalds #define SETB_PCIX_133MHZ_PM 0x54 1851da177e4SLinus Torvalds #define SETB_PCIX_66MHZ_EM 0x55 1861da177e4SLinus Torvalds #define SETB_PCIX_100MHZ_EM 0x56 1871da177e4SLinus Torvalds #define SETB_PCIX_133MHZ_EM 0x57 1881da177e4SLinus Torvalds #define SETB_PCIX_66MHZ_266 0x58 1891da177e4SLinus Torvalds #define SETB_PCIX_100MHZ_266 0x59 1901da177e4SLinus Torvalds #define SETB_PCIX_133MHZ_266 0x5a 1911da177e4SLinus Torvalds #define SETB_PCIX_66MHZ_533 0x5b 1921da177e4SLinus Torvalds #define SETB_PCIX_100MHZ_533 0x5c 1931da177e4SLinus Torvalds #define SETB_PCIX_133MHZ_533 0x5d 1944085399dSKenji Kaneshige #define SETB_RESERVED1 0x5e 1954085399dSKenji Kaneshige #define SETB_RESERVED2 0x5f 1961da177e4SLinus Torvalds 1974085399dSKenji Kaneshige /* 1984085399dSKenji Kaneshige * SHPC controller command error code 1994085399dSKenji Kaneshige */ 2001da177e4SLinus Torvalds #define SWITCH_OPEN 0x1 2011da177e4SLinus Torvalds #define INVALID_CMD 0x2 2021da177e4SLinus Torvalds #define INVALID_SPEED_MODE 0x4 2031da177e4SLinus Torvalds 2044085399dSKenji Kaneshige /* 2054085399dSKenji Kaneshige * For accessing SHPC Working Register Set via PCI Configuration Space 2064085399dSKenji Kaneshige */ 2071da177e4SLinus Torvalds #define DWORD_SELECT 0x2 2081da177e4SLinus Torvalds #define DWORD_DATA 0x4 2091da177e4SLinus Torvalds 2101da177e4SLinus Torvalds /* Field Offset in Logical Slot Register - byte boundary */ 2111da177e4SLinus Torvalds #define SLOT_EVENT_LATCH 0x2 2121da177e4SLinus Torvalds #define SLOT_SERR_INT_MASK 0x3 2131da177e4SLinus Torvalds 2141da177e4SLinus Torvalds DEFINE_DBG_BUFFER /* Debug string buffer for entire HPC defined here */ 21582d5f4aaSKenji Kaneshige static atomic_t shpchp_num_controllers = ATOMIC_INIT(0); 21682d5f4aaSKenji Kaneshige 2177d12e780SDavid Howells static irqreturn_t shpc_isr(int irq, void *dev_id); 2180abe68ceSKenji Kaneshige static void start_int_poll_timer(struct controller *ctrl, int sec); 219d29aaddaSKenji Kaneshige static int hpc_check_cmd_status(struct controller *ctrl); 2201da177e4SLinus Torvalds 22175d97c59SKenji Kaneshige static inline u8 shpc_readb(struct controller *ctrl, int reg) 22275d97c59SKenji Kaneshige { 2230abe68ceSKenji Kaneshige return readb(ctrl->creg + reg); 22475d97c59SKenji Kaneshige } 22575d97c59SKenji Kaneshige 22675d97c59SKenji Kaneshige static inline void shpc_writeb(struct controller *ctrl, int reg, u8 val) 22775d97c59SKenji Kaneshige { 2280abe68ceSKenji Kaneshige writeb(val, ctrl->creg + reg); 22975d97c59SKenji Kaneshige } 23075d97c59SKenji Kaneshige 23175d97c59SKenji Kaneshige static inline u16 shpc_readw(struct controller *ctrl, int reg) 23275d97c59SKenji Kaneshige { 2330abe68ceSKenji Kaneshige return readw(ctrl->creg + reg); 23475d97c59SKenji Kaneshige } 23575d97c59SKenji Kaneshige 23675d97c59SKenji Kaneshige static inline void shpc_writew(struct controller *ctrl, int reg, u16 val) 23775d97c59SKenji Kaneshige { 2380abe68ceSKenji Kaneshige writew(val, ctrl->creg + reg); 23975d97c59SKenji Kaneshige } 24075d97c59SKenji Kaneshige 24175d97c59SKenji Kaneshige static inline u32 shpc_readl(struct controller *ctrl, int reg) 24275d97c59SKenji Kaneshige { 2430abe68ceSKenji Kaneshige return readl(ctrl->creg + reg); 24475d97c59SKenji Kaneshige } 24575d97c59SKenji Kaneshige 24675d97c59SKenji Kaneshige static inline void shpc_writel(struct controller *ctrl, int reg, u32 val) 24775d97c59SKenji Kaneshige { 2480abe68ceSKenji Kaneshige writel(val, ctrl->creg + reg); 24975d97c59SKenji Kaneshige } 25075d97c59SKenji Kaneshige 25175d97c59SKenji Kaneshige static inline int shpc_indirect_read(struct controller *ctrl, int index, 25275d97c59SKenji Kaneshige u32 *value) 25375d97c59SKenji Kaneshige { 25475d97c59SKenji Kaneshige int rc; 25575d97c59SKenji Kaneshige u32 cap_offset = ctrl->cap_offset; 25675d97c59SKenji Kaneshige struct pci_dev *pdev = ctrl->pci_dev; 25775d97c59SKenji Kaneshige 25875d97c59SKenji Kaneshige rc = pci_write_config_byte(pdev, cap_offset + DWORD_SELECT, index); 25975d97c59SKenji Kaneshige if (rc) 26075d97c59SKenji Kaneshige return rc; 26175d97c59SKenji Kaneshige return pci_read_config_dword(pdev, cap_offset + DWORD_DATA, value); 26275d97c59SKenji Kaneshige } 26375d97c59SKenji Kaneshige 264f4263957SKenji Kaneshige /* 265f4263957SKenji Kaneshige * This is the interrupt polling timeout function. 266f4263957SKenji Kaneshige */ 2670abe68ceSKenji Kaneshige static void int_poll_timeout(unsigned long data) 2681da177e4SLinus Torvalds { 2690abe68ceSKenji Kaneshige struct controller *ctrl = (struct controller *)data; 2701da177e4SLinus Torvalds 2711da177e4SLinus Torvalds DBG_ENTER_ROUTINE 2721da177e4SLinus Torvalds 2731da177e4SLinus Torvalds /* Poll for interrupt events. regs == NULL => polling */ 2740abe68ceSKenji Kaneshige shpc_isr(0, ctrl); 2751da177e4SLinus Torvalds 2760abe68ceSKenji Kaneshige init_timer(&ctrl->poll_timer); 2771da177e4SLinus Torvalds if (!shpchp_poll_time) 278f4263957SKenji Kaneshige shpchp_poll_time = 2; /* default polling interval is 2 sec */ 2791da177e4SLinus Torvalds 2800abe68ceSKenji Kaneshige start_int_poll_timer(ctrl, shpchp_poll_time); 2811da177e4SLinus Torvalds 282f4263957SKenji Kaneshige DBG_LEAVE_ROUTINE 2831da177e4SLinus Torvalds } 2841da177e4SLinus Torvalds 285f4263957SKenji Kaneshige /* 286f4263957SKenji Kaneshige * This function starts the interrupt polling timer. 287f4263957SKenji Kaneshige */ 2880abe68ceSKenji Kaneshige static void start_int_poll_timer(struct controller *ctrl, int sec) 2891da177e4SLinus Torvalds { 290f4263957SKenji Kaneshige /* Clamp to sane value */ 291f4263957SKenji Kaneshige if ((sec <= 0) || (sec > 60)) 292f4263957SKenji Kaneshige sec = 2; 2931da177e4SLinus Torvalds 2940abe68ceSKenji Kaneshige ctrl->poll_timer.function = &int_poll_timeout; 2950abe68ceSKenji Kaneshige ctrl->poll_timer.data = (unsigned long)ctrl; 2960abe68ceSKenji Kaneshige ctrl->poll_timer.expires = jiffies + sec * HZ; 2970abe68ceSKenji Kaneshige add_timer(&ctrl->poll_timer); 2981da177e4SLinus Torvalds } 2991da177e4SLinus Torvalds 300d1729cceSKenji Kaneshige static inline int is_ctrl_busy(struct controller *ctrl) 301d1729cceSKenji Kaneshige { 302d1729cceSKenji Kaneshige u16 cmd_status = shpc_readw(ctrl, CMD_STATUS); 303d1729cceSKenji Kaneshige return cmd_status & 0x1; 304d1729cceSKenji Kaneshige } 305d1729cceSKenji Kaneshige 306b4a1efffSKenji Kaneshige /* 307b4a1efffSKenji Kaneshige * Returns 1 if SHPC finishes executing a command within 1 sec, 308b4a1efffSKenji Kaneshige * otherwise returns 0. 309b4a1efffSKenji Kaneshige */ 310b4a1efffSKenji Kaneshige static inline int shpc_poll_ctrl_busy(struct controller *ctrl) 311b4a1efffSKenji Kaneshige { 312b4a1efffSKenji Kaneshige int i; 313b4a1efffSKenji Kaneshige 314d1729cceSKenji Kaneshige if (!is_ctrl_busy(ctrl)) 315b4a1efffSKenji Kaneshige return 1; 316b4a1efffSKenji Kaneshige 317b4a1efffSKenji Kaneshige /* Check every 0.1 sec for a total of 1 sec */ 318b4a1efffSKenji Kaneshige for (i = 0; i < 10; i++) { 319b4a1efffSKenji Kaneshige msleep(100); 320d1729cceSKenji Kaneshige if (!is_ctrl_busy(ctrl)) 321b4a1efffSKenji Kaneshige return 1; 322b4a1efffSKenji Kaneshige } 323b4a1efffSKenji Kaneshige 324b4a1efffSKenji Kaneshige return 0; 325b4a1efffSKenji Kaneshige } 326b4a1efffSKenji Kaneshige 327bd62e271SKenji Kaneshige static inline int shpc_wait_cmd(struct controller *ctrl) 328bd62e271SKenji Kaneshige { 329bd62e271SKenji Kaneshige int retval = 0; 330b4a1efffSKenji Kaneshige unsigned long timeout = msecs_to_jiffies(1000); 331b4a1efffSKenji Kaneshige int rc; 332b4a1efffSKenji Kaneshige 333b4a1efffSKenji Kaneshige if (shpchp_poll_mode) 334b4a1efffSKenji Kaneshige rc = shpc_poll_ctrl_busy(ctrl); 335b4a1efffSKenji Kaneshige else 336b4a1efffSKenji Kaneshige rc = wait_event_interruptible_timeout(ctrl->queue, 3376aa562c2SKenji Kaneshige !is_ctrl_busy(ctrl), timeout); 338d1729cceSKenji Kaneshige if (!rc && is_ctrl_busy(ctrl)) { 339bd62e271SKenji Kaneshige retval = -EIO; 340b4a1efffSKenji Kaneshige err("Command not completed in 1000 msec\n"); 341bd62e271SKenji Kaneshige } else if (rc < 0) { 342bd62e271SKenji Kaneshige retval = -EINTR; 343bd62e271SKenji Kaneshige info("Command was interrupted by a signal\n"); 344bd62e271SKenji Kaneshige } 345bd62e271SKenji Kaneshige 346bd62e271SKenji Kaneshige return retval; 347bd62e271SKenji Kaneshige } 348bd62e271SKenji Kaneshige 3491da177e4SLinus Torvalds static int shpc_write_cmd(struct slot *slot, u8 t_slot, u8 cmd) 3501da177e4SLinus Torvalds { 35175d97c59SKenji Kaneshige struct controller *ctrl = slot->ctrl; 3521da177e4SLinus Torvalds u16 cmd_status; 3531da177e4SLinus Torvalds int retval = 0; 3541da177e4SLinus Torvalds u16 temp_word; 3551da177e4SLinus Torvalds 3561da177e4SLinus Torvalds DBG_ENTER_ROUTINE 3571da177e4SLinus Torvalds 358d29aaddaSKenji Kaneshige mutex_lock(&slot->ctrl->cmd_lock); 359d29aaddaSKenji Kaneshige 360b4a1efffSKenji Kaneshige if (!shpc_poll_ctrl_busy(ctrl)) { 3611da177e4SLinus Torvalds /* After 1 sec and and the controller is still busy */ 362b4a1efffSKenji Kaneshige err("%s : Controller is still busy after 1 sec.\n", 363b4a1efffSKenji Kaneshige __FUNCTION__); 364d29aaddaSKenji Kaneshige retval = -EBUSY; 365d29aaddaSKenji Kaneshige goto out; 3661da177e4SLinus Torvalds } 3671da177e4SLinus Torvalds 3681da177e4SLinus Torvalds ++t_slot; 3691da177e4SLinus Torvalds temp_word = (t_slot << 8) | (cmd & 0xFF); 3701da177e4SLinus Torvalds dbg("%s: t_slot %x cmd %x\n", __FUNCTION__, t_slot, cmd); 3711da177e4SLinus Torvalds 3721da177e4SLinus Torvalds /* To make sure the Controller Busy bit is 0 before we send out the 3731da177e4SLinus Torvalds * command. 3741da177e4SLinus Torvalds */ 37575d97c59SKenji Kaneshige shpc_writew(ctrl, CMD, temp_word); 3761da177e4SLinus Torvalds 377bd62e271SKenji Kaneshige /* 378bd62e271SKenji Kaneshige * Wait for command completion. 379bd62e271SKenji Kaneshige */ 380bd62e271SKenji Kaneshige retval = shpc_wait_cmd(slot->ctrl); 381d29aaddaSKenji Kaneshige if (retval) 382d29aaddaSKenji Kaneshige goto out; 383d29aaddaSKenji Kaneshige 384d29aaddaSKenji Kaneshige cmd_status = hpc_check_cmd_status(slot->ctrl); 385d29aaddaSKenji Kaneshige if (cmd_status) { 386d29aaddaSKenji Kaneshige err("%s: Failed to issued command 0x%x (error code = %d)\n", 387d29aaddaSKenji Kaneshige __FUNCTION__, cmd, cmd_status); 388d29aaddaSKenji Kaneshige retval = -EIO; 389d29aaddaSKenji Kaneshige } 390d29aaddaSKenji Kaneshige out: 391d29aaddaSKenji Kaneshige mutex_unlock(&slot->ctrl->cmd_lock); 392bd62e271SKenji Kaneshige 3931da177e4SLinus Torvalds DBG_LEAVE_ROUTINE 3941da177e4SLinus Torvalds return retval; 3951da177e4SLinus Torvalds } 3961da177e4SLinus Torvalds 3971da177e4SLinus Torvalds static int hpc_check_cmd_status(struct controller *ctrl) 3981da177e4SLinus Torvalds { 3991da177e4SLinus Torvalds u16 cmd_status; 4001da177e4SLinus Torvalds int retval = 0; 4011da177e4SLinus Torvalds 4021da177e4SLinus Torvalds DBG_ENTER_ROUTINE 4031da177e4SLinus Torvalds 40475d97c59SKenji Kaneshige cmd_status = shpc_readw(ctrl, CMD_STATUS) & 0x000F; 4051da177e4SLinus Torvalds 4061da177e4SLinus Torvalds switch (cmd_status >> 1) { 4071da177e4SLinus Torvalds case 0: 4081da177e4SLinus Torvalds retval = 0; 4091da177e4SLinus Torvalds break; 4101da177e4SLinus Torvalds case 1: 4111da177e4SLinus Torvalds retval = SWITCH_OPEN; 4121da177e4SLinus Torvalds err("%s: Switch opened!\n", __FUNCTION__); 4131da177e4SLinus Torvalds break; 4141da177e4SLinus Torvalds case 2: 4151da177e4SLinus Torvalds retval = INVALID_CMD; 4161da177e4SLinus Torvalds err("%s: Invalid HPC command!\n", __FUNCTION__); 4171da177e4SLinus Torvalds break; 4181da177e4SLinus Torvalds case 4: 4191da177e4SLinus Torvalds retval = INVALID_SPEED_MODE; 4201da177e4SLinus Torvalds err("%s: Invalid bus speed/mode!\n", __FUNCTION__); 4211da177e4SLinus Torvalds break; 4221da177e4SLinus Torvalds default: 4231da177e4SLinus Torvalds retval = cmd_status; 4241da177e4SLinus Torvalds } 4251da177e4SLinus Torvalds 4261da177e4SLinus Torvalds DBG_LEAVE_ROUTINE 4271da177e4SLinus Torvalds return retval; 4281da177e4SLinus Torvalds } 4291da177e4SLinus Torvalds 4301da177e4SLinus Torvalds 4311da177e4SLinus Torvalds static int hpc_get_attention_status(struct slot *slot, u8 *status) 4321da177e4SLinus Torvalds { 43375d97c59SKenji Kaneshige struct controller *ctrl = slot->ctrl; 4341da177e4SLinus Torvalds u32 slot_reg; 4355858759cSKenji Kaneshige u8 state; 4361da177e4SLinus Torvalds 4371da177e4SLinus Torvalds DBG_ENTER_ROUTINE 4381da177e4SLinus Torvalds 4392b34da7eSKenji Kaneshige slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); 4405858759cSKenji Kaneshige state = (slot_reg & ATN_LED_STATE_MASK) >> ATN_LED_STATE_SHIFT; 4411da177e4SLinus Torvalds 4425858759cSKenji Kaneshige switch (state) { 4435858759cSKenji Kaneshige case ATN_LED_STATE_ON: 4441da177e4SLinus Torvalds *status = 1; /* On */ 4451da177e4SLinus Torvalds break; 4465858759cSKenji Kaneshige case ATN_LED_STATE_BLINK: 4471da177e4SLinus Torvalds *status = 2; /* Blink */ 4481da177e4SLinus Torvalds break; 4495858759cSKenji Kaneshige case ATN_LED_STATE_OFF: 4501da177e4SLinus Torvalds *status = 0; /* Off */ 4511da177e4SLinus Torvalds break; 4521da177e4SLinus Torvalds default: 4535858759cSKenji Kaneshige *status = 0xFF; /* Reserved */ 4541da177e4SLinus Torvalds break; 4551da177e4SLinus Torvalds } 4561da177e4SLinus Torvalds 4571da177e4SLinus Torvalds DBG_LEAVE_ROUTINE 4581da177e4SLinus Torvalds return 0; 4591da177e4SLinus Torvalds } 4601da177e4SLinus Torvalds 4611da177e4SLinus Torvalds static int hpc_get_power_status(struct slot * slot, u8 *status) 4621da177e4SLinus Torvalds { 46375d97c59SKenji Kaneshige struct controller *ctrl = slot->ctrl; 4641da177e4SLinus Torvalds u32 slot_reg; 4655858759cSKenji Kaneshige u8 state; 4661da177e4SLinus Torvalds 4671da177e4SLinus Torvalds DBG_ENTER_ROUTINE 4681da177e4SLinus Torvalds 4692b34da7eSKenji Kaneshige slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); 4705858759cSKenji Kaneshige state = (slot_reg & SLOT_STATE_MASK) >> SLOT_STATE_SHIFT; 4711da177e4SLinus Torvalds 4725858759cSKenji Kaneshige switch (state) { 4735858759cSKenji Kaneshige case SLOT_STATE_PWRONLY: 4741da177e4SLinus Torvalds *status = 2; /* Powered only */ 4751da177e4SLinus Torvalds break; 4765858759cSKenji Kaneshige case SLOT_STATE_ENABLED: 4771da177e4SLinus Torvalds *status = 1; /* Enabled */ 4781da177e4SLinus Torvalds break; 4795858759cSKenji Kaneshige case SLOT_STATE_DISABLED: 4801da177e4SLinus Torvalds *status = 0; /* Disabled */ 4811da177e4SLinus Torvalds break; 4821da177e4SLinus Torvalds default: 4835858759cSKenji Kaneshige *status = 0xFF; /* Reserved */ 4841da177e4SLinus Torvalds break; 4851da177e4SLinus Torvalds } 4861da177e4SLinus Torvalds 4871da177e4SLinus Torvalds DBG_LEAVE_ROUTINE 4885858759cSKenji Kaneshige return 0; 4891da177e4SLinus Torvalds } 4901da177e4SLinus Torvalds 4911da177e4SLinus Torvalds 4921da177e4SLinus Torvalds static int hpc_get_latch_status(struct slot *slot, u8 *status) 4931da177e4SLinus Torvalds { 49475d97c59SKenji Kaneshige struct controller *ctrl = slot->ctrl; 4951da177e4SLinus Torvalds u32 slot_reg; 4961da177e4SLinus Torvalds 4971da177e4SLinus Torvalds DBG_ENTER_ROUTINE 4981da177e4SLinus Torvalds 4992b34da7eSKenji Kaneshige slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); 5005858759cSKenji Kaneshige *status = !!(slot_reg & MRL_SENSOR); /* 0 -> close; 1 -> open */ 5011da177e4SLinus Torvalds 5021da177e4SLinus Torvalds DBG_LEAVE_ROUTINE 5031da177e4SLinus Torvalds return 0; 5041da177e4SLinus Torvalds } 5051da177e4SLinus Torvalds 5061da177e4SLinus Torvalds static int hpc_get_adapter_status(struct slot *slot, u8 *status) 5071da177e4SLinus Torvalds { 50875d97c59SKenji Kaneshige struct controller *ctrl = slot->ctrl; 5091da177e4SLinus Torvalds u32 slot_reg; 5105858759cSKenji Kaneshige u8 state; 5111da177e4SLinus Torvalds 5121da177e4SLinus Torvalds DBG_ENTER_ROUTINE 5131da177e4SLinus Torvalds 5142b34da7eSKenji Kaneshige slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); 5155858759cSKenji Kaneshige state = (slot_reg & PRSNT_MASK) >> PRSNT_SHIFT; 5165858759cSKenji Kaneshige *status = (state != 0x3) ? 1 : 0; 5171da177e4SLinus Torvalds 5181da177e4SLinus Torvalds DBG_LEAVE_ROUTINE 5191da177e4SLinus Torvalds return 0; 5201da177e4SLinus Torvalds } 5211da177e4SLinus Torvalds 5221da177e4SLinus Torvalds static int hpc_get_prog_int(struct slot *slot, u8 *prog_int) 5231da177e4SLinus Torvalds { 52475d97c59SKenji Kaneshige struct controller *ctrl = slot->ctrl; 5251da177e4SLinus Torvalds 5261da177e4SLinus Torvalds DBG_ENTER_ROUTINE 5271da177e4SLinus Torvalds 52875d97c59SKenji Kaneshige *prog_int = shpc_readb(ctrl, PROG_INTERFACE); 5291da177e4SLinus Torvalds 5301da177e4SLinus Torvalds DBG_LEAVE_ROUTINE 5311da177e4SLinus Torvalds return 0; 5321da177e4SLinus Torvalds } 5331da177e4SLinus Torvalds 5341da177e4SLinus Torvalds static int hpc_get_adapter_speed(struct slot *slot, enum pci_bus_speed *value) 5351da177e4SLinus Torvalds { 5361da177e4SLinus Torvalds int retval = 0; 53775d97c59SKenji Kaneshige struct controller *ctrl = slot->ctrl; 5382b34da7eSKenji Kaneshige u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); 5395858759cSKenji Kaneshige u8 m66_cap = !!(slot_reg & MHZ66_CAP); 540795eb5c4SKenji Kaneshige u8 pi, pcix_cap; 5411da177e4SLinus Torvalds 5421da177e4SLinus Torvalds DBG_ENTER_ROUTINE 5431da177e4SLinus Torvalds 544795eb5c4SKenji Kaneshige if ((retval = hpc_get_prog_int(slot, &pi))) 545795eb5c4SKenji Kaneshige return retval; 546795eb5c4SKenji Kaneshige 547795eb5c4SKenji Kaneshige switch (pi) { 548795eb5c4SKenji Kaneshige case 1: 549795eb5c4SKenji Kaneshige pcix_cap = (slot_reg & PCIX_CAP_MASK_PI1) >> PCIX_CAP_SHIFT; 550795eb5c4SKenji Kaneshige break; 551795eb5c4SKenji Kaneshige case 2: 552795eb5c4SKenji Kaneshige pcix_cap = (slot_reg & PCIX_CAP_MASK_PI2) >> PCIX_CAP_SHIFT; 553795eb5c4SKenji Kaneshige break; 554795eb5c4SKenji Kaneshige default: 555795eb5c4SKenji Kaneshige return -ENODEV; 556795eb5c4SKenji Kaneshige } 557795eb5c4SKenji Kaneshige 5580afabe90SKenji Kaneshige dbg("%s: slot_reg = %x, pcix_cap = %x, m66_cap = %x\n", 5590afabe90SKenji Kaneshige __FUNCTION__, slot_reg, pcix_cap, m66_cap); 5601da177e4SLinus Torvalds 5611da177e4SLinus Torvalds switch (pcix_cap) { 5620afabe90SKenji Kaneshige case 0x0: 5631da177e4SLinus Torvalds *value = m66_cap ? PCI_SPEED_66MHz : PCI_SPEED_33MHz; 5641da177e4SLinus Torvalds break; 5650afabe90SKenji Kaneshige case 0x1: 5661da177e4SLinus Torvalds *value = PCI_SPEED_66MHz_PCIX; 5671da177e4SLinus Torvalds break; 5680afabe90SKenji Kaneshige case 0x3: 5691da177e4SLinus Torvalds *value = PCI_SPEED_133MHz_PCIX; 5701da177e4SLinus Torvalds break; 5710afabe90SKenji Kaneshige case 0x4: 5721da177e4SLinus Torvalds *value = PCI_SPEED_133MHz_PCIX_266; 5731da177e4SLinus Torvalds break; 5740afabe90SKenji Kaneshige case 0x5: 5751da177e4SLinus Torvalds *value = PCI_SPEED_133MHz_PCIX_533; 5761da177e4SLinus Torvalds break; 5770afabe90SKenji Kaneshige case 0x2: 5781da177e4SLinus Torvalds default: 5791da177e4SLinus Torvalds *value = PCI_SPEED_UNKNOWN; 5801da177e4SLinus Torvalds retval = -ENODEV; 5811da177e4SLinus Torvalds break; 5821da177e4SLinus Torvalds } 5831da177e4SLinus Torvalds 5841da177e4SLinus Torvalds dbg("Adapter speed = %d\n", *value); 5851da177e4SLinus Torvalds DBG_LEAVE_ROUTINE 5861da177e4SLinus Torvalds return retval; 5871da177e4SLinus Torvalds } 5881da177e4SLinus Torvalds 5891da177e4SLinus Torvalds static int hpc_get_mode1_ECC_cap(struct slot *slot, u8 *mode) 5901da177e4SLinus Torvalds { 59175d97c59SKenji Kaneshige struct controller *ctrl = slot->ctrl; 5921da177e4SLinus Torvalds u16 sec_bus_status; 5931da177e4SLinus Torvalds u8 pi; 5941da177e4SLinus Torvalds int retval = 0; 5951da177e4SLinus Torvalds 5961da177e4SLinus Torvalds DBG_ENTER_ROUTINE 5971da177e4SLinus Torvalds 59875d97c59SKenji Kaneshige pi = shpc_readb(ctrl, PROG_INTERFACE); 59975d97c59SKenji Kaneshige sec_bus_status = shpc_readw(ctrl, SEC_BUS_CONFIG); 6001da177e4SLinus Torvalds 6011da177e4SLinus Torvalds if (pi == 2) { 60287d6c559SKenji Kaneshige *mode = (sec_bus_status & 0x0100) >> 8; 6031da177e4SLinus Torvalds } else { 6041da177e4SLinus Torvalds retval = -1; 6051da177e4SLinus Torvalds } 6061da177e4SLinus Torvalds 6071da177e4SLinus Torvalds dbg("Mode 1 ECC cap = %d\n", *mode); 6081da177e4SLinus Torvalds 6091da177e4SLinus Torvalds DBG_LEAVE_ROUTINE 6101da177e4SLinus Torvalds return retval; 6111da177e4SLinus Torvalds } 6121da177e4SLinus Torvalds 6131da177e4SLinus Torvalds static int hpc_query_power_fault(struct slot * slot) 6141da177e4SLinus Torvalds { 61575d97c59SKenji Kaneshige struct controller *ctrl = slot->ctrl; 6161da177e4SLinus Torvalds u32 slot_reg; 6171da177e4SLinus Torvalds 6181da177e4SLinus Torvalds DBG_ENTER_ROUTINE 6191da177e4SLinus Torvalds 6202b34da7eSKenji Kaneshige slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); 6211da177e4SLinus Torvalds 6221da177e4SLinus Torvalds DBG_LEAVE_ROUTINE 6231da177e4SLinus Torvalds /* Note: Logic 0 => fault */ 6245858759cSKenji Kaneshige return !(slot_reg & POWER_FAULT); 6251da177e4SLinus Torvalds } 6261da177e4SLinus Torvalds 6271da177e4SLinus Torvalds static int hpc_set_attention_status(struct slot *slot, u8 value) 6281da177e4SLinus Torvalds { 6291da177e4SLinus Torvalds u8 slot_cmd = 0; 6301da177e4SLinus Torvalds 6311da177e4SLinus Torvalds switch (value) { 6321da177e4SLinus Torvalds case 0 : 6334085399dSKenji Kaneshige slot_cmd = SET_ATTN_OFF; /* OFF */ 6341da177e4SLinus Torvalds break; 6351da177e4SLinus Torvalds case 1: 6364085399dSKenji Kaneshige slot_cmd = SET_ATTN_ON; /* ON */ 6371da177e4SLinus Torvalds break; 6381da177e4SLinus Torvalds case 2: 6394085399dSKenji Kaneshige slot_cmd = SET_ATTN_BLINK; /* BLINK */ 6401da177e4SLinus Torvalds break; 6411da177e4SLinus Torvalds default: 6421da177e4SLinus Torvalds return -1; 6431da177e4SLinus Torvalds } 6441da177e4SLinus Torvalds 645d4fbf600SKenji Kaneshige return shpc_write_cmd(slot, slot->hp_slot, slot_cmd); 6461da177e4SLinus Torvalds } 6471da177e4SLinus Torvalds 6481da177e4SLinus Torvalds 6491da177e4SLinus Torvalds static void hpc_set_green_led_on(struct slot *slot) 6501da177e4SLinus Torvalds { 6514085399dSKenji Kaneshige shpc_write_cmd(slot, slot->hp_slot, SET_PWR_ON); 6521da177e4SLinus Torvalds } 6531da177e4SLinus Torvalds 6541da177e4SLinus Torvalds static void hpc_set_green_led_off(struct slot *slot) 6551da177e4SLinus Torvalds { 6564085399dSKenji Kaneshige shpc_write_cmd(slot, slot->hp_slot, SET_PWR_OFF); 6571da177e4SLinus Torvalds } 6581da177e4SLinus Torvalds 6591da177e4SLinus Torvalds static void hpc_set_green_led_blink(struct slot *slot) 6601da177e4SLinus Torvalds { 6614085399dSKenji Kaneshige shpc_write_cmd(slot, slot->hp_slot, SET_PWR_BLINK); 6621da177e4SLinus Torvalds } 6631da177e4SLinus Torvalds 6641da177e4SLinus Torvalds static void hpc_release_ctlr(struct controller *ctrl) 6651da177e4SLinus Torvalds { 666f7391f53SKenji Kaneshige int i; 667d49f2c49SKenji Kaneshige u32 slot_reg, serr_int; 6681da177e4SLinus Torvalds 6691da177e4SLinus Torvalds DBG_ENTER_ROUTINE 6701da177e4SLinus Torvalds 671f7391f53SKenji Kaneshige /* 672795eb5c4SKenji Kaneshige * Mask event interrupts and SERRs of all slots 673f7391f53SKenji Kaneshige */ 674795eb5c4SKenji Kaneshige for (i = 0; i < ctrl->num_slots; i++) { 675795eb5c4SKenji Kaneshige slot_reg = shpc_readl(ctrl, SLOT_REG(i)); 676795eb5c4SKenji Kaneshige slot_reg |= (PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK | 677795eb5c4SKenji Kaneshige BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK | 678795eb5c4SKenji Kaneshige CON_PFAULT_INTR_MASK | MRL_CHANGE_SERR_MASK | 679795eb5c4SKenji Kaneshige CON_PFAULT_SERR_MASK); 680795eb5c4SKenji Kaneshige slot_reg &= ~SLOT_REG_RSVDZ_MASK; 681795eb5c4SKenji Kaneshige shpc_writel(ctrl, SLOT_REG(i), slot_reg); 682795eb5c4SKenji Kaneshige } 683f7391f53SKenji Kaneshige 684f7391f53SKenji Kaneshige cleanup_slots(ctrl); 685f7391f53SKenji Kaneshige 686d49f2c49SKenji Kaneshige /* 687d49f2c49SKenji Kaneshige * Mask SERR and System Interrut generation 688d49f2c49SKenji Kaneshige */ 689d49f2c49SKenji Kaneshige serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE); 690d49f2c49SKenji Kaneshige serr_int |= (GLOBAL_INTR_MASK | GLOBAL_SERR_MASK | 691d49f2c49SKenji Kaneshige COMMAND_INTR_MASK | ARBITER_SERR_MASK); 692d49f2c49SKenji Kaneshige serr_int &= ~SERR_INTR_RSVDZ_MASK; 693d49f2c49SKenji Kaneshige shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int); 694d49f2c49SKenji Kaneshige 6950abe68ceSKenji Kaneshige if (shpchp_poll_mode) 6960abe68ceSKenji Kaneshige del_timer(&ctrl->poll_timer); 6970abe68ceSKenji Kaneshige else { 6980abe68ceSKenji Kaneshige free_irq(ctrl->pci_dev->irq, ctrl); 6990abe68ceSKenji Kaneshige pci_disable_msi(ctrl->pci_dev); 7001da177e4SLinus Torvalds } 701f7391f53SKenji Kaneshige 7020abe68ceSKenji Kaneshige iounmap(ctrl->creg); 7030455986cSKenji Kaneshige release_mem_region(ctrl->mmio_base, ctrl->mmio_size); 7041da177e4SLinus Torvalds 70582d5f4aaSKenji Kaneshige /* 70682d5f4aaSKenji Kaneshige * If this is the last controller to be released, destroy the 70782d5f4aaSKenji Kaneshige * shpchpd work queue 70882d5f4aaSKenji Kaneshige */ 70982d5f4aaSKenji Kaneshige if (atomic_dec_and_test(&shpchp_num_controllers)) 71082d5f4aaSKenji Kaneshige destroy_workqueue(shpchp_wq); 71182d5f4aaSKenji Kaneshige 7121da177e4SLinus Torvalds DBG_LEAVE_ROUTINE 7131da177e4SLinus Torvalds } 7141da177e4SLinus Torvalds 7151da177e4SLinus Torvalds static int hpc_power_on_slot(struct slot * slot) 7161da177e4SLinus Torvalds { 717d4fbf600SKenji Kaneshige int retval; 7181da177e4SLinus Torvalds 7191da177e4SLinus Torvalds DBG_ENTER_ROUTINE 7201da177e4SLinus Torvalds 7214085399dSKenji Kaneshige retval = shpc_write_cmd(slot, slot->hp_slot, SET_SLOT_PWR); 7221da177e4SLinus Torvalds if (retval) { 7231da177e4SLinus Torvalds err("%s: Write command failed!\n", __FUNCTION__); 724d4fbf600SKenji Kaneshige return retval; 7251da177e4SLinus Torvalds } 7261da177e4SLinus Torvalds 7271da177e4SLinus Torvalds DBG_LEAVE_ROUTINE 7281da177e4SLinus Torvalds 729d4fbf600SKenji Kaneshige return 0; 7301da177e4SLinus Torvalds } 7311da177e4SLinus Torvalds 7321da177e4SLinus Torvalds static int hpc_slot_enable(struct slot * slot) 7331da177e4SLinus Torvalds { 734d4fbf600SKenji Kaneshige int retval; 7351da177e4SLinus Torvalds 7361da177e4SLinus Torvalds DBG_ENTER_ROUTINE 7371da177e4SLinus Torvalds 7384085399dSKenji Kaneshige /* Slot - Enable, Power Indicator - Blink, Attention Indicator - Off */ 7394085399dSKenji Kaneshige retval = shpc_write_cmd(slot, slot->hp_slot, 7404085399dSKenji Kaneshige SET_SLOT_ENABLE | SET_PWR_BLINK | SET_ATTN_OFF); 7411da177e4SLinus Torvalds if (retval) { 7421da177e4SLinus Torvalds err("%s: Write command failed!\n", __FUNCTION__); 743d4fbf600SKenji Kaneshige return retval; 7441da177e4SLinus Torvalds } 7451da177e4SLinus Torvalds 7461da177e4SLinus Torvalds DBG_LEAVE_ROUTINE 747d4fbf600SKenji Kaneshige return 0; 7481da177e4SLinus Torvalds } 7491da177e4SLinus Torvalds 7501da177e4SLinus Torvalds static int hpc_slot_disable(struct slot * slot) 7511da177e4SLinus Torvalds { 752d4fbf600SKenji Kaneshige int retval; 7531da177e4SLinus Torvalds 7541da177e4SLinus Torvalds DBG_ENTER_ROUTINE 7551da177e4SLinus Torvalds 7564085399dSKenji Kaneshige /* Slot - Disable, Power Indicator - Off, Attention Indicator - On */ 7574085399dSKenji Kaneshige retval = shpc_write_cmd(slot, slot->hp_slot, 7584085399dSKenji Kaneshige SET_SLOT_DISABLE | SET_PWR_OFF | SET_ATTN_ON); 7591da177e4SLinus Torvalds if (retval) { 7601da177e4SLinus Torvalds err("%s: Write command failed!\n", __FUNCTION__); 761d4fbf600SKenji Kaneshige return retval; 7621da177e4SLinus Torvalds } 7631da177e4SLinus Torvalds 7641da177e4SLinus Torvalds DBG_LEAVE_ROUTINE 765d4fbf600SKenji Kaneshige return 0; 7661da177e4SLinus Torvalds } 7671da177e4SLinus Torvalds 7681da177e4SLinus Torvalds static int hpc_set_bus_speed_mode(struct slot * slot, enum pci_bus_speed value) 7691da177e4SLinus Torvalds { 7700afabe90SKenji Kaneshige int retval; 77175d97c59SKenji Kaneshige struct controller *ctrl = slot->ctrl; 7720afabe90SKenji Kaneshige u8 pi, cmd; 7731da177e4SLinus Torvalds 7741da177e4SLinus Torvalds DBG_ENTER_ROUTINE 7751da177e4SLinus Torvalds 77675d97c59SKenji Kaneshige pi = shpc_readb(ctrl, PROG_INTERFACE); 7770afabe90SKenji Kaneshige if ((pi == 1) && (value > PCI_SPEED_133MHz_PCIX)) 7780afabe90SKenji Kaneshige return -EINVAL; 7791da177e4SLinus Torvalds 7801da177e4SLinus Torvalds switch (value) { 7810afabe90SKenji Kaneshige case PCI_SPEED_33MHz: 7820afabe90SKenji Kaneshige cmd = SETA_PCI_33MHZ; 7831da177e4SLinus Torvalds break; 7840afabe90SKenji Kaneshige case PCI_SPEED_66MHz: 7850afabe90SKenji Kaneshige cmd = SETA_PCI_66MHZ; 7861da177e4SLinus Torvalds break; 7870afabe90SKenji Kaneshige case PCI_SPEED_66MHz_PCIX: 7880afabe90SKenji Kaneshige cmd = SETA_PCIX_66MHZ; 7891da177e4SLinus Torvalds break; 7900afabe90SKenji Kaneshige case PCI_SPEED_100MHz_PCIX: 7910afabe90SKenji Kaneshige cmd = SETA_PCIX_100MHZ; 7921da177e4SLinus Torvalds break; 7930afabe90SKenji Kaneshige case PCI_SPEED_133MHz_PCIX: 7940afabe90SKenji Kaneshige cmd = SETA_PCIX_133MHZ; 7950afabe90SKenji Kaneshige break; 7960afabe90SKenji Kaneshige case PCI_SPEED_66MHz_PCIX_ECC: 7970afabe90SKenji Kaneshige cmd = SETB_PCIX_66MHZ_EM; 7980afabe90SKenji Kaneshige break; 7990afabe90SKenji Kaneshige case PCI_SPEED_100MHz_PCIX_ECC: 8000afabe90SKenji Kaneshige cmd = SETB_PCIX_100MHZ_EM; 8010afabe90SKenji Kaneshige break; 8020afabe90SKenji Kaneshige case PCI_SPEED_133MHz_PCIX_ECC: 8030afabe90SKenji Kaneshige cmd = SETB_PCIX_133MHZ_EM; 8040afabe90SKenji Kaneshige break; 8050afabe90SKenji Kaneshige case PCI_SPEED_66MHz_PCIX_266: 8060afabe90SKenji Kaneshige cmd = SETB_PCIX_66MHZ_266; 8070afabe90SKenji Kaneshige break; 8080afabe90SKenji Kaneshige case PCI_SPEED_100MHz_PCIX_266: 8090afabe90SKenji Kaneshige cmd = SETB_PCIX_100MHZ_266; 8100afabe90SKenji Kaneshige break; 8110afabe90SKenji Kaneshige case PCI_SPEED_133MHz_PCIX_266: 8120afabe90SKenji Kaneshige cmd = SETB_PCIX_133MHZ_266; 8130afabe90SKenji Kaneshige break; 8140afabe90SKenji Kaneshige case PCI_SPEED_66MHz_PCIX_533: 8150afabe90SKenji Kaneshige cmd = SETB_PCIX_66MHZ_533; 8160afabe90SKenji Kaneshige break; 8170afabe90SKenji Kaneshige case PCI_SPEED_100MHz_PCIX_533: 8180afabe90SKenji Kaneshige cmd = SETB_PCIX_100MHZ_533; 8190afabe90SKenji Kaneshige break; 8200afabe90SKenji Kaneshige case PCI_SPEED_133MHz_PCIX_533: 8210afabe90SKenji Kaneshige cmd = SETB_PCIX_133MHZ_533; 8221da177e4SLinus Torvalds break; 8231da177e4SLinus Torvalds default: 8240afabe90SKenji Kaneshige return -EINVAL; 8251da177e4SLinus Torvalds } 8261da177e4SLinus Torvalds 8270afabe90SKenji Kaneshige retval = shpc_write_cmd(slot, 0, cmd); 8280afabe90SKenji Kaneshige if (retval) 8291da177e4SLinus Torvalds err("%s: Write command failed!\n", __FUNCTION__); 8301da177e4SLinus Torvalds 8311da177e4SLinus Torvalds DBG_LEAVE_ROUTINE 8321da177e4SLinus Torvalds return retval; 8331da177e4SLinus Torvalds } 8341da177e4SLinus Torvalds 8357d12e780SDavid Howells static irqreturn_t shpc_isr(int irq, void *dev_id) 8361da177e4SLinus Torvalds { 837c4cecc19SKenji Kaneshige struct controller *ctrl = (struct controller *)dev_id; 838c4cecc19SKenji Kaneshige u32 serr_int, slot_reg, intr_loc, intr_loc2; 8391da177e4SLinus Torvalds int hp_slot; 8401da177e4SLinus Torvalds 8411da177e4SLinus Torvalds /* Check to see if it was our interrupt */ 84275d97c59SKenji Kaneshige intr_loc = shpc_readl(ctrl, INTR_LOC); 8431da177e4SLinus Torvalds if (!intr_loc) 8441da177e4SLinus Torvalds return IRQ_NONE; 845c4cecc19SKenji Kaneshige 8461da177e4SLinus Torvalds dbg("%s: intr_loc = %x\n",__FUNCTION__, intr_loc); 8471da177e4SLinus Torvalds 8481da177e4SLinus Torvalds if(!shpchp_poll_mode) { 849c4cecc19SKenji Kaneshige /* 850c4cecc19SKenji Kaneshige * Mask Global Interrupt Mask - see implementation 851c4cecc19SKenji Kaneshige * note on p. 139 of SHPC spec rev 1.0 852c4cecc19SKenji Kaneshige */ 853c4cecc19SKenji Kaneshige serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE); 854c4cecc19SKenji Kaneshige serr_int |= GLOBAL_INTR_MASK; 855c4cecc19SKenji Kaneshige serr_int &= ~SERR_INTR_RSVDZ_MASK; 856c4cecc19SKenji Kaneshige shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int); 8571da177e4SLinus Torvalds 85875d97c59SKenji Kaneshige intr_loc2 = shpc_readl(ctrl, INTR_LOC); 8591da177e4SLinus Torvalds dbg("%s: intr_loc2 = %x\n",__FUNCTION__, intr_loc2); 8601da177e4SLinus Torvalds } 8611da177e4SLinus Torvalds 862c4cecc19SKenji Kaneshige if (intr_loc & CMD_INTR_PENDING) { 8631da177e4SLinus Torvalds /* 8641da177e4SLinus Torvalds * Command Complete Interrupt Pending 865f467f618SKenji Kaneshige * RO only - clear by writing 1 to the Command Completion 8661da177e4SLinus Torvalds * Detect bit in Controller SERR-INT register 8671da177e4SLinus Torvalds */ 868c4cecc19SKenji Kaneshige serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE); 869c4cecc19SKenji Kaneshige serr_int &= ~SERR_INTR_RSVDZ_MASK; 870c4cecc19SKenji Kaneshige shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int); 871c4cecc19SKenji Kaneshige 8721da177e4SLinus Torvalds wake_up_interruptible(&ctrl->queue); 8731da177e4SLinus Torvalds } 8741da177e4SLinus Torvalds 875c4cecc19SKenji Kaneshige if (!(intr_loc & ~CMD_INTR_PENDING)) 876e4e73041SKenji Kaneshige goto out; 8771da177e4SLinus Torvalds 8781da177e4SLinus Torvalds for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) { 8791da177e4SLinus Torvalds /* To find out which slot has interrupt pending */ 880c4cecc19SKenji Kaneshige if (!(intr_loc & SLOT_INTR_PENDING(hp_slot))) 881c4cecc19SKenji Kaneshige continue; 882c4cecc19SKenji Kaneshige 883c4cecc19SKenji Kaneshige slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot)); 8847c8942f9Srajesh.shah@intel.com dbg("%s: Slot %x with intr, slot register = %x\n", 885c4cecc19SKenji Kaneshige __FUNCTION__, hp_slot, slot_reg); 886c4cecc19SKenji Kaneshige 887c4cecc19SKenji Kaneshige if (slot_reg & MRL_CHANGE_DETECTED) 8880abe68ceSKenji Kaneshige shpchp_handle_switch_change(hp_slot, ctrl); 889c4cecc19SKenji Kaneshige 890c4cecc19SKenji Kaneshige if (slot_reg & BUTTON_PRESS_DETECTED) 8910abe68ceSKenji Kaneshige shpchp_handle_attention_button(hp_slot, ctrl); 892c4cecc19SKenji Kaneshige 893c4cecc19SKenji Kaneshige if (slot_reg & PRSNT_CHANGE_DETECTED) 8940abe68ceSKenji Kaneshige shpchp_handle_presence_change(hp_slot, ctrl); 895c4cecc19SKenji Kaneshige 896c4cecc19SKenji Kaneshige if (slot_reg & (ISO_PFAULT_DETECTED | CON_PFAULT_DETECTED)) 8970abe68ceSKenji Kaneshige shpchp_handle_power_fault(hp_slot, ctrl); 8981da177e4SLinus Torvalds 8991da177e4SLinus Torvalds /* Clear all slot events */ 900c4cecc19SKenji Kaneshige slot_reg &= ~SLOT_REG_RSVDZ_MASK; 901c4cecc19SKenji Kaneshige shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg); 9021da177e4SLinus Torvalds } 903e4e73041SKenji Kaneshige out: 9041da177e4SLinus Torvalds if (!shpchp_poll_mode) { 9051da177e4SLinus Torvalds /* Unmask Global Interrupt Mask */ 906c4cecc19SKenji Kaneshige serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE); 907c4cecc19SKenji Kaneshige serr_int &= ~(GLOBAL_INTR_MASK | SERR_INTR_RSVDZ_MASK); 908c4cecc19SKenji Kaneshige shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int); 9091da177e4SLinus Torvalds } 9101da177e4SLinus Torvalds 9111da177e4SLinus Torvalds return IRQ_HANDLED; 9121da177e4SLinus Torvalds } 9131da177e4SLinus Torvalds 9141da177e4SLinus Torvalds static int hpc_get_max_bus_speed (struct slot *slot, enum pci_bus_speed *value) 9151da177e4SLinus Torvalds { 9160afabe90SKenji Kaneshige int retval = 0; 91775d97c59SKenji Kaneshige struct controller *ctrl = slot->ctrl; 9181da177e4SLinus Torvalds enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN; 91975d97c59SKenji Kaneshige u8 pi = shpc_readb(ctrl, PROG_INTERFACE); 92075d97c59SKenji Kaneshige u32 slot_avail1 = shpc_readl(ctrl, SLOT_AVAIL1); 92175d97c59SKenji Kaneshige u32 slot_avail2 = shpc_readl(ctrl, SLOT_AVAIL2); 9221da177e4SLinus Torvalds 9231da177e4SLinus Torvalds DBG_ENTER_ROUTINE 9241da177e4SLinus Torvalds 9251da177e4SLinus Torvalds if (pi == 2) { 9266558b6abSKenji Kaneshige if (slot_avail2 & SLOT_133MHZ_PCIX_533) 9270afabe90SKenji Kaneshige bus_speed = PCI_SPEED_133MHz_PCIX_533; 9286558b6abSKenji Kaneshige else if (slot_avail2 & SLOT_100MHZ_PCIX_533) 9290afabe90SKenji Kaneshige bus_speed = PCI_SPEED_100MHz_PCIX_533; 9306558b6abSKenji Kaneshige else if (slot_avail2 & SLOT_66MHZ_PCIX_533) 9310afabe90SKenji Kaneshige bus_speed = PCI_SPEED_66MHz_PCIX_533; 9326558b6abSKenji Kaneshige else if (slot_avail2 & SLOT_133MHZ_PCIX_266) 9330afabe90SKenji Kaneshige bus_speed = PCI_SPEED_133MHz_PCIX_266; 9346558b6abSKenji Kaneshige else if (slot_avail2 & SLOT_100MHZ_PCIX_266) 9350afabe90SKenji Kaneshige bus_speed = PCI_SPEED_100MHz_PCIX_266; 9366558b6abSKenji Kaneshige else if (slot_avail2 & SLOT_66MHZ_PCIX_266) 9370afabe90SKenji Kaneshige bus_speed = PCI_SPEED_66MHz_PCIX_266; 9380afabe90SKenji Kaneshige } 9390afabe90SKenji Kaneshige 9400afabe90SKenji Kaneshige if (bus_speed == PCI_SPEED_UNKNOWN) { 9416558b6abSKenji Kaneshige if (slot_avail1 & SLOT_133MHZ_PCIX) 9420afabe90SKenji Kaneshige bus_speed = PCI_SPEED_133MHz_PCIX; 9436558b6abSKenji Kaneshige else if (slot_avail1 & SLOT_100MHZ_PCIX) 9440afabe90SKenji Kaneshige bus_speed = PCI_SPEED_100MHz_PCIX; 9456558b6abSKenji Kaneshige else if (slot_avail1 & SLOT_66MHZ_PCIX) 9460afabe90SKenji Kaneshige bus_speed = PCI_SPEED_66MHz_PCIX; 9476558b6abSKenji Kaneshige else if (slot_avail2 & SLOT_66MHZ) 9480afabe90SKenji Kaneshige bus_speed = PCI_SPEED_66MHz; 9496558b6abSKenji Kaneshige else if (slot_avail1 & SLOT_33MHZ) 9500afabe90SKenji Kaneshige bus_speed = PCI_SPEED_33MHz; 9510afabe90SKenji Kaneshige else 9520afabe90SKenji Kaneshige retval = -ENODEV; 9531da177e4SLinus Torvalds } 9541da177e4SLinus Torvalds 9551da177e4SLinus Torvalds *value = bus_speed; 9561da177e4SLinus Torvalds dbg("Max bus speed = %d\n", bus_speed); 9571da177e4SLinus Torvalds DBG_LEAVE_ROUTINE 9581da177e4SLinus Torvalds return retval; 9591da177e4SLinus Torvalds } 9601da177e4SLinus Torvalds 9611da177e4SLinus Torvalds static int hpc_get_cur_bus_speed (struct slot *slot, enum pci_bus_speed *value) 9621da177e4SLinus Torvalds { 9630afabe90SKenji Kaneshige int retval = 0; 96475d97c59SKenji Kaneshige struct controller *ctrl = slot->ctrl; 9651da177e4SLinus Torvalds enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN; 96675d97c59SKenji Kaneshige u16 sec_bus_reg = shpc_readw(ctrl, SEC_BUS_CONFIG); 96775d97c59SKenji Kaneshige u8 pi = shpc_readb(ctrl, PROG_INTERFACE); 9680afabe90SKenji Kaneshige u8 speed_mode = (pi == 2) ? (sec_bus_reg & 0xF) : (sec_bus_reg & 0x7); 9691da177e4SLinus Torvalds 9701da177e4SLinus Torvalds DBG_ENTER_ROUTINE 9711da177e4SLinus Torvalds 9720afabe90SKenji Kaneshige if ((pi == 1) && (speed_mode > 4)) { 9730afabe90SKenji Kaneshige *value = PCI_SPEED_UNKNOWN; 9740afabe90SKenji Kaneshige return -ENODEV; 9751da177e4SLinus Torvalds } 9761da177e4SLinus Torvalds 9770afabe90SKenji Kaneshige switch (speed_mode) { 9780afabe90SKenji Kaneshige case 0x0: 9790afabe90SKenji Kaneshige *value = PCI_SPEED_33MHz; 9801da177e4SLinus Torvalds break; 9810afabe90SKenji Kaneshige case 0x1: 9820afabe90SKenji Kaneshige *value = PCI_SPEED_66MHz; 9831da177e4SLinus Torvalds break; 9840afabe90SKenji Kaneshige case 0x2: 9850afabe90SKenji Kaneshige *value = PCI_SPEED_66MHz_PCIX; 9861da177e4SLinus Torvalds break; 9870afabe90SKenji Kaneshige case 0x3: 9880afabe90SKenji Kaneshige *value = PCI_SPEED_100MHz_PCIX; 9891da177e4SLinus Torvalds break; 9900afabe90SKenji Kaneshige case 0x4: 9910afabe90SKenji Kaneshige *value = PCI_SPEED_133MHz_PCIX; 9921da177e4SLinus Torvalds break; 9930afabe90SKenji Kaneshige case 0x5: 9940afabe90SKenji Kaneshige *value = PCI_SPEED_66MHz_PCIX_ECC; 9951da177e4SLinus Torvalds break; 9960afabe90SKenji Kaneshige case 0x6: 9970afabe90SKenji Kaneshige *value = PCI_SPEED_100MHz_PCIX_ECC; 9981da177e4SLinus Torvalds break; 9990afabe90SKenji Kaneshige case 0x7: 10000afabe90SKenji Kaneshige *value = PCI_SPEED_133MHz_PCIX_ECC; 10011da177e4SLinus Torvalds break; 10020afabe90SKenji Kaneshige case 0x8: 10030afabe90SKenji Kaneshige *value = PCI_SPEED_66MHz_PCIX_266; 10041da177e4SLinus Torvalds break; 10050afabe90SKenji Kaneshige case 0x9: 10060afabe90SKenji Kaneshige *value = PCI_SPEED_100MHz_PCIX_266; 10071da177e4SLinus Torvalds break; 10081da177e4SLinus Torvalds case 0xa: 10090afabe90SKenji Kaneshige *value = PCI_SPEED_133MHz_PCIX_266; 10101da177e4SLinus Torvalds break; 10111da177e4SLinus Torvalds case 0xb: 10120afabe90SKenji Kaneshige *value = PCI_SPEED_66MHz_PCIX_533; 10131da177e4SLinus Torvalds break; 10141da177e4SLinus Torvalds case 0xc: 10150afabe90SKenji Kaneshige *value = PCI_SPEED_100MHz_PCIX_533; 10161da177e4SLinus Torvalds break; 10171da177e4SLinus Torvalds case 0xd: 10180afabe90SKenji Kaneshige *value = PCI_SPEED_133MHz_PCIX_533; 10191da177e4SLinus Torvalds break; 10201da177e4SLinus Torvalds default: 10210afabe90SKenji Kaneshige *value = PCI_SPEED_UNKNOWN; 10220afabe90SKenji Kaneshige retval = -ENODEV; 10231da177e4SLinus Torvalds break; 10241da177e4SLinus Torvalds } 10251da177e4SLinus Torvalds 10261da177e4SLinus Torvalds dbg("Current bus speed = %d\n", bus_speed); 10271da177e4SLinus Torvalds DBG_LEAVE_ROUTINE 10281da177e4SLinus Torvalds return retval; 10291da177e4SLinus Torvalds } 10301da177e4SLinus Torvalds 10311da177e4SLinus Torvalds static struct hpc_ops shpchp_hpc_ops = { 10321da177e4SLinus Torvalds .power_on_slot = hpc_power_on_slot, 10331da177e4SLinus Torvalds .slot_enable = hpc_slot_enable, 10341da177e4SLinus Torvalds .slot_disable = hpc_slot_disable, 10351da177e4SLinus Torvalds .set_bus_speed_mode = hpc_set_bus_speed_mode, 10361da177e4SLinus Torvalds .set_attention_status = hpc_set_attention_status, 10371da177e4SLinus Torvalds .get_power_status = hpc_get_power_status, 10381da177e4SLinus Torvalds .get_attention_status = hpc_get_attention_status, 10391da177e4SLinus Torvalds .get_latch_status = hpc_get_latch_status, 10401da177e4SLinus Torvalds .get_adapter_status = hpc_get_adapter_status, 10411da177e4SLinus Torvalds 10421da177e4SLinus Torvalds .get_max_bus_speed = hpc_get_max_bus_speed, 10431da177e4SLinus Torvalds .get_cur_bus_speed = hpc_get_cur_bus_speed, 10441da177e4SLinus Torvalds .get_adapter_speed = hpc_get_adapter_speed, 10451da177e4SLinus Torvalds .get_mode1_ECC_cap = hpc_get_mode1_ECC_cap, 10461da177e4SLinus Torvalds .get_prog_int = hpc_get_prog_int, 10471da177e4SLinus Torvalds 10481da177e4SLinus Torvalds .query_power_fault = hpc_query_power_fault, 10491da177e4SLinus Torvalds .green_led_on = hpc_set_green_led_on, 10501da177e4SLinus Torvalds .green_led_off = hpc_set_green_led_off, 10511da177e4SLinus Torvalds .green_led_blink = hpc_set_green_led_blink, 10521da177e4SLinus Torvalds 10531da177e4SLinus Torvalds .release_ctlr = hpc_release_ctlr, 10541da177e4SLinus Torvalds }; 10551da177e4SLinus Torvalds 1056ee138334Srajesh.shah@intel.com int shpc_init(struct controller *ctrl, struct pci_dev *pdev) 10571da177e4SLinus Torvalds { 1058662a98fbSAmol Lad int rc = -1, num_slots = 0; 10591da177e4SLinus Torvalds u8 hp_slot; 10600455986cSKenji Kaneshige u32 shpc_base_offset; 106175d97c59SKenji Kaneshige u32 tempdword, slot_reg, slot_config; 10621da177e4SLinus Torvalds u8 i; 10631da177e4SLinus Torvalds 10641da177e4SLinus Torvalds DBG_ENTER_ROUTINE 10651da177e4SLinus Torvalds 10660455986cSKenji Kaneshige ctrl->pci_dev = pdev; /* pci_dev of the P2P bridge */ 10670455986cSKenji Kaneshige 1068ee138334Srajesh.shah@intel.com if ((pdev->vendor == PCI_VENDOR_ID_AMD) || (pdev->device == 1069ee138334Srajesh.shah@intel.com PCI_DEVICE_ID_AMD_GOLAM_7450)) { 10700455986cSKenji Kaneshige /* amd shpc driver doesn't use Base Offset; assume 0 */ 10710455986cSKenji Kaneshige ctrl->mmio_base = pci_resource_start(pdev, 0); 10720455986cSKenji Kaneshige ctrl->mmio_size = pci_resource_len(pdev, 0); 10731da177e4SLinus Torvalds } else { 10740455986cSKenji Kaneshige ctrl->cap_offset = pci_find_capability(pdev, PCI_CAP_ID_SHPC); 10750455986cSKenji Kaneshige if (!ctrl->cap_offset) { 10760455986cSKenji Kaneshige err("%s : cap_offset == 0\n", __FUNCTION__); 10770abe68ceSKenji Kaneshige goto abort; 10781da177e4SLinus Torvalds } 10790455986cSKenji Kaneshige dbg("%s: cap_offset = %x\n", __FUNCTION__, ctrl->cap_offset); 10801da177e4SLinus Torvalds 108175d97c59SKenji Kaneshige rc = shpc_indirect_read(ctrl, 0, &shpc_base_offset); 10821da177e4SLinus Torvalds if (rc) { 10830455986cSKenji Kaneshige err("%s: cannot read base_offset\n", __FUNCTION__); 10840abe68ceSKenji Kaneshige goto abort; 10851da177e4SLinus Torvalds } 10861da177e4SLinus Torvalds 108775d97c59SKenji Kaneshige rc = shpc_indirect_read(ctrl, 3, &tempdword); 10881da177e4SLinus Torvalds if (rc) { 10890455986cSKenji Kaneshige err("%s: cannot read slot config\n", __FUNCTION__); 10900abe68ceSKenji Kaneshige goto abort; 10911da177e4SLinus Torvalds } 10920455986cSKenji Kaneshige num_slots = tempdword & SLOT_NUM; 10930455986cSKenji Kaneshige dbg("%s: num_slots (indirect) %x\n", __FUNCTION__, num_slots); 10941da177e4SLinus Torvalds 10950455986cSKenji Kaneshige for (i = 0; i < 9 + num_slots; i++) { 109675d97c59SKenji Kaneshige rc = shpc_indirect_read(ctrl, i, &tempdword); 10971da177e4SLinus Torvalds if (rc) { 10980455986cSKenji Kaneshige err("%s: cannot read creg (index = %d)\n", 10990455986cSKenji Kaneshige __FUNCTION__, i); 11000abe68ceSKenji Kaneshige goto abort; 11011da177e4SLinus Torvalds } 11027c8942f9Srajesh.shah@intel.com dbg("%s: offset %d: value %x\n", __FUNCTION__,i, 11037c8942f9Srajesh.shah@intel.com tempdword); 11041da177e4SLinus Torvalds } 11050455986cSKenji Kaneshige 11060455986cSKenji Kaneshige ctrl->mmio_base = 11070455986cSKenji Kaneshige pci_resource_start(pdev, 0) + shpc_base_offset; 11080455986cSKenji Kaneshige ctrl->mmio_size = 0x24 + 0x4 * num_slots; 11091da177e4SLinus Torvalds } 11101da177e4SLinus Torvalds 11111da177e4SLinus Torvalds info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", pdev->vendor, pdev->device, pdev->subsystem_vendor, 11121da177e4SLinus Torvalds pdev->subsystem_device); 11131da177e4SLinus Torvalds 1114662a98fbSAmol Lad rc = pci_enable_device(pdev); 1115662a98fbSAmol Lad if (rc) { 1116662a98fbSAmol Lad err("%s: pci_enable_device failed\n", __FUNCTION__); 11170abe68ceSKenji Kaneshige goto abort; 1118662a98fbSAmol Lad } 11191da177e4SLinus Torvalds 11200455986cSKenji Kaneshige if (!request_mem_region(ctrl->mmio_base, ctrl->mmio_size, MY_NAME)) { 11211da177e4SLinus Torvalds err("%s: cannot reserve MMIO region\n", __FUNCTION__); 1122662a98fbSAmol Lad rc = -1; 11230abe68ceSKenji Kaneshige goto abort; 11241da177e4SLinus Torvalds } 11251da177e4SLinus Torvalds 11260abe68ceSKenji Kaneshige ctrl->creg = ioremap(ctrl->mmio_base, ctrl->mmio_size); 11270abe68ceSKenji Kaneshige if (!ctrl->creg) { 11280455986cSKenji Kaneshige err("%s: cannot remap MMIO region %lx @ %lx\n", __FUNCTION__, 11290455986cSKenji Kaneshige ctrl->mmio_size, ctrl->mmio_base); 11300455986cSKenji Kaneshige release_mem_region(ctrl->mmio_base, ctrl->mmio_size); 1131662a98fbSAmol Lad rc = -1; 11320abe68ceSKenji Kaneshige goto abort; 11331da177e4SLinus Torvalds } 11340abe68ceSKenji Kaneshige dbg("%s: ctrl->creg %p\n", __FUNCTION__, ctrl->creg); 11351da177e4SLinus Torvalds 11366aa4cdd0SIngo Molnar mutex_init(&ctrl->crit_sect); 1137d29aaddaSKenji Kaneshige mutex_init(&ctrl->cmd_lock); 1138d29aaddaSKenji Kaneshige 11391da177e4SLinus Torvalds /* Setup wait queue */ 11401da177e4SLinus Torvalds init_waitqueue_head(&ctrl->queue); 11411da177e4SLinus Torvalds 114275d97c59SKenji Kaneshige ctrl->hpc_ops = &shpchp_hpc_ops; 114375d97c59SKenji Kaneshige 11441da177e4SLinus Torvalds /* Return PCI Controller Info */ 114575d97c59SKenji Kaneshige slot_config = shpc_readl(ctrl, SLOT_CONFIG); 11460abe68ceSKenji Kaneshige ctrl->slot_device_offset = (slot_config & FIRST_DEV_NUM) >> 8; 11470abe68ceSKenji Kaneshige ctrl->num_slots = slot_config & SLOT_NUM; 11480abe68ceSKenji Kaneshige ctrl->first_slot = (slot_config & PSN) >> 16; 11490abe68ceSKenji Kaneshige ctrl->slot_num_inc = ((slot_config & UPDOWN) >> 29) ? 1 : -1; 11501da177e4SLinus Torvalds 11511da177e4SLinus Torvalds /* Mask Global Interrupt Mask & Command Complete Interrupt Mask */ 115275d97c59SKenji Kaneshige tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); 11531da177e4SLinus Torvalds dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword); 1154e7138723SKenji Kaneshige tempdword |= (GLOBAL_INTR_MASK | GLOBAL_SERR_MASK | 1155e7138723SKenji Kaneshige COMMAND_INTR_MASK | ARBITER_SERR_MASK); 1156e7138723SKenji Kaneshige tempdword &= ~SERR_INTR_RSVDZ_MASK; 115775d97c59SKenji Kaneshige shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword); 115875d97c59SKenji Kaneshige tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); 11591da177e4SLinus Torvalds dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword); 11601da177e4SLinus Torvalds 11611da177e4SLinus Torvalds /* Mask the MRL sensor SERR Mask of individual slot in 11621da177e4SLinus Torvalds * Slot SERR-INT Mask & clear all the existing event if any 11631da177e4SLinus Torvalds */ 11640abe68ceSKenji Kaneshige for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) { 11652b34da7eSKenji Kaneshige slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot)); 11661da177e4SLinus Torvalds dbg("%s: Default Logical Slot Register %d value %x\n", __FUNCTION__, 11671da177e4SLinus Torvalds hp_slot, slot_reg); 1168795eb5c4SKenji Kaneshige slot_reg |= (PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK | 1169795eb5c4SKenji Kaneshige BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK | 1170795eb5c4SKenji Kaneshige CON_PFAULT_INTR_MASK | MRL_CHANGE_SERR_MASK | 1171795eb5c4SKenji Kaneshige CON_PFAULT_SERR_MASK); 1172795eb5c4SKenji Kaneshige slot_reg &= ~SLOT_REG_RSVDZ_MASK; 1173795eb5c4SKenji Kaneshige shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg); 11741da177e4SLinus Torvalds } 11751da177e4SLinus Torvalds 11760abe68ceSKenji Kaneshige if (shpchp_poll_mode) { 11770abe68ceSKenji Kaneshige /* Install interrupt polling timer. Start with 10 sec delay */ 11780abe68ceSKenji Kaneshige init_timer(&ctrl->poll_timer); 11790abe68ceSKenji Kaneshige start_int_poll_timer(ctrl, 10); 11801da177e4SLinus Torvalds } else { 11811da177e4SLinus Torvalds /* Installs the interrupt handler */ 11821da177e4SLinus Torvalds rc = pci_enable_msi(pdev); 11831da177e4SLinus Torvalds if (rc) { 11841da177e4SLinus Torvalds info("Can't get msi for the hotplug controller\n"); 11851da177e4SLinus Torvalds info("Use INTx for the hotplug controller\n"); 11860abe68ceSKenji Kaneshige } 11871da177e4SLinus Torvalds 11880abe68ceSKenji Kaneshige rc = request_irq(ctrl->pci_dev->irq, shpc_isr, IRQF_SHARED, 11890abe68ceSKenji Kaneshige MY_NAME, (void *)ctrl); 11900abe68ceSKenji Kaneshige dbg("%s: request_irq %d for hpc%d (returns %d)\n", 11910abe68ceSKenji Kaneshige __FUNCTION__, ctrl->pci_dev->irq, 11920abe68ceSKenji Kaneshige atomic_read(&shpchp_num_controllers), rc); 11931da177e4SLinus Torvalds if (rc) { 11940abe68ceSKenji Kaneshige err("Can't get irq %d for the hotplug controller\n", 11950abe68ceSKenji Kaneshige ctrl->pci_dev->irq); 11960abe68ceSKenji Kaneshige goto abort_iounmap; 11971da177e4SLinus Torvalds } 11981da177e4SLinus Torvalds } 11997c8942f9Srajesh.shah@intel.com dbg("%s: HPC at b:d:f:irq=0x%x:%x:%x:%x\n", __FUNCTION__, 12007c8942f9Srajesh.shah@intel.com pdev->bus->number, PCI_SLOT(pdev->devfn), 12017c8942f9Srajesh.shah@intel.com PCI_FUNC(pdev->devfn), pdev->irq); 1202424600f9Srajesh.shah@intel.com get_hp_hw_control_from_firmware(pdev); 12031da177e4SLinus Torvalds 1204795eb5c4SKenji Kaneshige /* 120582d5f4aaSKenji Kaneshige * If this is the first controller to be initialized, 120682d5f4aaSKenji Kaneshige * initialize the shpchpd work queue 120782d5f4aaSKenji Kaneshige */ 120882d5f4aaSKenji Kaneshige if (atomic_add_return(1, &shpchp_num_controllers) == 1) { 120982d5f4aaSKenji Kaneshige shpchp_wq = create_singlethread_workqueue("shpchpd"); 1210662a98fbSAmol Lad if (!shpchp_wq) { 1211662a98fbSAmol Lad rc = -ENOMEM; 12120abe68ceSKenji Kaneshige goto abort_iounmap; 1213662a98fbSAmol Lad } 121482d5f4aaSKenji Kaneshige } 121582d5f4aaSKenji Kaneshige 121682d5f4aaSKenji Kaneshige /* 1217795eb5c4SKenji Kaneshige * Unmask all event interrupts of all slots 1218795eb5c4SKenji Kaneshige */ 12190abe68ceSKenji Kaneshige for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) { 12202b34da7eSKenji Kaneshige slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot)); 12211da177e4SLinus Torvalds dbg("%s: Default Logical Slot Register %d value %x\n", __FUNCTION__, 12221da177e4SLinus Torvalds hp_slot, slot_reg); 1223795eb5c4SKenji Kaneshige slot_reg &= ~(PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK | 1224795eb5c4SKenji Kaneshige BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK | 1225795eb5c4SKenji Kaneshige CON_PFAULT_INTR_MASK | SLOT_REG_RSVDZ_MASK); 1226795eb5c4SKenji Kaneshige shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg); 12271da177e4SLinus Torvalds } 12281da177e4SLinus Torvalds if (!shpchp_poll_mode) { 12291da177e4SLinus Torvalds /* Unmask all general input interrupts and SERR */ 123075d97c59SKenji Kaneshige tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); 1231e7138723SKenji Kaneshige tempdword &= ~(GLOBAL_INTR_MASK | COMMAND_INTR_MASK | 1232e7138723SKenji Kaneshige SERR_INTR_RSVDZ_MASK); 123375d97c59SKenji Kaneshige shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword); 123475d97c59SKenji Kaneshige tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); 12351da177e4SLinus Torvalds dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword); 12361da177e4SLinus Torvalds } 12371da177e4SLinus Torvalds 12381da177e4SLinus Torvalds DBG_LEAVE_ROUTINE 12391da177e4SLinus Torvalds return 0; 12401da177e4SLinus Torvalds 12411da177e4SLinus Torvalds /* We end up here for the many possible ways to fail this API. */ 12420abe68ceSKenji Kaneshige abort_iounmap: 12430abe68ceSKenji Kaneshige iounmap(ctrl->creg); 12441da177e4SLinus Torvalds abort: 12451da177e4SLinus Torvalds DBG_LEAVE_ROUTINE 1246662a98fbSAmol Lad return rc; 12471da177e4SLinus Torvalds } 1248