1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Standard Hot Plug Controller Driver 4 * 5 * Copyright (C) 1995,2001 Compaq Computer Corporation 6 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com) 7 * Copyright (C) 2001 IBM 8 * Copyright (C) 2003-2004 Intel Corporation 9 * 10 * All rights reserved. 11 * 12 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com> 13 * 14 */ 15 #ifndef _SHPCHP_H 16 #define _SHPCHP_H 17 18 #include <linux/types.h> 19 #include <linux/pci.h> 20 #include <linux/pci_hotplug.h> 21 #include <linux/delay.h> 22 #include <linux/sched/signal.h> /* signal_pending(), struct timer_list */ 23 #include <linux/mutex.h> 24 #include <linux/workqueue.h> 25 26 #if !defined(MODULE) 27 #define MY_NAME "shpchp" 28 #else 29 #define MY_NAME THIS_MODULE->name 30 #endif 31 32 extern bool shpchp_poll_mode; 33 extern int shpchp_poll_time; 34 extern bool shpchp_debug; 35 36 #define dbg(format, arg...) \ 37 do { \ 38 if (shpchp_debug) \ 39 printk(KERN_DEBUG "%s: " format, MY_NAME, ## arg); \ 40 } while (0) 41 #define err(format, arg...) \ 42 printk(KERN_ERR "%s: " format, MY_NAME, ## arg) 43 #define info(format, arg...) \ 44 printk(KERN_INFO "%s: " format, MY_NAME, ## arg) 45 #define warn(format, arg...) \ 46 printk(KERN_WARNING "%s: " format, MY_NAME, ## arg) 47 48 #define ctrl_dbg(ctrl, format, arg...) \ 49 do { \ 50 if (shpchp_debug) \ 51 pci_printk(KERN_DEBUG, ctrl->pci_dev, \ 52 format, ## arg); \ 53 } while (0) 54 #define ctrl_err(ctrl, format, arg...) \ 55 pci_err(ctrl->pci_dev, format, ## arg) 56 #define ctrl_info(ctrl, format, arg...) \ 57 pci_info(ctrl->pci_dev, format, ## arg) 58 #define ctrl_warn(ctrl, format, arg...) \ 59 pci_warn(ctrl->pci_dev, format, ## arg) 60 61 62 #define SLOT_NAME_SIZE 10 63 struct slot { 64 u8 bus; 65 u8 device; 66 u16 status; 67 u32 number; 68 u8 is_a_board; 69 u8 state; 70 u8 presence_save; 71 u8 pwr_save; 72 struct controller *ctrl; 73 const struct hpc_ops *hpc_ops; 74 struct hotplug_slot *hotplug_slot; 75 struct list_head slot_list; 76 struct delayed_work work; /* work for button event */ 77 struct mutex lock; 78 struct workqueue_struct *wq; 79 u8 hp_slot; 80 }; 81 82 struct event_info { 83 u32 event_type; 84 struct slot *p_slot; 85 struct work_struct work; 86 }; 87 88 struct controller { 89 struct mutex crit_sect; /* critical section mutex */ 90 struct mutex cmd_lock; /* command lock */ 91 int num_slots; /* Number of slots on ctlr */ 92 int slot_num_inc; /* 1 or -1 */ 93 struct pci_dev *pci_dev; 94 struct list_head slot_list; 95 const struct hpc_ops *hpc_ops; 96 wait_queue_head_t queue; /* sleep & wake process */ 97 u8 slot_device_offset; 98 u32 pcix_misc2_reg; /* for amd pogo errata */ 99 u32 first_slot; /* First physical slot number */ 100 u32 cap_offset; 101 unsigned long mmio_base; 102 unsigned long mmio_size; 103 void __iomem *creg; 104 struct timer_list poll_timer; 105 }; 106 107 /* Define AMD SHPC ID */ 108 #define PCI_DEVICE_ID_AMD_GOLAM_7450 0x7450 109 #define PCI_DEVICE_ID_AMD_POGO_7458 0x7458 110 111 /* AMD PCI-X bridge registers */ 112 #define PCIX_MEM_BASE_LIMIT_OFFSET 0x1C 113 #define PCIX_MISCII_OFFSET 0x48 114 #define PCIX_MISC_BRIDGE_ERRORS_OFFSET 0x80 115 116 /* AMD PCIX_MISCII masks and offsets */ 117 #define PERRNONFATALENABLE_MASK 0x00040000 118 #define PERRFATALENABLE_MASK 0x00080000 119 #define PERRFLOODENABLE_MASK 0x00100000 120 #define SERRNONFATALENABLE_MASK 0x00200000 121 #define SERRFATALENABLE_MASK 0x00400000 122 123 /* AMD PCIX_MISC_BRIDGE_ERRORS masks and offsets */ 124 #define PERR_OBSERVED_MASK 0x00000001 125 126 /* AMD PCIX_MEM_BASE_LIMIT masks */ 127 #define RSE_MASK 0x40000000 128 129 #define INT_BUTTON_IGNORE 0 130 #define INT_PRESENCE_ON 1 131 #define INT_PRESENCE_OFF 2 132 #define INT_SWITCH_CLOSE 3 133 #define INT_SWITCH_OPEN 4 134 #define INT_POWER_FAULT 5 135 #define INT_POWER_FAULT_CLEAR 6 136 #define INT_BUTTON_PRESS 7 137 #define INT_BUTTON_RELEASE 8 138 #define INT_BUTTON_CANCEL 9 139 140 #define STATIC_STATE 0 141 #define BLINKINGON_STATE 1 142 #define BLINKINGOFF_STATE 2 143 #define POWERON_STATE 3 144 #define POWEROFF_STATE 4 145 146 /* Error messages */ 147 #define INTERLOCK_OPEN 0x00000002 148 #define ADD_NOT_SUPPORTED 0x00000003 149 #define CARD_FUNCTIONING 0x00000005 150 #define ADAPTER_NOT_SAME 0x00000006 151 #define NO_ADAPTER_PRESENT 0x00000009 152 #define NOT_ENOUGH_RESOURCES 0x0000000B 153 #define DEVICE_TYPE_NOT_SUPPORTED 0x0000000C 154 #define WRONG_BUS_FREQUENCY 0x0000000D 155 #define POWER_FAILURE 0x0000000E 156 157 int __must_check shpchp_create_ctrl_files(struct controller *ctrl); 158 void shpchp_remove_ctrl_files(struct controller *ctrl); 159 int shpchp_sysfs_enable_slot(struct slot *slot); 160 int shpchp_sysfs_disable_slot(struct slot *slot); 161 u8 shpchp_handle_attention_button(u8 hp_slot, struct controller *ctrl); 162 u8 shpchp_handle_switch_change(u8 hp_slot, struct controller *ctrl); 163 u8 shpchp_handle_presence_change(u8 hp_slot, struct controller *ctrl); 164 u8 shpchp_handle_power_fault(u8 hp_slot, struct controller *ctrl); 165 int shpchp_configure_device(struct slot *p_slot); 166 int shpchp_unconfigure_device(struct slot *p_slot); 167 void cleanup_slots(struct controller *ctrl); 168 void shpchp_queue_pushbutton_work(struct work_struct *work); 169 int shpc_init(struct controller *ctrl, struct pci_dev *pdev); 170 171 static inline const char *slot_name(struct slot *slot) 172 { 173 return hotplug_slot_name(slot->hotplug_slot); 174 } 175 176 #ifdef CONFIG_ACPI 177 #include <linux/pci-acpi.h> 178 static inline int get_hp_hw_control_from_firmware(struct pci_dev *dev) 179 { 180 u32 flags = OSC_PCI_SHPC_NATIVE_HP_CONTROL; 181 return acpi_get_hp_hw_control_from_firmware(dev, flags); 182 } 183 #else 184 #define get_hp_hw_control_from_firmware(dev) (0) 185 #endif 186 187 struct ctrl_reg { 188 volatile u32 base_offset; 189 volatile u32 slot_avail1; 190 volatile u32 slot_avail2; 191 volatile u32 slot_config; 192 volatile u16 sec_bus_config; 193 volatile u8 msi_ctrl; 194 volatile u8 prog_interface; 195 volatile u16 cmd; 196 volatile u16 cmd_status; 197 volatile u32 intr_loc; 198 volatile u32 serr_loc; 199 volatile u32 serr_intr_enable; 200 volatile u32 slot1; 201 } __attribute__ ((packed)); 202 203 /* offsets to the controller registers based on the above structure layout */ 204 enum ctrl_offsets { 205 BASE_OFFSET = offsetof(struct ctrl_reg, base_offset), 206 SLOT_AVAIL1 = offsetof(struct ctrl_reg, slot_avail1), 207 SLOT_AVAIL2 = offsetof(struct ctrl_reg, slot_avail2), 208 SLOT_CONFIG = offsetof(struct ctrl_reg, slot_config), 209 SEC_BUS_CONFIG = offsetof(struct ctrl_reg, sec_bus_config), 210 MSI_CTRL = offsetof(struct ctrl_reg, msi_ctrl), 211 PROG_INTERFACE = offsetof(struct ctrl_reg, prog_interface), 212 CMD = offsetof(struct ctrl_reg, cmd), 213 CMD_STATUS = offsetof(struct ctrl_reg, cmd_status), 214 INTR_LOC = offsetof(struct ctrl_reg, intr_loc), 215 SERR_LOC = offsetof(struct ctrl_reg, serr_loc), 216 SERR_INTR_ENABLE = offsetof(struct ctrl_reg, serr_intr_enable), 217 SLOT1 = offsetof(struct ctrl_reg, slot1), 218 }; 219 220 static inline struct slot *get_slot(struct hotplug_slot *hotplug_slot) 221 { 222 return hotplug_slot->private; 223 } 224 225 static inline struct slot *shpchp_find_slot(struct controller *ctrl, u8 device) 226 { 227 struct slot *slot; 228 229 list_for_each_entry(slot, &ctrl->slot_list, slot_list) { 230 if (slot->device == device) 231 return slot; 232 } 233 234 ctrl_err(ctrl, "Slot (device=0x%02x) not found\n", device); 235 return NULL; 236 } 237 238 static inline void amd_pogo_errata_save_misc_reg(struct slot *p_slot) 239 { 240 u32 pcix_misc2_temp; 241 242 /* save MiscII register */ 243 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp); 244 245 p_slot->ctrl->pcix_misc2_reg = pcix_misc2_temp; 246 247 /* clear SERR/PERR enable bits */ 248 pcix_misc2_temp &= ~SERRFATALENABLE_MASK; 249 pcix_misc2_temp &= ~SERRNONFATALENABLE_MASK; 250 pcix_misc2_temp &= ~PERRFLOODENABLE_MASK; 251 pcix_misc2_temp &= ~PERRFATALENABLE_MASK; 252 pcix_misc2_temp &= ~PERRNONFATALENABLE_MASK; 253 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp); 254 } 255 256 static inline void amd_pogo_errata_restore_misc_reg(struct slot *p_slot) 257 { 258 u32 pcix_misc2_temp; 259 u32 pcix_bridge_errors_reg; 260 u32 pcix_mem_base_reg; 261 u8 perr_set; 262 u8 rse_set; 263 264 /* write-one-to-clear Bridge_Errors[ PERR_OBSERVED ] */ 265 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, &pcix_bridge_errors_reg); 266 perr_set = pcix_bridge_errors_reg & PERR_OBSERVED_MASK; 267 if (perr_set) { 268 ctrl_dbg(p_slot->ctrl, 269 "Bridge_Errors[ PERR_OBSERVED = %08X] (W1C)\n", 270 perr_set); 271 272 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, perr_set); 273 } 274 275 /* write-one-to-clear Memory_Base_Limit[ RSE ] */ 276 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, &pcix_mem_base_reg); 277 rse_set = pcix_mem_base_reg & RSE_MASK; 278 if (rse_set) { 279 ctrl_dbg(p_slot->ctrl, "Memory_Base_Limit[ RSE ] (W1C)\n"); 280 281 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, rse_set); 282 } 283 /* restore MiscII register */ 284 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp); 285 286 if (p_slot->ctrl->pcix_misc2_reg & SERRFATALENABLE_MASK) 287 pcix_misc2_temp |= SERRFATALENABLE_MASK; 288 else 289 pcix_misc2_temp &= ~SERRFATALENABLE_MASK; 290 291 if (p_slot->ctrl->pcix_misc2_reg & SERRNONFATALENABLE_MASK) 292 pcix_misc2_temp |= SERRNONFATALENABLE_MASK; 293 else 294 pcix_misc2_temp &= ~SERRNONFATALENABLE_MASK; 295 296 if (p_slot->ctrl->pcix_misc2_reg & PERRFLOODENABLE_MASK) 297 pcix_misc2_temp |= PERRFLOODENABLE_MASK; 298 else 299 pcix_misc2_temp &= ~PERRFLOODENABLE_MASK; 300 301 if (p_slot->ctrl->pcix_misc2_reg & PERRFATALENABLE_MASK) 302 pcix_misc2_temp |= PERRFATALENABLE_MASK; 303 else 304 pcix_misc2_temp &= ~PERRFATALENABLE_MASK; 305 306 if (p_slot->ctrl->pcix_misc2_reg & PERRNONFATALENABLE_MASK) 307 pcix_misc2_temp |= PERRNONFATALENABLE_MASK; 308 else 309 pcix_misc2_temp &= ~PERRNONFATALENABLE_MASK; 310 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp); 311 } 312 313 struct hpc_ops { 314 int (*power_on_slot)(struct slot *slot); 315 int (*slot_enable)(struct slot *slot); 316 int (*slot_disable)(struct slot *slot); 317 int (*set_bus_speed_mode)(struct slot *slot, enum pci_bus_speed speed); 318 int (*get_power_status)(struct slot *slot, u8 *status); 319 int (*get_attention_status)(struct slot *slot, u8 *status); 320 int (*set_attention_status)(struct slot *slot, u8 status); 321 int (*get_latch_status)(struct slot *slot, u8 *status); 322 int (*get_adapter_status)(struct slot *slot, u8 *status); 323 int (*get_adapter_speed)(struct slot *slot, enum pci_bus_speed *speed); 324 int (*get_mode1_ECC_cap)(struct slot *slot, u8 *mode); 325 int (*get_prog_int)(struct slot *slot, u8 *prog_int); 326 int (*query_power_fault)(struct slot *slot); 327 void (*green_led_on)(struct slot *slot); 328 void (*green_led_off)(struct slot *slot); 329 void (*green_led_blink)(struct slot *slot); 330 void (*release_ctlr)(struct controller *ctrl); 331 int (*check_cmd_status)(struct controller *ctrl); 332 }; 333 334 #endif /* _SHPCHP_H */ 335