1 /* 2 * Standard Hot Plug Controller Driver 3 * 4 * Copyright (C) 1995,2001 Compaq Computer Corporation 5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com) 6 * Copyright (C) 2001 IBM 7 * Copyright (C) 2003-2004 Intel Corporation 8 * 9 * All rights reserved. 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or (at 14 * your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 19 * NON INFRINGEMENT. See the GNU General Public License for more 20 * details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 25 * 26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com> 27 * 28 */ 29 #ifndef _SHPCHP_H 30 #define _SHPCHP_H 31 32 #include <linux/types.h> 33 #include <linux/pci.h> 34 #include <linux/pci_hotplug.h> 35 #include <linux/delay.h> 36 #include <linux/sched.h> /* signal_pending(), struct timer_list */ 37 #include <linux/mutex.h> 38 39 #if !defined(MODULE) 40 #define MY_NAME "shpchp" 41 #else 42 #define MY_NAME THIS_MODULE->name 43 #endif 44 45 extern int shpchp_poll_mode; 46 extern int shpchp_poll_time; 47 extern int shpchp_debug; 48 extern struct workqueue_struct *shpchp_wq; 49 50 #define dbg(format, arg...) \ 51 do { \ 52 if (shpchp_debug) \ 53 printk("%s: " format, MY_NAME , ## arg); \ 54 } while (0) 55 #define err(format, arg...) \ 56 printk(KERN_ERR "%s: " format, MY_NAME , ## arg) 57 #define info(format, arg...) \ 58 printk(KERN_INFO "%s: " format, MY_NAME , ## arg) 59 #define warn(format, arg...) \ 60 printk(KERN_WARNING "%s: " format, MY_NAME , ## arg) 61 62 #define SLOT_NAME_SIZE 10 63 struct slot { 64 u8 bus; 65 u8 device; 66 u16 status; 67 u32 number; 68 u8 is_a_board; 69 u8 state; 70 u8 presence_save; 71 u8 pwr_save; 72 struct timer_list task_event; 73 u8 hp_slot; 74 struct controller *ctrl; 75 struct hpc_ops *hpc_ops; 76 struct hotplug_slot *hotplug_slot; 77 struct list_head slot_list; 78 char name[SLOT_NAME_SIZE]; 79 struct delayed_work work; /* work for button event */ 80 struct mutex lock; 81 }; 82 83 struct event_info { 84 u32 event_type; 85 struct slot *p_slot; 86 struct work_struct work; 87 }; 88 89 struct controller { 90 struct mutex crit_sect; /* critical section mutex */ 91 struct mutex cmd_lock; /* command lock */ 92 int num_slots; /* Number of slots on ctlr */ 93 int slot_num_inc; /* 1 or -1 */ 94 struct pci_dev *pci_dev; 95 struct list_head slot_list; 96 struct hpc_ops *hpc_ops; 97 wait_queue_head_t queue; /* sleep & wake process */ 98 u8 slot_device_offset; 99 u32 pcix_misc2_reg; /* for amd pogo errata */ 100 u32 first_slot; /* First physical slot number */ 101 u32 cap_offset; 102 unsigned long mmio_base; 103 unsigned long mmio_size; 104 void __iomem *creg; 105 struct timer_list poll_timer; 106 }; 107 108 /* Define AMD SHPC ID */ 109 #define PCI_DEVICE_ID_AMD_GOLAM_7450 0x7450 110 #define PCI_DEVICE_ID_AMD_POGO_7458 0x7458 111 112 /* AMD PCIX bridge registers */ 113 #define PCIX_MEM_BASE_LIMIT_OFFSET 0x1C 114 #define PCIX_MISCII_OFFSET 0x48 115 #define PCIX_MISC_BRIDGE_ERRORS_OFFSET 0x80 116 117 /* AMD PCIX_MISCII masks and offsets */ 118 #define PERRNONFATALENABLE_MASK 0x00040000 119 #define PERRFATALENABLE_MASK 0x00080000 120 #define PERRFLOODENABLE_MASK 0x00100000 121 #define SERRNONFATALENABLE_MASK 0x00200000 122 #define SERRFATALENABLE_MASK 0x00400000 123 124 /* AMD PCIX_MISC_BRIDGE_ERRORS masks and offsets */ 125 #define PERR_OBSERVED_MASK 0x00000001 126 127 /* AMD PCIX_MEM_BASE_LIMIT masks */ 128 #define RSE_MASK 0x40000000 129 130 #define INT_BUTTON_IGNORE 0 131 #define INT_PRESENCE_ON 1 132 #define INT_PRESENCE_OFF 2 133 #define INT_SWITCH_CLOSE 3 134 #define INT_SWITCH_OPEN 4 135 #define INT_POWER_FAULT 5 136 #define INT_POWER_FAULT_CLEAR 6 137 #define INT_BUTTON_PRESS 7 138 #define INT_BUTTON_RELEASE 8 139 #define INT_BUTTON_CANCEL 9 140 141 #define STATIC_STATE 0 142 #define BLINKINGON_STATE 1 143 #define BLINKINGOFF_STATE 2 144 #define POWERON_STATE 3 145 #define POWEROFF_STATE 4 146 147 /* Error messages */ 148 #define INTERLOCK_OPEN 0x00000002 149 #define ADD_NOT_SUPPORTED 0x00000003 150 #define CARD_FUNCTIONING 0x00000005 151 #define ADAPTER_NOT_SAME 0x00000006 152 #define NO_ADAPTER_PRESENT 0x00000009 153 #define NOT_ENOUGH_RESOURCES 0x0000000B 154 #define DEVICE_TYPE_NOT_SUPPORTED 0x0000000C 155 #define WRONG_BUS_FREQUENCY 0x0000000D 156 #define POWER_FAILURE 0x0000000E 157 158 extern int __must_check shpchp_create_ctrl_files(struct controller *ctrl); 159 extern void shpchp_remove_ctrl_files(struct controller *ctrl); 160 extern int shpchp_sysfs_enable_slot(struct slot *slot); 161 extern int shpchp_sysfs_disable_slot(struct slot *slot); 162 extern u8 shpchp_handle_attention_button(u8 hp_slot, struct controller *ctrl); 163 extern u8 shpchp_handle_switch_change(u8 hp_slot, struct controller *ctrl); 164 extern u8 shpchp_handle_presence_change(u8 hp_slot, struct controller *ctrl); 165 extern u8 shpchp_handle_power_fault(u8 hp_slot, struct controller *ctrl); 166 extern int shpchp_configure_device(struct slot *p_slot); 167 extern int shpchp_unconfigure_device(struct slot *p_slot); 168 extern void cleanup_slots(struct controller *ctrl); 169 extern void shpchp_queue_pushbutton_work(struct work_struct *work); 170 extern int shpc_init( struct controller *ctrl, struct pci_dev *pdev); 171 172 #ifdef CONFIG_ACPI 173 #include <linux/pci-acpi.h> 174 static inline int get_hp_params_from_firmware(struct pci_dev *dev, 175 struct hotplug_params *hpp) 176 { 177 if (ACPI_FAILURE(acpi_get_hp_params_from_firmware(dev->bus, hpp))) 178 return -ENODEV; 179 return 0; 180 } 181 182 static inline int get_hp_hw_control_from_firmware(struct pci_dev *dev) 183 { 184 u32 flags = OSC_SHPC_NATIVE_HP_CONTROL; 185 return acpi_get_hp_hw_control_from_firmware(dev, flags); 186 } 187 #else 188 #define get_hp_params_from_firmware(dev, hpp) (-ENODEV) 189 #define get_hp_hw_control_from_firmware(dev) (0) 190 #endif 191 192 struct ctrl_reg { 193 volatile u32 base_offset; 194 volatile u32 slot_avail1; 195 volatile u32 slot_avail2; 196 volatile u32 slot_config; 197 volatile u16 sec_bus_config; 198 volatile u8 msi_ctrl; 199 volatile u8 prog_interface; 200 volatile u16 cmd; 201 volatile u16 cmd_status; 202 volatile u32 intr_loc; 203 volatile u32 serr_loc; 204 volatile u32 serr_intr_enable; 205 volatile u32 slot1; 206 } __attribute__ ((packed)); 207 208 /* offsets to the controller registers based on the above structure layout */ 209 enum ctrl_offsets { 210 BASE_OFFSET = offsetof(struct ctrl_reg, base_offset), 211 SLOT_AVAIL1 = offsetof(struct ctrl_reg, slot_avail1), 212 SLOT_AVAIL2 = offsetof(struct ctrl_reg, slot_avail2), 213 SLOT_CONFIG = offsetof(struct ctrl_reg, slot_config), 214 SEC_BUS_CONFIG = offsetof(struct ctrl_reg, sec_bus_config), 215 MSI_CTRL = offsetof(struct ctrl_reg, msi_ctrl), 216 PROG_INTERFACE = offsetof(struct ctrl_reg, prog_interface), 217 CMD = offsetof(struct ctrl_reg, cmd), 218 CMD_STATUS = offsetof(struct ctrl_reg, cmd_status), 219 INTR_LOC = offsetof(struct ctrl_reg, intr_loc), 220 SERR_LOC = offsetof(struct ctrl_reg, serr_loc), 221 SERR_INTR_ENABLE = offsetof(struct ctrl_reg, serr_intr_enable), 222 SLOT1 = offsetof(struct ctrl_reg, slot1), 223 }; 224 225 static inline struct slot *get_slot(struct hotplug_slot *hotplug_slot) 226 { 227 return hotplug_slot->private; 228 } 229 230 static inline struct slot *shpchp_find_slot(struct controller *ctrl, u8 device) 231 { 232 struct slot *slot; 233 234 list_for_each_entry(slot, &ctrl->slot_list, slot_list) { 235 if (slot->device == device) 236 return slot; 237 } 238 239 err("%s: slot (device=0x%x) not found\n", __func__, device); 240 return NULL; 241 } 242 243 static inline void amd_pogo_errata_save_misc_reg(struct slot *p_slot) 244 { 245 u32 pcix_misc2_temp; 246 247 /* save MiscII register */ 248 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp); 249 250 p_slot->ctrl->pcix_misc2_reg = pcix_misc2_temp; 251 252 /* clear SERR/PERR enable bits */ 253 pcix_misc2_temp &= ~SERRFATALENABLE_MASK; 254 pcix_misc2_temp &= ~SERRNONFATALENABLE_MASK; 255 pcix_misc2_temp &= ~PERRFLOODENABLE_MASK; 256 pcix_misc2_temp &= ~PERRFATALENABLE_MASK; 257 pcix_misc2_temp &= ~PERRNONFATALENABLE_MASK; 258 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp); 259 } 260 261 static inline void amd_pogo_errata_restore_misc_reg(struct slot *p_slot) 262 { 263 u32 pcix_misc2_temp; 264 u32 pcix_bridge_errors_reg; 265 u32 pcix_mem_base_reg; 266 u8 perr_set; 267 u8 rse_set; 268 269 /* write-one-to-clear Bridge_Errors[ PERR_OBSERVED ] */ 270 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, &pcix_bridge_errors_reg); 271 perr_set = pcix_bridge_errors_reg & PERR_OBSERVED_MASK; 272 if (perr_set) { 273 dbg ("%s W1C: Bridge_Errors[ PERR_OBSERVED = %08X]\n",__func__ , perr_set); 274 275 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, perr_set); 276 } 277 278 /* write-one-to-clear Memory_Base_Limit[ RSE ] */ 279 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, &pcix_mem_base_reg); 280 rse_set = pcix_mem_base_reg & RSE_MASK; 281 if (rse_set) { 282 dbg ("%s W1C: Memory_Base_Limit[ RSE ]\n",__func__ ); 283 284 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, rse_set); 285 } 286 /* restore MiscII register */ 287 pci_read_config_dword( p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp ); 288 289 if (p_slot->ctrl->pcix_misc2_reg & SERRFATALENABLE_MASK) 290 pcix_misc2_temp |= SERRFATALENABLE_MASK; 291 else 292 pcix_misc2_temp &= ~SERRFATALENABLE_MASK; 293 294 if (p_slot->ctrl->pcix_misc2_reg & SERRNONFATALENABLE_MASK) 295 pcix_misc2_temp |= SERRNONFATALENABLE_MASK; 296 else 297 pcix_misc2_temp &= ~SERRNONFATALENABLE_MASK; 298 299 if (p_slot->ctrl->pcix_misc2_reg & PERRFLOODENABLE_MASK) 300 pcix_misc2_temp |= PERRFLOODENABLE_MASK; 301 else 302 pcix_misc2_temp &= ~PERRFLOODENABLE_MASK; 303 304 if (p_slot->ctrl->pcix_misc2_reg & PERRFATALENABLE_MASK) 305 pcix_misc2_temp |= PERRFATALENABLE_MASK; 306 else 307 pcix_misc2_temp &= ~PERRFATALENABLE_MASK; 308 309 if (p_slot->ctrl->pcix_misc2_reg & PERRNONFATALENABLE_MASK) 310 pcix_misc2_temp |= PERRNONFATALENABLE_MASK; 311 else 312 pcix_misc2_temp &= ~PERRNONFATALENABLE_MASK; 313 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp); 314 } 315 316 struct hpc_ops { 317 int (*power_on_slot)(struct slot *slot); 318 int (*slot_enable)(struct slot *slot); 319 int (*slot_disable)(struct slot *slot); 320 int (*set_bus_speed_mode)(struct slot *slot, enum pci_bus_speed speed); 321 int (*get_power_status)(struct slot *slot, u8 *status); 322 int (*get_attention_status)(struct slot *slot, u8 *status); 323 int (*set_attention_status)(struct slot *slot, u8 status); 324 int (*get_latch_status)(struct slot *slot, u8 *status); 325 int (*get_adapter_status)(struct slot *slot, u8 *status); 326 int (*get_max_bus_speed)(struct slot *slot, enum pci_bus_speed *speed); 327 int (*get_cur_bus_speed)(struct slot *slot, enum pci_bus_speed *speed); 328 int (*get_adapter_speed)(struct slot *slot, enum pci_bus_speed *speed); 329 int (*get_mode1_ECC_cap)(struct slot *slot, u8 *mode); 330 int (*get_prog_int)(struct slot *slot, u8 *prog_int); 331 int (*query_power_fault)(struct slot *slot); 332 void (*green_led_on)(struct slot *slot); 333 void (*green_led_off)(struct slot *slot); 334 void (*green_led_blink)(struct slot *slot); 335 void (*release_ctlr)(struct controller *ctrl); 336 int (*check_cmd_status)(struct controller *ctrl); 337 }; 338 339 #endif /* _SHPCHP_H */ 340