1736759efSBjorn Helgaas /* SPDX-License-Identifier: GPL-2.0+ */
21da177e4SLinus Torvalds /*
31da177e4SLinus Torvalds * Standard Hot Plug Controller Driver
41da177e4SLinus Torvalds *
51da177e4SLinus Torvalds * Copyright (C) 1995,2001 Compaq Computer Corporation
61da177e4SLinus Torvalds * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
71da177e4SLinus Torvalds * Copyright (C) 2001 IBM
81da177e4SLinus Torvalds * Copyright (C) 2003-2004 Intel Corporation
91da177e4SLinus Torvalds *
101da177e4SLinus Torvalds * All rights reserved.
111da177e4SLinus Torvalds *
128cf4c195SKristen Accardi * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
131da177e4SLinus Torvalds *
141da177e4SLinus Torvalds */
151da177e4SLinus Torvalds #ifndef _SHPCHP_H
161da177e4SLinus Torvalds #define _SHPCHP_H
171da177e4SLinus Torvalds
181da177e4SLinus Torvalds #include <linux/types.h>
191da177e4SLinus Torvalds #include <linux/pci.h>
207a54f25cSGreg Kroah-Hartman #include <linux/pci_hotplug.h>
211da177e4SLinus Torvalds #include <linux/delay.h>
22174cd4b1SIngo Molnar #include <linux/sched/signal.h> /* signal_pending(), struct timer_list */
236aa4cdd0SIngo Molnar #include <linux/mutex.h>
24e24dcbefSTejun Heo #include <linux/workqueue.h>
254e57b681STim Schmielau
261da177e4SLinus Torvalds #if !defined(MODULE)
271da177e4SLinus Torvalds #define MY_NAME "shpchp"
281da177e4SLinus Torvalds #else
291da177e4SLinus Torvalds #define MY_NAME THIS_MODULE->name
301da177e4SLinus Torvalds #endif
311da177e4SLinus Torvalds
3290ab5ee9SRusty Russell extern bool shpchp_poll_mode;
331da177e4SLinus Torvalds extern int shpchp_poll_time;
3490ab5ee9SRusty Russell extern bool shpchp_debug;
351da177e4SLinus Torvalds
368352e04eSKenji Kaneshige #define dbg(format, arg...) \
378352e04eSKenji Kaneshige do { \
388352e04eSKenji Kaneshige if (shpchp_debug) \
391c35b8e5SFrank Seidel printk(KERN_DEBUG "%s: " format, MY_NAME, ## arg); \
408352e04eSKenji Kaneshige } while (0)
418352e04eSKenji Kaneshige #define err(format, arg...) \
428352e04eSKenji Kaneshige printk(KERN_ERR "%s: " format, MY_NAME, ## arg)
438352e04eSKenji Kaneshige #define info(format, arg...) \
448352e04eSKenji Kaneshige printk(KERN_INFO "%s: " format, MY_NAME, ## arg)
458352e04eSKenji Kaneshige #define warn(format, arg...) \
468352e04eSKenji Kaneshige printk(KERN_WARNING "%s: " format, MY_NAME, ## arg)
471da177e4SLinus Torvalds
48f98ca311STaku Izumi #define ctrl_dbg(ctrl, format, arg...) \
49f98ca311STaku Izumi do { \
50f98ca311STaku Izumi if (shpchp_debug) \
517506dc79SFrederick Lawler pci_printk(KERN_DEBUG, ctrl->pci_dev, \
52f98ca311STaku Izumi format, ## arg); \
53f98ca311STaku Izumi } while (0)
54f98ca311STaku Izumi #define ctrl_err(ctrl, format, arg...) \
557506dc79SFrederick Lawler pci_err(ctrl->pci_dev, format, ## arg)
56f98ca311STaku Izumi #define ctrl_info(ctrl, format, arg...) \
577506dc79SFrederick Lawler pci_info(ctrl->pci_dev, format, ## arg)
58f98ca311STaku Izumi #define ctrl_warn(ctrl, format, arg...) \
597506dc79SFrederick Lawler pci_warn(ctrl->pci_dev, format, ## arg)
60f98ca311STaku Izumi
61f98ca311STaku Izumi
62bbe779dbSKenji Kaneshige #define SLOT_NAME_SIZE 10
631da177e4SLinus Torvalds struct slot {
641da177e4SLinus Torvalds u8 bus;
651da177e4SLinus Torvalds u8 device;
662178bfadSrajesh.shah@intel.com u16 status;
671da177e4SLinus Torvalds u32 number;
681da177e4SLinus Torvalds u8 is_a_board;
691da177e4SLinus Torvalds u8 state;
70a7da2161SLukas Wunner u8 attention_save;
711da177e4SLinus Torvalds u8 presence_save;
72a7da2161SLukas Wunner u8 latch_save;
732178bfadSrajesh.shah@intel.com u8 pwr_save;
741da177e4SLinus Torvalds struct controller *ctrl;
75bd790082SJulia Lawall const struct hpc_ops *hpc_ops;
76125450f8SLukas Wunner struct hotplug_slot hotplug_slot;
771da177e4SLinus Torvalds struct list_head slot_list;
78c4028958SDavid Howells struct delayed_work work; /* work for button event */
79a246fa4eSKenji Kaneshige struct mutex lock;
80f652e7d2SBjorn Helgaas struct workqueue_struct *wq;
8166f17055SAlex Chiang u8 hp_slot;
821da177e4SLinus Torvalds };
831da177e4SLinus Torvalds
841da177e4SLinus Torvalds struct event_info {
851da177e4SLinus Torvalds u32 event_type;
86f7391f53SKenji Kaneshige struct slot *p_slot;
87f7391f53SKenji Kaneshige struct work_struct work;
881da177e4SLinus Torvalds };
891da177e4SLinus Torvalds
901da177e4SLinus Torvalds struct controller {
916aa4cdd0SIngo Molnar struct mutex crit_sect; /* critical section mutex */
92d29aaddaSKenji Kaneshige struct mutex cmd_lock; /* command lock */
931da177e4SLinus Torvalds int num_slots; /* Number of slots on ctlr */
941da177e4SLinus Torvalds int slot_num_inc; /* 1 or -1 */
951da177e4SLinus Torvalds struct pci_dev *pci_dev;
965b1a960dSKenji Kaneshige struct list_head slot_list;
97bd790082SJulia Lawall const struct hpc_ops *hpc_ops;
981da177e4SLinus Torvalds wait_queue_head_t queue; /* sleep & wake process */
991da177e4SLinus Torvalds u8 slot_device_offset;
10053044f35SKeck, David u32 pcix_misc2_reg; /* for amd pogo errata */
1011da177e4SLinus Torvalds u32 first_slot; /* First physical slot number */
1020455986cSKenji Kaneshige u32 cap_offset;
1030455986cSKenji Kaneshige unsigned long mmio_base;
1040455986cSKenji Kaneshige unsigned long mmio_size;
1050abe68ceSKenji Kaneshige void __iomem *creg;
1060abe68ceSKenji Kaneshige struct timer_list poll_timer;
1071da177e4SLinus Torvalds };
1081da177e4SLinus Torvalds
1091da177e4SLinus Torvalds /* Define AMD SHPC ID */
11053044f35SKeck, David #define PCI_DEVICE_ID_AMD_POGO_7458 0x7458
11153044f35SKeck, David
11245e829eaSStefan Assmann /* AMD PCI-X bridge registers */
11353044f35SKeck, David #define PCIX_MEM_BASE_LIMIT_OFFSET 0x1C
11453044f35SKeck, David #define PCIX_MISCII_OFFSET 0x48
11553044f35SKeck, David #define PCIX_MISC_BRIDGE_ERRORS_OFFSET 0x80
11653044f35SKeck, David
11753044f35SKeck, David /* AMD PCIX_MISCII masks and offsets */
11853044f35SKeck, David #define PERRNONFATALENABLE_MASK 0x00040000
11953044f35SKeck, David #define PERRFATALENABLE_MASK 0x00080000
12053044f35SKeck, David #define PERRFLOODENABLE_MASK 0x00100000
12153044f35SKeck, David #define SERRNONFATALENABLE_MASK 0x00200000
12253044f35SKeck, David #define SERRFATALENABLE_MASK 0x00400000
12353044f35SKeck, David
12453044f35SKeck, David /* AMD PCIX_MISC_BRIDGE_ERRORS masks and offsets */
12553044f35SKeck, David #define PERR_OBSERVED_MASK 0x00000001
12653044f35SKeck, David
12753044f35SKeck, David /* AMD PCIX_MEM_BASE_LIMIT masks */
12853044f35SKeck, David #define RSE_MASK 0x40000000
1291da177e4SLinus Torvalds
1301da177e4SLinus Torvalds #define INT_BUTTON_IGNORE 0
1311da177e4SLinus Torvalds #define INT_PRESENCE_ON 1
1321da177e4SLinus Torvalds #define INT_PRESENCE_OFF 2
1331da177e4SLinus Torvalds #define INT_SWITCH_CLOSE 3
1341da177e4SLinus Torvalds #define INT_SWITCH_OPEN 4
1351da177e4SLinus Torvalds #define INT_POWER_FAULT 5
1361da177e4SLinus Torvalds #define INT_POWER_FAULT_CLEAR 6
1371da177e4SLinus Torvalds #define INT_BUTTON_PRESS 7
1381da177e4SLinus Torvalds #define INT_BUTTON_RELEASE 8
1391da177e4SLinus Torvalds #define INT_BUTTON_CANCEL 9
1401da177e4SLinus Torvalds
1411da177e4SLinus Torvalds #define STATIC_STATE 0
1421da177e4SLinus Torvalds #define BLINKINGON_STATE 1
1431da177e4SLinus Torvalds #define BLINKINGOFF_STATE 2
1441da177e4SLinus Torvalds #define POWERON_STATE 3
1451da177e4SLinus Torvalds #define POWEROFF_STATE 4
1461da177e4SLinus Torvalds
1471da177e4SLinus Torvalds /* Error messages */
1481da177e4SLinus Torvalds #define INTERLOCK_OPEN 0x00000002
1491da177e4SLinus Torvalds #define ADD_NOT_SUPPORTED 0x00000003
1501da177e4SLinus Torvalds #define CARD_FUNCTIONING 0x00000005
1511da177e4SLinus Torvalds #define ADAPTER_NOT_SAME 0x00000006
1521da177e4SLinus Torvalds #define NO_ADAPTER_PRESENT 0x00000009
1531da177e4SLinus Torvalds #define NOT_ENOUGH_RESOURCES 0x0000000B
1541da177e4SLinus Torvalds #define DEVICE_TYPE_NOT_SUPPORTED 0x0000000C
1551da177e4SLinus Torvalds #define WRONG_BUS_FREQUENCY 0x0000000D
1561da177e4SLinus Torvalds #define POWER_FAILURE 0x0000000E
1571da177e4SLinus Torvalds
158f39d5b72SBjorn Helgaas int __must_check shpchp_create_ctrl_files(struct controller *ctrl);
159f39d5b72SBjorn Helgaas void shpchp_remove_ctrl_files(struct controller *ctrl);
160f39d5b72SBjorn Helgaas int shpchp_sysfs_enable_slot(struct slot *slot);
161f39d5b72SBjorn Helgaas int shpchp_sysfs_disable_slot(struct slot *slot);
162f39d5b72SBjorn Helgaas u8 shpchp_handle_attention_button(u8 hp_slot, struct controller *ctrl);
163f39d5b72SBjorn Helgaas u8 shpchp_handle_switch_change(u8 hp_slot, struct controller *ctrl);
164f39d5b72SBjorn Helgaas u8 shpchp_handle_presence_change(u8 hp_slot, struct controller *ctrl);
165f39d5b72SBjorn Helgaas u8 shpchp_handle_power_fault(u8 hp_slot, struct controller *ctrl);
166f39d5b72SBjorn Helgaas int shpchp_configure_device(struct slot *p_slot);
167cfbd83d0SKrzysztof Wilczynski void shpchp_unconfigure_device(struct slot *p_slot);
168f39d5b72SBjorn Helgaas void cleanup_slots(struct controller *ctrl);
169f39d5b72SBjorn Helgaas void shpchp_queue_pushbutton_work(struct work_struct *work);
170f39d5b72SBjorn Helgaas int shpc_init(struct controller *ctrl, struct pci_dev *pdev);
171783c49fcSKristen Accardi
slot_name(struct slot * slot)17266f17055SAlex Chiang static inline const char *slot_name(struct slot *slot)
17366f17055SAlex Chiang {
174125450f8SLukas Wunner return hotplug_slot_name(&slot->hotplug_slot);
17566f17055SAlex Chiang }
17666f17055SAlex Chiang
1771da177e4SLinus Torvalds struct ctrl_reg {
1781da177e4SLinus Torvalds volatile u32 base_offset;
1791da177e4SLinus Torvalds volatile u32 slot_avail1;
1801da177e4SLinus Torvalds volatile u32 slot_avail2;
1811da177e4SLinus Torvalds volatile u32 slot_config;
1821da177e4SLinus Torvalds volatile u16 sec_bus_config;
1831da177e4SLinus Torvalds volatile u8 msi_ctrl;
1841da177e4SLinus Torvalds volatile u8 prog_interface;
1851da177e4SLinus Torvalds volatile u16 cmd;
1861da177e4SLinus Torvalds volatile u16 cmd_status;
1871da177e4SLinus Torvalds volatile u32 intr_loc;
1881da177e4SLinus Torvalds volatile u32 serr_loc;
1891da177e4SLinus Torvalds volatile u32 serr_intr_enable;
1901da177e4SLinus Torvalds volatile u32 slot1;
1911da177e4SLinus Torvalds } __attribute__ ((packed));
1921da177e4SLinus Torvalds
1931da177e4SLinus Torvalds /* offsets to the controller registers based on the above structure layout */
1941da177e4SLinus Torvalds enum ctrl_offsets {
1951da177e4SLinus Torvalds BASE_OFFSET = offsetof(struct ctrl_reg, base_offset),
1961da177e4SLinus Torvalds SLOT_AVAIL1 = offsetof(struct ctrl_reg, slot_avail1),
1971da177e4SLinus Torvalds SLOT_AVAIL2 = offsetof(struct ctrl_reg, slot_avail2),
1981da177e4SLinus Torvalds SLOT_CONFIG = offsetof(struct ctrl_reg, slot_config),
1991da177e4SLinus Torvalds SEC_BUS_CONFIG = offsetof(struct ctrl_reg, sec_bus_config),
2001da177e4SLinus Torvalds MSI_CTRL = offsetof(struct ctrl_reg, msi_ctrl),
2011da177e4SLinus Torvalds PROG_INTERFACE = offsetof(struct ctrl_reg, prog_interface),
2021da177e4SLinus Torvalds CMD = offsetof(struct ctrl_reg, cmd),
2031da177e4SLinus Torvalds CMD_STATUS = offsetof(struct ctrl_reg, cmd_status),
2041da177e4SLinus Torvalds INTR_LOC = offsetof(struct ctrl_reg, intr_loc),
2051da177e4SLinus Torvalds SERR_LOC = offsetof(struct ctrl_reg, serr_loc),
2061da177e4SLinus Torvalds SERR_INTR_ENABLE = offsetof(struct ctrl_reg, serr_intr_enable),
2071da177e4SLinus Torvalds SLOT1 = offsetof(struct ctrl_reg, slot1),
2081da177e4SLinus Torvalds };
2091da177e4SLinus Torvalds
get_slot(struct hotplug_slot * hotplug_slot)2108352e04eSKenji Kaneshige static inline struct slot *get_slot(struct hotplug_slot *hotplug_slot)
2111da177e4SLinus Torvalds {
212125450f8SLukas Wunner return container_of(hotplug_slot, struct slot, hotplug_slot);
2131da177e4SLinus Torvalds }
2141da177e4SLinus Torvalds
shpchp_find_slot(struct controller * ctrl,u8 device)2151da177e4SLinus Torvalds static inline struct slot *shpchp_find_slot(struct controller *ctrl, u8 device)
2161da177e4SLinus Torvalds {
2175b1a960dSKenji Kaneshige struct slot *slot;
2181da177e4SLinus Torvalds
2195b1a960dSKenji Kaneshige list_for_each_entry(slot, &ctrl->slot_list, slot_list) {
2205b1a960dSKenji Kaneshige if (slot->device == device)
2215b1a960dSKenji Kaneshige return slot;
2221da177e4SLinus Torvalds }
2231da177e4SLinus Torvalds
224be7bce25STaku Izumi ctrl_err(ctrl, "Slot (device=0x%02x) not found\n", device);
2255b1a960dSKenji Kaneshige return NULL;
2261da177e4SLinus Torvalds }
2271da177e4SLinus Torvalds
amd_pogo_errata_save_misc_reg(struct slot * p_slot)22853044f35SKeck, David static inline void amd_pogo_errata_save_misc_reg(struct slot *p_slot)
22953044f35SKeck, David {
23053044f35SKeck, David u32 pcix_misc2_temp;
23153044f35SKeck, David
23253044f35SKeck, David /* save MiscII register */
23353044f35SKeck, David pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp);
23453044f35SKeck, David
23553044f35SKeck, David p_slot->ctrl->pcix_misc2_reg = pcix_misc2_temp;
23653044f35SKeck, David
23753044f35SKeck, David /* clear SERR/PERR enable bits */
23853044f35SKeck, David pcix_misc2_temp &= ~SERRFATALENABLE_MASK;
23953044f35SKeck, David pcix_misc2_temp &= ~SERRNONFATALENABLE_MASK;
24053044f35SKeck, David pcix_misc2_temp &= ~PERRFLOODENABLE_MASK;
24153044f35SKeck, David pcix_misc2_temp &= ~PERRFATALENABLE_MASK;
24253044f35SKeck, David pcix_misc2_temp &= ~PERRNONFATALENABLE_MASK;
24353044f35SKeck, David pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp);
24453044f35SKeck, David }
24553044f35SKeck, David
amd_pogo_errata_restore_misc_reg(struct slot * p_slot)24653044f35SKeck, David static inline void amd_pogo_errata_restore_misc_reg(struct slot *p_slot)
24753044f35SKeck, David {
24853044f35SKeck, David u32 pcix_misc2_temp;
24953044f35SKeck, David u32 pcix_bridge_errors_reg;
25053044f35SKeck, David u32 pcix_mem_base_reg;
25153044f35SKeck, David u8 perr_set;
25253044f35SKeck, David u8 rse_set;
25353044f35SKeck, David
25453044f35SKeck, David /* write-one-to-clear Bridge_Errors[ PERR_OBSERVED ] */
25553044f35SKeck, David pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, &pcix_bridge_errors_reg);
25653044f35SKeck, David perr_set = pcix_bridge_errors_reg & PERR_OBSERVED_MASK;
25753044f35SKeck, David if (perr_set) {
258f98ca311STaku Izumi ctrl_dbg(p_slot->ctrl,
259be7bce25STaku Izumi "Bridge_Errors[ PERR_OBSERVED = %08X] (W1C)\n",
260be7bce25STaku Izumi perr_set);
26153044f35SKeck, David
26253044f35SKeck, David pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, perr_set);
26353044f35SKeck, David }
26453044f35SKeck, David
26553044f35SKeck, David /* write-one-to-clear Memory_Base_Limit[ RSE ] */
26653044f35SKeck, David pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, &pcix_mem_base_reg);
26753044f35SKeck, David rse_set = pcix_mem_base_reg & RSE_MASK;
26853044f35SKeck, David if (rse_set) {
269be7bce25STaku Izumi ctrl_dbg(p_slot->ctrl, "Memory_Base_Limit[ RSE ] (W1C)\n");
27053044f35SKeck, David
27153044f35SKeck, David pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, rse_set);
27253044f35SKeck, David }
27353044f35SKeck, David /* restore MiscII register */
27453044f35SKeck, David pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp);
27553044f35SKeck, David
27653044f35SKeck, David if (p_slot->ctrl->pcix_misc2_reg & SERRFATALENABLE_MASK)
27753044f35SKeck, David pcix_misc2_temp |= SERRFATALENABLE_MASK;
27853044f35SKeck, David else
27953044f35SKeck, David pcix_misc2_temp &= ~SERRFATALENABLE_MASK;
28053044f35SKeck, David
28153044f35SKeck, David if (p_slot->ctrl->pcix_misc2_reg & SERRNONFATALENABLE_MASK)
28253044f35SKeck, David pcix_misc2_temp |= SERRNONFATALENABLE_MASK;
28353044f35SKeck, David else
28453044f35SKeck, David pcix_misc2_temp &= ~SERRNONFATALENABLE_MASK;
28553044f35SKeck, David
28653044f35SKeck, David if (p_slot->ctrl->pcix_misc2_reg & PERRFLOODENABLE_MASK)
28753044f35SKeck, David pcix_misc2_temp |= PERRFLOODENABLE_MASK;
28853044f35SKeck, David else
28953044f35SKeck, David pcix_misc2_temp &= ~PERRFLOODENABLE_MASK;
29053044f35SKeck, David
29153044f35SKeck, David if (p_slot->ctrl->pcix_misc2_reg & PERRFATALENABLE_MASK)
29253044f35SKeck, David pcix_misc2_temp |= PERRFATALENABLE_MASK;
29353044f35SKeck, David else
29453044f35SKeck, David pcix_misc2_temp &= ~PERRFATALENABLE_MASK;
29553044f35SKeck, David
29653044f35SKeck, David if (p_slot->ctrl->pcix_misc2_reg & PERRNONFATALENABLE_MASK)
29753044f35SKeck, David pcix_misc2_temp |= PERRNONFATALENABLE_MASK;
29853044f35SKeck, David else
29953044f35SKeck, David pcix_misc2_temp &= ~PERRNONFATALENABLE_MASK;
30053044f35SKeck, David pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp);
30153044f35SKeck, David }
30253044f35SKeck, David
3031da177e4SLinus Torvalds struct hpc_ops {
3041da177e4SLinus Torvalds int (*power_on_slot)(struct slot *slot);
3051da177e4SLinus Torvalds int (*slot_enable)(struct slot *slot);
3061da177e4SLinus Torvalds int (*slot_disable)(struct slot *slot);
3071da177e4SLinus Torvalds int (*set_bus_speed_mode)(struct slot *slot, enum pci_bus_speed speed);
3081da177e4SLinus Torvalds int (*get_power_status)(struct slot *slot, u8 *status);
3091da177e4SLinus Torvalds int (*get_attention_status)(struct slot *slot, u8 *status);
3101da177e4SLinus Torvalds int (*set_attention_status)(struct slot *slot, u8 status);
3111da177e4SLinus Torvalds int (*get_latch_status)(struct slot *slot, u8 *status);
3121da177e4SLinus Torvalds int (*get_adapter_status)(struct slot *slot, u8 *status);
3131da177e4SLinus Torvalds int (*get_adapter_speed)(struct slot *slot, enum pci_bus_speed *speed);
3141da177e4SLinus Torvalds int (*get_prog_int)(struct slot *slot, u8 *prog_int);
3151da177e4SLinus Torvalds int (*query_power_fault)(struct slot *slot);
3161da177e4SLinus Torvalds void (*green_led_on)(struct slot *slot);
3171da177e4SLinus Torvalds void (*green_led_off)(struct slot *slot);
3181da177e4SLinus Torvalds void (*green_led_blink)(struct slot *slot);
3191da177e4SLinus Torvalds void (*release_ctlr)(struct controller *ctrl);
3201da177e4SLinus Torvalds int (*check_cmd_status)(struct controller *ctrl);
3211da177e4SLinus Torvalds };
3221da177e4SLinus Torvalds
3231da177e4SLinus Torvalds #endif /* _SHPCHP_H */
324