1 /* 2 * PCI Express PCI Hot Plug Driver 3 * 4 * Copyright (C) 1995,2001 Compaq Computer Corporation 5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com) 6 * Copyright (C) 2001 IBM Corp. 7 * Copyright (C) 2003-2004 Intel Corporation 8 * 9 * All rights reserved. 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or (at 14 * your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 19 * NON INFRINGEMENT. See the GNU General Public License for more 20 * details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 25 * 26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com> 27 * 28 */ 29 30 #include <linux/kernel.h> 31 #include <linux/module.h> 32 #include <linux/types.h> 33 #include <linux/signal.h> 34 #include <linux/jiffies.h> 35 #include <linux/timer.h> 36 #include <linux/pci.h> 37 #include <linux/interrupt.h> 38 #include <linux/time.h> 39 40 #include "../pci.h" 41 #include "pciehp.h" 42 43 static atomic_t pciehp_num_controllers = ATOMIC_INIT(0); 44 45 static inline int pciehp_readw(struct controller *ctrl, int reg, u16 *value) 46 { 47 struct pci_dev *dev = ctrl->pcie->port; 48 return pci_read_config_word(dev, ctrl->cap_base + reg, value); 49 } 50 51 static inline int pciehp_readl(struct controller *ctrl, int reg, u32 *value) 52 { 53 struct pci_dev *dev = ctrl->pcie->port; 54 return pci_read_config_dword(dev, ctrl->cap_base + reg, value); 55 } 56 57 static inline int pciehp_writew(struct controller *ctrl, int reg, u16 value) 58 { 59 struct pci_dev *dev = ctrl->pcie->port; 60 return pci_write_config_word(dev, ctrl->cap_base + reg, value); 61 } 62 63 static inline int pciehp_writel(struct controller *ctrl, int reg, u32 value) 64 { 65 struct pci_dev *dev = ctrl->pcie->port; 66 return pci_write_config_dword(dev, ctrl->cap_base + reg, value); 67 } 68 69 /* Power Control Command */ 70 #define POWER_ON 0 71 #define POWER_OFF PCI_EXP_SLTCTL_PCC 72 73 static irqreturn_t pcie_isr(int irq, void *dev_id); 74 static void start_int_poll_timer(struct controller *ctrl, int sec); 75 76 /* This is the interrupt polling timeout function. */ 77 static void int_poll_timeout(unsigned long data) 78 { 79 struct controller *ctrl = (struct controller *)data; 80 81 /* Poll for interrupt events. regs == NULL => polling */ 82 pcie_isr(0, ctrl); 83 84 init_timer(&ctrl->poll_timer); 85 if (!pciehp_poll_time) 86 pciehp_poll_time = 2; /* default polling interval is 2 sec */ 87 88 start_int_poll_timer(ctrl, pciehp_poll_time); 89 } 90 91 /* This function starts the interrupt polling timer. */ 92 static void start_int_poll_timer(struct controller *ctrl, int sec) 93 { 94 /* Clamp to sane value */ 95 if ((sec <= 0) || (sec > 60)) 96 sec = 2; 97 98 ctrl->poll_timer.function = &int_poll_timeout; 99 ctrl->poll_timer.data = (unsigned long)ctrl; 100 ctrl->poll_timer.expires = jiffies + sec * HZ; 101 add_timer(&ctrl->poll_timer); 102 } 103 104 static inline int pciehp_request_irq(struct controller *ctrl) 105 { 106 int retval, irq = ctrl->pcie->irq; 107 108 /* Install interrupt polling timer. Start with 10 sec delay */ 109 if (pciehp_poll_mode) { 110 init_timer(&ctrl->poll_timer); 111 start_int_poll_timer(ctrl, 10); 112 return 0; 113 } 114 115 /* Installs the interrupt handler */ 116 retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl); 117 if (retval) 118 ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n", 119 irq); 120 return retval; 121 } 122 123 static inline void pciehp_free_irq(struct controller *ctrl) 124 { 125 if (pciehp_poll_mode) 126 del_timer_sync(&ctrl->poll_timer); 127 else 128 free_irq(ctrl->pcie->irq, ctrl); 129 } 130 131 static int pcie_poll_cmd(struct controller *ctrl) 132 { 133 u16 slot_status; 134 int err, timeout = 1000; 135 136 err = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); 137 if (!err && (slot_status & PCI_EXP_SLTSTA_CC)) { 138 pciehp_writew(ctrl, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_CC); 139 return 1; 140 } 141 while (timeout > 0) { 142 msleep(10); 143 timeout -= 10; 144 err = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); 145 if (!err && (slot_status & PCI_EXP_SLTSTA_CC)) { 146 pciehp_writew(ctrl, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_CC); 147 return 1; 148 } 149 } 150 return 0; /* timeout */ 151 } 152 153 static void pcie_wait_cmd(struct controller *ctrl, int poll) 154 { 155 unsigned int msecs = pciehp_poll_mode ? 2500 : 1000; 156 unsigned long timeout = msecs_to_jiffies(msecs); 157 int rc; 158 159 if (poll) 160 rc = pcie_poll_cmd(ctrl); 161 else 162 rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout); 163 if (!rc) 164 ctrl_dbg(ctrl, "Command not completed in 1000 msec\n"); 165 } 166 167 /** 168 * pcie_write_cmd - Issue controller command 169 * @ctrl: controller to which the command is issued 170 * @cmd: command value written to slot control register 171 * @mask: bitmask of slot control register to be modified 172 */ 173 static int pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask) 174 { 175 int retval = 0; 176 u16 slot_status; 177 u16 slot_ctrl; 178 179 mutex_lock(&ctrl->ctrl_lock); 180 181 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); 182 if (retval) { 183 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n", 184 __func__); 185 goto out; 186 } 187 188 if (slot_status & PCI_EXP_SLTSTA_CC) { 189 if (!ctrl->no_cmd_complete) { 190 /* 191 * After 1 sec and CMD_COMPLETED still not set, just 192 * proceed forward to issue the next command according 193 * to spec. Just print out the error message. 194 */ 195 ctrl_dbg(ctrl, "CMD_COMPLETED not clear after 1 sec\n"); 196 } else if (!NO_CMD_CMPL(ctrl)) { 197 /* 198 * This controller semms to notify of command completed 199 * event even though it supports none of power 200 * controller, attention led, power led and EMI. 201 */ 202 ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Need to " 203 "wait for command completed event.\n"); 204 ctrl->no_cmd_complete = 0; 205 } else { 206 ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Maybe " 207 "the controller is broken.\n"); 208 } 209 } 210 211 retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl); 212 if (retval) { 213 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__); 214 goto out; 215 } 216 217 slot_ctrl &= ~mask; 218 slot_ctrl |= (cmd & mask); 219 ctrl->cmd_busy = 1; 220 smp_mb(); 221 retval = pciehp_writew(ctrl, PCI_EXP_SLTCTL, slot_ctrl); 222 if (retval) 223 ctrl_err(ctrl, "Cannot write to SLOTCTRL register\n"); 224 225 /* 226 * Wait for command completion. 227 */ 228 if (!retval && !ctrl->no_cmd_complete) { 229 int poll = 0; 230 /* 231 * if hotplug interrupt is not enabled or command 232 * completed interrupt is not enabled, we need to poll 233 * command completed event. 234 */ 235 if (!(slot_ctrl & PCI_EXP_SLTCTL_HPIE) || 236 !(slot_ctrl & PCI_EXP_SLTCTL_CCIE)) 237 poll = 1; 238 pcie_wait_cmd(ctrl, poll); 239 } 240 out: 241 mutex_unlock(&ctrl->ctrl_lock); 242 return retval; 243 } 244 245 static inline int check_link_active(struct controller *ctrl) 246 { 247 u16 link_status; 248 249 if (pciehp_readw(ctrl, PCI_EXP_LNKSTA, &link_status)) 250 return 0; 251 return !!(link_status & PCI_EXP_LNKSTA_DLLLA); 252 } 253 254 static void pcie_wait_link_active(struct controller *ctrl) 255 { 256 int timeout = 1000; 257 258 if (check_link_active(ctrl)) 259 return; 260 while (timeout > 0) { 261 msleep(10); 262 timeout -= 10; 263 if (check_link_active(ctrl)) 264 return; 265 } 266 ctrl_dbg(ctrl, "Data Link Layer Link Active not set in 1000 msec\n"); 267 } 268 269 int pciehp_check_link_status(struct controller *ctrl) 270 { 271 u16 lnk_status; 272 int retval = 0; 273 274 /* 275 * Data Link Layer Link Active Reporting must be capable for 276 * hot-plug capable downstream port. But old controller might 277 * not implement it. In this case, we wait for 1000 ms. 278 */ 279 if (ctrl->link_active_reporting){ 280 /* Wait for Data Link Layer Link Active bit to be set */ 281 pcie_wait_link_active(ctrl); 282 /* 283 * We must wait for 100 ms after the Data Link Layer 284 * Link Active bit reads 1b before initiating a 285 * configuration access to the hot added device. 286 */ 287 msleep(100); 288 } else 289 msleep(1000); 290 291 retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status); 292 if (retval) { 293 ctrl_err(ctrl, "Cannot read LNKSTATUS register\n"); 294 return retval; 295 } 296 297 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status); 298 if ((lnk_status & PCI_EXP_LNKSTA_LT) || 299 !(lnk_status & PCI_EXP_LNKSTA_NLW)) { 300 ctrl_err(ctrl, "Link Training Error occurs \n"); 301 retval = -1; 302 return retval; 303 } 304 305 return retval; 306 } 307 308 int pciehp_get_attention_status(struct slot *slot, u8 *status) 309 { 310 struct controller *ctrl = slot->ctrl; 311 u16 slot_ctrl; 312 u8 atten_led_state; 313 int retval = 0; 314 315 retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl); 316 if (retval) { 317 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__); 318 return retval; 319 } 320 321 ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", 322 __func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_ctrl); 323 324 atten_led_state = (slot_ctrl & PCI_EXP_SLTCTL_AIC) >> 6; 325 326 switch (atten_led_state) { 327 case 0: 328 *status = 0xFF; /* Reserved */ 329 break; 330 case 1: 331 *status = 1; /* On */ 332 break; 333 case 2: 334 *status = 2; /* Blink */ 335 break; 336 case 3: 337 *status = 0; /* Off */ 338 break; 339 default: 340 *status = 0xFF; 341 break; 342 } 343 344 return 0; 345 } 346 347 int pciehp_get_power_status(struct slot *slot, u8 *status) 348 { 349 struct controller *ctrl = slot->ctrl; 350 u16 slot_ctrl; 351 u8 pwr_state; 352 int retval = 0; 353 354 retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl); 355 if (retval) { 356 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__); 357 return retval; 358 } 359 ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", 360 __func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_ctrl); 361 362 pwr_state = (slot_ctrl & PCI_EXP_SLTCTL_PCC) >> 10; 363 364 switch (pwr_state) { 365 case 0: 366 *status = 1; 367 break; 368 case 1: 369 *status = 0; 370 break; 371 default: 372 *status = 0xFF; 373 break; 374 } 375 376 return retval; 377 } 378 379 int pciehp_get_latch_status(struct slot *slot, u8 *status) 380 { 381 struct controller *ctrl = slot->ctrl; 382 u16 slot_status; 383 int retval; 384 385 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); 386 if (retval) { 387 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n", 388 __func__); 389 return retval; 390 } 391 *status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS); 392 return 0; 393 } 394 395 int pciehp_get_adapter_status(struct slot *slot, u8 *status) 396 { 397 struct controller *ctrl = slot->ctrl; 398 u16 slot_status; 399 int retval; 400 401 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); 402 if (retval) { 403 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n", 404 __func__); 405 return retval; 406 } 407 *status = !!(slot_status & PCI_EXP_SLTSTA_PDS); 408 return 0; 409 } 410 411 int pciehp_query_power_fault(struct slot *slot) 412 { 413 struct controller *ctrl = slot->ctrl; 414 u16 slot_status; 415 int retval; 416 417 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); 418 if (retval) { 419 ctrl_err(ctrl, "Cannot check for power fault\n"); 420 return retval; 421 } 422 return !!(slot_status & PCI_EXP_SLTSTA_PFD); 423 } 424 425 int pciehp_set_attention_status(struct slot *slot, u8 value) 426 { 427 struct controller *ctrl = slot->ctrl; 428 u16 slot_cmd; 429 u16 cmd_mask; 430 int rc; 431 432 cmd_mask = PCI_EXP_SLTCTL_AIC; 433 switch (value) { 434 case 0 : /* turn off */ 435 slot_cmd = 0x00C0; 436 break; 437 case 1: /* turn on */ 438 slot_cmd = 0x0040; 439 break; 440 case 2: /* turn blink */ 441 slot_cmd = 0x0080; 442 break; 443 default: 444 return -1; 445 } 446 rc = pcie_write_cmd(ctrl, slot_cmd, cmd_mask); 447 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", 448 __func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_cmd); 449 450 return rc; 451 } 452 453 void pciehp_green_led_on(struct slot *slot) 454 { 455 struct controller *ctrl = slot->ctrl; 456 u16 slot_cmd; 457 u16 cmd_mask; 458 459 slot_cmd = 0x0100; 460 cmd_mask = PCI_EXP_SLTCTL_PIC; 461 pcie_write_cmd(ctrl, slot_cmd, cmd_mask); 462 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", 463 __func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_cmd); 464 } 465 466 void pciehp_green_led_off(struct slot *slot) 467 { 468 struct controller *ctrl = slot->ctrl; 469 u16 slot_cmd; 470 u16 cmd_mask; 471 472 slot_cmd = 0x0300; 473 cmd_mask = PCI_EXP_SLTCTL_PIC; 474 pcie_write_cmd(ctrl, slot_cmd, cmd_mask); 475 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", 476 __func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_cmd); 477 } 478 479 void pciehp_green_led_blink(struct slot *slot) 480 { 481 struct controller *ctrl = slot->ctrl; 482 u16 slot_cmd; 483 u16 cmd_mask; 484 485 slot_cmd = 0x0200; 486 cmd_mask = PCI_EXP_SLTCTL_PIC; 487 pcie_write_cmd(ctrl, slot_cmd, cmd_mask); 488 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", 489 __func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_cmd); 490 } 491 492 int pciehp_power_on_slot(struct slot * slot) 493 { 494 struct controller *ctrl = slot->ctrl; 495 u16 slot_cmd; 496 u16 cmd_mask; 497 u16 slot_status; 498 int retval = 0; 499 500 /* Clear sticky power-fault bit from previous power failures */ 501 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); 502 if (retval) { 503 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n", 504 __func__); 505 return retval; 506 } 507 slot_status &= PCI_EXP_SLTSTA_PFD; 508 if (slot_status) { 509 retval = pciehp_writew(ctrl, PCI_EXP_SLTSTA, slot_status); 510 if (retval) { 511 ctrl_err(ctrl, 512 "%s: Cannot write to SLOTSTATUS register\n", 513 __func__); 514 return retval; 515 } 516 } 517 518 slot_cmd = POWER_ON; 519 cmd_mask = PCI_EXP_SLTCTL_PCC; 520 if (!pciehp_poll_mode) { 521 /* Enable power fault detection turned off at power off time */ 522 slot_cmd |= PCI_EXP_SLTCTL_PFDE; 523 cmd_mask |= PCI_EXP_SLTCTL_PFDE; 524 } 525 526 retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask); 527 if (retval) { 528 ctrl_err(ctrl, "Write %x command failed!\n", slot_cmd); 529 return retval; 530 } 531 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", 532 __func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_cmd); 533 534 ctrl->power_fault_detected = 0; 535 return retval; 536 } 537 538 static inline int pcie_mask_bad_dllp(struct controller *ctrl) 539 { 540 struct pci_dev *dev = ctrl->pcie->port; 541 int pos; 542 u32 reg; 543 544 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); 545 if (!pos) 546 return 0; 547 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, ®); 548 if (reg & PCI_ERR_COR_BAD_DLLP) 549 return 0; 550 reg |= PCI_ERR_COR_BAD_DLLP; 551 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg); 552 return 1; 553 } 554 555 static inline void pcie_unmask_bad_dllp(struct controller *ctrl) 556 { 557 struct pci_dev *dev = ctrl->pcie->port; 558 u32 reg; 559 int pos; 560 561 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); 562 if (!pos) 563 return; 564 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, ®); 565 if (!(reg & PCI_ERR_COR_BAD_DLLP)) 566 return; 567 reg &= ~PCI_ERR_COR_BAD_DLLP; 568 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg); 569 } 570 571 int pciehp_power_off_slot(struct slot * slot) 572 { 573 struct controller *ctrl = slot->ctrl; 574 u16 slot_cmd; 575 u16 cmd_mask; 576 int retval = 0; 577 int changed; 578 579 /* 580 * Set Bad DLLP Mask bit in Correctable Error Mask 581 * Register. This is the workaround against Bad DLLP error 582 * that sometimes happens during turning power off the slot 583 * which conforms to PCI Express 1.0a spec. 584 */ 585 changed = pcie_mask_bad_dllp(ctrl); 586 587 slot_cmd = POWER_OFF; 588 cmd_mask = PCI_EXP_SLTCTL_PCC; 589 if (!pciehp_poll_mode) { 590 /* Disable power fault detection */ 591 slot_cmd &= ~PCI_EXP_SLTCTL_PFDE; 592 cmd_mask |= PCI_EXP_SLTCTL_PFDE; 593 } 594 595 retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask); 596 if (retval) { 597 ctrl_err(ctrl, "Write command failed!\n"); 598 retval = -1; 599 goto out; 600 } 601 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", 602 __func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_cmd); 603 out: 604 if (changed) 605 pcie_unmask_bad_dllp(ctrl); 606 607 return retval; 608 } 609 610 static irqreturn_t pcie_isr(int irq, void *dev_id) 611 { 612 struct controller *ctrl = (struct controller *)dev_id; 613 struct slot *slot = ctrl->slot; 614 u16 detected, intr_loc; 615 616 /* 617 * In order to guarantee that all interrupt events are 618 * serviced, we need to re-inspect Slot Status register after 619 * clearing what is presumed to be the last pending interrupt. 620 */ 621 intr_loc = 0; 622 do { 623 if (pciehp_readw(ctrl, PCI_EXP_SLTSTA, &detected)) { 624 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS\n", 625 __func__); 626 return IRQ_NONE; 627 } 628 629 detected &= (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD | 630 PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC | 631 PCI_EXP_SLTSTA_CC); 632 detected &= ~intr_loc; 633 intr_loc |= detected; 634 if (!intr_loc) 635 return IRQ_NONE; 636 if (detected && pciehp_writew(ctrl, PCI_EXP_SLTSTA, intr_loc)) { 637 ctrl_err(ctrl, "%s: Cannot write to SLOTSTATUS\n", 638 __func__); 639 return IRQ_NONE; 640 } 641 } while (detected); 642 643 ctrl_dbg(ctrl, "%s: intr_loc %x\n", __func__, intr_loc); 644 645 /* Check Command Complete Interrupt Pending */ 646 if (intr_loc & PCI_EXP_SLTSTA_CC) { 647 ctrl->cmd_busy = 0; 648 smp_mb(); 649 wake_up(&ctrl->queue); 650 } 651 652 if (!(intr_loc & ~PCI_EXP_SLTSTA_CC)) 653 return IRQ_HANDLED; 654 655 /* Check MRL Sensor Changed */ 656 if (intr_loc & PCI_EXP_SLTSTA_MRLSC) 657 pciehp_handle_switch_change(slot); 658 659 /* Check Attention Button Pressed */ 660 if (intr_loc & PCI_EXP_SLTSTA_ABP) 661 pciehp_handle_attention_button(slot); 662 663 /* Check Presence Detect Changed */ 664 if (intr_loc & PCI_EXP_SLTSTA_PDC) 665 pciehp_handle_presence_change(slot); 666 667 /* Check Power Fault Detected */ 668 if ((intr_loc & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) { 669 ctrl->power_fault_detected = 1; 670 pciehp_handle_power_fault(slot); 671 } 672 return IRQ_HANDLED; 673 } 674 675 int pciehp_get_max_link_speed(struct slot *slot, enum pci_bus_speed *value) 676 { 677 struct controller *ctrl = slot->ctrl; 678 enum pcie_link_speed lnk_speed; 679 u32 lnk_cap; 680 int retval = 0; 681 682 retval = pciehp_readl(ctrl, PCI_EXP_LNKCAP, &lnk_cap); 683 if (retval) { 684 ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__); 685 return retval; 686 } 687 688 switch (lnk_cap & 0x000F) { 689 case 1: 690 lnk_speed = PCIE_2_5GB; 691 break; 692 case 2: 693 lnk_speed = PCIE_5_0GB; 694 break; 695 default: 696 lnk_speed = PCIE_LNK_SPEED_UNKNOWN; 697 break; 698 } 699 700 *value = lnk_speed; 701 ctrl_dbg(ctrl, "Max link speed = %d\n", lnk_speed); 702 703 return retval; 704 } 705 706 int pciehp_get_max_lnk_width(struct slot *slot, 707 enum pcie_link_width *value) 708 { 709 struct controller *ctrl = slot->ctrl; 710 enum pcie_link_width lnk_wdth; 711 u32 lnk_cap; 712 int retval = 0; 713 714 retval = pciehp_readl(ctrl, PCI_EXP_LNKCAP, &lnk_cap); 715 if (retval) { 716 ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__); 717 return retval; 718 } 719 720 switch ((lnk_cap & PCI_EXP_LNKSTA_NLW) >> 4){ 721 case 0: 722 lnk_wdth = PCIE_LNK_WIDTH_RESRV; 723 break; 724 case 1: 725 lnk_wdth = PCIE_LNK_X1; 726 break; 727 case 2: 728 lnk_wdth = PCIE_LNK_X2; 729 break; 730 case 4: 731 lnk_wdth = PCIE_LNK_X4; 732 break; 733 case 8: 734 lnk_wdth = PCIE_LNK_X8; 735 break; 736 case 12: 737 lnk_wdth = PCIE_LNK_X12; 738 break; 739 case 16: 740 lnk_wdth = PCIE_LNK_X16; 741 break; 742 case 32: 743 lnk_wdth = PCIE_LNK_X32; 744 break; 745 default: 746 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; 747 break; 748 } 749 750 *value = lnk_wdth; 751 ctrl_dbg(ctrl, "Max link width = %d\n", lnk_wdth); 752 753 return retval; 754 } 755 756 int pciehp_get_cur_link_speed(struct slot *slot, enum pci_bus_speed *value) 757 { 758 struct controller *ctrl = slot->ctrl; 759 enum pcie_link_speed lnk_speed = PCI_SPEED_UNKNOWN; 760 int retval = 0; 761 u16 lnk_status; 762 763 retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status); 764 if (retval) { 765 ctrl_err(ctrl, "%s: Cannot read LNKSTATUS register\n", 766 __func__); 767 return retval; 768 } 769 770 switch (lnk_status & PCI_EXP_LNKSTA_CLS) { 771 case 1: 772 lnk_speed = PCIE_2_5GB; 773 break; 774 case 2: 775 lnk_speed = PCIE_5_0GB; 776 break; 777 default: 778 lnk_speed = PCIE_LNK_SPEED_UNKNOWN; 779 break; 780 } 781 782 *value = lnk_speed; 783 ctrl_dbg(ctrl, "Current link speed = %d\n", lnk_speed); 784 785 return retval; 786 } 787 788 int pciehp_get_cur_lnk_width(struct slot *slot, 789 enum pcie_link_width *value) 790 { 791 struct controller *ctrl = slot->ctrl; 792 enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; 793 int retval = 0; 794 u16 lnk_status; 795 796 retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status); 797 if (retval) { 798 ctrl_err(ctrl, "%s: Cannot read LNKSTATUS register\n", 799 __func__); 800 return retval; 801 } 802 803 switch ((lnk_status & PCI_EXP_LNKSTA_NLW) >> 4){ 804 case 0: 805 lnk_wdth = PCIE_LNK_WIDTH_RESRV; 806 break; 807 case 1: 808 lnk_wdth = PCIE_LNK_X1; 809 break; 810 case 2: 811 lnk_wdth = PCIE_LNK_X2; 812 break; 813 case 4: 814 lnk_wdth = PCIE_LNK_X4; 815 break; 816 case 8: 817 lnk_wdth = PCIE_LNK_X8; 818 break; 819 case 12: 820 lnk_wdth = PCIE_LNK_X12; 821 break; 822 case 16: 823 lnk_wdth = PCIE_LNK_X16; 824 break; 825 case 32: 826 lnk_wdth = PCIE_LNK_X32; 827 break; 828 default: 829 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; 830 break; 831 } 832 833 *value = lnk_wdth; 834 ctrl_dbg(ctrl, "Current link width = %d\n", lnk_wdth); 835 836 return retval; 837 } 838 839 int pcie_enable_notification(struct controller *ctrl) 840 { 841 u16 cmd, mask; 842 843 cmd = PCI_EXP_SLTCTL_PDCE; 844 if (ATTN_BUTTN(ctrl)) 845 cmd |= PCI_EXP_SLTCTL_ABPE; 846 if (POWER_CTRL(ctrl)) 847 cmd |= PCI_EXP_SLTCTL_PFDE; 848 if (MRL_SENS(ctrl)) 849 cmd |= PCI_EXP_SLTCTL_MRLSCE; 850 if (!pciehp_poll_mode) 851 cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE; 852 853 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE | 854 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE | 855 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE); 856 857 if (pcie_write_cmd(ctrl, cmd, mask)) { 858 ctrl_err(ctrl, "Cannot enable software notification\n"); 859 return -1; 860 } 861 return 0; 862 } 863 864 static void pcie_disable_notification(struct controller *ctrl) 865 { 866 u16 mask; 867 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE | 868 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE | 869 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE); 870 if (pcie_write_cmd(ctrl, 0, mask)) 871 ctrl_warn(ctrl, "Cannot disable software notification\n"); 872 } 873 874 int pcie_init_notification(struct controller *ctrl) 875 { 876 if (pciehp_request_irq(ctrl)) 877 return -1; 878 if (pcie_enable_notification(ctrl)) { 879 pciehp_free_irq(ctrl); 880 return -1; 881 } 882 ctrl->notification_enabled = 1; 883 return 0; 884 } 885 886 static void pcie_shutdown_notification(struct controller *ctrl) 887 { 888 if (ctrl->notification_enabled) { 889 pcie_disable_notification(ctrl); 890 pciehp_free_irq(ctrl); 891 ctrl->notification_enabled = 0; 892 } 893 } 894 895 static int pcie_init_slot(struct controller *ctrl) 896 { 897 struct slot *slot; 898 899 slot = kzalloc(sizeof(*slot), GFP_KERNEL); 900 if (!slot) 901 return -ENOMEM; 902 903 slot->ctrl = ctrl; 904 mutex_init(&slot->lock); 905 INIT_DELAYED_WORK(&slot->work, pciehp_queue_pushbutton_work); 906 ctrl->slot = slot; 907 return 0; 908 } 909 910 static void pcie_cleanup_slot(struct controller *ctrl) 911 { 912 struct slot *slot = ctrl->slot; 913 cancel_delayed_work(&slot->work); 914 flush_scheduled_work(); 915 flush_workqueue(pciehp_wq); 916 kfree(slot); 917 } 918 919 static inline void dbg_ctrl(struct controller *ctrl) 920 { 921 int i; 922 u16 reg16; 923 struct pci_dev *pdev = ctrl->pcie->port; 924 925 if (!pciehp_debug) 926 return; 927 928 ctrl_info(ctrl, "Hotplug Controller:\n"); 929 ctrl_info(ctrl, " Seg/Bus/Dev/Func/IRQ : %s IRQ %d\n", 930 pci_name(pdev), pdev->irq); 931 ctrl_info(ctrl, " Vendor ID : 0x%04x\n", pdev->vendor); 932 ctrl_info(ctrl, " Device ID : 0x%04x\n", pdev->device); 933 ctrl_info(ctrl, " Subsystem ID : 0x%04x\n", 934 pdev->subsystem_device); 935 ctrl_info(ctrl, " Subsystem Vendor ID : 0x%04x\n", 936 pdev->subsystem_vendor); 937 ctrl_info(ctrl, " PCIe Cap offset : 0x%02x\n", ctrl->cap_base); 938 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 939 if (!pci_resource_len(pdev, i)) 940 continue; 941 ctrl_info(ctrl, " PCI resource [%d] : 0x%llx@0x%llx\n", 942 i, (unsigned long long)pci_resource_len(pdev, i), 943 (unsigned long long)pci_resource_start(pdev, i)); 944 } 945 ctrl_info(ctrl, "Slot Capabilities : 0x%08x\n", ctrl->slot_cap); 946 ctrl_info(ctrl, " Physical Slot Number : %d\n", PSN(ctrl)); 947 ctrl_info(ctrl, " Attention Button : %3s\n", 948 ATTN_BUTTN(ctrl) ? "yes" : "no"); 949 ctrl_info(ctrl, " Power Controller : %3s\n", 950 POWER_CTRL(ctrl) ? "yes" : "no"); 951 ctrl_info(ctrl, " MRL Sensor : %3s\n", 952 MRL_SENS(ctrl) ? "yes" : "no"); 953 ctrl_info(ctrl, " Attention Indicator : %3s\n", 954 ATTN_LED(ctrl) ? "yes" : "no"); 955 ctrl_info(ctrl, " Power Indicator : %3s\n", 956 PWR_LED(ctrl) ? "yes" : "no"); 957 ctrl_info(ctrl, " Hot-Plug Surprise : %3s\n", 958 HP_SUPR_RM(ctrl) ? "yes" : "no"); 959 ctrl_info(ctrl, " EMI Present : %3s\n", 960 EMI(ctrl) ? "yes" : "no"); 961 ctrl_info(ctrl, " Command Completed : %3s\n", 962 NO_CMD_CMPL(ctrl) ? "no" : "yes"); 963 pciehp_readw(ctrl, PCI_EXP_SLTSTA, ®16); 964 ctrl_info(ctrl, "Slot Status : 0x%04x\n", reg16); 965 pciehp_readw(ctrl, PCI_EXP_SLTCTL, ®16); 966 ctrl_info(ctrl, "Slot Control : 0x%04x\n", reg16); 967 } 968 969 struct controller *pcie_init(struct pcie_device *dev) 970 { 971 struct controller *ctrl; 972 u32 slot_cap, link_cap; 973 struct pci_dev *pdev = dev->port; 974 975 ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL); 976 if (!ctrl) { 977 dev_err(&dev->device, "%s: Out of memory\n", __func__); 978 goto abort; 979 } 980 ctrl->pcie = dev; 981 ctrl->cap_base = pci_find_capability(pdev, PCI_CAP_ID_EXP); 982 if (!ctrl->cap_base) { 983 ctrl_err(ctrl, "Cannot find PCI Express capability\n"); 984 goto abort_ctrl; 985 } 986 if (pciehp_readl(ctrl, PCI_EXP_SLTCAP, &slot_cap)) { 987 ctrl_err(ctrl, "Cannot read SLOTCAP register\n"); 988 goto abort_ctrl; 989 } 990 991 ctrl->slot_cap = slot_cap; 992 mutex_init(&ctrl->ctrl_lock); 993 init_waitqueue_head(&ctrl->queue); 994 dbg_ctrl(ctrl); 995 /* 996 * Controller doesn't notify of command completion if the "No 997 * Command Completed Support" bit is set in Slot Capability 998 * register or the controller supports none of power 999 * controller, attention led, power led and EMI. 1000 */ 1001 if (NO_CMD_CMPL(ctrl) || 1002 !(POWER_CTRL(ctrl) | ATTN_LED(ctrl) | PWR_LED(ctrl) | EMI(ctrl))) 1003 ctrl->no_cmd_complete = 1; 1004 1005 /* Check if Data Link Layer Link Active Reporting is implemented */ 1006 if (pciehp_readl(ctrl, PCI_EXP_LNKCAP, &link_cap)) { 1007 ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__); 1008 goto abort_ctrl; 1009 } 1010 if (link_cap & PCI_EXP_LNKCAP_DLLLARC) { 1011 ctrl_dbg(ctrl, "Link Active Reporting supported\n"); 1012 ctrl->link_active_reporting = 1; 1013 } 1014 1015 /* Clear all remaining event bits in Slot Status register */ 1016 if (pciehp_writew(ctrl, PCI_EXP_SLTSTA, 0x1f)) 1017 goto abort_ctrl; 1018 1019 /* Disable sotfware notification */ 1020 pcie_disable_notification(ctrl); 1021 1022 /* 1023 * If this is the first controller to be initialized, 1024 * initialize the pciehp work queue 1025 */ 1026 if (atomic_add_return(1, &pciehp_num_controllers) == 1) { 1027 pciehp_wq = create_singlethread_workqueue("pciehpd"); 1028 if (!pciehp_wq) 1029 goto abort_ctrl; 1030 } 1031 1032 ctrl_info(ctrl, "HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", 1033 pdev->vendor, pdev->device, pdev->subsystem_vendor, 1034 pdev->subsystem_device); 1035 1036 if (pcie_init_slot(ctrl)) 1037 goto abort_ctrl; 1038 1039 return ctrl; 1040 1041 abort_ctrl: 1042 kfree(ctrl); 1043 abort: 1044 return NULL; 1045 } 1046 1047 void pciehp_release_ctrl(struct controller *ctrl) 1048 { 1049 pcie_shutdown_notification(ctrl); 1050 pcie_cleanup_slot(ctrl); 1051 /* 1052 * If this is the last controller to be released, destroy the 1053 * pciehp work queue 1054 */ 1055 if (atomic_dec_and_test(&pciehp_num_controllers)) 1056 destroy_workqueue(pciehp_wq); 1057 kfree(ctrl); 1058 } 1059