1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * PCI Express PCI Hot Plug Driver 4 * 5 * Copyright (C) 1995,2001 Compaq Computer Corporation 6 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com) 7 * Copyright (C) 2001 IBM Corp. 8 * Copyright (C) 2003-2004 Intel Corporation 9 * 10 * All rights reserved. 11 * 12 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com> 13 */ 14 15 #define dev_fmt(fmt) "pciehp: " fmt 16 17 #include <linux/dmi.h> 18 #include <linux/kernel.h> 19 #include <linux/types.h> 20 #include <linux/jiffies.h> 21 #include <linux/kthread.h> 22 #include <linux/pci.h> 23 #include <linux/pm_runtime.h> 24 #include <linux/interrupt.h> 25 #include <linux/slab.h> 26 27 #include "../pci.h" 28 #include "pciehp.h" 29 30 static const struct dmi_system_id inband_presence_disabled_dmi_table[] = { 31 /* 32 * Match all Dell systems, as some Dell systems have inband 33 * presence disabled on NVMe slots (but don't support the bit to 34 * report it). Setting inband presence disabled should have no 35 * negative effect, except on broken hotplug slots that never 36 * assert presence detect--and those will still work, they will 37 * just have a bit of extra delay before being probed. 38 */ 39 { 40 .ident = "Dell System", 41 .matches = { 42 DMI_MATCH(DMI_OEM_STRING, "Dell System"), 43 }, 44 }, 45 {} 46 }; 47 48 static inline struct pci_dev *ctrl_dev(struct controller *ctrl) 49 { 50 return ctrl->pcie->port; 51 } 52 53 static irqreturn_t pciehp_isr(int irq, void *dev_id); 54 static irqreturn_t pciehp_ist(int irq, void *dev_id); 55 static int pciehp_poll(void *data); 56 57 static inline int pciehp_request_irq(struct controller *ctrl) 58 { 59 int retval, irq = ctrl->pcie->irq; 60 61 if (pciehp_poll_mode) { 62 ctrl->poll_thread = kthread_run(&pciehp_poll, ctrl, 63 "pciehp_poll-%s", 64 slot_name(ctrl)); 65 return PTR_ERR_OR_ZERO(ctrl->poll_thread); 66 } 67 68 /* Installs the interrupt handler */ 69 retval = request_threaded_irq(irq, pciehp_isr, pciehp_ist, 70 IRQF_SHARED, "pciehp", ctrl); 71 if (retval) 72 ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n", 73 irq); 74 return retval; 75 } 76 77 static inline void pciehp_free_irq(struct controller *ctrl) 78 { 79 if (pciehp_poll_mode) 80 kthread_stop(ctrl->poll_thread); 81 else 82 free_irq(ctrl->pcie->irq, ctrl); 83 } 84 85 static int pcie_poll_cmd(struct controller *ctrl, int timeout) 86 { 87 struct pci_dev *pdev = ctrl_dev(ctrl); 88 u16 slot_status; 89 90 do { 91 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); 92 if (PCI_POSSIBLE_ERROR(slot_status)) { 93 ctrl_info(ctrl, "%s: no response from device\n", 94 __func__); 95 return 0; 96 } 97 98 if (slot_status & PCI_EXP_SLTSTA_CC) { 99 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, 100 PCI_EXP_SLTSTA_CC); 101 return 1; 102 } 103 msleep(10); 104 timeout -= 10; 105 } while (timeout >= 0); 106 return 0; /* timeout */ 107 } 108 109 static void pcie_wait_cmd(struct controller *ctrl) 110 { 111 unsigned int msecs = pciehp_poll_mode ? 2500 : 1000; 112 unsigned long duration = msecs_to_jiffies(msecs); 113 unsigned long cmd_timeout = ctrl->cmd_started + duration; 114 unsigned long now, timeout; 115 int rc; 116 117 /* 118 * If the controller does not generate notifications for command 119 * completions, we never need to wait between writes. 120 */ 121 if (NO_CMD_CMPL(ctrl)) 122 return; 123 124 if (!ctrl->cmd_busy) 125 return; 126 127 /* 128 * Even if the command has already timed out, we want to call 129 * pcie_poll_cmd() so it can clear PCI_EXP_SLTSTA_CC. 130 */ 131 now = jiffies; 132 if (time_before_eq(cmd_timeout, now)) 133 timeout = 1; 134 else 135 timeout = cmd_timeout - now; 136 137 if (ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE && 138 ctrl->slot_ctrl & PCI_EXP_SLTCTL_CCIE) 139 rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout); 140 else 141 rc = pcie_poll_cmd(ctrl, jiffies_to_msecs(timeout)); 142 143 if (!rc) 144 ctrl_info(ctrl, "Timeout on hotplug command %#06x (issued %u msec ago)\n", 145 ctrl->slot_ctrl, 146 jiffies_to_msecs(jiffies - ctrl->cmd_started)); 147 } 148 149 #define CC_ERRATUM_MASK (PCI_EXP_SLTCTL_PCC | \ 150 PCI_EXP_SLTCTL_PIC | \ 151 PCI_EXP_SLTCTL_AIC | \ 152 PCI_EXP_SLTCTL_EIC) 153 154 static void pcie_do_write_cmd(struct controller *ctrl, u16 cmd, 155 u16 mask, bool wait) 156 { 157 struct pci_dev *pdev = ctrl_dev(ctrl); 158 u16 slot_ctrl_orig, slot_ctrl; 159 160 mutex_lock(&ctrl->ctrl_lock); 161 162 /* 163 * Always wait for any previous command that might still be in progress 164 */ 165 pcie_wait_cmd(ctrl); 166 167 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl); 168 if (PCI_POSSIBLE_ERROR(slot_ctrl)) { 169 ctrl_info(ctrl, "%s: no response from device\n", __func__); 170 goto out; 171 } 172 173 slot_ctrl_orig = slot_ctrl; 174 slot_ctrl &= ~mask; 175 slot_ctrl |= (cmd & mask); 176 ctrl->cmd_busy = 1; 177 smp_mb(); 178 ctrl->slot_ctrl = slot_ctrl; 179 pcie_capability_write_word(pdev, PCI_EXP_SLTCTL, slot_ctrl); 180 ctrl->cmd_started = jiffies; 181 182 /* 183 * Controllers with the Intel CF118 and similar errata advertise 184 * Command Completed support, but they only set Command Completed 185 * if we change the "Control" bits for power, power indicator, 186 * attention indicator, or interlock. If we only change the 187 * "Enable" bits, they never set the Command Completed bit. 188 */ 189 if (pdev->broken_cmd_compl && 190 (slot_ctrl_orig & CC_ERRATUM_MASK) == (slot_ctrl & CC_ERRATUM_MASK)) 191 ctrl->cmd_busy = 0; 192 193 /* 194 * Optionally wait for the hardware to be ready for a new command, 195 * indicating completion of the above issued command. 196 */ 197 if (wait) 198 pcie_wait_cmd(ctrl); 199 200 out: 201 mutex_unlock(&ctrl->ctrl_lock); 202 } 203 204 /** 205 * pcie_write_cmd - Issue controller command 206 * @ctrl: controller to which the command is issued 207 * @cmd: command value written to slot control register 208 * @mask: bitmask of slot control register to be modified 209 */ 210 static void pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask) 211 { 212 pcie_do_write_cmd(ctrl, cmd, mask, true); 213 } 214 215 /* Same as above without waiting for the hardware to latch */ 216 static void pcie_write_cmd_nowait(struct controller *ctrl, u16 cmd, u16 mask) 217 { 218 pcie_do_write_cmd(ctrl, cmd, mask, false); 219 } 220 221 /** 222 * pciehp_check_link_active() - Is the link active 223 * @ctrl: PCIe hotplug controller 224 * 225 * Check whether the downstream link is currently active. Note it is 226 * possible that the card is removed immediately after this so the 227 * caller may need to take it into account. 228 * 229 * If the hotplug controller itself is not available anymore returns 230 * %-ENODEV. 231 */ 232 int pciehp_check_link_active(struct controller *ctrl) 233 { 234 struct pci_dev *pdev = ctrl_dev(ctrl); 235 u16 lnk_status; 236 int ret; 237 238 ret = pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status); 239 if (ret == PCIBIOS_DEVICE_NOT_FOUND || PCI_POSSIBLE_ERROR(lnk_status)) 240 return -ENODEV; 241 242 ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA); 243 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status); 244 245 return ret; 246 } 247 248 static bool pci_bus_check_dev(struct pci_bus *bus, int devfn) 249 { 250 u32 l; 251 int count = 0; 252 int delay = 1000, step = 20; 253 bool found = false; 254 255 do { 256 found = pci_bus_read_dev_vendor_id(bus, devfn, &l, 0); 257 count++; 258 259 if (found) 260 break; 261 262 msleep(step); 263 delay -= step; 264 } while (delay > 0); 265 266 if (count > 1) 267 pr_debug("pci %04x:%02x:%02x.%d id reading try %d times with interval %d ms to get %08x\n", 268 pci_domain_nr(bus), bus->number, PCI_SLOT(devfn), 269 PCI_FUNC(devfn), count, step, l); 270 271 return found; 272 } 273 274 static void pcie_wait_for_presence(struct pci_dev *pdev) 275 { 276 int timeout = 1250; 277 u16 slot_status; 278 279 do { 280 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); 281 if (slot_status & PCI_EXP_SLTSTA_PDS) 282 return; 283 msleep(10); 284 timeout -= 10; 285 } while (timeout > 0); 286 } 287 288 int pciehp_check_link_status(struct controller *ctrl) 289 { 290 struct pci_dev *pdev = ctrl_dev(ctrl); 291 bool found; 292 u16 lnk_status; 293 294 if (!pcie_wait_for_link(pdev, true)) { 295 ctrl_info(ctrl, "Slot(%s): No link\n", slot_name(ctrl)); 296 return -1; 297 } 298 299 if (ctrl->inband_presence_disabled) 300 pcie_wait_for_presence(pdev); 301 302 found = pci_bus_check_dev(ctrl->pcie->port->subordinate, 303 PCI_DEVFN(0, 0)); 304 305 /* ignore link or presence changes up to this point */ 306 if (found) 307 atomic_and(~(PCI_EXP_SLTSTA_DLLSC | PCI_EXP_SLTSTA_PDC), 308 &ctrl->pending_events); 309 310 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status); 311 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status); 312 if ((lnk_status & PCI_EXP_LNKSTA_LT) || 313 !(lnk_status & PCI_EXP_LNKSTA_NLW)) { 314 ctrl_info(ctrl, "Slot(%s): Cannot train link: status %#06x\n", 315 slot_name(ctrl), lnk_status); 316 return -1; 317 } 318 319 pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status); 320 321 if (!found) { 322 ctrl_info(ctrl, "Slot(%s): No device found\n", 323 slot_name(ctrl)); 324 return -1; 325 } 326 327 return 0; 328 } 329 330 static int __pciehp_link_set(struct controller *ctrl, bool enable) 331 { 332 struct pci_dev *pdev = ctrl_dev(ctrl); 333 u16 lnk_ctrl; 334 335 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &lnk_ctrl); 336 337 if (enable) 338 lnk_ctrl &= ~PCI_EXP_LNKCTL_LD; 339 else 340 lnk_ctrl |= PCI_EXP_LNKCTL_LD; 341 342 pcie_capability_write_word(pdev, PCI_EXP_LNKCTL, lnk_ctrl); 343 ctrl_dbg(ctrl, "%s: lnk_ctrl = %x\n", __func__, lnk_ctrl); 344 return 0; 345 } 346 347 static int pciehp_link_enable(struct controller *ctrl) 348 { 349 return __pciehp_link_set(ctrl, true); 350 } 351 352 int pciehp_get_raw_indicator_status(struct hotplug_slot *hotplug_slot, 353 u8 *status) 354 { 355 struct controller *ctrl = to_ctrl(hotplug_slot); 356 struct pci_dev *pdev = ctrl_dev(ctrl); 357 u16 slot_ctrl; 358 359 pci_config_pm_runtime_get(pdev); 360 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl); 361 pci_config_pm_runtime_put(pdev); 362 *status = (slot_ctrl & (PCI_EXP_SLTCTL_AIC | PCI_EXP_SLTCTL_PIC)) >> 6; 363 return 0; 364 } 365 366 int pciehp_get_attention_status(struct hotplug_slot *hotplug_slot, u8 *status) 367 { 368 struct controller *ctrl = to_ctrl(hotplug_slot); 369 struct pci_dev *pdev = ctrl_dev(ctrl); 370 u16 slot_ctrl; 371 372 pci_config_pm_runtime_get(pdev); 373 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl); 374 pci_config_pm_runtime_put(pdev); 375 ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__, 376 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl); 377 378 switch (slot_ctrl & PCI_EXP_SLTCTL_AIC) { 379 case PCI_EXP_SLTCTL_ATTN_IND_ON: 380 *status = 1; /* On */ 381 break; 382 case PCI_EXP_SLTCTL_ATTN_IND_BLINK: 383 *status = 2; /* Blink */ 384 break; 385 case PCI_EXP_SLTCTL_ATTN_IND_OFF: 386 *status = 0; /* Off */ 387 break; 388 default: 389 *status = 0xFF; 390 break; 391 } 392 393 return 0; 394 } 395 396 void pciehp_get_power_status(struct controller *ctrl, u8 *status) 397 { 398 struct pci_dev *pdev = ctrl_dev(ctrl); 399 u16 slot_ctrl; 400 401 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl); 402 ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__, 403 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl); 404 405 switch (slot_ctrl & PCI_EXP_SLTCTL_PCC) { 406 case PCI_EXP_SLTCTL_PWR_ON: 407 *status = 1; /* On */ 408 break; 409 case PCI_EXP_SLTCTL_PWR_OFF: 410 *status = 0; /* Off */ 411 break; 412 default: 413 *status = 0xFF; 414 break; 415 } 416 } 417 418 void pciehp_get_latch_status(struct controller *ctrl, u8 *status) 419 { 420 struct pci_dev *pdev = ctrl_dev(ctrl); 421 u16 slot_status; 422 423 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); 424 *status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS); 425 } 426 427 /** 428 * pciehp_card_present() - Is the card present 429 * @ctrl: PCIe hotplug controller 430 * 431 * Function checks whether the card is currently present in the slot and 432 * in that case returns true. Note it is possible that the card is 433 * removed immediately after the check so the caller may need to take 434 * this into account. 435 * 436 * It the hotplug controller itself is not available anymore returns 437 * %-ENODEV. 438 */ 439 int pciehp_card_present(struct controller *ctrl) 440 { 441 struct pci_dev *pdev = ctrl_dev(ctrl); 442 u16 slot_status; 443 int ret; 444 445 ret = pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); 446 if (ret == PCIBIOS_DEVICE_NOT_FOUND || PCI_POSSIBLE_ERROR(slot_status)) 447 return -ENODEV; 448 449 return !!(slot_status & PCI_EXP_SLTSTA_PDS); 450 } 451 452 /** 453 * pciehp_card_present_or_link_active() - whether given slot is occupied 454 * @ctrl: PCIe hotplug controller 455 * 456 * Unlike pciehp_card_present(), which determines presence solely from the 457 * Presence Detect State bit, this helper also returns true if the Link Active 458 * bit is set. This is a concession to broken hotplug ports which hardwire 459 * Presence Detect State to zero, such as Wilocity's [1ae9:0200]. 460 * 461 * Returns: %1 if the slot is occupied and %0 if it is not. If the hotplug 462 * port is not present anymore returns %-ENODEV. 463 */ 464 int pciehp_card_present_or_link_active(struct controller *ctrl) 465 { 466 int ret; 467 468 ret = pciehp_card_present(ctrl); 469 if (ret) 470 return ret; 471 472 return pciehp_check_link_active(ctrl); 473 } 474 475 int pciehp_query_power_fault(struct controller *ctrl) 476 { 477 struct pci_dev *pdev = ctrl_dev(ctrl); 478 u16 slot_status; 479 480 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); 481 return !!(slot_status & PCI_EXP_SLTSTA_PFD); 482 } 483 484 int pciehp_set_raw_indicator_status(struct hotplug_slot *hotplug_slot, 485 u8 status) 486 { 487 struct controller *ctrl = to_ctrl(hotplug_slot); 488 struct pci_dev *pdev = ctrl_dev(ctrl); 489 490 pci_config_pm_runtime_get(pdev); 491 pcie_write_cmd_nowait(ctrl, status << 6, 492 PCI_EXP_SLTCTL_AIC | PCI_EXP_SLTCTL_PIC); 493 pci_config_pm_runtime_put(pdev); 494 return 0; 495 } 496 497 /** 498 * pciehp_set_indicators() - set attention indicator, power indicator, or both 499 * @ctrl: PCIe hotplug controller 500 * @pwr: one of: 501 * PCI_EXP_SLTCTL_PWR_IND_ON 502 * PCI_EXP_SLTCTL_PWR_IND_BLINK 503 * PCI_EXP_SLTCTL_PWR_IND_OFF 504 * @attn: one of: 505 * PCI_EXP_SLTCTL_ATTN_IND_ON 506 * PCI_EXP_SLTCTL_ATTN_IND_BLINK 507 * PCI_EXP_SLTCTL_ATTN_IND_OFF 508 * 509 * Either @pwr or @attn can also be INDICATOR_NOOP to leave that indicator 510 * unchanged. 511 */ 512 void pciehp_set_indicators(struct controller *ctrl, int pwr, int attn) 513 { 514 u16 cmd = 0, mask = 0; 515 516 if (PWR_LED(ctrl) && pwr != INDICATOR_NOOP) { 517 cmd |= (pwr & PCI_EXP_SLTCTL_PIC); 518 mask |= PCI_EXP_SLTCTL_PIC; 519 } 520 521 if (ATTN_LED(ctrl) && attn != INDICATOR_NOOP) { 522 cmd |= (attn & PCI_EXP_SLTCTL_AIC); 523 mask |= PCI_EXP_SLTCTL_AIC; 524 } 525 526 if (cmd) { 527 pcie_write_cmd_nowait(ctrl, cmd, mask); 528 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 529 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, cmd); 530 } 531 } 532 533 int pciehp_power_on_slot(struct controller *ctrl) 534 { 535 struct pci_dev *pdev = ctrl_dev(ctrl); 536 u16 slot_status; 537 int retval; 538 539 /* Clear power-fault bit from previous power failures */ 540 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); 541 if (slot_status & PCI_EXP_SLTSTA_PFD) 542 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, 543 PCI_EXP_SLTSTA_PFD); 544 ctrl->power_fault_detected = 0; 545 546 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_ON, PCI_EXP_SLTCTL_PCC); 547 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 548 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 549 PCI_EXP_SLTCTL_PWR_ON); 550 551 retval = pciehp_link_enable(ctrl); 552 if (retval) 553 ctrl_err(ctrl, "%s: Can not enable the link!\n", __func__); 554 555 return retval; 556 } 557 558 void pciehp_power_off_slot(struct controller *ctrl) 559 { 560 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_OFF, PCI_EXP_SLTCTL_PCC); 561 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 562 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 563 PCI_EXP_SLTCTL_PWR_OFF); 564 } 565 566 static void pciehp_ignore_dpc_link_change(struct controller *ctrl, 567 struct pci_dev *pdev, int irq) 568 { 569 /* 570 * Ignore link changes which occurred while waiting for DPC recovery. 571 * Could be several if DPC triggered multiple times consecutively. 572 */ 573 synchronize_hardirq(irq); 574 atomic_and(~PCI_EXP_SLTSTA_DLLSC, &ctrl->pending_events); 575 if (pciehp_poll_mode) 576 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, 577 PCI_EXP_SLTSTA_DLLSC); 578 ctrl_info(ctrl, "Slot(%s): Link Down/Up ignored (recovered by DPC)\n", 579 slot_name(ctrl)); 580 581 /* 582 * If the link is unexpectedly down after successful recovery, 583 * the corresponding link change may have been ignored above. 584 * Synthesize it to ensure that it is acted on. 585 */ 586 down_read_nested(&ctrl->reset_lock, ctrl->depth); 587 if (!pciehp_check_link_active(ctrl)) 588 pciehp_request(ctrl, PCI_EXP_SLTSTA_DLLSC); 589 up_read(&ctrl->reset_lock); 590 } 591 592 static irqreturn_t pciehp_isr(int irq, void *dev_id) 593 { 594 struct controller *ctrl = (struct controller *)dev_id; 595 struct pci_dev *pdev = ctrl_dev(ctrl); 596 struct device *parent = pdev->dev.parent; 597 u16 status, events = 0; 598 599 /* 600 * Interrupts only occur in D3hot or shallower and only if enabled 601 * in the Slot Control register (PCIe r4.0, sec 6.7.3.4). 602 */ 603 if (pdev->current_state == PCI_D3cold || 604 (!(ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE) && !pciehp_poll_mode)) 605 return IRQ_NONE; 606 607 /* 608 * Keep the port accessible by holding a runtime PM ref on its parent. 609 * Defer resume of the parent to the IRQ thread if it's suspended. 610 * Mask the interrupt until then. 611 */ 612 if (parent) { 613 pm_runtime_get_noresume(parent); 614 if (!pm_runtime_active(parent)) { 615 pm_runtime_put(parent); 616 disable_irq_nosync(irq); 617 atomic_or(RERUN_ISR, &ctrl->pending_events); 618 return IRQ_WAKE_THREAD; 619 } 620 } 621 622 read_status: 623 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &status); 624 if (PCI_POSSIBLE_ERROR(status)) { 625 ctrl_info(ctrl, "%s: no response from device\n", __func__); 626 if (parent) 627 pm_runtime_put(parent); 628 return IRQ_NONE; 629 } 630 631 /* 632 * Slot Status contains plain status bits as well as event 633 * notification bits; right now we only want the event bits. 634 */ 635 status &= PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD | 636 PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_CC | 637 PCI_EXP_SLTSTA_DLLSC; 638 639 /* 640 * If we've already reported a power fault, don't report it again 641 * until we've done something to handle it. 642 */ 643 if (ctrl->power_fault_detected) 644 status &= ~PCI_EXP_SLTSTA_PFD; 645 else if (status & PCI_EXP_SLTSTA_PFD) 646 ctrl->power_fault_detected = true; 647 648 events |= status; 649 if (!events) { 650 if (parent) 651 pm_runtime_put(parent); 652 return IRQ_NONE; 653 } 654 655 if (status) { 656 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, status); 657 658 /* 659 * In MSI mode, all event bits must be zero before the port 660 * will send a new interrupt (PCIe Base Spec r5.0 sec 6.7.3.4). 661 * So re-read the Slot Status register in case a bit was set 662 * between read and write. 663 */ 664 if (pci_dev_msi_enabled(pdev) && !pciehp_poll_mode) 665 goto read_status; 666 } 667 668 ctrl_dbg(ctrl, "pending interrupts %#06x from Slot Status\n", events); 669 if (parent) 670 pm_runtime_put(parent); 671 672 /* 673 * Command Completed notifications are not deferred to the 674 * IRQ thread because it may be waiting for their arrival. 675 */ 676 if (events & PCI_EXP_SLTSTA_CC) { 677 ctrl->cmd_busy = 0; 678 smp_mb(); 679 wake_up(&ctrl->queue); 680 681 if (events == PCI_EXP_SLTSTA_CC) 682 return IRQ_HANDLED; 683 684 events &= ~PCI_EXP_SLTSTA_CC; 685 } 686 687 if (pdev->ignore_hotplug) { 688 ctrl_dbg(ctrl, "ignoring hotplug event %#06x\n", events); 689 return IRQ_HANDLED; 690 } 691 692 /* Save pending events for consumption by IRQ thread. */ 693 atomic_or(events, &ctrl->pending_events); 694 return IRQ_WAKE_THREAD; 695 } 696 697 static irqreturn_t pciehp_ist(int irq, void *dev_id) 698 { 699 struct controller *ctrl = (struct controller *)dev_id; 700 struct pci_dev *pdev = ctrl_dev(ctrl); 701 irqreturn_t ret; 702 u32 events; 703 704 ctrl->ist_running = true; 705 pci_config_pm_runtime_get(pdev); 706 707 /* rerun pciehp_isr() if the port was inaccessible on interrupt */ 708 if (atomic_fetch_and(~RERUN_ISR, &ctrl->pending_events) & RERUN_ISR) { 709 ret = pciehp_isr(irq, dev_id); 710 enable_irq(irq); 711 if (ret != IRQ_WAKE_THREAD) 712 goto out; 713 } 714 715 synchronize_hardirq(irq); 716 events = atomic_xchg(&ctrl->pending_events, 0); 717 if (!events) { 718 ret = IRQ_NONE; 719 goto out; 720 } 721 722 /* Check Attention Button Pressed */ 723 if (events & PCI_EXP_SLTSTA_ABP) { 724 ctrl_info(ctrl, "Slot(%s): Attention button pressed\n", 725 slot_name(ctrl)); 726 pciehp_handle_button_press(ctrl); 727 } 728 729 /* Check Power Fault Detected */ 730 if (events & PCI_EXP_SLTSTA_PFD) { 731 ctrl_err(ctrl, "Slot(%s): Power fault\n", slot_name(ctrl)); 732 pciehp_set_indicators(ctrl, PCI_EXP_SLTCTL_PWR_IND_OFF, 733 PCI_EXP_SLTCTL_ATTN_IND_ON); 734 } 735 736 /* 737 * Ignore Link Down/Up events caused by Downstream Port Containment 738 * if recovery from the error succeeded. 739 */ 740 if ((events & PCI_EXP_SLTSTA_DLLSC) && pci_dpc_recovered(pdev) && 741 ctrl->state == ON_STATE) { 742 events &= ~PCI_EXP_SLTSTA_DLLSC; 743 pciehp_ignore_dpc_link_change(ctrl, pdev, irq); 744 } 745 746 /* 747 * Disable requests have higher priority than Presence Detect Changed 748 * or Data Link Layer State Changed events. 749 */ 750 down_read_nested(&ctrl->reset_lock, ctrl->depth); 751 if (events & DISABLE_SLOT) 752 pciehp_handle_disable_request(ctrl); 753 else if (events & (PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_DLLSC)) 754 pciehp_handle_presence_or_link_change(ctrl, events); 755 up_read(&ctrl->reset_lock); 756 757 ret = IRQ_HANDLED; 758 out: 759 pci_config_pm_runtime_put(pdev); 760 ctrl->ist_running = false; 761 wake_up(&ctrl->requester); 762 return ret; 763 } 764 765 static int pciehp_poll(void *data) 766 { 767 struct controller *ctrl = data; 768 769 schedule_timeout_idle(10 * HZ); /* start with 10 sec delay */ 770 771 while (!kthread_should_stop()) { 772 /* poll for interrupt events or user requests */ 773 while (pciehp_isr(IRQ_NOTCONNECTED, ctrl) == IRQ_WAKE_THREAD || 774 atomic_read(&ctrl->pending_events)) 775 pciehp_ist(IRQ_NOTCONNECTED, ctrl); 776 777 if (pciehp_poll_time <= 0 || pciehp_poll_time > 60) 778 pciehp_poll_time = 2; /* clamp to sane value */ 779 780 schedule_timeout_idle(pciehp_poll_time * HZ); 781 } 782 783 return 0; 784 } 785 786 static void pcie_enable_notification(struct controller *ctrl) 787 { 788 u16 cmd, mask; 789 790 /* 791 * TBD: Power fault detected software notification support. 792 * 793 * Power fault detected software notification is not enabled 794 * now, because it caused power fault detected interrupt storm 795 * on some machines. On those machines, power fault detected 796 * bit in the slot status register was set again immediately 797 * when it is cleared in the interrupt service routine, and 798 * next power fault detected interrupt was notified again. 799 */ 800 801 /* 802 * Always enable link events: thus link-up and link-down shall 803 * always be treated as hotplug and unplug respectively. Enable 804 * presence detect only if Attention Button is not present. 805 */ 806 cmd = PCI_EXP_SLTCTL_DLLSCE; 807 if (ATTN_BUTTN(ctrl)) 808 cmd |= PCI_EXP_SLTCTL_ABPE; 809 else 810 cmd |= PCI_EXP_SLTCTL_PDCE; 811 if (!pciehp_poll_mode) 812 cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE; 813 814 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE | 815 PCI_EXP_SLTCTL_PFDE | 816 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE | 817 PCI_EXP_SLTCTL_DLLSCE); 818 819 pcie_write_cmd_nowait(ctrl, cmd, mask); 820 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 821 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, cmd); 822 } 823 824 static void pcie_disable_notification(struct controller *ctrl) 825 { 826 u16 mask; 827 828 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE | 829 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE | 830 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE | 831 PCI_EXP_SLTCTL_DLLSCE); 832 pcie_write_cmd(ctrl, 0, mask); 833 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 834 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0); 835 } 836 837 void pcie_clear_hotplug_events(struct controller *ctrl) 838 { 839 pcie_capability_write_word(ctrl_dev(ctrl), PCI_EXP_SLTSTA, 840 PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_DLLSC); 841 } 842 843 void pcie_enable_interrupt(struct controller *ctrl) 844 { 845 u16 mask; 846 847 mask = PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_DLLSCE; 848 pcie_write_cmd(ctrl, mask, mask); 849 } 850 851 void pcie_disable_interrupt(struct controller *ctrl) 852 { 853 u16 mask; 854 855 /* 856 * Mask hot-plug interrupt to prevent it triggering immediately 857 * when the link goes inactive (we still get PME when any of the 858 * enabled events is detected). Same goes with Link Layer State 859 * changed event which generates PME immediately when the link goes 860 * inactive so mask it as well. 861 */ 862 mask = PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_DLLSCE; 863 pcie_write_cmd(ctrl, 0, mask); 864 } 865 866 /** 867 * pciehp_slot_reset() - ignore link event caused by error-induced hot reset 868 * @dev: PCI Express port service device 869 * 870 * Called from pcie_portdrv_slot_reset() after AER or DPC initiated a reset 871 * further up in the hierarchy to recover from an error. The reset was 872 * propagated down to this hotplug port. Ignore the resulting link flap. 873 * If the link failed to retrain successfully, synthesize the ignored event. 874 * Surprise removal during reset is detected through Presence Detect Changed. 875 */ 876 int pciehp_slot_reset(struct pcie_device *dev) 877 { 878 struct controller *ctrl = get_service_data(dev); 879 880 if (ctrl->state != ON_STATE) 881 return 0; 882 883 pcie_capability_write_word(dev->port, PCI_EXP_SLTSTA, 884 PCI_EXP_SLTSTA_DLLSC); 885 886 if (!pciehp_check_link_active(ctrl)) 887 pciehp_request(ctrl, PCI_EXP_SLTSTA_DLLSC); 888 889 return 0; 890 } 891 892 /* 893 * pciehp has a 1:1 bus:slot relationship so we ultimately want a secondary 894 * bus reset of the bridge, but at the same time we want to ensure that it is 895 * not seen as a hot-unplug, followed by the hot-plug of the device. Thus, 896 * disable link state notification and presence detection change notification 897 * momentarily, if we see that they could interfere. Also, clear any spurious 898 * events after. 899 */ 900 int pciehp_reset_slot(struct hotplug_slot *hotplug_slot, bool probe) 901 { 902 struct controller *ctrl = to_ctrl(hotplug_slot); 903 struct pci_dev *pdev = ctrl_dev(ctrl); 904 u16 stat_mask = 0, ctrl_mask = 0; 905 int rc; 906 907 if (probe) 908 return 0; 909 910 down_write_nested(&ctrl->reset_lock, ctrl->depth); 911 912 if (!ATTN_BUTTN(ctrl)) { 913 ctrl_mask |= PCI_EXP_SLTCTL_PDCE; 914 stat_mask |= PCI_EXP_SLTSTA_PDC; 915 } 916 ctrl_mask |= PCI_EXP_SLTCTL_DLLSCE; 917 stat_mask |= PCI_EXP_SLTSTA_DLLSC; 918 919 pcie_write_cmd(ctrl, 0, ctrl_mask); 920 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 921 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0); 922 923 rc = pci_bridge_secondary_bus_reset(ctrl->pcie->port); 924 925 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, stat_mask); 926 pcie_write_cmd_nowait(ctrl, ctrl_mask, ctrl_mask); 927 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 928 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, ctrl_mask); 929 930 up_write(&ctrl->reset_lock); 931 return rc; 932 } 933 934 int pcie_init_notification(struct controller *ctrl) 935 { 936 if (pciehp_request_irq(ctrl)) 937 return -1; 938 pcie_enable_notification(ctrl); 939 ctrl->notification_enabled = 1; 940 return 0; 941 } 942 943 void pcie_shutdown_notification(struct controller *ctrl) 944 { 945 if (ctrl->notification_enabled) { 946 pcie_disable_notification(ctrl); 947 pciehp_free_irq(ctrl); 948 ctrl->notification_enabled = 0; 949 } 950 } 951 952 static inline void dbg_ctrl(struct controller *ctrl) 953 { 954 struct pci_dev *pdev = ctrl->pcie->port; 955 u16 reg16; 956 957 ctrl_dbg(ctrl, "Slot Capabilities : 0x%08x\n", ctrl->slot_cap); 958 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, ®16); 959 ctrl_dbg(ctrl, "Slot Status : 0x%04x\n", reg16); 960 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, ®16); 961 ctrl_dbg(ctrl, "Slot Control : 0x%04x\n", reg16); 962 } 963 964 #define FLAG(x, y) (((x) & (y)) ? '+' : '-') 965 966 static inline int pcie_hotplug_depth(struct pci_dev *dev) 967 { 968 struct pci_bus *bus = dev->bus; 969 int depth = 0; 970 971 while (bus->parent) { 972 bus = bus->parent; 973 if (bus->self && bus->self->is_hotplug_bridge) 974 depth++; 975 } 976 977 return depth; 978 } 979 980 struct controller *pcie_init(struct pcie_device *dev) 981 { 982 struct controller *ctrl; 983 u32 slot_cap, slot_cap2, link_cap; 984 u8 poweron; 985 struct pci_dev *pdev = dev->port; 986 struct pci_bus *subordinate = pdev->subordinate; 987 988 ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL); 989 if (!ctrl) 990 return NULL; 991 992 ctrl->pcie = dev; 993 ctrl->depth = pcie_hotplug_depth(dev->port); 994 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap); 995 996 if (pdev->hotplug_user_indicators) 997 slot_cap &= ~(PCI_EXP_SLTCAP_AIP | PCI_EXP_SLTCAP_PIP); 998 999 /* 1000 * We assume no Thunderbolt controllers support Command Complete events, 1001 * but some controllers falsely claim they do. 1002 */ 1003 if (pdev->is_thunderbolt) 1004 slot_cap |= PCI_EXP_SLTCAP_NCCS; 1005 1006 ctrl->slot_cap = slot_cap; 1007 mutex_init(&ctrl->ctrl_lock); 1008 mutex_init(&ctrl->state_lock); 1009 init_rwsem(&ctrl->reset_lock); 1010 init_waitqueue_head(&ctrl->requester); 1011 init_waitqueue_head(&ctrl->queue); 1012 INIT_DELAYED_WORK(&ctrl->button_work, pciehp_queue_pushbutton_work); 1013 dbg_ctrl(ctrl); 1014 1015 down_read(&pci_bus_sem); 1016 ctrl->state = list_empty(&subordinate->devices) ? OFF_STATE : ON_STATE; 1017 up_read(&pci_bus_sem); 1018 1019 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP2, &slot_cap2); 1020 if (slot_cap2 & PCI_EXP_SLTCAP2_IBPD) { 1021 pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_IBPD_DISABLE, 1022 PCI_EXP_SLTCTL_IBPD_DISABLE); 1023 ctrl->inband_presence_disabled = 1; 1024 } 1025 1026 if (dmi_first_match(inband_presence_disabled_dmi_table)) 1027 ctrl->inband_presence_disabled = 1; 1028 1029 /* Check if Data Link Layer Link Active Reporting is implemented */ 1030 pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &link_cap); 1031 1032 /* Clear all remaining event bits in Slot Status register. */ 1033 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, 1034 PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD | 1035 PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_CC | 1036 PCI_EXP_SLTSTA_DLLSC | PCI_EXP_SLTSTA_PDC); 1037 1038 ctrl_info(ctrl, "Slot #%d AttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surprise%c Interlock%c NoCompl%c IbPresDis%c LLActRep%c%s\n", 1039 (slot_cap & PCI_EXP_SLTCAP_PSN) >> 19, 1040 FLAG(slot_cap, PCI_EXP_SLTCAP_ABP), 1041 FLAG(slot_cap, PCI_EXP_SLTCAP_PCP), 1042 FLAG(slot_cap, PCI_EXP_SLTCAP_MRLSP), 1043 FLAG(slot_cap, PCI_EXP_SLTCAP_AIP), 1044 FLAG(slot_cap, PCI_EXP_SLTCAP_PIP), 1045 FLAG(slot_cap, PCI_EXP_SLTCAP_HPC), 1046 FLAG(slot_cap, PCI_EXP_SLTCAP_HPS), 1047 FLAG(slot_cap, PCI_EXP_SLTCAP_EIP), 1048 FLAG(slot_cap, PCI_EXP_SLTCAP_NCCS), 1049 FLAG(slot_cap2, PCI_EXP_SLTCAP2_IBPD), 1050 FLAG(link_cap, PCI_EXP_LNKCAP_DLLLARC), 1051 pdev->broken_cmd_compl ? " (with Cmd Compl erratum)" : ""); 1052 1053 /* 1054 * If empty slot's power status is on, turn power off. The IRQ isn't 1055 * requested yet, so avoid triggering a notification with this command. 1056 */ 1057 if (POWER_CTRL(ctrl)) { 1058 pciehp_get_power_status(ctrl, &poweron); 1059 if (!pciehp_card_present_or_link_active(ctrl) && poweron) { 1060 pcie_disable_notification(ctrl); 1061 pciehp_power_off_slot(ctrl); 1062 } 1063 } 1064 1065 return ctrl; 1066 } 1067 1068 void pciehp_release_ctrl(struct controller *ctrl) 1069 { 1070 cancel_delayed_work_sync(&ctrl->button_work); 1071 kfree(ctrl); 1072 } 1073 1074 static void quirk_cmd_compl(struct pci_dev *pdev) 1075 { 1076 u32 slot_cap; 1077 1078 if (pci_is_pcie(pdev)) { 1079 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap); 1080 if (slot_cap & PCI_EXP_SLTCAP_HPC && 1081 !(slot_cap & PCI_EXP_SLTCAP_NCCS)) 1082 pdev->broken_cmd_compl = 1; 1083 } 1084 } 1085 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 1086 PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl); 1087 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_QCOM, 0x0400, 1088 PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl); 1089 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_QCOM, 0x0401, 1090 PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl); 1091 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_HXT, 0x0401, 1092 PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl); 1093