1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * PCI Express PCI Hot Plug Driver 4 * 5 * Copyright (C) 1995,2001 Compaq Computer Corporation 6 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com) 7 * Copyright (C) 2001 IBM Corp. 8 * Copyright (C) 2003-2004 Intel Corporation 9 * 10 * All rights reserved. 11 * 12 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com> 13 */ 14 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/types.h> 18 #include <linux/signal.h> 19 #include <linux/jiffies.h> 20 #include <linux/timer.h> 21 #include <linux/pci.h> 22 #include <linux/interrupt.h> 23 #include <linux/time.h> 24 #include <linux/slab.h> 25 26 #include "../pci.h" 27 #include "pciehp.h" 28 29 static inline struct pci_dev *ctrl_dev(struct controller *ctrl) 30 { 31 return ctrl->pcie->port; 32 } 33 34 static irqreturn_t pcie_isr(int irq, void *dev_id); 35 static void start_int_poll_timer(struct controller *ctrl, int sec); 36 37 /* This is the interrupt polling timeout function. */ 38 static void int_poll_timeout(struct timer_list *t) 39 { 40 struct controller *ctrl = from_timer(ctrl, t, poll_timer); 41 42 /* Poll for interrupt events. regs == NULL => polling */ 43 pcie_isr(0, ctrl); 44 45 if (!pciehp_poll_time) 46 pciehp_poll_time = 2; /* default polling interval is 2 sec */ 47 48 start_int_poll_timer(ctrl, pciehp_poll_time); 49 } 50 51 /* This function starts the interrupt polling timer. */ 52 static void start_int_poll_timer(struct controller *ctrl, int sec) 53 { 54 /* Clamp to sane value */ 55 if ((sec <= 0) || (sec > 60)) 56 sec = 2; 57 58 ctrl->poll_timer.expires = jiffies + sec * HZ; 59 add_timer(&ctrl->poll_timer); 60 } 61 62 static inline int pciehp_request_irq(struct controller *ctrl) 63 { 64 int retval, irq = ctrl->pcie->irq; 65 66 /* Install interrupt polling timer. Start with 10 sec delay */ 67 if (pciehp_poll_mode) { 68 timer_setup(&ctrl->poll_timer, int_poll_timeout, 0); 69 start_int_poll_timer(ctrl, 10); 70 return 0; 71 } 72 73 /* Installs the interrupt handler */ 74 retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl); 75 if (retval) 76 ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n", 77 irq); 78 return retval; 79 } 80 81 static inline void pciehp_free_irq(struct controller *ctrl) 82 { 83 if (pciehp_poll_mode) 84 del_timer_sync(&ctrl->poll_timer); 85 else 86 free_irq(ctrl->pcie->irq, ctrl); 87 } 88 89 static int pcie_poll_cmd(struct controller *ctrl, int timeout) 90 { 91 struct pci_dev *pdev = ctrl_dev(ctrl); 92 u16 slot_status; 93 94 while (true) { 95 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); 96 if (slot_status == (u16) ~0) { 97 ctrl_info(ctrl, "%s: no response from device\n", 98 __func__); 99 return 0; 100 } 101 102 if (slot_status & PCI_EXP_SLTSTA_CC) { 103 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, 104 PCI_EXP_SLTSTA_CC); 105 return 1; 106 } 107 if (timeout < 0) 108 break; 109 msleep(10); 110 timeout -= 10; 111 } 112 return 0; /* timeout */ 113 } 114 115 static void pcie_wait_cmd(struct controller *ctrl) 116 { 117 unsigned int msecs = pciehp_poll_mode ? 2500 : 1000; 118 unsigned long duration = msecs_to_jiffies(msecs); 119 unsigned long cmd_timeout = ctrl->cmd_started + duration; 120 unsigned long now, timeout; 121 int rc; 122 123 /* 124 * If the controller does not generate notifications for command 125 * completions, we never need to wait between writes. 126 */ 127 if (NO_CMD_CMPL(ctrl)) 128 return; 129 130 if (!ctrl->cmd_busy) 131 return; 132 133 /* 134 * Even if the command has already timed out, we want to call 135 * pcie_poll_cmd() so it can clear PCI_EXP_SLTSTA_CC. 136 */ 137 now = jiffies; 138 if (time_before_eq(cmd_timeout, now)) 139 timeout = 1; 140 else 141 timeout = cmd_timeout - now; 142 143 if (ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE && 144 ctrl->slot_ctrl & PCI_EXP_SLTCTL_CCIE) 145 rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout); 146 else 147 rc = pcie_poll_cmd(ctrl, jiffies_to_msecs(timeout)); 148 149 if (!rc) 150 ctrl_info(ctrl, "Timeout on hotplug command %#06x (issued %u msec ago)\n", 151 ctrl->slot_ctrl, 152 jiffies_to_msecs(jiffies - ctrl->cmd_started)); 153 } 154 155 #define CC_ERRATUM_MASK (PCI_EXP_SLTCTL_PCC | \ 156 PCI_EXP_SLTCTL_PIC | \ 157 PCI_EXP_SLTCTL_AIC | \ 158 PCI_EXP_SLTCTL_EIC) 159 160 static void pcie_do_write_cmd(struct controller *ctrl, u16 cmd, 161 u16 mask, bool wait) 162 { 163 struct pci_dev *pdev = ctrl_dev(ctrl); 164 u16 slot_ctrl_orig, slot_ctrl; 165 166 mutex_lock(&ctrl->ctrl_lock); 167 168 /* 169 * Always wait for any previous command that might still be in progress 170 */ 171 pcie_wait_cmd(ctrl); 172 173 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl); 174 if (slot_ctrl == (u16) ~0) { 175 ctrl_info(ctrl, "%s: no response from device\n", __func__); 176 goto out; 177 } 178 179 slot_ctrl_orig = slot_ctrl; 180 slot_ctrl &= ~mask; 181 slot_ctrl |= (cmd & mask); 182 ctrl->cmd_busy = 1; 183 smp_mb(); 184 pcie_capability_write_word(pdev, PCI_EXP_SLTCTL, slot_ctrl); 185 ctrl->cmd_started = jiffies; 186 ctrl->slot_ctrl = slot_ctrl; 187 188 /* 189 * Controllers with the Intel CF118 and similar errata advertise 190 * Command Completed support, but they only set Command Completed 191 * if we change the "Control" bits for power, power indicator, 192 * attention indicator, or interlock. If we only change the 193 * "Enable" bits, they never set the Command Completed bit. 194 */ 195 if (pdev->broken_cmd_compl && 196 (slot_ctrl_orig & CC_ERRATUM_MASK) == (slot_ctrl & CC_ERRATUM_MASK)) 197 ctrl->cmd_busy = 0; 198 199 /* 200 * Optionally wait for the hardware to be ready for a new command, 201 * indicating completion of the above issued command. 202 */ 203 if (wait) 204 pcie_wait_cmd(ctrl); 205 206 out: 207 mutex_unlock(&ctrl->ctrl_lock); 208 } 209 210 /** 211 * pcie_write_cmd - Issue controller command 212 * @ctrl: controller to which the command is issued 213 * @cmd: command value written to slot control register 214 * @mask: bitmask of slot control register to be modified 215 */ 216 static void pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask) 217 { 218 pcie_do_write_cmd(ctrl, cmd, mask, true); 219 } 220 221 /* Same as above without waiting for the hardware to latch */ 222 static void pcie_write_cmd_nowait(struct controller *ctrl, u16 cmd, u16 mask) 223 { 224 pcie_do_write_cmd(ctrl, cmd, mask, false); 225 } 226 227 bool pciehp_check_link_active(struct controller *ctrl) 228 { 229 struct pci_dev *pdev = ctrl_dev(ctrl); 230 u16 lnk_status; 231 bool ret; 232 233 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status); 234 ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA); 235 236 if (ret) 237 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status); 238 239 return ret; 240 } 241 242 static void pcie_wait_link_active(struct controller *ctrl) 243 { 244 struct pci_dev *pdev = ctrl_dev(ctrl); 245 246 pcie_wait_for_link(pdev, true); 247 } 248 249 static bool pci_bus_check_dev(struct pci_bus *bus, int devfn) 250 { 251 u32 l; 252 int count = 0; 253 int delay = 1000, step = 20; 254 bool found = false; 255 256 do { 257 found = pci_bus_read_dev_vendor_id(bus, devfn, &l, 0); 258 count++; 259 260 if (found) 261 break; 262 263 msleep(step); 264 delay -= step; 265 } while (delay > 0); 266 267 if (count > 1 && pciehp_debug) 268 printk(KERN_DEBUG "pci %04x:%02x:%02x.%d id reading try %d times with interval %d ms to get %08x\n", 269 pci_domain_nr(bus), bus->number, PCI_SLOT(devfn), 270 PCI_FUNC(devfn), count, step, l); 271 272 return found; 273 } 274 275 int pciehp_check_link_status(struct controller *ctrl) 276 { 277 struct pci_dev *pdev = ctrl_dev(ctrl); 278 bool found; 279 u16 lnk_status; 280 281 /* 282 * Data Link Layer Link Active Reporting must be capable for 283 * hot-plug capable downstream port. But old controller might 284 * not implement it. In this case, we wait for 1000 ms. 285 */ 286 if (ctrl->link_active_reporting) 287 pcie_wait_link_active(ctrl); 288 else 289 msleep(1000); 290 291 /* wait 100ms before read pci conf, and try in 1s */ 292 msleep(100); 293 found = pci_bus_check_dev(ctrl->pcie->port->subordinate, 294 PCI_DEVFN(0, 0)); 295 296 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status); 297 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status); 298 if ((lnk_status & PCI_EXP_LNKSTA_LT) || 299 !(lnk_status & PCI_EXP_LNKSTA_NLW)) { 300 ctrl_err(ctrl, "link training error: status %#06x\n", 301 lnk_status); 302 return -1; 303 } 304 305 pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status); 306 307 if (!found) 308 return -1; 309 310 return 0; 311 } 312 313 static int __pciehp_link_set(struct controller *ctrl, bool enable) 314 { 315 struct pci_dev *pdev = ctrl_dev(ctrl); 316 u16 lnk_ctrl; 317 318 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &lnk_ctrl); 319 320 if (enable) 321 lnk_ctrl &= ~PCI_EXP_LNKCTL_LD; 322 else 323 lnk_ctrl |= PCI_EXP_LNKCTL_LD; 324 325 pcie_capability_write_word(pdev, PCI_EXP_LNKCTL, lnk_ctrl); 326 ctrl_dbg(ctrl, "%s: lnk_ctrl = %x\n", __func__, lnk_ctrl); 327 return 0; 328 } 329 330 static int pciehp_link_enable(struct controller *ctrl) 331 { 332 return __pciehp_link_set(ctrl, true); 333 } 334 335 int pciehp_get_raw_indicator_status(struct hotplug_slot *hotplug_slot, 336 u8 *status) 337 { 338 struct slot *slot = hotplug_slot->private; 339 struct pci_dev *pdev = ctrl_dev(slot->ctrl); 340 u16 slot_ctrl; 341 342 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl); 343 *status = (slot_ctrl & (PCI_EXP_SLTCTL_AIC | PCI_EXP_SLTCTL_PIC)) >> 6; 344 return 0; 345 } 346 347 void pciehp_get_attention_status(struct slot *slot, u8 *status) 348 { 349 struct controller *ctrl = slot->ctrl; 350 struct pci_dev *pdev = ctrl_dev(ctrl); 351 u16 slot_ctrl; 352 353 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl); 354 ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__, 355 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl); 356 357 switch (slot_ctrl & PCI_EXP_SLTCTL_AIC) { 358 case PCI_EXP_SLTCTL_ATTN_IND_ON: 359 *status = 1; /* On */ 360 break; 361 case PCI_EXP_SLTCTL_ATTN_IND_BLINK: 362 *status = 2; /* Blink */ 363 break; 364 case PCI_EXP_SLTCTL_ATTN_IND_OFF: 365 *status = 0; /* Off */ 366 break; 367 default: 368 *status = 0xFF; 369 break; 370 } 371 } 372 373 void pciehp_get_power_status(struct slot *slot, u8 *status) 374 { 375 struct controller *ctrl = slot->ctrl; 376 struct pci_dev *pdev = ctrl_dev(ctrl); 377 u16 slot_ctrl; 378 379 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl); 380 ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__, 381 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl); 382 383 switch (slot_ctrl & PCI_EXP_SLTCTL_PCC) { 384 case PCI_EXP_SLTCTL_PWR_ON: 385 *status = 1; /* On */ 386 break; 387 case PCI_EXP_SLTCTL_PWR_OFF: 388 *status = 0; /* Off */ 389 break; 390 default: 391 *status = 0xFF; 392 break; 393 } 394 } 395 396 void pciehp_get_latch_status(struct slot *slot, u8 *status) 397 { 398 struct pci_dev *pdev = ctrl_dev(slot->ctrl); 399 u16 slot_status; 400 401 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); 402 *status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS); 403 } 404 405 void pciehp_get_adapter_status(struct slot *slot, u8 *status) 406 { 407 struct pci_dev *pdev = ctrl_dev(slot->ctrl); 408 u16 slot_status; 409 410 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); 411 *status = !!(slot_status & PCI_EXP_SLTSTA_PDS); 412 } 413 414 int pciehp_query_power_fault(struct slot *slot) 415 { 416 struct pci_dev *pdev = ctrl_dev(slot->ctrl); 417 u16 slot_status; 418 419 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); 420 return !!(slot_status & PCI_EXP_SLTSTA_PFD); 421 } 422 423 int pciehp_set_raw_indicator_status(struct hotplug_slot *hotplug_slot, 424 u8 status) 425 { 426 struct slot *slot = hotplug_slot->private; 427 struct controller *ctrl = slot->ctrl; 428 429 pcie_write_cmd_nowait(ctrl, status << 6, 430 PCI_EXP_SLTCTL_AIC | PCI_EXP_SLTCTL_PIC); 431 return 0; 432 } 433 434 void pciehp_set_attention_status(struct slot *slot, u8 value) 435 { 436 struct controller *ctrl = slot->ctrl; 437 u16 slot_cmd; 438 439 if (!ATTN_LED(ctrl)) 440 return; 441 442 switch (value) { 443 case 0: /* turn off */ 444 slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_OFF; 445 break; 446 case 1: /* turn on */ 447 slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_ON; 448 break; 449 case 2: /* turn blink */ 450 slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_BLINK; 451 break; 452 default: 453 return; 454 } 455 pcie_write_cmd_nowait(ctrl, slot_cmd, PCI_EXP_SLTCTL_AIC); 456 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 457 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); 458 } 459 460 void pciehp_green_led_on(struct slot *slot) 461 { 462 struct controller *ctrl = slot->ctrl; 463 464 if (!PWR_LED(ctrl)) 465 return; 466 467 pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_ON, 468 PCI_EXP_SLTCTL_PIC); 469 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 470 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 471 PCI_EXP_SLTCTL_PWR_IND_ON); 472 } 473 474 void pciehp_green_led_off(struct slot *slot) 475 { 476 struct controller *ctrl = slot->ctrl; 477 478 if (!PWR_LED(ctrl)) 479 return; 480 481 pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_OFF, 482 PCI_EXP_SLTCTL_PIC); 483 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 484 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 485 PCI_EXP_SLTCTL_PWR_IND_OFF); 486 } 487 488 void pciehp_green_led_blink(struct slot *slot) 489 { 490 struct controller *ctrl = slot->ctrl; 491 492 if (!PWR_LED(ctrl)) 493 return; 494 495 pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_BLINK, 496 PCI_EXP_SLTCTL_PIC); 497 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 498 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 499 PCI_EXP_SLTCTL_PWR_IND_BLINK); 500 } 501 502 int pciehp_power_on_slot(struct slot *slot) 503 { 504 struct controller *ctrl = slot->ctrl; 505 struct pci_dev *pdev = ctrl_dev(ctrl); 506 u16 slot_status; 507 int retval; 508 509 /* Clear sticky power-fault bit from previous power failures */ 510 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); 511 if (slot_status & PCI_EXP_SLTSTA_PFD) 512 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, 513 PCI_EXP_SLTSTA_PFD); 514 ctrl->power_fault_detected = 0; 515 516 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_ON, PCI_EXP_SLTCTL_PCC); 517 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 518 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 519 PCI_EXP_SLTCTL_PWR_ON); 520 521 retval = pciehp_link_enable(ctrl); 522 if (retval) 523 ctrl_err(ctrl, "%s: Can not enable the link!\n", __func__); 524 525 return retval; 526 } 527 528 void pciehp_power_off_slot(struct slot *slot) 529 { 530 struct controller *ctrl = slot->ctrl; 531 532 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_OFF, PCI_EXP_SLTCTL_PCC); 533 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 534 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 535 PCI_EXP_SLTCTL_PWR_OFF); 536 } 537 538 static irqreturn_t pciehp_isr(int irq, void *dev_id) 539 { 540 struct controller *ctrl = (struct controller *)dev_id; 541 struct pci_dev *pdev = ctrl_dev(ctrl); 542 struct pci_bus *subordinate = pdev->subordinate; 543 struct pci_dev *dev; 544 struct slot *slot = ctrl->slot; 545 u16 status, events; 546 u8 present; 547 bool link; 548 549 /* Interrupts cannot originate from a controller that's asleep */ 550 if (pdev->current_state == PCI_D3cold) 551 return IRQ_NONE; 552 553 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &status); 554 if (status == (u16) ~0) { 555 ctrl_info(ctrl, "%s: no response from device\n", __func__); 556 return IRQ_NONE; 557 } 558 559 /* 560 * Slot Status contains plain status bits as well as event 561 * notification bits; right now we only want the event bits. 562 */ 563 events = status & (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD | 564 PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_CC | 565 PCI_EXP_SLTSTA_DLLSC); 566 567 /* 568 * If we've already reported a power fault, don't report it again 569 * until we've done something to handle it. 570 */ 571 if (ctrl->power_fault_detected) 572 events &= ~PCI_EXP_SLTSTA_PFD; 573 574 if (!events) 575 return IRQ_NONE; 576 577 /* Capture link status before clearing interrupts */ 578 if (events & PCI_EXP_SLTSTA_DLLSC) 579 link = pciehp_check_link_active(ctrl); 580 581 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, events); 582 ctrl_dbg(ctrl, "pending interrupts %#06x from Slot Status\n", events); 583 584 /* Check Command Complete Interrupt Pending */ 585 if (events & PCI_EXP_SLTSTA_CC) { 586 ctrl->cmd_busy = 0; 587 smp_mb(); 588 wake_up(&ctrl->queue); 589 } 590 591 if (subordinate) { 592 list_for_each_entry(dev, &subordinate->devices, bus_list) { 593 if (dev->ignore_hotplug) { 594 ctrl_dbg(ctrl, "ignoring hotplug event %#06x (%s requested no hotplug)\n", 595 events, pci_name(dev)); 596 return IRQ_HANDLED; 597 } 598 } 599 } 600 601 /* Check Attention Button Pressed */ 602 if (events & PCI_EXP_SLTSTA_ABP) { 603 ctrl_info(ctrl, "Slot(%s): Attention button pressed\n", 604 slot_name(slot)); 605 pciehp_queue_interrupt_event(slot, INT_BUTTON_PRESS); 606 } 607 608 /* 609 * Check Link Status Changed at higher precedence than Presence 610 * Detect Changed. The PDS value may be set to "card present" from 611 * out-of-band detection, which may be in conflict with a Link Down 612 * and cause the wrong event to queue. 613 */ 614 if (events & PCI_EXP_SLTSTA_DLLSC) { 615 ctrl_info(ctrl, "Slot(%s): Link %s\n", slot_name(slot), 616 link ? "Up" : "Down"); 617 pciehp_queue_interrupt_event(slot, link ? INT_LINK_UP : 618 INT_LINK_DOWN); 619 } else if (events & PCI_EXP_SLTSTA_PDC) { 620 present = !!(status & PCI_EXP_SLTSTA_PDS); 621 ctrl_info(ctrl, "Slot(%s): Card %spresent\n", slot_name(slot), 622 present ? "" : "not "); 623 pciehp_queue_interrupt_event(slot, present ? INT_PRESENCE_ON : 624 INT_PRESENCE_OFF); 625 } 626 627 /* Check Power Fault Detected */ 628 if ((events & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) { 629 ctrl->power_fault_detected = 1; 630 ctrl_err(ctrl, "Slot(%s): Power fault\n", slot_name(slot)); 631 pciehp_queue_interrupt_event(slot, INT_POWER_FAULT); 632 } 633 634 return IRQ_HANDLED; 635 } 636 637 static irqreturn_t pcie_isr(int irq, void *dev_id) 638 { 639 irqreturn_t rc, handled = IRQ_NONE; 640 641 /* 642 * To guarantee that all interrupt events are serviced, we need to 643 * re-inspect Slot Status register after clearing what is presumed 644 * to be the last pending interrupt. 645 */ 646 do { 647 rc = pciehp_isr(irq, dev_id); 648 if (rc == IRQ_HANDLED) 649 handled = IRQ_HANDLED; 650 } while (rc == IRQ_HANDLED); 651 652 /* Return IRQ_HANDLED if we handled one or more events */ 653 return handled; 654 } 655 656 static void pcie_enable_notification(struct controller *ctrl) 657 { 658 u16 cmd, mask; 659 660 /* 661 * TBD: Power fault detected software notification support. 662 * 663 * Power fault detected software notification is not enabled 664 * now, because it caused power fault detected interrupt storm 665 * on some machines. On those machines, power fault detected 666 * bit in the slot status register was set again immediately 667 * when it is cleared in the interrupt service routine, and 668 * next power fault detected interrupt was notified again. 669 */ 670 671 /* 672 * Always enable link events: thus link-up and link-down shall 673 * always be treated as hotplug and unplug respectively. Enable 674 * presence detect only if Attention Button is not present. 675 */ 676 cmd = PCI_EXP_SLTCTL_DLLSCE; 677 if (ATTN_BUTTN(ctrl)) 678 cmd |= PCI_EXP_SLTCTL_ABPE; 679 else 680 cmd |= PCI_EXP_SLTCTL_PDCE; 681 if (!pciehp_poll_mode) 682 cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE; 683 684 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE | 685 PCI_EXP_SLTCTL_PFDE | 686 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE | 687 PCI_EXP_SLTCTL_DLLSCE); 688 689 pcie_write_cmd_nowait(ctrl, cmd, mask); 690 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 691 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, cmd); 692 } 693 694 void pcie_reenable_notification(struct controller *ctrl) 695 { 696 /* 697 * Clear both Presence and Data Link Layer Changed to make sure 698 * those events still fire after we have re-enabled them. 699 */ 700 pcie_capability_write_word(ctrl->pcie->port, PCI_EXP_SLTSTA, 701 PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_DLLSC); 702 pcie_enable_notification(ctrl); 703 } 704 705 static void pcie_disable_notification(struct controller *ctrl) 706 { 707 u16 mask; 708 709 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE | 710 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE | 711 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE | 712 PCI_EXP_SLTCTL_DLLSCE); 713 pcie_write_cmd(ctrl, 0, mask); 714 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 715 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0); 716 } 717 718 /* 719 * pciehp has a 1:1 bus:slot relationship so we ultimately want a secondary 720 * bus reset of the bridge, but at the same time we want to ensure that it is 721 * not seen as a hot-unplug, followed by the hot-plug of the device. Thus, 722 * disable link state notification and presence detection change notification 723 * momentarily, if we see that they could interfere. Also, clear any spurious 724 * events after. 725 */ 726 int pciehp_reset_slot(struct slot *slot, int probe) 727 { 728 struct controller *ctrl = slot->ctrl; 729 struct pci_dev *pdev = ctrl_dev(ctrl); 730 u16 stat_mask = 0, ctrl_mask = 0; 731 732 if (probe) 733 return 0; 734 735 if (!ATTN_BUTTN(ctrl)) { 736 ctrl_mask |= PCI_EXP_SLTCTL_PDCE; 737 stat_mask |= PCI_EXP_SLTSTA_PDC; 738 } 739 ctrl_mask |= PCI_EXP_SLTCTL_DLLSCE; 740 stat_mask |= PCI_EXP_SLTSTA_DLLSC; 741 742 pcie_write_cmd(ctrl, 0, ctrl_mask); 743 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 744 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0); 745 if (pciehp_poll_mode) 746 del_timer_sync(&ctrl->poll_timer); 747 748 pci_reset_bridge_secondary_bus(ctrl->pcie->port); 749 750 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, stat_mask); 751 pcie_write_cmd_nowait(ctrl, ctrl_mask, ctrl_mask); 752 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 753 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, ctrl_mask); 754 if (pciehp_poll_mode) 755 int_poll_timeout(&ctrl->poll_timer); 756 return 0; 757 } 758 759 int pcie_init_notification(struct controller *ctrl) 760 { 761 if (pciehp_request_irq(ctrl)) 762 return -1; 763 pcie_enable_notification(ctrl); 764 ctrl->notification_enabled = 1; 765 return 0; 766 } 767 768 static void pcie_shutdown_notification(struct controller *ctrl) 769 { 770 if (ctrl->notification_enabled) { 771 pcie_disable_notification(ctrl); 772 pciehp_free_irq(ctrl); 773 ctrl->notification_enabled = 0; 774 } 775 } 776 777 static int pcie_init_slot(struct controller *ctrl) 778 { 779 struct slot *slot; 780 781 slot = kzalloc(sizeof(*slot), GFP_KERNEL); 782 if (!slot) 783 return -ENOMEM; 784 785 slot->wq = alloc_ordered_workqueue("pciehp-%u", 0, PSN(ctrl)); 786 if (!slot->wq) 787 goto abort; 788 789 slot->ctrl = ctrl; 790 mutex_init(&slot->lock); 791 mutex_init(&slot->hotplug_lock); 792 INIT_DELAYED_WORK(&slot->work, pciehp_queue_pushbutton_work); 793 ctrl->slot = slot; 794 return 0; 795 abort: 796 kfree(slot); 797 return -ENOMEM; 798 } 799 800 static void pcie_cleanup_slot(struct controller *ctrl) 801 { 802 struct slot *slot = ctrl->slot; 803 cancel_delayed_work(&slot->work); 804 destroy_workqueue(slot->wq); 805 kfree(slot); 806 } 807 808 static inline void dbg_ctrl(struct controller *ctrl) 809 { 810 struct pci_dev *pdev = ctrl->pcie->port; 811 u16 reg16; 812 813 if (!pciehp_debug) 814 return; 815 816 ctrl_info(ctrl, "Slot Capabilities : 0x%08x\n", ctrl->slot_cap); 817 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, ®16); 818 ctrl_info(ctrl, "Slot Status : 0x%04x\n", reg16); 819 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, ®16); 820 ctrl_info(ctrl, "Slot Control : 0x%04x\n", reg16); 821 } 822 823 #define FLAG(x, y) (((x) & (y)) ? '+' : '-') 824 825 struct controller *pcie_init(struct pcie_device *dev) 826 { 827 struct controller *ctrl; 828 u32 slot_cap, link_cap; 829 struct pci_dev *pdev = dev->port; 830 831 ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL); 832 if (!ctrl) 833 goto abort; 834 835 ctrl->pcie = dev; 836 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap); 837 838 if (pdev->hotplug_user_indicators) 839 slot_cap &= ~(PCI_EXP_SLTCAP_AIP | PCI_EXP_SLTCAP_PIP); 840 841 /* 842 * We assume no Thunderbolt controllers support Command Complete events, 843 * but some controllers falsely claim they do. 844 */ 845 if (pdev->is_thunderbolt) 846 slot_cap |= PCI_EXP_SLTCAP_NCCS; 847 848 ctrl->slot_cap = slot_cap; 849 mutex_init(&ctrl->ctrl_lock); 850 init_waitqueue_head(&ctrl->queue); 851 dbg_ctrl(ctrl); 852 853 /* Check if Data Link Layer Link Active Reporting is implemented */ 854 pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &link_cap); 855 if (link_cap & PCI_EXP_LNKCAP_DLLLARC) 856 ctrl->link_active_reporting = 1; 857 858 /* 859 * Clear all remaining event bits in Slot Status register except 860 * Presence Detect Changed. We want to make sure possible 861 * hotplug event is triggered when the interrupt is unmasked so 862 * that we don't lose that event. 863 */ 864 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, 865 PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD | 866 PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_CC | 867 PCI_EXP_SLTSTA_DLLSC); 868 869 ctrl_info(ctrl, "Slot #%d AttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surprise%c Interlock%c NoCompl%c LLActRep%c%s\n", 870 (slot_cap & PCI_EXP_SLTCAP_PSN) >> 19, 871 FLAG(slot_cap, PCI_EXP_SLTCAP_ABP), 872 FLAG(slot_cap, PCI_EXP_SLTCAP_PCP), 873 FLAG(slot_cap, PCI_EXP_SLTCAP_MRLSP), 874 FLAG(slot_cap, PCI_EXP_SLTCAP_AIP), 875 FLAG(slot_cap, PCI_EXP_SLTCAP_PIP), 876 FLAG(slot_cap, PCI_EXP_SLTCAP_HPC), 877 FLAG(slot_cap, PCI_EXP_SLTCAP_HPS), 878 FLAG(slot_cap, PCI_EXP_SLTCAP_EIP), 879 FLAG(slot_cap, PCI_EXP_SLTCAP_NCCS), 880 FLAG(link_cap, PCI_EXP_LNKCAP_DLLLARC), 881 pdev->broken_cmd_compl ? " (with Cmd Compl erratum)" : ""); 882 883 if (pcie_init_slot(ctrl)) 884 goto abort_ctrl; 885 886 return ctrl; 887 888 abort_ctrl: 889 kfree(ctrl); 890 abort: 891 return NULL; 892 } 893 894 void pciehp_release_ctrl(struct controller *ctrl) 895 { 896 pcie_shutdown_notification(ctrl); 897 pcie_cleanup_slot(ctrl); 898 kfree(ctrl); 899 } 900 901 static void quirk_cmd_compl(struct pci_dev *pdev) 902 { 903 u32 slot_cap; 904 905 if (pci_is_pcie(pdev)) { 906 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap); 907 if (slot_cap & PCI_EXP_SLTCAP_HPC && 908 !(slot_cap & PCI_EXP_SLTCAP_NCCS)) 909 pdev->broken_cmd_compl = 1; 910 } 911 } 912 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 913 PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl); 914 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_QCOM, 0x0400, 915 PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl); 916 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_QCOM, 0x0401, 917 PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl); 918