1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * PCI Express PCI Hot Plug Driver 4 * 5 * Copyright (C) 1995,2001 Compaq Computer Corporation 6 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com) 7 * Copyright (C) 2001 IBM Corp. 8 * Copyright (C) 2003-2004 Intel Corporation 9 * 10 * All rights reserved. 11 * 12 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com> 13 */ 14 15 #define dev_fmt(fmt) "pciehp: " fmt 16 17 #include <linux/kernel.h> 18 #include <linux/types.h> 19 #include <linux/jiffies.h> 20 #include <linux/kthread.h> 21 #include <linux/pci.h> 22 #include <linux/pm_runtime.h> 23 #include <linux/interrupt.h> 24 #include <linux/slab.h> 25 26 #include "../pci.h" 27 #include "pciehp.h" 28 29 static inline struct pci_dev *ctrl_dev(struct controller *ctrl) 30 { 31 return ctrl->pcie->port; 32 } 33 34 static irqreturn_t pciehp_isr(int irq, void *dev_id); 35 static irqreturn_t pciehp_ist(int irq, void *dev_id); 36 static int pciehp_poll(void *data); 37 38 static inline int pciehp_request_irq(struct controller *ctrl) 39 { 40 int retval, irq = ctrl->pcie->irq; 41 42 if (pciehp_poll_mode) { 43 ctrl->poll_thread = kthread_run(&pciehp_poll, ctrl, 44 "pciehp_poll-%s", 45 slot_name(ctrl)); 46 return PTR_ERR_OR_ZERO(ctrl->poll_thread); 47 } 48 49 /* Installs the interrupt handler */ 50 retval = request_threaded_irq(irq, pciehp_isr, pciehp_ist, 51 IRQF_SHARED, "pciehp", ctrl); 52 if (retval) 53 ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n", 54 irq); 55 return retval; 56 } 57 58 static inline void pciehp_free_irq(struct controller *ctrl) 59 { 60 if (pciehp_poll_mode) 61 kthread_stop(ctrl->poll_thread); 62 else 63 free_irq(ctrl->pcie->irq, ctrl); 64 } 65 66 static int pcie_poll_cmd(struct controller *ctrl, int timeout) 67 { 68 struct pci_dev *pdev = ctrl_dev(ctrl); 69 u16 slot_status; 70 71 while (true) { 72 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); 73 if (slot_status == (u16) ~0) { 74 ctrl_info(ctrl, "%s: no response from device\n", 75 __func__); 76 return 0; 77 } 78 79 if (slot_status & PCI_EXP_SLTSTA_CC) { 80 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, 81 PCI_EXP_SLTSTA_CC); 82 return 1; 83 } 84 if (timeout < 0) 85 break; 86 msleep(10); 87 timeout -= 10; 88 } 89 return 0; /* timeout */ 90 } 91 92 static void pcie_wait_cmd(struct controller *ctrl) 93 { 94 unsigned int msecs = pciehp_poll_mode ? 2500 : 1000; 95 unsigned long duration = msecs_to_jiffies(msecs); 96 unsigned long cmd_timeout = ctrl->cmd_started + duration; 97 unsigned long now, timeout; 98 int rc; 99 100 /* 101 * If the controller does not generate notifications for command 102 * completions, we never need to wait between writes. 103 */ 104 if (NO_CMD_CMPL(ctrl)) 105 return; 106 107 if (!ctrl->cmd_busy) 108 return; 109 110 /* 111 * Even if the command has already timed out, we want to call 112 * pcie_poll_cmd() so it can clear PCI_EXP_SLTSTA_CC. 113 */ 114 now = jiffies; 115 if (time_before_eq(cmd_timeout, now)) 116 timeout = 1; 117 else 118 timeout = cmd_timeout - now; 119 120 if (ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE && 121 ctrl->slot_ctrl & PCI_EXP_SLTCTL_CCIE) 122 rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout); 123 else 124 rc = pcie_poll_cmd(ctrl, jiffies_to_msecs(timeout)); 125 126 if (!rc) 127 ctrl_info(ctrl, "Timeout on hotplug command %#06x (issued %u msec ago)\n", 128 ctrl->slot_ctrl, 129 jiffies_to_msecs(jiffies - ctrl->cmd_started)); 130 } 131 132 #define CC_ERRATUM_MASK (PCI_EXP_SLTCTL_PCC | \ 133 PCI_EXP_SLTCTL_PIC | \ 134 PCI_EXP_SLTCTL_AIC | \ 135 PCI_EXP_SLTCTL_EIC) 136 137 static void pcie_do_write_cmd(struct controller *ctrl, u16 cmd, 138 u16 mask, bool wait) 139 { 140 struct pci_dev *pdev = ctrl_dev(ctrl); 141 u16 slot_ctrl_orig, slot_ctrl; 142 143 mutex_lock(&ctrl->ctrl_lock); 144 145 /* 146 * Always wait for any previous command that might still be in progress 147 */ 148 pcie_wait_cmd(ctrl); 149 150 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl); 151 if (slot_ctrl == (u16) ~0) { 152 ctrl_info(ctrl, "%s: no response from device\n", __func__); 153 goto out; 154 } 155 156 slot_ctrl_orig = slot_ctrl; 157 slot_ctrl &= ~mask; 158 slot_ctrl |= (cmd & mask); 159 ctrl->cmd_busy = 1; 160 smp_mb(); 161 ctrl->slot_ctrl = slot_ctrl; 162 pcie_capability_write_word(pdev, PCI_EXP_SLTCTL, slot_ctrl); 163 ctrl->cmd_started = jiffies; 164 165 /* 166 * Controllers with the Intel CF118 and similar errata advertise 167 * Command Completed support, but they only set Command Completed 168 * if we change the "Control" bits for power, power indicator, 169 * attention indicator, or interlock. If we only change the 170 * "Enable" bits, they never set the Command Completed bit. 171 */ 172 if (pdev->broken_cmd_compl && 173 (slot_ctrl_orig & CC_ERRATUM_MASK) == (slot_ctrl & CC_ERRATUM_MASK)) 174 ctrl->cmd_busy = 0; 175 176 /* 177 * Optionally wait for the hardware to be ready for a new command, 178 * indicating completion of the above issued command. 179 */ 180 if (wait) 181 pcie_wait_cmd(ctrl); 182 183 out: 184 mutex_unlock(&ctrl->ctrl_lock); 185 } 186 187 /** 188 * pcie_write_cmd - Issue controller command 189 * @ctrl: controller to which the command is issued 190 * @cmd: command value written to slot control register 191 * @mask: bitmask of slot control register to be modified 192 */ 193 static void pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask) 194 { 195 pcie_do_write_cmd(ctrl, cmd, mask, true); 196 } 197 198 /* Same as above without waiting for the hardware to latch */ 199 static void pcie_write_cmd_nowait(struct controller *ctrl, u16 cmd, u16 mask) 200 { 201 pcie_do_write_cmd(ctrl, cmd, mask, false); 202 } 203 204 bool pciehp_check_link_active(struct controller *ctrl) 205 { 206 struct pci_dev *pdev = ctrl_dev(ctrl); 207 u16 lnk_status; 208 bool ret; 209 210 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status); 211 ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA); 212 213 if (ret) 214 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status); 215 216 return ret; 217 } 218 219 static bool pci_bus_check_dev(struct pci_bus *bus, int devfn) 220 { 221 u32 l; 222 int count = 0; 223 int delay = 1000, step = 20; 224 bool found = false; 225 226 do { 227 found = pci_bus_read_dev_vendor_id(bus, devfn, &l, 0); 228 count++; 229 230 if (found) 231 break; 232 233 msleep(step); 234 delay -= step; 235 } while (delay > 0); 236 237 if (count > 1) 238 pr_debug("pci %04x:%02x:%02x.%d id reading try %d times with interval %d ms to get %08x\n", 239 pci_domain_nr(bus), bus->number, PCI_SLOT(devfn), 240 PCI_FUNC(devfn), count, step, l); 241 242 return found; 243 } 244 245 int pciehp_check_link_status(struct controller *ctrl) 246 { 247 struct pci_dev *pdev = ctrl_dev(ctrl); 248 bool found; 249 u16 lnk_status; 250 251 if (!pcie_wait_for_link(pdev, true)) 252 return -1; 253 254 found = pci_bus_check_dev(ctrl->pcie->port->subordinate, 255 PCI_DEVFN(0, 0)); 256 257 /* ignore link or presence changes up to this point */ 258 if (found) 259 atomic_and(~(PCI_EXP_SLTSTA_DLLSC | PCI_EXP_SLTSTA_PDC), 260 &ctrl->pending_events); 261 262 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status); 263 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status); 264 if ((lnk_status & PCI_EXP_LNKSTA_LT) || 265 !(lnk_status & PCI_EXP_LNKSTA_NLW)) { 266 ctrl_err(ctrl, "link training error: status %#06x\n", 267 lnk_status); 268 return -1; 269 } 270 271 pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status); 272 273 if (!found) 274 return -1; 275 276 return 0; 277 } 278 279 static int __pciehp_link_set(struct controller *ctrl, bool enable) 280 { 281 struct pci_dev *pdev = ctrl_dev(ctrl); 282 u16 lnk_ctrl; 283 284 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &lnk_ctrl); 285 286 if (enable) 287 lnk_ctrl &= ~PCI_EXP_LNKCTL_LD; 288 else 289 lnk_ctrl |= PCI_EXP_LNKCTL_LD; 290 291 pcie_capability_write_word(pdev, PCI_EXP_LNKCTL, lnk_ctrl); 292 ctrl_dbg(ctrl, "%s: lnk_ctrl = %x\n", __func__, lnk_ctrl); 293 return 0; 294 } 295 296 static int pciehp_link_enable(struct controller *ctrl) 297 { 298 return __pciehp_link_set(ctrl, true); 299 } 300 301 int pciehp_get_raw_indicator_status(struct hotplug_slot *hotplug_slot, 302 u8 *status) 303 { 304 struct controller *ctrl = to_ctrl(hotplug_slot); 305 struct pci_dev *pdev = ctrl_dev(ctrl); 306 u16 slot_ctrl; 307 308 pci_config_pm_runtime_get(pdev); 309 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl); 310 pci_config_pm_runtime_put(pdev); 311 *status = (slot_ctrl & (PCI_EXP_SLTCTL_AIC | PCI_EXP_SLTCTL_PIC)) >> 6; 312 return 0; 313 } 314 315 int pciehp_get_attention_status(struct hotplug_slot *hotplug_slot, u8 *status) 316 { 317 struct controller *ctrl = to_ctrl(hotplug_slot); 318 struct pci_dev *pdev = ctrl_dev(ctrl); 319 u16 slot_ctrl; 320 321 pci_config_pm_runtime_get(pdev); 322 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl); 323 pci_config_pm_runtime_put(pdev); 324 ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__, 325 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl); 326 327 switch (slot_ctrl & PCI_EXP_SLTCTL_AIC) { 328 case PCI_EXP_SLTCTL_ATTN_IND_ON: 329 *status = 1; /* On */ 330 break; 331 case PCI_EXP_SLTCTL_ATTN_IND_BLINK: 332 *status = 2; /* Blink */ 333 break; 334 case PCI_EXP_SLTCTL_ATTN_IND_OFF: 335 *status = 0; /* Off */ 336 break; 337 default: 338 *status = 0xFF; 339 break; 340 } 341 342 return 0; 343 } 344 345 void pciehp_get_power_status(struct controller *ctrl, u8 *status) 346 { 347 struct pci_dev *pdev = ctrl_dev(ctrl); 348 u16 slot_ctrl; 349 350 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl); 351 ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__, 352 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl); 353 354 switch (slot_ctrl & PCI_EXP_SLTCTL_PCC) { 355 case PCI_EXP_SLTCTL_PWR_ON: 356 *status = 1; /* On */ 357 break; 358 case PCI_EXP_SLTCTL_PWR_OFF: 359 *status = 0; /* Off */ 360 break; 361 default: 362 *status = 0xFF; 363 break; 364 } 365 } 366 367 void pciehp_get_latch_status(struct controller *ctrl, u8 *status) 368 { 369 struct pci_dev *pdev = ctrl_dev(ctrl); 370 u16 slot_status; 371 372 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); 373 *status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS); 374 } 375 376 bool pciehp_card_present(struct controller *ctrl) 377 { 378 struct pci_dev *pdev = ctrl_dev(ctrl); 379 u16 slot_status; 380 381 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); 382 return slot_status & PCI_EXP_SLTSTA_PDS; 383 } 384 385 /** 386 * pciehp_card_present_or_link_active() - whether given slot is occupied 387 * @ctrl: PCIe hotplug controller 388 * 389 * Unlike pciehp_card_present(), which determines presence solely from the 390 * Presence Detect State bit, this helper also returns true if the Link Active 391 * bit is set. This is a concession to broken hotplug ports which hardwire 392 * Presence Detect State to zero, such as Wilocity's [1ae9:0200]. 393 */ 394 bool pciehp_card_present_or_link_active(struct controller *ctrl) 395 { 396 return pciehp_card_present(ctrl) || pciehp_check_link_active(ctrl); 397 } 398 399 int pciehp_query_power_fault(struct controller *ctrl) 400 { 401 struct pci_dev *pdev = ctrl_dev(ctrl); 402 u16 slot_status; 403 404 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); 405 return !!(slot_status & PCI_EXP_SLTSTA_PFD); 406 } 407 408 int pciehp_set_raw_indicator_status(struct hotplug_slot *hotplug_slot, 409 u8 status) 410 { 411 struct controller *ctrl = to_ctrl(hotplug_slot); 412 struct pci_dev *pdev = ctrl_dev(ctrl); 413 414 pci_config_pm_runtime_get(pdev); 415 pcie_write_cmd_nowait(ctrl, status << 6, 416 PCI_EXP_SLTCTL_AIC | PCI_EXP_SLTCTL_PIC); 417 pci_config_pm_runtime_put(pdev); 418 return 0; 419 } 420 421 void pciehp_set_attention_status(struct controller *ctrl, u8 value) 422 { 423 u16 slot_cmd; 424 425 if (!ATTN_LED(ctrl)) 426 return; 427 428 switch (value) { 429 case 0: /* turn off */ 430 slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_OFF; 431 break; 432 case 1: /* turn on */ 433 slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_ON; 434 break; 435 case 2: /* turn blink */ 436 slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_BLINK; 437 break; 438 default: 439 return; 440 } 441 pcie_write_cmd_nowait(ctrl, slot_cmd, PCI_EXP_SLTCTL_AIC); 442 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 443 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); 444 } 445 446 void pciehp_green_led_on(struct controller *ctrl) 447 { 448 if (!PWR_LED(ctrl)) 449 return; 450 451 pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_ON, 452 PCI_EXP_SLTCTL_PIC); 453 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 454 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 455 PCI_EXP_SLTCTL_PWR_IND_ON); 456 } 457 458 void pciehp_green_led_off(struct controller *ctrl) 459 { 460 if (!PWR_LED(ctrl)) 461 return; 462 463 pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_OFF, 464 PCI_EXP_SLTCTL_PIC); 465 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 466 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 467 PCI_EXP_SLTCTL_PWR_IND_OFF); 468 } 469 470 void pciehp_green_led_blink(struct controller *ctrl) 471 { 472 if (!PWR_LED(ctrl)) 473 return; 474 475 pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_BLINK, 476 PCI_EXP_SLTCTL_PIC); 477 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 478 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 479 PCI_EXP_SLTCTL_PWR_IND_BLINK); 480 } 481 482 int pciehp_power_on_slot(struct controller *ctrl) 483 { 484 struct pci_dev *pdev = ctrl_dev(ctrl); 485 u16 slot_status; 486 int retval; 487 488 /* Clear power-fault bit from previous power failures */ 489 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); 490 if (slot_status & PCI_EXP_SLTSTA_PFD) 491 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, 492 PCI_EXP_SLTSTA_PFD); 493 ctrl->power_fault_detected = 0; 494 495 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_ON, PCI_EXP_SLTCTL_PCC); 496 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 497 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 498 PCI_EXP_SLTCTL_PWR_ON); 499 500 retval = pciehp_link_enable(ctrl); 501 if (retval) 502 ctrl_err(ctrl, "%s: Can not enable the link!\n", __func__); 503 504 return retval; 505 } 506 507 void pciehp_power_off_slot(struct controller *ctrl) 508 { 509 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_OFF, PCI_EXP_SLTCTL_PCC); 510 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 511 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 512 PCI_EXP_SLTCTL_PWR_OFF); 513 } 514 515 static irqreturn_t pciehp_isr(int irq, void *dev_id) 516 { 517 struct controller *ctrl = (struct controller *)dev_id; 518 struct pci_dev *pdev = ctrl_dev(ctrl); 519 struct device *parent = pdev->dev.parent; 520 u16 status, events; 521 522 /* 523 * Interrupts only occur in D3hot or shallower and only if enabled 524 * in the Slot Control register (PCIe r4.0, sec 6.7.3.4). 525 */ 526 if (pdev->current_state == PCI_D3cold || 527 (!(ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE) && !pciehp_poll_mode)) 528 return IRQ_NONE; 529 530 /* 531 * Keep the port accessible by holding a runtime PM ref on its parent. 532 * Defer resume of the parent to the IRQ thread if it's suspended. 533 * Mask the interrupt until then. 534 */ 535 if (parent) { 536 pm_runtime_get_noresume(parent); 537 if (!pm_runtime_active(parent)) { 538 pm_runtime_put(parent); 539 disable_irq_nosync(irq); 540 atomic_or(RERUN_ISR, &ctrl->pending_events); 541 return IRQ_WAKE_THREAD; 542 } 543 } 544 545 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &status); 546 if (status == (u16) ~0) { 547 ctrl_info(ctrl, "%s: no response from device\n", __func__); 548 if (parent) 549 pm_runtime_put(parent); 550 return IRQ_NONE; 551 } 552 553 /* 554 * Slot Status contains plain status bits as well as event 555 * notification bits; right now we only want the event bits. 556 */ 557 events = status & (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD | 558 PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_CC | 559 PCI_EXP_SLTSTA_DLLSC); 560 561 /* 562 * If we've already reported a power fault, don't report it again 563 * until we've done something to handle it. 564 */ 565 if (ctrl->power_fault_detected) 566 events &= ~PCI_EXP_SLTSTA_PFD; 567 568 if (!events) { 569 if (parent) 570 pm_runtime_put(parent); 571 return IRQ_NONE; 572 } 573 574 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, events); 575 ctrl_dbg(ctrl, "pending interrupts %#06x from Slot Status\n", events); 576 if (parent) 577 pm_runtime_put(parent); 578 579 /* 580 * Command Completed notifications are not deferred to the 581 * IRQ thread because it may be waiting for their arrival. 582 */ 583 if (events & PCI_EXP_SLTSTA_CC) { 584 ctrl->cmd_busy = 0; 585 smp_mb(); 586 wake_up(&ctrl->queue); 587 588 if (events == PCI_EXP_SLTSTA_CC) 589 return IRQ_HANDLED; 590 591 events &= ~PCI_EXP_SLTSTA_CC; 592 } 593 594 if (pdev->ignore_hotplug) { 595 ctrl_dbg(ctrl, "ignoring hotplug event %#06x\n", events); 596 return IRQ_HANDLED; 597 } 598 599 /* Save pending events for consumption by IRQ thread. */ 600 atomic_or(events, &ctrl->pending_events); 601 return IRQ_WAKE_THREAD; 602 } 603 604 static irqreturn_t pciehp_ist(int irq, void *dev_id) 605 { 606 struct controller *ctrl = (struct controller *)dev_id; 607 struct pci_dev *pdev = ctrl_dev(ctrl); 608 irqreturn_t ret; 609 u32 events; 610 611 pci_config_pm_runtime_get(pdev); 612 613 /* rerun pciehp_isr() if the port was inaccessible on interrupt */ 614 if (atomic_fetch_and(~RERUN_ISR, &ctrl->pending_events) & RERUN_ISR) { 615 ret = pciehp_isr(irq, dev_id); 616 enable_irq(irq); 617 if (ret != IRQ_WAKE_THREAD) { 618 pci_config_pm_runtime_put(pdev); 619 return ret; 620 } 621 } 622 623 synchronize_hardirq(irq); 624 events = atomic_xchg(&ctrl->pending_events, 0); 625 if (!events) { 626 pci_config_pm_runtime_put(pdev); 627 return IRQ_NONE; 628 } 629 630 /* Check Attention Button Pressed */ 631 if (events & PCI_EXP_SLTSTA_ABP) { 632 ctrl_info(ctrl, "Slot(%s): Attention button pressed\n", 633 slot_name(ctrl)); 634 pciehp_handle_button_press(ctrl); 635 } 636 637 /* Check Power Fault Detected */ 638 if ((events & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) { 639 ctrl->power_fault_detected = 1; 640 ctrl_err(ctrl, "Slot(%s): Power fault\n", slot_name(ctrl)); 641 pciehp_set_attention_status(ctrl, 1); 642 pciehp_green_led_off(ctrl); 643 } 644 645 /* 646 * Disable requests have higher priority than Presence Detect Changed 647 * or Data Link Layer State Changed events. 648 */ 649 down_read(&ctrl->reset_lock); 650 if (events & DISABLE_SLOT) 651 pciehp_handle_disable_request(ctrl); 652 else if (events & (PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_DLLSC)) 653 pciehp_handle_presence_or_link_change(ctrl, events); 654 up_read(&ctrl->reset_lock); 655 656 pci_config_pm_runtime_put(pdev); 657 wake_up(&ctrl->requester); 658 return IRQ_HANDLED; 659 } 660 661 static int pciehp_poll(void *data) 662 { 663 struct controller *ctrl = data; 664 665 schedule_timeout_idle(10 * HZ); /* start with 10 sec delay */ 666 667 while (!kthread_should_stop()) { 668 /* poll for interrupt events or user requests */ 669 while (pciehp_isr(IRQ_NOTCONNECTED, ctrl) == IRQ_WAKE_THREAD || 670 atomic_read(&ctrl->pending_events)) 671 pciehp_ist(IRQ_NOTCONNECTED, ctrl); 672 673 if (pciehp_poll_time <= 0 || pciehp_poll_time > 60) 674 pciehp_poll_time = 2; /* clamp to sane value */ 675 676 schedule_timeout_idle(pciehp_poll_time * HZ); 677 } 678 679 return 0; 680 } 681 682 static void pcie_enable_notification(struct controller *ctrl) 683 { 684 u16 cmd, mask; 685 686 /* 687 * TBD: Power fault detected software notification support. 688 * 689 * Power fault detected software notification is not enabled 690 * now, because it caused power fault detected interrupt storm 691 * on some machines. On those machines, power fault detected 692 * bit in the slot status register was set again immediately 693 * when it is cleared in the interrupt service routine, and 694 * next power fault detected interrupt was notified again. 695 */ 696 697 /* 698 * Always enable link events: thus link-up and link-down shall 699 * always be treated as hotplug and unplug respectively. Enable 700 * presence detect only if Attention Button is not present. 701 */ 702 cmd = PCI_EXP_SLTCTL_DLLSCE; 703 if (ATTN_BUTTN(ctrl)) 704 cmd |= PCI_EXP_SLTCTL_ABPE; 705 else 706 cmd |= PCI_EXP_SLTCTL_PDCE; 707 if (!pciehp_poll_mode) 708 cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE; 709 710 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE | 711 PCI_EXP_SLTCTL_PFDE | 712 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE | 713 PCI_EXP_SLTCTL_DLLSCE); 714 715 pcie_write_cmd_nowait(ctrl, cmd, mask); 716 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 717 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, cmd); 718 } 719 720 static void pcie_disable_notification(struct controller *ctrl) 721 { 722 u16 mask; 723 724 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE | 725 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE | 726 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE | 727 PCI_EXP_SLTCTL_DLLSCE); 728 pcie_write_cmd(ctrl, 0, mask); 729 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 730 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0); 731 } 732 733 void pcie_clear_hotplug_events(struct controller *ctrl) 734 { 735 pcie_capability_write_word(ctrl_dev(ctrl), PCI_EXP_SLTSTA, 736 PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_DLLSC); 737 } 738 739 void pcie_enable_interrupt(struct controller *ctrl) 740 { 741 u16 mask; 742 743 mask = PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_DLLSCE; 744 pcie_write_cmd(ctrl, mask, mask); 745 } 746 747 void pcie_disable_interrupt(struct controller *ctrl) 748 { 749 u16 mask; 750 751 /* 752 * Mask hot-plug interrupt to prevent it triggering immediately 753 * when the link goes inactive (we still get PME when any of the 754 * enabled events is detected). Same goes with Link Layer State 755 * changed event which generates PME immediately when the link goes 756 * inactive so mask it as well. 757 */ 758 mask = PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_DLLSCE; 759 pcie_write_cmd(ctrl, 0, mask); 760 } 761 762 /* 763 * pciehp has a 1:1 bus:slot relationship so we ultimately want a secondary 764 * bus reset of the bridge, but at the same time we want to ensure that it is 765 * not seen as a hot-unplug, followed by the hot-plug of the device. Thus, 766 * disable link state notification and presence detection change notification 767 * momentarily, if we see that they could interfere. Also, clear any spurious 768 * events after. 769 */ 770 int pciehp_reset_slot(struct hotplug_slot *hotplug_slot, int probe) 771 { 772 struct controller *ctrl = to_ctrl(hotplug_slot); 773 struct pci_dev *pdev = ctrl_dev(ctrl); 774 u16 stat_mask = 0, ctrl_mask = 0; 775 int rc; 776 777 if (probe) 778 return 0; 779 780 down_write(&ctrl->reset_lock); 781 782 if (!ATTN_BUTTN(ctrl)) { 783 ctrl_mask |= PCI_EXP_SLTCTL_PDCE; 784 stat_mask |= PCI_EXP_SLTSTA_PDC; 785 } 786 ctrl_mask |= PCI_EXP_SLTCTL_DLLSCE; 787 stat_mask |= PCI_EXP_SLTSTA_DLLSC; 788 789 pcie_write_cmd(ctrl, 0, ctrl_mask); 790 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 791 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0); 792 793 rc = pci_bridge_secondary_bus_reset(ctrl->pcie->port); 794 795 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, stat_mask); 796 pcie_write_cmd_nowait(ctrl, ctrl_mask, ctrl_mask); 797 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 798 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, ctrl_mask); 799 800 up_write(&ctrl->reset_lock); 801 return rc; 802 } 803 804 int pcie_init_notification(struct controller *ctrl) 805 { 806 if (pciehp_request_irq(ctrl)) 807 return -1; 808 pcie_enable_notification(ctrl); 809 ctrl->notification_enabled = 1; 810 return 0; 811 } 812 813 void pcie_shutdown_notification(struct controller *ctrl) 814 { 815 if (ctrl->notification_enabled) { 816 pcie_disable_notification(ctrl); 817 pciehp_free_irq(ctrl); 818 ctrl->notification_enabled = 0; 819 } 820 } 821 822 static inline void dbg_ctrl(struct controller *ctrl) 823 { 824 struct pci_dev *pdev = ctrl->pcie->port; 825 u16 reg16; 826 827 ctrl_dbg(ctrl, "Slot Capabilities : 0x%08x\n", ctrl->slot_cap); 828 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, ®16); 829 ctrl_dbg(ctrl, "Slot Status : 0x%04x\n", reg16); 830 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, ®16); 831 ctrl_dbg(ctrl, "Slot Control : 0x%04x\n", reg16); 832 } 833 834 #define FLAG(x, y) (((x) & (y)) ? '+' : '-') 835 836 struct controller *pcie_init(struct pcie_device *dev) 837 { 838 struct controller *ctrl; 839 u32 slot_cap, link_cap; 840 u8 poweron; 841 struct pci_dev *pdev = dev->port; 842 struct pci_bus *subordinate = pdev->subordinate; 843 844 ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL); 845 if (!ctrl) 846 return NULL; 847 848 ctrl->pcie = dev; 849 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap); 850 851 if (pdev->hotplug_user_indicators) 852 slot_cap &= ~(PCI_EXP_SLTCAP_AIP | PCI_EXP_SLTCAP_PIP); 853 854 /* 855 * We assume no Thunderbolt controllers support Command Complete events, 856 * but some controllers falsely claim they do. 857 */ 858 if (pdev->is_thunderbolt) 859 slot_cap |= PCI_EXP_SLTCAP_NCCS; 860 861 ctrl->slot_cap = slot_cap; 862 mutex_init(&ctrl->ctrl_lock); 863 mutex_init(&ctrl->state_lock); 864 init_rwsem(&ctrl->reset_lock); 865 init_waitqueue_head(&ctrl->requester); 866 init_waitqueue_head(&ctrl->queue); 867 INIT_DELAYED_WORK(&ctrl->button_work, pciehp_queue_pushbutton_work); 868 dbg_ctrl(ctrl); 869 870 down_read(&pci_bus_sem); 871 ctrl->state = list_empty(&subordinate->devices) ? OFF_STATE : ON_STATE; 872 up_read(&pci_bus_sem); 873 874 /* Check if Data Link Layer Link Active Reporting is implemented */ 875 pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &link_cap); 876 877 /* Clear all remaining event bits in Slot Status register. */ 878 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, 879 PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD | 880 PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_CC | 881 PCI_EXP_SLTSTA_DLLSC | PCI_EXP_SLTSTA_PDC); 882 883 ctrl_info(ctrl, "Slot #%d AttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surprise%c Interlock%c NoCompl%c LLActRep%c%s\n", 884 (slot_cap & PCI_EXP_SLTCAP_PSN) >> 19, 885 FLAG(slot_cap, PCI_EXP_SLTCAP_ABP), 886 FLAG(slot_cap, PCI_EXP_SLTCAP_PCP), 887 FLAG(slot_cap, PCI_EXP_SLTCAP_MRLSP), 888 FLAG(slot_cap, PCI_EXP_SLTCAP_AIP), 889 FLAG(slot_cap, PCI_EXP_SLTCAP_PIP), 890 FLAG(slot_cap, PCI_EXP_SLTCAP_HPC), 891 FLAG(slot_cap, PCI_EXP_SLTCAP_HPS), 892 FLAG(slot_cap, PCI_EXP_SLTCAP_EIP), 893 FLAG(slot_cap, PCI_EXP_SLTCAP_NCCS), 894 FLAG(link_cap, PCI_EXP_LNKCAP_DLLLARC), 895 pdev->broken_cmd_compl ? " (with Cmd Compl erratum)" : ""); 896 897 /* 898 * If empty slot's power status is on, turn power off. The IRQ isn't 899 * requested yet, so avoid triggering a notification with this command. 900 */ 901 if (POWER_CTRL(ctrl)) { 902 pciehp_get_power_status(ctrl, &poweron); 903 if (!pciehp_card_present_or_link_active(ctrl) && poweron) { 904 pcie_disable_notification(ctrl); 905 pciehp_power_off_slot(ctrl); 906 } 907 } 908 909 return ctrl; 910 } 911 912 void pciehp_release_ctrl(struct controller *ctrl) 913 { 914 cancel_delayed_work_sync(&ctrl->button_work); 915 kfree(ctrl); 916 } 917 918 static void quirk_cmd_compl(struct pci_dev *pdev) 919 { 920 u32 slot_cap; 921 922 if (pci_is_pcie(pdev)) { 923 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap); 924 if (slot_cap & PCI_EXP_SLTCAP_HPC && 925 !(slot_cap & PCI_EXP_SLTCAP_NCCS)) 926 pdev->broken_cmd_compl = 1; 927 } 928 } 929 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 930 PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl); 931 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_QCOM, 0x0400, 932 PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl); 933 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_QCOM, 0x0401, 934 PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl); 935 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_HXT, 0x0401, 936 PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl); 937