1 /* 2 * PCI Express PCI Hot Plug Driver 3 * 4 * Copyright (C) 1995,2001 Compaq Computer Corporation 5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com) 6 * Copyright (C) 2001 IBM Corp. 7 * Copyright (C) 2003-2004 Intel Corporation 8 * 9 * All rights reserved. 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or (at 14 * your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 19 * NON INFRINGEMENT. See the GNU General Public License for more 20 * details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 25 * 26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com> 27 * 28 */ 29 30 #include <linux/kernel.h> 31 #include <linux/module.h> 32 #include <linux/types.h> 33 #include <linux/signal.h> 34 #include <linux/jiffies.h> 35 #include <linux/timer.h> 36 #include <linux/pci.h> 37 #include <linux/interrupt.h> 38 #include <linux/time.h> 39 40 #include "../pci.h" 41 #include "pciehp.h" 42 43 static atomic_t pciehp_num_controllers = ATOMIC_INIT(0); 44 45 static inline int pciehp_readw(struct controller *ctrl, int reg, u16 *value) 46 { 47 struct pci_dev *dev = ctrl->pcie->port; 48 return pci_read_config_word(dev, pci_pcie_cap(dev) + reg, value); 49 } 50 51 static inline int pciehp_readl(struct controller *ctrl, int reg, u32 *value) 52 { 53 struct pci_dev *dev = ctrl->pcie->port; 54 return pci_read_config_dword(dev, pci_pcie_cap(dev) + reg, value); 55 } 56 57 static inline int pciehp_writew(struct controller *ctrl, int reg, u16 value) 58 { 59 struct pci_dev *dev = ctrl->pcie->port; 60 return pci_write_config_word(dev, pci_pcie_cap(dev) + reg, value); 61 } 62 63 static inline int pciehp_writel(struct controller *ctrl, int reg, u32 value) 64 { 65 struct pci_dev *dev = ctrl->pcie->port; 66 return pci_write_config_dword(dev, pci_pcie_cap(dev) + reg, value); 67 } 68 69 /* Power Control Command */ 70 #define POWER_ON 0 71 #define POWER_OFF PCI_EXP_SLTCTL_PCC 72 73 static irqreturn_t pcie_isr(int irq, void *dev_id); 74 static void start_int_poll_timer(struct controller *ctrl, int sec); 75 76 /* This is the interrupt polling timeout function. */ 77 static void int_poll_timeout(unsigned long data) 78 { 79 struct controller *ctrl = (struct controller *)data; 80 81 /* Poll for interrupt events. regs == NULL => polling */ 82 pcie_isr(0, ctrl); 83 84 init_timer(&ctrl->poll_timer); 85 if (!pciehp_poll_time) 86 pciehp_poll_time = 2; /* default polling interval is 2 sec */ 87 88 start_int_poll_timer(ctrl, pciehp_poll_time); 89 } 90 91 /* This function starts the interrupt polling timer. */ 92 static void start_int_poll_timer(struct controller *ctrl, int sec) 93 { 94 /* Clamp to sane value */ 95 if ((sec <= 0) || (sec > 60)) 96 sec = 2; 97 98 ctrl->poll_timer.function = &int_poll_timeout; 99 ctrl->poll_timer.data = (unsigned long)ctrl; 100 ctrl->poll_timer.expires = jiffies + sec * HZ; 101 add_timer(&ctrl->poll_timer); 102 } 103 104 static inline int pciehp_request_irq(struct controller *ctrl) 105 { 106 int retval, irq = ctrl->pcie->irq; 107 108 /* Install interrupt polling timer. Start with 10 sec delay */ 109 if (pciehp_poll_mode) { 110 init_timer(&ctrl->poll_timer); 111 start_int_poll_timer(ctrl, 10); 112 return 0; 113 } 114 115 /* Installs the interrupt handler */ 116 retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl); 117 if (retval) 118 ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n", 119 irq); 120 return retval; 121 } 122 123 static inline void pciehp_free_irq(struct controller *ctrl) 124 { 125 if (pciehp_poll_mode) 126 del_timer_sync(&ctrl->poll_timer); 127 else 128 free_irq(ctrl->pcie->irq, ctrl); 129 } 130 131 static int pcie_poll_cmd(struct controller *ctrl) 132 { 133 u16 slot_status; 134 int err, timeout = 1000; 135 136 err = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); 137 if (!err && (slot_status & PCI_EXP_SLTSTA_CC)) { 138 pciehp_writew(ctrl, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_CC); 139 return 1; 140 } 141 while (timeout > 0) { 142 msleep(10); 143 timeout -= 10; 144 err = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); 145 if (!err && (slot_status & PCI_EXP_SLTSTA_CC)) { 146 pciehp_writew(ctrl, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_CC); 147 return 1; 148 } 149 } 150 return 0; /* timeout */ 151 } 152 153 static void pcie_wait_cmd(struct controller *ctrl, int poll) 154 { 155 unsigned int msecs = pciehp_poll_mode ? 2500 : 1000; 156 unsigned long timeout = msecs_to_jiffies(msecs); 157 int rc; 158 159 if (poll) 160 rc = pcie_poll_cmd(ctrl); 161 else 162 rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout); 163 if (!rc) 164 ctrl_dbg(ctrl, "Command not completed in 1000 msec\n"); 165 } 166 167 /** 168 * pcie_write_cmd - Issue controller command 169 * @ctrl: controller to which the command is issued 170 * @cmd: command value written to slot control register 171 * @mask: bitmask of slot control register to be modified 172 */ 173 static int pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask) 174 { 175 int retval = 0; 176 u16 slot_status; 177 u16 slot_ctrl; 178 179 mutex_lock(&ctrl->ctrl_lock); 180 181 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); 182 if (retval) { 183 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n", 184 __func__); 185 goto out; 186 } 187 188 if (slot_status & PCI_EXP_SLTSTA_CC) { 189 if (!ctrl->no_cmd_complete) { 190 /* 191 * After 1 sec and CMD_COMPLETED still not set, just 192 * proceed forward to issue the next command according 193 * to spec. Just print out the error message. 194 */ 195 ctrl_dbg(ctrl, "CMD_COMPLETED not clear after 1 sec\n"); 196 } else if (!NO_CMD_CMPL(ctrl)) { 197 /* 198 * This controller semms to notify of command completed 199 * event even though it supports none of power 200 * controller, attention led, power led and EMI. 201 */ 202 ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Need to " 203 "wait for command completed event.\n"); 204 ctrl->no_cmd_complete = 0; 205 } else { 206 ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Maybe " 207 "the controller is broken.\n"); 208 } 209 } 210 211 retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl); 212 if (retval) { 213 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__); 214 goto out; 215 } 216 217 slot_ctrl &= ~mask; 218 slot_ctrl |= (cmd & mask); 219 ctrl->cmd_busy = 1; 220 smp_mb(); 221 retval = pciehp_writew(ctrl, PCI_EXP_SLTCTL, slot_ctrl); 222 if (retval) 223 ctrl_err(ctrl, "Cannot write to SLOTCTRL register\n"); 224 225 /* 226 * Wait for command completion. 227 */ 228 if (!retval && !ctrl->no_cmd_complete) { 229 int poll = 0; 230 /* 231 * if hotplug interrupt is not enabled or command 232 * completed interrupt is not enabled, we need to poll 233 * command completed event. 234 */ 235 if (!(slot_ctrl & PCI_EXP_SLTCTL_HPIE) || 236 !(slot_ctrl & PCI_EXP_SLTCTL_CCIE)) 237 poll = 1; 238 pcie_wait_cmd(ctrl, poll); 239 } 240 out: 241 mutex_unlock(&ctrl->ctrl_lock); 242 return retval; 243 } 244 245 static inline int check_link_active(struct controller *ctrl) 246 { 247 u16 link_status; 248 249 if (pciehp_readw(ctrl, PCI_EXP_LNKSTA, &link_status)) 250 return 0; 251 return !!(link_status & PCI_EXP_LNKSTA_DLLLA); 252 } 253 254 static void pcie_wait_link_active(struct controller *ctrl) 255 { 256 int timeout = 1000; 257 258 if (check_link_active(ctrl)) 259 return; 260 while (timeout > 0) { 261 msleep(10); 262 timeout -= 10; 263 if (check_link_active(ctrl)) 264 return; 265 } 266 ctrl_dbg(ctrl, "Data Link Layer Link Active not set in 1000 msec\n"); 267 } 268 269 int pciehp_check_link_status(struct controller *ctrl) 270 { 271 u16 lnk_status; 272 int retval = 0; 273 274 /* 275 * Data Link Layer Link Active Reporting must be capable for 276 * hot-plug capable downstream port. But old controller might 277 * not implement it. In this case, we wait for 1000 ms. 278 */ 279 if (ctrl->link_active_reporting){ 280 /* Wait for Data Link Layer Link Active bit to be set */ 281 pcie_wait_link_active(ctrl); 282 /* 283 * We must wait for 100 ms after the Data Link Layer 284 * Link Active bit reads 1b before initiating a 285 * configuration access to the hot added device. 286 */ 287 msleep(100); 288 } else 289 msleep(1000); 290 291 retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status); 292 if (retval) { 293 ctrl_err(ctrl, "Cannot read LNKSTATUS register\n"); 294 return retval; 295 } 296 297 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status); 298 if ((lnk_status & PCI_EXP_LNKSTA_LT) || 299 !(lnk_status & PCI_EXP_LNKSTA_NLW)) { 300 ctrl_err(ctrl, "Link Training Error occurs \n"); 301 retval = -1; 302 return retval; 303 } 304 305 return retval; 306 } 307 308 int pciehp_get_attention_status(struct slot *slot, u8 *status) 309 { 310 struct controller *ctrl = slot->ctrl; 311 u16 slot_ctrl; 312 u8 atten_led_state; 313 int retval = 0; 314 315 retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl); 316 if (retval) { 317 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__); 318 return retval; 319 } 320 321 ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__, 322 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl); 323 324 atten_led_state = (slot_ctrl & PCI_EXP_SLTCTL_AIC) >> 6; 325 326 switch (atten_led_state) { 327 case 0: 328 *status = 0xFF; /* Reserved */ 329 break; 330 case 1: 331 *status = 1; /* On */ 332 break; 333 case 2: 334 *status = 2; /* Blink */ 335 break; 336 case 3: 337 *status = 0; /* Off */ 338 break; 339 default: 340 *status = 0xFF; 341 break; 342 } 343 344 return 0; 345 } 346 347 int pciehp_get_power_status(struct slot *slot, u8 *status) 348 { 349 struct controller *ctrl = slot->ctrl; 350 u16 slot_ctrl; 351 u8 pwr_state; 352 int retval = 0; 353 354 retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl); 355 if (retval) { 356 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__); 357 return retval; 358 } 359 ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__, 360 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl); 361 362 pwr_state = (slot_ctrl & PCI_EXP_SLTCTL_PCC) >> 10; 363 364 switch (pwr_state) { 365 case 0: 366 *status = 1; 367 break; 368 case 1: 369 *status = 0; 370 break; 371 default: 372 *status = 0xFF; 373 break; 374 } 375 376 return retval; 377 } 378 379 int pciehp_get_latch_status(struct slot *slot, u8 *status) 380 { 381 struct controller *ctrl = slot->ctrl; 382 u16 slot_status; 383 int retval; 384 385 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); 386 if (retval) { 387 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n", 388 __func__); 389 return retval; 390 } 391 *status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS); 392 return 0; 393 } 394 395 int pciehp_get_adapter_status(struct slot *slot, u8 *status) 396 { 397 struct controller *ctrl = slot->ctrl; 398 u16 slot_status; 399 int retval; 400 401 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); 402 if (retval) { 403 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n", 404 __func__); 405 return retval; 406 } 407 *status = !!(slot_status & PCI_EXP_SLTSTA_PDS); 408 return 0; 409 } 410 411 int pciehp_query_power_fault(struct slot *slot) 412 { 413 struct controller *ctrl = slot->ctrl; 414 u16 slot_status; 415 int retval; 416 417 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); 418 if (retval) { 419 ctrl_err(ctrl, "Cannot check for power fault\n"); 420 return retval; 421 } 422 return !!(slot_status & PCI_EXP_SLTSTA_PFD); 423 } 424 425 int pciehp_set_attention_status(struct slot *slot, u8 value) 426 { 427 struct controller *ctrl = slot->ctrl; 428 u16 slot_cmd; 429 u16 cmd_mask; 430 431 cmd_mask = PCI_EXP_SLTCTL_AIC; 432 switch (value) { 433 case 0 : /* turn off */ 434 slot_cmd = 0x00C0; 435 break; 436 case 1: /* turn on */ 437 slot_cmd = 0x0040; 438 break; 439 case 2: /* turn blink */ 440 slot_cmd = 0x0080; 441 break; 442 default: 443 return -EINVAL; 444 } 445 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 446 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); 447 return pcie_write_cmd(ctrl, slot_cmd, cmd_mask); 448 } 449 450 void pciehp_green_led_on(struct slot *slot) 451 { 452 struct controller *ctrl = slot->ctrl; 453 u16 slot_cmd; 454 u16 cmd_mask; 455 456 slot_cmd = 0x0100; 457 cmd_mask = PCI_EXP_SLTCTL_PIC; 458 pcie_write_cmd(ctrl, slot_cmd, cmd_mask); 459 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 460 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); 461 } 462 463 void pciehp_green_led_off(struct slot *slot) 464 { 465 struct controller *ctrl = slot->ctrl; 466 u16 slot_cmd; 467 u16 cmd_mask; 468 469 slot_cmd = 0x0300; 470 cmd_mask = PCI_EXP_SLTCTL_PIC; 471 pcie_write_cmd(ctrl, slot_cmd, cmd_mask); 472 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 473 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); 474 } 475 476 void pciehp_green_led_blink(struct slot *slot) 477 { 478 struct controller *ctrl = slot->ctrl; 479 u16 slot_cmd; 480 u16 cmd_mask; 481 482 slot_cmd = 0x0200; 483 cmd_mask = PCI_EXP_SLTCTL_PIC; 484 pcie_write_cmd(ctrl, slot_cmd, cmd_mask); 485 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 486 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); 487 } 488 489 int pciehp_power_on_slot(struct slot * slot) 490 { 491 struct controller *ctrl = slot->ctrl; 492 u16 slot_cmd; 493 u16 cmd_mask; 494 u16 slot_status; 495 int retval = 0; 496 497 /* Clear sticky power-fault bit from previous power failures */ 498 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); 499 if (retval) { 500 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n", 501 __func__); 502 return retval; 503 } 504 slot_status &= PCI_EXP_SLTSTA_PFD; 505 if (slot_status) { 506 retval = pciehp_writew(ctrl, PCI_EXP_SLTSTA, slot_status); 507 if (retval) { 508 ctrl_err(ctrl, 509 "%s: Cannot write to SLOTSTATUS register\n", 510 __func__); 511 return retval; 512 } 513 } 514 ctrl->power_fault_detected = 0; 515 516 slot_cmd = POWER_ON; 517 cmd_mask = PCI_EXP_SLTCTL_PCC; 518 retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask); 519 if (retval) { 520 ctrl_err(ctrl, "Write %x command failed!\n", slot_cmd); 521 return retval; 522 } 523 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 524 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); 525 526 return retval; 527 } 528 529 int pciehp_power_off_slot(struct slot * slot) 530 { 531 struct controller *ctrl = slot->ctrl; 532 u16 slot_cmd; 533 u16 cmd_mask; 534 int retval; 535 536 slot_cmd = POWER_OFF; 537 cmd_mask = PCI_EXP_SLTCTL_PCC; 538 retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask); 539 if (retval) { 540 ctrl_err(ctrl, "Write command failed!\n"); 541 return retval; 542 } 543 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 544 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); 545 return 0; 546 } 547 548 static irqreturn_t pcie_isr(int irq, void *dev_id) 549 { 550 struct controller *ctrl = (struct controller *)dev_id; 551 struct slot *slot = ctrl->slot; 552 u16 detected, intr_loc; 553 554 /* 555 * In order to guarantee that all interrupt events are 556 * serviced, we need to re-inspect Slot Status register after 557 * clearing what is presumed to be the last pending interrupt. 558 */ 559 intr_loc = 0; 560 do { 561 if (pciehp_readw(ctrl, PCI_EXP_SLTSTA, &detected)) { 562 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS\n", 563 __func__); 564 return IRQ_NONE; 565 } 566 567 detected &= (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD | 568 PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC | 569 PCI_EXP_SLTSTA_CC); 570 detected &= ~intr_loc; 571 intr_loc |= detected; 572 if (!intr_loc) 573 return IRQ_NONE; 574 if (detected && pciehp_writew(ctrl, PCI_EXP_SLTSTA, intr_loc)) { 575 ctrl_err(ctrl, "%s: Cannot write to SLOTSTATUS\n", 576 __func__); 577 return IRQ_NONE; 578 } 579 } while (detected); 580 581 ctrl_dbg(ctrl, "%s: intr_loc %x\n", __func__, intr_loc); 582 583 /* Check Command Complete Interrupt Pending */ 584 if (intr_loc & PCI_EXP_SLTSTA_CC) { 585 ctrl->cmd_busy = 0; 586 smp_mb(); 587 wake_up(&ctrl->queue); 588 } 589 590 if (!(intr_loc & ~PCI_EXP_SLTSTA_CC)) 591 return IRQ_HANDLED; 592 593 /* Check MRL Sensor Changed */ 594 if (intr_loc & PCI_EXP_SLTSTA_MRLSC) 595 pciehp_handle_switch_change(slot); 596 597 /* Check Attention Button Pressed */ 598 if (intr_loc & PCI_EXP_SLTSTA_ABP) 599 pciehp_handle_attention_button(slot); 600 601 /* Check Presence Detect Changed */ 602 if (intr_loc & PCI_EXP_SLTSTA_PDC) 603 pciehp_handle_presence_change(slot); 604 605 /* Check Power Fault Detected */ 606 if ((intr_loc & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) { 607 ctrl->power_fault_detected = 1; 608 pciehp_handle_power_fault(slot); 609 } 610 return IRQ_HANDLED; 611 } 612 613 int pciehp_get_max_link_speed(struct slot *slot, enum pci_bus_speed *value) 614 { 615 struct controller *ctrl = slot->ctrl; 616 enum pcie_link_speed lnk_speed; 617 u32 lnk_cap; 618 int retval = 0; 619 620 retval = pciehp_readl(ctrl, PCI_EXP_LNKCAP, &lnk_cap); 621 if (retval) { 622 ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__); 623 return retval; 624 } 625 626 switch (lnk_cap & 0x000F) { 627 case 1: 628 lnk_speed = PCIE_2_5GB; 629 break; 630 case 2: 631 lnk_speed = PCIE_5_0GB; 632 break; 633 default: 634 lnk_speed = PCIE_LNK_SPEED_UNKNOWN; 635 break; 636 } 637 638 *value = lnk_speed; 639 ctrl_dbg(ctrl, "Max link speed = %d\n", lnk_speed); 640 641 return retval; 642 } 643 644 int pciehp_get_max_lnk_width(struct slot *slot, 645 enum pcie_link_width *value) 646 { 647 struct controller *ctrl = slot->ctrl; 648 enum pcie_link_width lnk_wdth; 649 u32 lnk_cap; 650 int retval = 0; 651 652 retval = pciehp_readl(ctrl, PCI_EXP_LNKCAP, &lnk_cap); 653 if (retval) { 654 ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__); 655 return retval; 656 } 657 658 switch ((lnk_cap & PCI_EXP_LNKSTA_NLW) >> 4){ 659 case 0: 660 lnk_wdth = PCIE_LNK_WIDTH_RESRV; 661 break; 662 case 1: 663 lnk_wdth = PCIE_LNK_X1; 664 break; 665 case 2: 666 lnk_wdth = PCIE_LNK_X2; 667 break; 668 case 4: 669 lnk_wdth = PCIE_LNK_X4; 670 break; 671 case 8: 672 lnk_wdth = PCIE_LNK_X8; 673 break; 674 case 12: 675 lnk_wdth = PCIE_LNK_X12; 676 break; 677 case 16: 678 lnk_wdth = PCIE_LNK_X16; 679 break; 680 case 32: 681 lnk_wdth = PCIE_LNK_X32; 682 break; 683 default: 684 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; 685 break; 686 } 687 688 *value = lnk_wdth; 689 ctrl_dbg(ctrl, "Max link width = %d\n", lnk_wdth); 690 691 return retval; 692 } 693 694 int pciehp_get_cur_link_speed(struct slot *slot, enum pci_bus_speed *value) 695 { 696 struct controller *ctrl = slot->ctrl; 697 enum pcie_link_speed lnk_speed = PCI_SPEED_UNKNOWN; 698 int retval = 0; 699 u16 lnk_status; 700 701 retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status); 702 if (retval) { 703 ctrl_err(ctrl, "%s: Cannot read LNKSTATUS register\n", 704 __func__); 705 return retval; 706 } 707 708 switch (lnk_status & PCI_EXP_LNKSTA_CLS) { 709 case 1: 710 lnk_speed = PCIE_2_5GB; 711 break; 712 case 2: 713 lnk_speed = PCIE_5_0GB; 714 break; 715 default: 716 lnk_speed = PCIE_LNK_SPEED_UNKNOWN; 717 break; 718 } 719 720 *value = lnk_speed; 721 ctrl_dbg(ctrl, "Current link speed = %d\n", lnk_speed); 722 723 return retval; 724 } 725 726 int pciehp_get_cur_lnk_width(struct slot *slot, 727 enum pcie_link_width *value) 728 { 729 struct controller *ctrl = slot->ctrl; 730 enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; 731 int retval = 0; 732 u16 lnk_status; 733 734 retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status); 735 if (retval) { 736 ctrl_err(ctrl, "%s: Cannot read LNKSTATUS register\n", 737 __func__); 738 return retval; 739 } 740 741 switch ((lnk_status & PCI_EXP_LNKSTA_NLW) >> 4){ 742 case 0: 743 lnk_wdth = PCIE_LNK_WIDTH_RESRV; 744 break; 745 case 1: 746 lnk_wdth = PCIE_LNK_X1; 747 break; 748 case 2: 749 lnk_wdth = PCIE_LNK_X2; 750 break; 751 case 4: 752 lnk_wdth = PCIE_LNK_X4; 753 break; 754 case 8: 755 lnk_wdth = PCIE_LNK_X8; 756 break; 757 case 12: 758 lnk_wdth = PCIE_LNK_X12; 759 break; 760 case 16: 761 lnk_wdth = PCIE_LNK_X16; 762 break; 763 case 32: 764 lnk_wdth = PCIE_LNK_X32; 765 break; 766 default: 767 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; 768 break; 769 } 770 771 *value = lnk_wdth; 772 ctrl_dbg(ctrl, "Current link width = %d\n", lnk_wdth); 773 774 return retval; 775 } 776 777 int pcie_enable_notification(struct controller *ctrl) 778 { 779 u16 cmd, mask; 780 781 /* 782 * TBD: Power fault detected software notification support. 783 * 784 * Power fault detected software notification is not enabled 785 * now, because it caused power fault detected interrupt storm 786 * on some machines. On those machines, power fault detected 787 * bit in the slot status register was set again immediately 788 * when it is cleared in the interrupt service routine, and 789 * next power fault detected interrupt was notified again. 790 */ 791 cmd = PCI_EXP_SLTCTL_PDCE; 792 if (ATTN_BUTTN(ctrl)) 793 cmd |= PCI_EXP_SLTCTL_ABPE; 794 if (MRL_SENS(ctrl)) 795 cmd |= PCI_EXP_SLTCTL_MRLSCE; 796 if (!pciehp_poll_mode) 797 cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE; 798 799 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE | 800 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE | 801 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE); 802 803 if (pcie_write_cmd(ctrl, cmd, mask)) { 804 ctrl_err(ctrl, "Cannot enable software notification\n"); 805 return -1; 806 } 807 return 0; 808 } 809 810 static void pcie_disable_notification(struct controller *ctrl) 811 { 812 u16 mask; 813 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE | 814 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE | 815 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE | 816 PCI_EXP_SLTCTL_DLLSCE); 817 if (pcie_write_cmd(ctrl, 0, mask)) 818 ctrl_warn(ctrl, "Cannot disable software notification\n"); 819 } 820 821 int pcie_init_notification(struct controller *ctrl) 822 { 823 if (pciehp_request_irq(ctrl)) 824 return -1; 825 if (pcie_enable_notification(ctrl)) { 826 pciehp_free_irq(ctrl); 827 return -1; 828 } 829 ctrl->notification_enabled = 1; 830 return 0; 831 } 832 833 static void pcie_shutdown_notification(struct controller *ctrl) 834 { 835 if (ctrl->notification_enabled) { 836 pcie_disable_notification(ctrl); 837 pciehp_free_irq(ctrl); 838 ctrl->notification_enabled = 0; 839 } 840 } 841 842 static int pcie_init_slot(struct controller *ctrl) 843 { 844 struct slot *slot; 845 846 slot = kzalloc(sizeof(*slot), GFP_KERNEL); 847 if (!slot) 848 return -ENOMEM; 849 850 slot->ctrl = ctrl; 851 mutex_init(&slot->lock); 852 INIT_DELAYED_WORK(&slot->work, pciehp_queue_pushbutton_work); 853 ctrl->slot = slot; 854 return 0; 855 } 856 857 static void pcie_cleanup_slot(struct controller *ctrl) 858 { 859 struct slot *slot = ctrl->slot; 860 cancel_delayed_work(&slot->work); 861 flush_scheduled_work(); 862 flush_workqueue(pciehp_wq); 863 kfree(slot); 864 } 865 866 static inline void dbg_ctrl(struct controller *ctrl) 867 { 868 int i; 869 u16 reg16; 870 struct pci_dev *pdev = ctrl->pcie->port; 871 872 if (!pciehp_debug) 873 return; 874 875 ctrl_info(ctrl, "Hotplug Controller:\n"); 876 ctrl_info(ctrl, " Seg/Bus/Dev/Func/IRQ : %s IRQ %d\n", 877 pci_name(pdev), pdev->irq); 878 ctrl_info(ctrl, " Vendor ID : 0x%04x\n", pdev->vendor); 879 ctrl_info(ctrl, " Device ID : 0x%04x\n", pdev->device); 880 ctrl_info(ctrl, " Subsystem ID : 0x%04x\n", 881 pdev->subsystem_device); 882 ctrl_info(ctrl, " Subsystem Vendor ID : 0x%04x\n", 883 pdev->subsystem_vendor); 884 ctrl_info(ctrl, " PCIe Cap offset : 0x%02x\n", 885 pci_pcie_cap(pdev)); 886 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 887 if (!pci_resource_len(pdev, i)) 888 continue; 889 ctrl_info(ctrl, " PCI resource [%d] : 0x%llx@0x%llx\n", 890 i, (unsigned long long)pci_resource_len(pdev, i), 891 (unsigned long long)pci_resource_start(pdev, i)); 892 } 893 ctrl_info(ctrl, "Slot Capabilities : 0x%08x\n", ctrl->slot_cap); 894 ctrl_info(ctrl, " Physical Slot Number : %d\n", PSN(ctrl)); 895 ctrl_info(ctrl, " Attention Button : %3s\n", 896 ATTN_BUTTN(ctrl) ? "yes" : "no"); 897 ctrl_info(ctrl, " Power Controller : %3s\n", 898 POWER_CTRL(ctrl) ? "yes" : "no"); 899 ctrl_info(ctrl, " MRL Sensor : %3s\n", 900 MRL_SENS(ctrl) ? "yes" : "no"); 901 ctrl_info(ctrl, " Attention Indicator : %3s\n", 902 ATTN_LED(ctrl) ? "yes" : "no"); 903 ctrl_info(ctrl, " Power Indicator : %3s\n", 904 PWR_LED(ctrl) ? "yes" : "no"); 905 ctrl_info(ctrl, " Hot-Plug Surprise : %3s\n", 906 HP_SUPR_RM(ctrl) ? "yes" : "no"); 907 ctrl_info(ctrl, " EMI Present : %3s\n", 908 EMI(ctrl) ? "yes" : "no"); 909 ctrl_info(ctrl, " Command Completed : %3s\n", 910 NO_CMD_CMPL(ctrl) ? "no" : "yes"); 911 pciehp_readw(ctrl, PCI_EXP_SLTSTA, ®16); 912 ctrl_info(ctrl, "Slot Status : 0x%04x\n", reg16); 913 pciehp_readw(ctrl, PCI_EXP_SLTCTL, ®16); 914 ctrl_info(ctrl, "Slot Control : 0x%04x\n", reg16); 915 } 916 917 struct controller *pcie_init(struct pcie_device *dev) 918 { 919 struct controller *ctrl; 920 u32 slot_cap, link_cap; 921 struct pci_dev *pdev = dev->port; 922 923 ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL); 924 if (!ctrl) { 925 dev_err(&dev->device, "%s: Out of memory\n", __func__); 926 goto abort; 927 } 928 ctrl->pcie = dev; 929 if (!pci_pcie_cap(pdev)) { 930 ctrl_err(ctrl, "Cannot find PCI Express capability\n"); 931 goto abort_ctrl; 932 } 933 if (pciehp_readl(ctrl, PCI_EXP_SLTCAP, &slot_cap)) { 934 ctrl_err(ctrl, "Cannot read SLOTCAP register\n"); 935 goto abort_ctrl; 936 } 937 938 ctrl->slot_cap = slot_cap; 939 mutex_init(&ctrl->ctrl_lock); 940 init_waitqueue_head(&ctrl->queue); 941 dbg_ctrl(ctrl); 942 /* 943 * Controller doesn't notify of command completion if the "No 944 * Command Completed Support" bit is set in Slot Capability 945 * register or the controller supports none of power 946 * controller, attention led, power led and EMI. 947 */ 948 if (NO_CMD_CMPL(ctrl) || 949 !(POWER_CTRL(ctrl) | ATTN_LED(ctrl) | PWR_LED(ctrl) | EMI(ctrl))) 950 ctrl->no_cmd_complete = 1; 951 952 /* Check if Data Link Layer Link Active Reporting is implemented */ 953 if (pciehp_readl(ctrl, PCI_EXP_LNKCAP, &link_cap)) { 954 ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__); 955 goto abort_ctrl; 956 } 957 if (link_cap & PCI_EXP_LNKCAP_DLLLARC) { 958 ctrl_dbg(ctrl, "Link Active Reporting supported\n"); 959 ctrl->link_active_reporting = 1; 960 } 961 962 /* Clear all remaining event bits in Slot Status register */ 963 if (pciehp_writew(ctrl, PCI_EXP_SLTSTA, 0x1f)) 964 goto abort_ctrl; 965 966 /* Disable sotfware notification */ 967 pcie_disable_notification(ctrl); 968 969 /* 970 * If this is the first controller to be initialized, 971 * initialize the pciehp work queue 972 */ 973 if (atomic_add_return(1, &pciehp_num_controllers) == 1) { 974 pciehp_wq = create_singlethread_workqueue("pciehpd"); 975 if (!pciehp_wq) 976 goto abort_ctrl; 977 } 978 979 ctrl_info(ctrl, "HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", 980 pdev->vendor, pdev->device, pdev->subsystem_vendor, 981 pdev->subsystem_device); 982 983 if (pcie_init_slot(ctrl)) 984 goto abort_ctrl; 985 986 return ctrl; 987 988 abort_ctrl: 989 kfree(ctrl); 990 abort: 991 return NULL; 992 } 993 994 void pciehp_release_ctrl(struct controller *ctrl) 995 { 996 pcie_shutdown_notification(ctrl); 997 pcie_cleanup_slot(ctrl); 998 /* 999 * If this is the last controller to be released, destroy the 1000 * pciehp work queue 1001 */ 1002 if (atomic_dec_and_test(&pciehp_num_controllers)) 1003 destroy_workqueue(pciehp_wq); 1004 kfree(ctrl); 1005 } 1006