1 /* 2 * PCI Express PCI Hot Plug Driver 3 * 4 * Copyright (C) 1995,2001 Compaq Computer Corporation 5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com) 6 * Copyright (C) 2001 IBM Corp. 7 * Copyright (C) 2003-2004 Intel Corporation 8 * 9 * All rights reserved. 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or (at 14 * your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 19 * NON INFRINGEMENT. See the GNU General Public License for more 20 * details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 25 * 26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com> 27 * 28 */ 29 30 #include <linux/kernel.h> 31 #include <linux/module.h> 32 #include <linux/types.h> 33 #include <linux/signal.h> 34 #include <linux/jiffies.h> 35 #include <linux/timer.h> 36 #include <linux/pci.h> 37 #include <linux/interrupt.h> 38 #include <linux/time.h> 39 #include <linux/slab.h> 40 41 #include "../pci.h" 42 #include "pciehp.h" 43 44 static inline int pciehp_readw(struct controller *ctrl, int reg, u16 *value) 45 { 46 struct pci_dev *dev = ctrl->pcie->port; 47 return pci_read_config_word(dev, pci_pcie_cap(dev) + reg, value); 48 } 49 50 static inline int pciehp_readl(struct controller *ctrl, int reg, u32 *value) 51 { 52 struct pci_dev *dev = ctrl->pcie->port; 53 return pci_read_config_dword(dev, pci_pcie_cap(dev) + reg, value); 54 } 55 56 static inline int pciehp_writew(struct controller *ctrl, int reg, u16 value) 57 { 58 struct pci_dev *dev = ctrl->pcie->port; 59 return pci_write_config_word(dev, pci_pcie_cap(dev) + reg, value); 60 } 61 62 static inline int pciehp_writel(struct controller *ctrl, int reg, u32 value) 63 { 64 struct pci_dev *dev = ctrl->pcie->port; 65 return pci_write_config_dword(dev, pci_pcie_cap(dev) + reg, value); 66 } 67 68 /* Power Control Command */ 69 #define POWER_ON 0 70 #define POWER_OFF PCI_EXP_SLTCTL_PCC 71 72 static irqreturn_t pcie_isr(int irq, void *dev_id); 73 static void start_int_poll_timer(struct controller *ctrl, int sec); 74 75 /* This is the interrupt polling timeout function. */ 76 static void int_poll_timeout(unsigned long data) 77 { 78 struct controller *ctrl = (struct controller *)data; 79 80 /* Poll for interrupt events. regs == NULL => polling */ 81 pcie_isr(0, ctrl); 82 83 init_timer(&ctrl->poll_timer); 84 if (!pciehp_poll_time) 85 pciehp_poll_time = 2; /* default polling interval is 2 sec */ 86 87 start_int_poll_timer(ctrl, pciehp_poll_time); 88 } 89 90 /* This function starts the interrupt polling timer. */ 91 static void start_int_poll_timer(struct controller *ctrl, int sec) 92 { 93 /* Clamp to sane value */ 94 if ((sec <= 0) || (sec > 60)) 95 sec = 2; 96 97 ctrl->poll_timer.function = &int_poll_timeout; 98 ctrl->poll_timer.data = (unsigned long)ctrl; 99 ctrl->poll_timer.expires = jiffies + sec * HZ; 100 add_timer(&ctrl->poll_timer); 101 } 102 103 static inline int pciehp_request_irq(struct controller *ctrl) 104 { 105 int retval, irq = ctrl->pcie->irq; 106 107 /* Install interrupt polling timer. Start with 10 sec delay */ 108 if (pciehp_poll_mode) { 109 init_timer(&ctrl->poll_timer); 110 start_int_poll_timer(ctrl, 10); 111 return 0; 112 } 113 114 /* Installs the interrupt handler */ 115 retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl); 116 if (retval) 117 ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n", 118 irq); 119 return retval; 120 } 121 122 static inline void pciehp_free_irq(struct controller *ctrl) 123 { 124 if (pciehp_poll_mode) 125 del_timer_sync(&ctrl->poll_timer); 126 else 127 free_irq(ctrl->pcie->irq, ctrl); 128 } 129 130 static int pcie_poll_cmd(struct controller *ctrl) 131 { 132 u16 slot_status; 133 int err, timeout = 1000; 134 135 err = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); 136 if (!err && (slot_status & PCI_EXP_SLTSTA_CC)) { 137 pciehp_writew(ctrl, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_CC); 138 return 1; 139 } 140 while (timeout > 0) { 141 msleep(10); 142 timeout -= 10; 143 err = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); 144 if (!err && (slot_status & PCI_EXP_SLTSTA_CC)) { 145 pciehp_writew(ctrl, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_CC); 146 return 1; 147 } 148 } 149 return 0; /* timeout */ 150 } 151 152 static void pcie_wait_cmd(struct controller *ctrl, int poll) 153 { 154 unsigned int msecs = pciehp_poll_mode ? 2500 : 1000; 155 unsigned long timeout = msecs_to_jiffies(msecs); 156 int rc; 157 158 if (poll) 159 rc = pcie_poll_cmd(ctrl); 160 else 161 rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout); 162 if (!rc) 163 ctrl_dbg(ctrl, "Command not completed in 1000 msec\n"); 164 } 165 166 /** 167 * pcie_write_cmd - Issue controller command 168 * @ctrl: controller to which the command is issued 169 * @cmd: command value written to slot control register 170 * @mask: bitmask of slot control register to be modified 171 */ 172 static int pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask) 173 { 174 int retval = 0; 175 u16 slot_status; 176 u16 slot_ctrl; 177 178 mutex_lock(&ctrl->ctrl_lock); 179 180 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); 181 if (retval) { 182 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n", 183 __func__); 184 goto out; 185 } 186 187 if (slot_status & PCI_EXP_SLTSTA_CC) { 188 if (!ctrl->no_cmd_complete) { 189 /* 190 * After 1 sec and CMD_COMPLETED still not set, just 191 * proceed forward to issue the next command according 192 * to spec. Just print out the error message. 193 */ 194 ctrl_dbg(ctrl, "CMD_COMPLETED not clear after 1 sec\n"); 195 } else if (!NO_CMD_CMPL(ctrl)) { 196 /* 197 * This controller semms to notify of command completed 198 * event even though it supports none of power 199 * controller, attention led, power led and EMI. 200 */ 201 ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Need to " 202 "wait for command completed event.\n"); 203 ctrl->no_cmd_complete = 0; 204 } else { 205 ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Maybe " 206 "the controller is broken.\n"); 207 } 208 } 209 210 retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl); 211 if (retval) { 212 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__); 213 goto out; 214 } 215 216 slot_ctrl &= ~mask; 217 slot_ctrl |= (cmd & mask); 218 ctrl->cmd_busy = 1; 219 smp_mb(); 220 retval = pciehp_writew(ctrl, PCI_EXP_SLTCTL, slot_ctrl); 221 if (retval) 222 ctrl_err(ctrl, "Cannot write to SLOTCTRL register\n"); 223 224 /* 225 * Wait for command completion. 226 */ 227 if (!retval && !ctrl->no_cmd_complete) { 228 int poll = 0; 229 /* 230 * if hotplug interrupt is not enabled or command 231 * completed interrupt is not enabled, we need to poll 232 * command completed event. 233 */ 234 if (!(slot_ctrl & PCI_EXP_SLTCTL_HPIE) || 235 !(slot_ctrl & PCI_EXP_SLTCTL_CCIE)) 236 poll = 1; 237 pcie_wait_cmd(ctrl, poll); 238 } 239 out: 240 mutex_unlock(&ctrl->ctrl_lock); 241 return retval; 242 } 243 244 static inline int check_link_active(struct controller *ctrl) 245 { 246 u16 link_status; 247 248 if (pciehp_readw(ctrl, PCI_EXP_LNKSTA, &link_status)) 249 return 0; 250 return !!(link_status & PCI_EXP_LNKSTA_DLLLA); 251 } 252 253 static void pcie_wait_link_active(struct controller *ctrl) 254 { 255 int timeout = 1000; 256 257 if (check_link_active(ctrl)) 258 return; 259 while (timeout > 0) { 260 msleep(10); 261 timeout -= 10; 262 if (check_link_active(ctrl)) 263 return; 264 } 265 ctrl_dbg(ctrl, "Data Link Layer Link Active not set in 1000 msec\n"); 266 } 267 268 int pciehp_check_link_status(struct controller *ctrl) 269 { 270 u16 lnk_status; 271 int retval = 0; 272 273 /* 274 * Data Link Layer Link Active Reporting must be capable for 275 * hot-plug capable downstream port. But old controller might 276 * not implement it. In this case, we wait for 1000 ms. 277 */ 278 if (ctrl->link_active_reporting) 279 pcie_wait_link_active(ctrl); 280 else 281 msleep(1000); 282 283 retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status); 284 if (retval) { 285 ctrl_err(ctrl, "Cannot read LNKSTATUS register\n"); 286 return retval; 287 } 288 289 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status); 290 if ((lnk_status & PCI_EXP_LNKSTA_LT) || 291 !(lnk_status & PCI_EXP_LNKSTA_NLW)) { 292 ctrl_err(ctrl, "Link Training Error occurs \n"); 293 retval = -1; 294 return retval; 295 } 296 297 return retval; 298 } 299 300 int pciehp_get_attention_status(struct slot *slot, u8 *status) 301 { 302 struct controller *ctrl = slot->ctrl; 303 u16 slot_ctrl; 304 u8 atten_led_state; 305 int retval = 0; 306 307 retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl); 308 if (retval) { 309 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__); 310 return retval; 311 } 312 313 ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__, 314 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl); 315 316 atten_led_state = (slot_ctrl & PCI_EXP_SLTCTL_AIC) >> 6; 317 318 switch (atten_led_state) { 319 case 0: 320 *status = 0xFF; /* Reserved */ 321 break; 322 case 1: 323 *status = 1; /* On */ 324 break; 325 case 2: 326 *status = 2; /* Blink */ 327 break; 328 case 3: 329 *status = 0; /* Off */ 330 break; 331 default: 332 *status = 0xFF; 333 break; 334 } 335 336 return 0; 337 } 338 339 int pciehp_get_power_status(struct slot *slot, u8 *status) 340 { 341 struct controller *ctrl = slot->ctrl; 342 u16 slot_ctrl; 343 u8 pwr_state; 344 int retval = 0; 345 346 retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl); 347 if (retval) { 348 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__); 349 return retval; 350 } 351 ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__, 352 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl); 353 354 pwr_state = (slot_ctrl & PCI_EXP_SLTCTL_PCC) >> 10; 355 356 switch (pwr_state) { 357 case 0: 358 *status = 1; 359 break; 360 case 1: 361 *status = 0; 362 break; 363 default: 364 *status = 0xFF; 365 break; 366 } 367 368 return retval; 369 } 370 371 int pciehp_get_latch_status(struct slot *slot, u8 *status) 372 { 373 struct controller *ctrl = slot->ctrl; 374 u16 slot_status; 375 int retval; 376 377 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); 378 if (retval) { 379 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n", 380 __func__); 381 return retval; 382 } 383 *status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS); 384 return 0; 385 } 386 387 int pciehp_get_adapter_status(struct slot *slot, u8 *status) 388 { 389 struct controller *ctrl = slot->ctrl; 390 u16 slot_status; 391 int retval; 392 393 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); 394 if (retval) { 395 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n", 396 __func__); 397 return retval; 398 } 399 *status = !!(slot_status & PCI_EXP_SLTSTA_PDS); 400 return 0; 401 } 402 403 int pciehp_query_power_fault(struct slot *slot) 404 { 405 struct controller *ctrl = slot->ctrl; 406 u16 slot_status; 407 int retval; 408 409 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); 410 if (retval) { 411 ctrl_err(ctrl, "Cannot check for power fault\n"); 412 return retval; 413 } 414 return !!(slot_status & PCI_EXP_SLTSTA_PFD); 415 } 416 417 int pciehp_set_attention_status(struct slot *slot, u8 value) 418 { 419 struct controller *ctrl = slot->ctrl; 420 u16 slot_cmd; 421 u16 cmd_mask; 422 423 cmd_mask = PCI_EXP_SLTCTL_AIC; 424 switch (value) { 425 case 0 : /* turn off */ 426 slot_cmd = 0x00C0; 427 break; 428 case 1: /* turn on */ 429 slot_cmd = 0x0040; 430 break; 431 case 2: /* turn blink */ 432 slot_cmd = 0x0080; 433 break; 434 default: 435 return -EINVAL; 436 } 437 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 438 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); 439 return pcie_write_cmd(ctrl, slot_cmd, cmd_mask); 440 } 441 442 void pciehp_green_led_on(struct slot *slot) 443 { 444 struct controller *ctrl = slot->ctrl; 445 u16 slot_cmd; 446 u16 cmd_mask; 447 448 slot_cmd = 0x0100; 449 cmd_mask = PCI_EXP_SLTCTL_PIC; 450 pcie_write_cmd(ctrl, slot_cmd, cmd_mask); 451 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 452 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); 453 } 454 455 void pciehp_green_led_off(struct slot *slot) 456 { 457 struct controller *ctrl = slot->ctrl; 458 u16 slot_cmd; 459 u16 cmd_mask; 460 461 slot_cmd = 0x0300; 462 cmd_mask = PCI_EXP_SLTCTL_PIC; 463 pcie_write_cmd(ctrl, slot_cmd, cmd_mask); 464 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 465 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); 466 } 467 468 void pciehp_green_led_blink(struct slot *slot) 469 { 470 struct controller *ctrl = slot->ctrl; 471 u16 slot_cmd; 472 u16 cmd_mask; 473 474 slot_cmd = 0x0200; 475 cmd_mask = PCI_EXP_SLTCTL_PIC; 476 pcie_write_cmd(ctrl, slot_cmd, cmd_mask); 477 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 478 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); 479 } 480 481 int pciehp_power_on_slot(struct slot * slot) 482 { 483 struct controller *ctrl = slot->ctrl; 484 u16 slot_cmd; 485 u16 cmd_mask; 486 u16 slot_status; 487 u16 lnk_status; 488 int retval = 0; 489 490 /* Clear sticky power-fault bit from previous power failures */ 491 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); 492 if (retval) { 493 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n", 494 __func__); 495 return retval; 496 } 497 slot_status &= PCI_EXP_SLTSTA_PFD; 498 if (slot_status) { 499 retval = pciehp_writew(ctrl, PCI_EXP_SLTSTA, slot_status); 500 if (retval) { 501 ctrl_err(ctrl, 502 "%s: Cannot write to SLOTSTATUS register\n", 503 __func__); 504 return retval; 505 } 506 } 507 ctrl->power_fault_detected = 0; 508 509 slot_cmd = POWER_ON; 510 cmd_mask = PCI_EXP_SLTCTL_PCC; 511 retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask); 512 if (retval) { 513 ctrl_err(ctrl, "Write %x command failed!\n", slot_cmd); 514 return retval; 515 } 516 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 517 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); 518 519 retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status); 520 if (retval) { 521 ctrl_err(ctrl, "%s: Cannot read LNKSTA register\n", 522 __func__); 523 return retval; 524 } 525 pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status); 526 527 return retval; 528 } 529 530 int pciehp_power_off_slot(struct slot * slot) 531 { 532 struct controller *ctrl = slot->ctrl; 533 u16 slot_cmd; 534 u16 cmd_mask; 535 int retval; 536 537 slot_cmd = POWER_OFF; 538 cmd_mask = PCI_EXP_SLTCTL_PCC; 539 retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask); 540 if (retval) { 541 ctrl_err(ctrl, "Write command failed!\n"); 542 return retval; 543 } 544 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 545 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); 546 return 0; 547 } 548 549 static irqreturn_t pcie_isr(int irq, void *dev_id) 550 { 551 struct controller *ctrl = (struct controller *)dev_id; 552 struct slot *slot = ctrl->slot; 553 u16 detected, intr_loc; 554 555 /* 556 * In order to guarantee that all interrupt events are 557 * serviced, we need to re-inspect Slot Status register after 558 * clearing what is presumed to be the last pending interrupt. 559 */ 560 intr_loc = 0; 561 do { 562 if (pciehp_readw(ctrl, PCI_EXP_SLTSTA, &detected)) { 563 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS\n", 564 __func__); 565 return IRQ_NONE; 566 } 567 568 detected &= (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD | 569 PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC | 570 PCI_EXP_SLTSTA_CC); 571 detected &= ~intr_loc; 572 intr_loc |= detected; 573 if (!intr_loc) 574 return IRQ_NONE; 575 if (detected && pciehp_writew(ctrl, PCI_EXP_SLTSTA, intr_loc)) { 576 ctrl_err(ctrl, "%s: Cannot write to SLOTSTATUS\n", 577 __func__); 578 return IRQ_NONE; 579 } 580 } while (detected); 581 582 ctrl_dbg(ctrl, "%s: intr_loc %x\n", __func__, intr_loc); 583 584 /* Check Command Complete Interrupt Pending */ 585 if (intr_loc & PCI_EXP_SLTSTA_CC) { 586 ctrl->cmd_busy = 0; 587 smp_mb(); 588 wake_up(&ctrl->queue); 589 } 590 591 if (!(intr_loc & ~PCI_EXP_SLTSTA_CC)) 592 return IRQ_HANDLED; 593 594 /* Check MRL Sensor Changed */ 595 if (intr_loc & PCI_EXP_SLTSTA_MRLSC) 596 pciehp_handle_switch_change(slot); 597 598 /* Check Attention Button Pressed */ 599 if (intr_loc & PCI_EXP_SLTSTA_ABP) 600 pciehp_handle_attention_button(slot); 601 602 /* Check Presence Detect Changed */ 603 if (intr_loc & PCI_EXP_SLTSTA_PDC) 604 pciehp_handle_presence_change(slot); 605 606 /* Check Power Fault Detected */ 607 if ((intr_loc & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) { 608 ctrl->power_fault_detected = 1; 609 pciehp_handle_power_fault(slot); 610 } 611 return IRQ_HANDLED; 612 } 613 614 int pciehp_get_max_lnk_width(struct slot *slot, 615 enum pcie_link_width *value) 616 { 617 struct controller *ctrl = slot->ctrl; 618 enum pcie_link_width lnk_wdth; 619 u32 lnk_cap; 620 int retval = 0; 621 622 retval = pciehp_readl(ctrl, PCI_EXP_LNKCAP, &lnk_cap); 623 if (retval) { 624 ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__); 625 return retval; 626 } 627 628 switch ((lnk_cap & PCI_EXP_LNKSTA_NLW) >> 4){ 629 case 0: 630 lnk_wdth = PCIE_LNK_WIDTH_RESRV; 631 break; 632 case 1: 633 lnk_wdth = PCIE_LNK_X1; 634 break; 635 case 2: 636 lnk_wdth = PCIE_LNK_X2; 637 break; 638 case 4: 639 lnk_wdth = PCIE_LNK_X4; 640 break; 641 case 8: 642 lnk_wdth = PCIE_LNK_X8; 643 break; 644 case 12: 645 lnk_wdth = PCIE_LNK_X12; 646 break; 647 case 16: 648 lnk_wdth = PCIE_LNK_X16; 649 break; 650 case 32: 651 lnk_wdth = PCIE_LNK_X32; 652 break; 653 default: 654 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; 655 break; 656 } 657 658 *value = lnk_wdth; 659 ctrl_dbg(ctrl, "Max link width = %d\n", lnk_wdth); 660 661 return retval; 662 } 663 664 int pciehp_get_cur_lnk_width(struct slot *slot, 665 enum pcie_link_width *value) 666 { 667 struct controller *ctrl = slot->ctrl; 668 enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; 669 int retval = 0; 670 u16 lnk_status; 671 672 retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status); 673 if (retval) { 674 ctrl_err(ctrl, "%s: Cannot read LNKSTATUS register\n", 675 __func__); 676 return retval; 677 } 678 679 switch ((lnk_status & PCI_EXP_LNKSTA_NLW) >> 4){ 680 case 0: 681 lnk_wdth = PCIE_LNK_WIDTH_RESRV; 682 break; 683 case 1: 684 lnk_wdth = PCIE_LNK_X1; 685 break; 686 case 2: 687 lnk_wdth = PCIE_LNK_X2; 688 break; 689 case 4: 690 lnk_wdth = PCIE_LNK_X4; 691 break; 692 case 8: 693 lnk_wdth = PCIE_LNK_X8; 694 break; 695 case 12: 696 lnk_wdth = PCIE_LNK_X12; 697 break; 698 case 16: 699 lnk_wdth = PCIE_LNK_X16; 700 break; 701 case 32: 702 lnk_wdth = PCIE_LNK_X32; 703 break; 704 default: 705 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; 706 break; 707 } 708 709 *value = lnk_wdth; 710 ctrl_dbg(ctrl, "Current link width = %d\n", lnk_wdth); 711 712 return retval; 713 } 714 715 int pcie_enable_notification(struct controller *ctrl) 716 { 717 u16 cmd, mask; 718 719 /* 720 * TBD: Power fault detected software notification support. 721 * 722 * Power fault detected software notification is not enabled 723 * now, because it caused power fault detected interrupt storm 724 * on some machines. On those machines, power fault detected 725 * bit in the slot status register was set again immediately 726 * when it is cleared in the interrupt service routine, and 727 * next power fault detected interrupt was notified again. 728 */ 729 cmd = PCI_EXP_SLTCTL_PDCE; 730 if (ATTN_BUTTN(ctrl)) 731 cmd |= PCI_EXP_SLTCTL_ABPE; 732 if (MRL_SENS(ctrl)) 733 cmd |= PCI_EXP_SLTCTL_MRLSCE; 734 if (!pciehp_poll_mode) 735 cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE; 736 737 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE | 738 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE | 739 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE); 740 741 if (pcie_write_cmd(ctrl, cmd, mask)) { 742 ctrl_err(ctrl, "Cannot enable software notification\n"); 743 return -1; 744 } 745 return 0; 746 } 747 748 static void pcie_disable_notification(struct controller *ctrl) 749 { 750 u16 mask; 751 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE | 752 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE | 753 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE | 754 PCI_EXP_SLTCTL_DLLSCE); 755 if (pcie_write_cmd(ctrl, 0, mask)) 756 ctrl_warn(ctrl, "Cannot disable software notification\n"); 757 } 758 759 int pcie_init_notification(struct controller *ctrl) 760 { 761 if (pciehp_request_irq(ctrl)) 762 return -1; 763 if (pcie_enable_notification(ctrl)) { 764 pciehp_free_irq(ctrl); 765 return -1; 766 } 767 ctrl->notification_enabled = 1; 768 return 0; 769 } 770 771 static void pcie_shutdown_notification(struct controller *ctrl) 772 { 773 if (ctrl->notification_enabled) { 774 pcie_disable_notification(ctrl); 775 pciehp_free_irq(ctrl); 776 ctrl->notification_enabled = 0; 777 } 778 } 779 780 static int pcie_init_slot(struct controller *ctrl) 781 { 782 struct slot *slot; 783 784 slot = kzalloc(sizeof(*slot), GFP_KERNEL); 785 if (!slot) 786 return -ENOMEM; 787 788 slot->ctrl = ctrl; 789 mutex_init(&slot->lock); 790 INIT_DELAYED_WORK(&slot->work, pciehp_queue_pushbutton_work); 791 ctrl->slot = slot; 792 return 0; 793 } 794 795 static void pcie_cleanup_slot(struct controller *ctrl) 796 { 797 struct slot *slot = ctrl->slot; 798 cancel_delayed_work(&slot->work); 799 flush_workqueue(pciehp_wq); 800 flush_workqueue(pciehp_ordered_wq); 801 kfree(slot); 802 } 803 804 static inline void dbg_ctrl(struct controller *ctrl) 805 { 806 int i; 807 u16 reg16; 808 struct pci_dev *pdev = ctrl->pcie->port; 809 810 if (!pciehp_debug) 811 return; 812 813 ctrl_info(ctrl, "Hotplug Controller:\n"); 814 ctrl_info(ctrl, " Seg/Bus/Dev/Func/IRQ : %s IRQ %d\n", 815 pci_name(pdev), pdev->irq); 816 ctrl_info(ctrl, " Vendor ID : 0x%04x\n", pdev->vendor); 817 ctrl_info(ctrl, " Device ID : 0x%04x\n", pdev->device); 818 ctrl_info(ctrl, " Subsystem ID : 0x%04x\n", 819 pdev->subsystem_device); 820 ctrl_info(ctrl, " Subsystem Vendor ID : 0x%04x\n", 821 pdev->subsystem_vendor); 822 ctrl_info(ctrl, " PCIe Cap offset : 0x%02x\n", 823 pci_pcie_cap(pdev)); 824 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 825 if (!pci_resource_len(pdev, i)) 826 continue; 827 ctrl_info(ctrl, " PCI resource [%d] : %pR\n", 828 i, &pdev->resource[i]); 829 } 830 ctrl_info(ctrl, "Slot Capabilities : 0x%08x\n", ctrl->slot_cap); 831 ctrl_info(ctrl, " Physical Slot Number : %d\n", PSN(ctrl)); 832 ctrl_info(ctrl, " Attention Button : %3s\n", 833 ATTN_BUTTN(ctrl) ? "yes" : "no"); 834 ctrl_info(ctrl, " Power Controller : %3s\n", 835 POWER_CTRL(ctrl) ? "yes" : "no"); 836 ctrl_info(ctrl, " MRL Sensor : %3s\n", 837 MRL_SENS(ctrl) ? "yes" : "no"); 838 ctrl_info(ctrl, " Attention Indicator : %3s\n", 839 ATTN_LED(ctrl) ? "yes" : "no"); 840 ctrl_info(ctrl, " Power Indicator : %3s\n", 841 PWR_LED(ctrl) ? "yes" : "no"); 842 ctrl_info(ctrl, " Hot-Plug Surprise : %3s\n", 843 HP_SUPR_RM(ctrl) ? "yes" : "no"); 844 ctrl_info(ctrl, " EMI Present : %3s\n", 845 EMI(ctrl) ? "yes" : "no"); 846 ctrl_info(ctrl, " Command Completed : %3s\n", 847 NO_CMD_CMPL(ctrl) ? "no" : "yes"); 848 pciehp_readw(ctrl, PCI_EXP_SLTSTA, ®16); 849 ctrl_info(ctrl, "Slot Status : 0x%04x\n", reg16); 850 pciehp_readw(ctrl, PCI_EXP_SLTCTL, ®16); 851 ctrl_info(ctrl, "Slot Control : 0x%04x\n", reg16); 852 } 853 854 struct controller *pcie_init(struct pcie_device *dev) 855 { 856 struct controller *ctrl; 857 u32 slot_cap, link_cap; 858 struct pci_dev *pdev = dev->port; 859 860 ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL); 861 if (!ctrl) { 862 dev_err(&dev->device, "%s: Out of memory\n", __func__); 863 goto abort; 864 } 865 ctrl->pcie = dev; 866 if (!pci_pcie_cap(pdev)) { 867 ctrl_err(ctrl, "Cannot find PCI Express capability\n"); 868 goto abort_ctrl; 869 } 870 if (pciehp_readl(ctrl, PCI_EXP_SLTCAP, &slot_cap)) { 871 ctrl_err(ctrl, "Cannot read SLOTCAP register\n"); 872 goto abort_ctrl; 873 } 874 875 ctrl->slot_cap = slot_cap; 876 mutex_init(&ctrl->ctrl_lock); 877 init_waitqueue_head(&ctrl->queue); 878 dbg_ctrl(ctrl); 879 /* 880 * Controller doesn't notify of command completion if the "No 881 * Command Completed Support" bit is set in Slot Capability 882 * register or the controller supports none of power 883 * controller, attention led, power led and EMI. 884 */ 885 if (NO_CMD_CMPL(ctrl) || 886 !(POWER_CTRL(ctrl) | ATTN_LED(ctrl) | PWR_LED(ctrl) | EMI(ctrl))) 887 ctrl->no_cmd_complete = 1; 888 889 /* Check if Data Link Layer Link Active Reporting is implemented */ 890 if (pciehp_readl(ctrl, PCI_EXP_LNKCAP, &link_cap)) { 891 ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__); 892 goto abort_ctrl; 893 } 894 if (link_cap & PCI_EXP_LNKCAP_DLLLARC) { 895 ctrl_dbg(ctrl, "Link Active Reporting supported\n"); 896 ctrl->link_active_reporting = 1; 897 } 898 899 /* Clear all remaining event bits in Slot Status register */ 900 if (pciehp_writew(ctrl, PCI_EXP_SLTSTA, 0x1f)) 901 goto abort_ctrl; 902 903 /* Disable sotfware notification */ 904 pcie_disable_notification(ctrl); 905 906 ctrl_info(ctrl, "HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", 907 pdev->vendor, pdev->device, pdev->subsystem_vendor, 908 pdev->subsystem_device); 909 910 if (pcie_init_slot(ctrl)) 911 goto abort_ctrl; 912 913 return ctrl; 914 915 abort_ctrl: 916 kfree(ctrl); 917 abort: 918 return NULL; 919 } 920 921 void pciehp_release_ctrl(struct controller *ctrl) 922 { 923 pcie_shutdown_notification(ctrl); 924 pcie_cleanup_slot(ctrl); 925 kfree(ctrl); 926 } 927