1 /* 2 * PCI Express PCI Hot Plug Driver 3 * 4 * Copyright (C) 1995,2001 Compaq Computer Corporation 5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com) 6 * Copyright (C) 2001 IBM Corp. 7 * Copyright (C) 2003-2004 Intel Corporation 8 * 9 * All rights reserved. 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or (at 14 * your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 19 * NON INFRINGEMENT. See the GNU General Public License for more 20 * details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 25 * 26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com> 27 * 28 */ 29 30 #include <linux/kernel.h> 31 #include <linux/module.h> 32 #include <linux/types.h> 33 #include <linux/signal.h> 34 #include <linux/jiffies.h> 35 #include <linux/timer.h> 36 #include <linux/pci.h> 37 #include <linux/interrupt.h> 38 #include <linux/time.h> 39 40 #include "../pci.h" 41 #include "pciehp.h" 42 43 static atomic_t pciehp_num_controllers = ATOMIC_INIT(0); 44 45 struct ctrl_reg { 46 u8 cap_id; 47 u8 nxt_ptr; 48 u16 cap_reg; 49 u32 dev_cap; 50 u16 dev_ctrl; 51 u16 dev_status; 52 u32 lnk_cap; 53 u16 lnk_ctrl; 54 u16 lnk_status; 55 u32 slot_cap; 56 u16 slot_ctrl; 57 u16 slot_status; 58 u16 root_ctrl; 59 u16 rsvp; 60 u32 root_status; 61 } __attribute__ ((packed)); 62 63 /* offsets to the controller registers based on the above structure layout */ 64 enum ctrl_offsets { 65 PCIECAPID = offsetof(struct ctrl_reg, cap_id), 66 NXTCAPPTR = offsetof(struct ctrl_reg, nxt_ptr), 67 CAPREG = offsetof(struct ctrl_reg, cap_reg), 68 DEVCAP = offsetof(struct ctrl_reg, dev_cap), 69 DEVCTRL = offsetof(struct ctrl_reg, dev_ctrl), 70 DEVSTATUS = offsetof(struct ctrl_reg, dev_status), 71 LNKCAP = offsetof(struct ctrl_reg, lnk_cap), 72 LNKCTRL = offsetof(struct ctrl_reg, lnk_ctrl), 73 LNKSTATUS = offsetof(struct ctrl_reg, lnk_status), 74 SLOTCAP = offsetof(struct ctrl_reg, slot_cap), 75 SLOTCTRL = offsetof(struct ctrl_reg, slot_ctrl), 76 SLOTSTATUS = offsetof(struct ctrl_reg, slot_status), 77 ROOTCTRL = offsetof(struct ctrl_reg, root_ctrl), 78 ROOTSTATUS = offsetof(struct ctrl_reg, root_status), 79 }; 80 81 static inline int pciehp_readw(struct controller *ctrl, int reg, u16 *value) 82 { 83 struct pci_dev *dev = ctrl->pci_dev; 84 return pci_read_config_word(dev, ctrl->cap_base + reg, value); 85 } 86 87 static inline int pciehp_readl(struct controller *ctrl, int reg, u32 *value) 88 { 89 struct pci_dev *dev = ctrl->pci_dev; 90 return pci_read_config_dword(dev, ctrl->cap_base + reg, value); 91 } 92 93 static inline int pciehp_writew(struct controller *ctrl, int reg, u16 value) 94 { 95 struct pci_dev *dev = ctrl->pci_dev; 96 return pci_write_config_word(dev, ctrl->cap_base + reg, value); 97 } 98 99 static inline int pciehp_writel(struct controller *ctrl, int reg, u32 value) 100 { 101 struct pci_dev *dev = ctrl->pci_dev; 102 return pci_write_config_dword(dev, ctrl->cap_base + reg, value); 103 } 104 105 /* Field definitions in PCI Express Capabilities Register */ 106 #define CAP_VER 0x000F 107 #define DEV_PORT_TYPE 0x00F0 108 #define SLOT_IMPL 0x0100 109 #define MSG_NUM 0x3E00 110 111 /* Device or Port Type */ 112 #define NAT_ENDPT 0x00 113 #define LEG_ENDPT 0x01 114 #define ROOT_PORT 0x04 115 #define UP_STREAM 0x05 116 #define DN_STREAM 0x06 117 #define PCIE_PCI_BRDG 0x07 118 #define PCI_PCIE_BRDG 0x10 119 120 /* Field definitions in Device Capabilities Register */ 121 #define DATTN_BUTTN_PRSN 0x1000 122 #define DATTN_LED_PRSN 0x2000 123 #define DPWR_LED_PRSN 0x4000 124 125 /* Field definitions in Link Capabilities Register */ 126 #define MAX_LNK_SPEED 0x000F 127 #define MAX_LNK_WIDTH 0x03F0 128 129 /* Link Width Encoding */ 130 #define LNK_X1 0x01 131 #define LNK_X2 0x02 132 #define LNK_X4 0x04 133 #define LNK_X8 0x08 134 #define LNK_X12 0x0C 135 #define LNK_X16 0x10 136 #define LNK_X32 0x20 137 138 /*Field definitions of Link Status Register */ 139 #define LNK_SPEED 0x000F 140 #define NEG_LINK_WD 0x03F0 141 #define LNK_TRN_ERR 0x0400 142 #define LNK_TRN 0x0800 143 #define SLOT_CLK_CONF 0x1000 144 145 /* Field definitions in Slot Capabilities Register */ 146 #define ATTN_BUTTN_PRSN 0x00000001 147 #define PWR_CTRL_PRSN 0x00000002 148 #define MRL_SENS_PRSN 0x00000004 149 #define ATTN_LED_PRSN 0x00000008 150 #define PWR_LED_PRSN 0x00000010 151 #define HP_SUPR_RM_SUP 0x00000020 152 #define HP_CAP 0x00000040 153 #define SLOT_PWR_VALUE 0x000003F8 154 #define SLOT_PWR_LIMIT 0x00000C00 155 #define PSN 0xFFF80000 /* PSN: Physical Slot Number */ 156 157 /* Field definitions in Slot Control Register */ 158 #define ATTN_BUTTN_ENABLE 0x0001 159 #define PWR_FAULT_DETECT_ENABLE 0x0002 160 #define MRL_DETECT_ENABLE 0x0004 161 #define PRSN_DETECT_ENABLE 0x0008 162 #define CMD_CMPL_INTR_ENABLE 0x0010 163 #define HP_INTR_ENABLE 0x0020 164 #define ATTN_LED_CTRL 0x00C0 165 #define PWR_LED_CTRL 0x0300 166 #define PWR_CTRL 0x0400 167 #define EMI_CTRL 0x0800 168 169 /* Attention indicator and Power indicator states */ 170 #define LED_ON 0x01 171 #define LED_BLINK 0x10 172 #define LED_OFF 0x11 173 174 /* Power Control Command */ 175 #define POWER_ON 0 176 #define POWER_OFF 0x0400 177 178 /* EMI Status defines */ 179 #define EMI_DISENGAGED 0 180 #define EMI_ENGAGED 1 181 182 /* Field definitions in Slot Status Register */ 183 #define ATTN_BUTTN_PRESSED 0x0001 184 #define PWR_FAULT_DETECTED 0x0002 185 #define MRL_SENS_CHANGED 0x0004 186 #define PRSN_DETECT_CHANGED 0x0008 187 #define CMD_COMPLETED 0x0010 188 #define MRL_STATE 0x0020 189 #define PRSN_STATE 0x0040 190 #define EMI_STATE 0x0080 191 #define EMI_STATUS_BIT 7 192 193 static irqreturn_t pcie_isr(int irq, void *dev_id); 194 static void start_int_poll_timer(struct controller *ctrl, int sec); 195 196 /* This is the interrupt polling timeout function. */ 197 static void int_poll_timeout(unsigned long data) 198 { 199 struct controller *ctrl = (struct controller *)data; 200 201 /* Poll for interrupt events. regs == NULL => polling */ 202 pcie_isr(0, ctrl); 203 204 init_timer(&ctrl->poll_timer); 205 if (!pciehp_poll_time) 206 pciehp_poll_time = 2; /* default polling interval is 2 sec */ 207 208 start_int_poll_timer(ctrl, pciehp_poll_time); 209 } 210 211 /* This function starts the interrupt polling timer. */ 212 static void start_int_poll_timer(struct controller *ctrl, int sec) 213 { 214 /* Clamp to sane value */ 215 if ((sec <= 0) || (sec > 60)) 216 sec = 2; 217 218 ctrl->poll_timer.function = &int_poll_timeout; 219 ctrl->poll_timer.data = (unsigned long)ctrl; 220 ctrl->poll_timer.expires = jiffies + sec * HZ; 221 add_timer(&ctrl->poll_timer); 222 } 223 224 static inline int pciehp_request_irq(struct controller *ctrl) 225 { 226 int retval, irq = ctrl->pci_dev->irq; 227 228 /* Install interrupt polling timer. Start with 10 sec delay */ 229 if (pciehp_poll_mode) { 230 init_timer(&ctrl->poll_timer); 231 start_int_poll_timer(ctrl, 10); 232 return 0; 233 } 234 235 /* Installs the interrupt handler */ 236 retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl); 237 if (retval) 238 err("Cannot get irq %d for the hotplug controller\n", irq); 239 return retval; 240 } 241 242 static inline void pciehp_free_irq(struct controller *ctrl) 243 { 244 if (pciehp_poll_mode) 245 del_timer_sync(&ctrl->poll_timer); 246 else 247 free_irq(ctrl->pci_dev->irq, ctrl); 248 } 249 250 static int pcie_poll_cmd(struct controller *ctrl) 251 { 252 u16 slot_status; 253 int timeout = 1000; 254 255 if (!pciehp_readw(ctrl, SLOTSTATUS, &slot_status)) { 256 if (slot_status & CMD_COMPLETED) { 257 pciehp_writew(ctrl, SLOTSTATUS, CMD_COMPLETED); 258 return 1; 259 } 260 } 261 while (timeout > 1000) { 262 msleep(10); 263 timeout -= 10; 264 if (!pciehp_readw(ctrl, SLOTSTATUS, &slot_status)) { 265 if (slot_status & CMD_COMPLETED) { 266 pciehp_writew(ctrl, SLOTSTATUS, CMD_COMPLETED); 267 return 1; 268 } 269 } 270 } 271 return 0; /* timeout */ 272 } 273 274 static void pcie_wait_cmd(struct controller *ctrl, int poll) 275 { 276 unsigned int msecs = pciehp_poll_mode ? 2500 : 1000; 277 unsigned long timeout = msecs_to_jiffies(msecs); 278 int rc; 279 280 if (poll) 281 rc = pcie_poll_cmd(ctrl); 282 else 283 rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout); 284 if (!rc) 285 dbg("Command not completed in 1000 msec\n"); 286 } 287 288 /** 289 * pcie_write_cmd - Issue controller command 290 * @ctrl: controller to which the command is issued 291 * @cmd: command value written to slot control register 292 * @mask: bitmask of slot control register to be modified 293 */ 294 static int pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask) 295 { 296 int retval = 0; 297 u16 slot_status; 298 u16 slot_ctrl; 299 300 mutex_lock(&ctrl->ctrl_lock); 301 302 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); 303 if (retval) { 304 err("%s: Cannot read SLOTSTATUS register\n", __func__); 305 goto out; 306 } 307 308 if (slot_status & CMD_COMPLETED) { 309 if (!ctrl->no_cmd_complete) { 310 /* 311 * After 1 sec and CMD_COMPLETED still not set, just 312 * proceed forward to issue the next command according 313 * to spec. Just print out the error message. 314 */ 315 dbg("%s: CMD_COMPLETED not clear after 1 sec.\n", 316 __func__); 317 } else if (!NO_CMD_CMPL(ctrl)) { 318 /* 319 * This controller semms to notify of command completed 320 * event even though it supports none of power 321 * controller, attention led, power led and EMI. 322 */ 323 dbg("%s: Unexpected CMD_COMPLETED. Need to wait for " 324 "command completed event.\n", __func__); 325 ctrl->no_cmd_complete = 0; 326 } else { 327 dbg("%s: Unexpected CMD_COMPLETED. Maybe the " 328 "controller is broken.\n", __func__); 329 } 330 } 331 332 retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl); 333 if (retval) { 334 err("%s: Cannot read SLOTCTRL register\n", __func__); 335 goto out; 336 } 337 338 slot_ctrl &= ~mask; 339 slot_ctrl |= (cmd & mask); 340 ctrl->cmd_busy = 1; 341 smp_mb(); 342 retval = pciehp_writew(ctrl, SLOTCTRL, slot_ctrl); 343 if (retval) 344 err("%s: Cannot write to SLOTCTRL register\n", __func__); 345 346 /* 347 * Wait for command completion. 348 */ 349 if (!retval && !ctrl->no_cmd_complete) { 350 int poll = 0; 351 /* 352 * if hotplug interrupt is not enabled or command 353 * completed interrupt is not enabled, we need to poll 354 * command completed event. 355 */ 356 if (!(slot_ctrl & HP_INTR_ENABLE) || 357 !(slot_ctrl & CMD_CMPL_INTR_ENABLE)) 358 poll = 1; 359 pcie_wait_cmd(ctrl, poll); 360 } 361 out: 362 mutex_unlock(&ctrl->ctrl_lock); 363 return retval; 364 } 365 366 static int hpc_check_lnk_status(struct controller *ctrl) 367 { 368 u16 lnk_status; 369 int retval = 0; 370 371 retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status); 372 if (retval) { 373 err("%s: Cannot read LNKSTATUS register\n", __func__); 374 return retval; 375 } 376 377 dbg("%s: lnk_status = %x\n", __func__, lnk_status); 378 if ( (lnk_status & LNK_TRN) || (lnk_status & LNK_TRN_ERR) || 379 !(lnk_status & NEG_LINK_WD)) { 380 err("%s : Link Training Error occurs \n", __func__); 381 retval = -1; 382 return retval; 383 } 384 385 return retval; 386 } 387 388 static int hpc_get_attention_status(struct slot *slot, u8 *status) 389 { 390 struct controller *ctrl = slot->ctrl; 391 u16 slot_ctrl; 392 u8 atten_led_state; 393 int retval = 0; 394 395 retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl); 396 if (retval) { 397 err("%s: Cannot read SLOTCTRL register\n", __func__); 398 return retval; 399 } 400 401 dbg("%s: SLOTCTRL %x, value read %x\n", 402 __func__, ctrl->cap_base + SLOTCTRL, slot_ctrl); 403 404 atten_led_state = (slot_ctrl & ATTN_LED_CTRL) >> 6; 405 406 switch (atten_led_state) { 407 case 0: 408 *status = 0xFF; /* Reserved */ 409 break; 410 case 1: 411 *status = 1; /* On */ 412 break; 413 case 2: 414 *status = 2; /* Blink */ 415 break; 416 case 3: 417 *status = 0; /* Off */ 418 break; 419 default: 420 *status = 0xFF; 421 break; 422 } 423 424 return 0; 425 } 426 427 static int hpc_get_power_status(struct slot *slot, u8 *status) 428 { 429 struct controller *ctrl = slot->ctrl; 430 u16 slot_ctrl; 431 u8 pwr_state; 432 int retval = 0; 433 434 retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl); 435 if (retval) { 436 err("%s: Cannot read SLOTCTRL register\n", __func__); 437 return retval; 438 } 439 dbg("%s: SLOTCTRL %x value read %x\n", 440 __func__, ctrl->cap_base + SLOTCTRL, slot_ctrl); 441 442 pwr_state = (slot_ctrl & PWR_CTRL) >> 10; 443 444 switch (pwr_state) { 445 case 0: 446 *status = 1; 447 break; 448 case 1: 449 *status = 0; 450 break; 451 default: 452 *status = 0xFF; 453 break; 454 } 455 456 return retval; 457 } 458 459 static int hpc_get_latch_status(struct slot *slot, u8 *status) 460 { 461 struct controller *ctrl = slot->ctrl; 462 u16 slot_status; 463 int retval = 0; 464 465 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); 466 if (retval) { 467 err("%s: Cannot read SLOTSTATUS register\n", __func__); 468 return retval; 469 } 470 471 *status = (((slot_status & MRL_STATE) >> 5) == 0) ? 0 : 1; 472 473 return 0; 474 } 475 476 static int hpc_get_adapter_status(struct slot *slot, u8 *status) 477 { 478 struct controller *ctrl = slot->ctrl; 479 u16 slot_status; 480 u8 card_state; 481 int retval = 0; 482 483 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); 484 if (retval) { 485 err("%s: Cannot read SLOTSTATUS register\n", __func__); 486 return retval; 487 } 488 card_state = (u8)((slot_status & PRSN_STATE) >> 6); 489 *status = (card_state == 1) ? 1 : 0; 490 491 return 0; 492 } 493 494 static int hpc_query_power_fault(struct slot *slot) 495 { 496 struct controller *ctrl = slot->ctrl; 497 u16 slot_status; 498 u8 pwr_fault; 499 int retval = 0; 500 501 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); 502 if (retval) { 503 err("%s: Cannot check for power fault\n", __func__); 504 return retval; 505 } 506 pwr_fault = (u8)((slot_status & PWR_FAULT_DETECTED) >> 1); 507 508 return pwr_fault; 509 } 510 511 static int hpc_get_emi_status(struct slot *slot, u8 *status) 512 { 513 struct controller *ctrl = slot->ctrl; 514 u16 slot_status; 515 int retval = 0; 516 517 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); 518 if (retval) { 519 err("%s : Cannot check EMI status\n", __func__); 520 return retval; 521 } 522 *status = (slot_status & EMI_STATE) >> EMI_STATUS_BIT; 523 524 return retval; 525 } 526 527 static int hpc_toggle_emi(struct slot *slot) 528 { 529 u16 slot_cmd; 530 u16 cmd_mask; 531 int rc; 532 533 slot_cmd = EMI_CTRL; 534 cmd_mask = EMI_CTRL; 535 rc = pcie_write_cmd(slot->ctrl, slot_cmd, cmd_mask); 536 slot->last_emi_toggle = get_seconds(); 537 538 return rc; 539 } 540 541 static int hpc_set_attention_status(struct slot *slot, u8 value) 542 { 543 struct controller *ctrl = slot->ctrl; 544 u16 slot_cmd; 545 u16 cmd_mask; 546 int rc; 547 548 cmd_mask = ATTN_LED_CTRL; 549 switch (value) { 550 case 0 : /* turn off */ 551 slot_cmd = 0x00C0; 552 break; 553 case 1: /* turn on */ 554 slot_cmd = 0x0040; 555 break; 556 case 2: /* turn blink */ 557 slot_cmd = 0x0080; 558 break; 559 default: 560 return -1; 561 } 562 rc = pcie_write_cmd(ctrl, slot_cmd, cmd_mask); 563 dbg("%s: SLOTCTRL %x write cmd %x\n", 564 __func__, ctrl->cap_base + SLOTCTRL, slot_cmd); 565 566 return rc; 567 } 568 569 static void hpc_set_green_led_on(struct slot *slot) 570 { 571 struct controller *ctrl = slot->ctrl; 572 u16 slot_cmd; 573 u16 cmd_mask; 574 575 slot_cmd = 0x0100; 576 cmd_mask = PWR_LED_CTRL; 577 pcie_write_cmd(ctrl, slot_cmd, cmd_mask); 578 dbg("%s: SLOTCTRL %x write cmd %x\n", 579 __func__, ctrl->cap_base + SLOTCTRL, slot_cmd); 580 } 581 582 static void hpc_set_green_led_off(struct slot *slot) 583 { 584 struct controller *ctrl = slot->ctrl; 585 u16 slot_cmd; 586 u16 cmd_mask; 587 588 slot_cmd = 0x0300; 589 cmd_mask = PWR_LED_CTRL; 590 pcie_write_cmd(ctrl, slot_cmd, cmd_mask); 591 dbg("%s: SLOTCTRL %x write cmd %x\n", 592 __func__, ctrl->cap_base + SLOTCTRL, slot_cmd); 593 } 594 595 static void hpc_set_green_led_blink(struct slot *slot) 596 { 597 struct controller *ctrl = slot->ctrl; 598 u16 slot_cmd; 599 u16 cmd_mask; 600 601 slot_cmd = 0x0200; 602 cmd_mask = PWR_LED_CTRL; 603 pcie_write_cmd(ctrl, slot_cmd, cmd_mask); 604 dbg("%s: SLOTCTRL %x write cmd %x\n", 605 __func__, ctrl->cap_base + SLOTCTRL, slot_cmd); 606 } 607 608 static int hpc_power_on_slot(struct slot * slot) 609 { 610 struct controller *ctrl = slot->ctrl; 611 u16 slot_cmd; 612 u16 cmd_mask; 613 u16 slot_status; 614 int retval = 0; 615 616 dbg("%s: slot->hp_slot %x\n", __func__, slot->hp_slot); 617 618 /* Clear sticky power-fault bit from previous power failures */ 619 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); 620 if (retval) { 621 err("%s: Cannot read SLOTSTATUS register\n", __func__); 622 return retval; 623 } 624 slot_status &= PWR_FAULT_DETECTED; 625 if (slot_status) { 626 retval = pciehp_writew(ctrl, SLOTSTATUS, slot_status); 627 if (retval) { 628 err("%s: Cannot write to SLOTSTATUS register\n", 629 __func__); 630 return retval; 631 } 632 } 633 634 slot_cmd = POWER_ON; 635 cmd_mask = PWR_CTRL; 636 /* Enable detection that we turned off at slot power-off time */ 637 if (!pciehp_poll_mode) { 638 slot_cmd |= (PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE | 639 PRSN_DETECT_ENABLE); 640 cmd_mask |= (PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE | 641 PRSN_DETECT_ENABLE); 642 } 643 644 retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask); 645 646 if (retval) { 647 err("%s: Write %x command failed!\n", __func__, slot_cmd); 648 return -1; 649 } 650 dbg("%s: SLOTCTRL %x write cmd %x\n", 651 __func__, ctrl->cap_base + SLOTCTRL, slot_cmd); 652 653 return retval; 654 } 655 656 static inline int pcie_mask_bad_dllp(struct controller *ctrl) 657 { 658 struct pci_dev *dev = ctrl->pci_dev; 659 int pos; 660 u32 reg; 661 662 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); 663 if (!pos) 664 return 0; 665 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, ®); 666 if (reg & PCI_ERR_COR_BAD_DLLP) 667 return 0; 668 reg |= PCI_ERR_COR_BAD_DLLP; 669 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg); 670 return 1; 671 } 672 673 static inline void pcie_unmask_bad_dllp(struct controller *ctrl) 674 { 675 struct pci_dev *dev = ctrl->pci_dev; 676 u32 reg; 677 int pos; 678 679 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); 680 if (!pos) 681 return; 682 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, ®); 683 if (!(reg & PCI_ERR_COR_BAD_DLLP)) 684 return; 685 reg &= ~PCI_ERR_COR_BAD_DLLP; 686 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg); 687 } 688 689 static int hpc_power_off_slot(struct slot * slot) 690 { 691 struct controller *ctrl = slot->ctrl; 692 u16 slot_cmd; 693 u16 cmd_mask; 694 int retval = 0; 695 int changed; 696 697 dbg("%s: slot->hp_slot %x\n", __func__, slot->hp_slot); 698 699 /* 700 * Set Bad DLLP Mask bit in Correctable Error Mask 701 * Register. This is the workaround against Bad DLLP error 702 * that sometimes happens during turning power off the slot 703 * which conforms to PCI Express 1.0a spec. 704 */ 705 changed = pcie_mask_bad_dllp(ctrl); 706 707 slot_cmd = POWER_OFF; 708 cmd_mask = PWR_CTRL; 709 /* 710 * If we get MRL or presence detect interrupts now, the isr 711 * will notice the sticky power-fault bit too and issue power 712 * indicator change commands. This will lead to an endless loop 713 * of command completions, since the power-fault bit remains on 714 * till the slot is powered on again. 715 */ 716 if (!pciehp_poll_mode) { 717 slot_cmd &= ~(PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE | 718 PRSN_DETECT_ENABLE); 719 cmd_mask |= (PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE | 720 PRSN_DETECT_ENABLE); 721 } 722 723 retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask); 724 if (retval) { 725 err("%s: Write command failed!\n", __func__); 726 retval = -1; 727 goto out; 728 } 729 dbg("%s: SLOTCTRL %x write cmd %x\n", 730 __func__, ctrl->cap_base + SLOTCTRL, slot_cmd); 731 out: 732 if (changed) 733 pcie_unmask_bad_dllp(ctrl); 734 735 return retval; 736 } 737 738 static irqreturn_t pcie_isr(int irq, void *dev_id) 739 { 740 struct controller *ctrl = (struct controller *)dev_id; 741 u16 detected, intr_loc; 742 struct slot *p_slot; 743 744 /* 745 * In order to guarantee that all interrupt events are 746 * serviced, we need to re-inspect Slot Status register after 747 * clearing what is presumed to be the last pending interrupt. 748 */ 749 intr_loc = 0; 750 do { 751 if (pciehp_readw(ctrl, SLOTSTATUS, &detected)) { 752 err("%s: Cannot read SLOTSTATUS\n", __func__); 753 return IRQ_NONE; 754 } 755 756 detected &= (ATTN_BUTTN_PRESSED | PWR_FAULT_DETECTED | 757 MRL_SENS_CHANGED | PRSN_DETECT_CHANGED | 758 CMD_COMPLETED); 759 intr_loc |= detected; 760 if (!intr_loc) 761 return IRQ_NONE; 762 if (detected && pciehp_writew(ctrl, SLOTSTATUS, detected)) { 763 err("%s: Cannot write to SLOTSTATUS\n", __func__); 764 return IRQ_NONE; 765 } 766 } while (detected); 767 768 dbg("%s: intr_loc %x\n", __FUNCTION__, intr_loc); 769 770 /* Check Command Complete Interrupt Pending */ 771 if (intr_loc & CMD_COMPLETED) { 772 ctrl->cmd_busy = 0; 773 smp_mb(); 774 wake_up(&ctrl->queue); 775 } 776 777 if (!(intr_loc & ~CMD_COMPLETED)) 778 return IRQ_HANDLED; 779 780 p_slot = pciehp_find_slot(ctrl, ctrl->slot_device_offset); 781 782 /* Check MRL Sensor Changed */ 783 if (intr_loc & MRL_SENS_CHANGED) 784 pciehp_handle_switch_change(p_slot); 785 786 /* Check Attention Button Pressed */ 787 if (intr_loc & ATTN_BUTTN_PRESSED) 788 pciehp_handle_attention_button(p_slot); 789 790 /* Check Presence Detect Changed */ 791 if (intr_loc & PRSN_DETECT_CHANGED) 792 pciehp_handle_presence_change(p_slot); 793 794 /* Check Power Fault Detected */ 795 if (intr_loc & PWR_FAULT_DETECTED) 796 pciehp_handle_power_fault(p_slot); 797 798 return IRQ_HANDLED; 799 } 800 801 static int hpc_get_max_lnk_speed(struct slot *slot, enum pci_bus_speed *value) 802 { 803 struct controller *ctrl = slot->ctrl; 804 enum pcie_link_speed lnk_speed; 805 u32 lnk_cap; 806 int retval = 0; 807 808 retval = pciehp_readl(ctrl, LNKCAP, &lnk_cap); 809 if (retval) { 810 err("%s: Cannot read LNKCAP register\n", __func__); 811 return retval; 812 } 813 814 switch (lnk_cap & 0x000F) { 815 case 1: 816 lnk_speed = PCIE_2PT5GB; 817 break; 818 default: 819 lnk_speed = PCIE_LNK_SPEED_UNKNOWN; 820 break; 821 } 822 823 *value = lnk_speed; 824 dbg("Max link speed = %d\n", lnk_speed); 825 826 return retval; 827 } 828 829 static int hpc_get_max_lnk_width(struct slot *slot, 830 enum pcie_link_width *value) 831 { 832 struct controller *ctrl = slot->ctrl; 833 enum pcie_link_width lnk_wdth; 834 u32 lnk_cap; 835 int retval = 0; 836 837 retval = pciehp_readl(ctrl, LNKCAP, &lnk_cap); 838 if (retval) { 839 err("%s: Cannot read LNKCAP register\n", __func__); 840 return retval; 841 } 842 843 switch ((lnk_cap & 0x03F0) >> 4){ 844 case 0: 845 lnk_wdth = PCIE_LNK_WIDTH_RESRV; 846 break; 847 case 1: 848 lnk_wdth = PCIE_LNK_X1; 849 break; 850 case 2: 851 lnk_wdth = PCIE_LNK_X2; 852 break; 853 case 4: 854 lnk_wdth = PCIE_LNK_X4; 855 break; 856 case 8: 857 lnk_wdth = PCIE_LNK_X8; 858 break; 859 case 12: 860 lnk_wdth = PCIE_LNK_X12; 861 break; 862 case 16: 863 lnk_wdth = PCIE_LNK_X16; 864 break; 865 case 32: 866 lnk_wdth = PCIE_LNK_X32; 867 break; 868 default: 869 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; 870 break; 871 } 872 873 *value = lnk_wdth; 874 dbg("Max link width = %d\n", lnk_wdth); 875 876 return retval; 877 } 878 879 static int hpc_get_cur_lnk_speed(struct slot *slot, enum pci_bus_speed *value) 880 { 881 struct controller *ctrl = slot->ctrl; 882 enum pcie_link_speed lnk_speed = PCI_SPEED_UNKNOWN; 883 int retval = 0; 884 u16 lnk_status; 885 886 retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status); 887 if (retval) { 888 err("%s: Cannot read LNKSTATUS register\n", __func__); 889 return retval; 890 } 891 892 switch (lnk_status & 0x0F) { 893 case 1: 894 lnk_speed = PCIE_2PT5GB; 895 break; 896 default: 897 lnk_speed = PCIE_LNK_SPEED_UNKNOWN; 898 break; 899 } 900 901 *value = lnk_speed; 902 dbg("Current link speed = %d\n", lnk_speed); 903 904 return retval; 905 } 906 907 static int hpc_get_cur_lnk_width(struct slot *slot, 908 enum pcie_link_width *value) 909 { 910 struct controller *ctrl = slot->ctrl; 911 enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; 912 int retval = 0; 913 u16 lnk_status; 914 915 retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status); 916 if (retval) { 917 err("%s: Cannot read LNKSTATUS register\n", __func__); 918 return retval; 919 } 920 921 switch ((lnk_status & 0x03F0) >> 4){ 922 case 0: 923 lnk_wdth = PCIE_LNK_WIDTH_RESRV; 924 break; 925 case 1: 926 lnk_wdth = PCIE_LNK_X1; 927 break; 928 case 2: 929 lnk_wdth = PCIE_LNK_X2; 930 break; 931 case 4: 932 lnk_wdth = PCIE_LNK_X4; 933 break; 934 case 8: 935 lnk_wdth = PCIE_LNK_X8; 936 break; 937 case 12: 938 lnk_wdth = PCIE_LNK_X12; 939 break; 940 case 16: 941 lnk_wdth = PCIE_LNK_X16; 942 break; 943 case 32: 944 lnk_wdth = PCIE_LNK_X32; 945 break; 946 default: 947 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; 948 break; 949 } 950 951 *value = lnk_wdth; 952 dbg("Current link width = %d\n", lnk_wdth); 953 954 return retval; 955 } 956 957 static void pcie_release_ctrl(struct controller *ctrl); 958 static struct hpc_ops pciehp_hpc_ops = { 959 .power_on_slot = hpc_power_on_slot, 960 .power_off_slot = hpc_power_off_slot, 961 .set_attention_status = hpc_set_attention_status, 962 .get_power_status = hpc_get_power_status, 963 .get_attention_status = hpc_get_attention_status, 964 .get_latch_status = hpc_get_latch_status, 965 .get_adapter_status = hpc_get_adapter_status, 966 .get_emi_status = hpc_get_emi_status, 967 .toggle_emi = hpc_toggle_emi, 968 969 .get_max_bus_speed = hpc_get_max_lnk_speed, 970 .get_cur_bus_speed = hpc_get_cur_lnk_speed, 971 .get_max_lnk_width = hpc_get_max_lnk_width, 972 .get_cur_lnk_width = hpc_get_cur_lnk_width, 973 974 .query_power_fault = hpc_query_power_fault, 975 .green_led_on = hpc_set_green_led_on, 976 .green_led_off = hpc_set_green_led_off, 977 .green_led_blink = hpc_set_green_led_blink, 978 979 .release_ctlr = pcie_release_ctrl, 980 .check_lnk_status = hpc_check_lnk_status, 981 }; 982 983 int pcie_enable_notification(struct controller *ctrl) 984 { 985 u16 cmd, mask; 986 987 cmd = PRSN_DETECT_ENABLE; 988 if (ATTN_BUTTN(ctrl)) 989 cmd |= ATTN_BUTTN_ENABLE; 990 if (POWER_CTRL(ctrl)) 991 cmd |= PWR_FAULT_DETECT_ENABLE; 992 if (MRL_SENS(ctrl)) 993 cmd |= MRL_DETECT_ENABLE; 994 if (!pciehp_poll_mode) 995 cmd |= HP_INTR_ENABLE | CMD_CMPL_INTR_ENABLE; 996 997 mask = PRSN_DETECT_ENABLE | ATTN_BUTTN_ENABLE | MRL_DETECT_ENABLE | 998 PWR_FAULT_DETECT_ENABLE | HP_INTR_ENABLE | CMD_CMPL_INTR_ENABLE; 999 1000 if (pcie_write_cmd(ctrl, cmd, mask)) { 1001 err("%s: Cannot enable software notification\n", __func__); 1002 return -1; 1003 } 1004 return 0; 1005 } 1006 1007 static void pcie_disable_notification(struct controller *ctrl) 1008 { 1009 u16 mask; 1010 mask = PRSN_DETECT_ENABLE | ATTN_BUTTN_ENABLE | MRL_DETECT_ENABLE | 1011 PWR_FAULT_DETECT_ENABLE | HP_INTR_ENABLE | CMD_CMPL_INTR_ENABLE; 1012 if (pcie_write_cmd(ctrl, 0, mask)) 1013 warn("%s: Cannot disable software notification\n", __func__); 1014 } 1015 1016 static int pcie_init_notification(struct controller *ctrl) 1017 { 1018 if (pciehp_request_irq(ctrl)) 1019 return -1; 1020 if (pcie_enable_notification(ctrl)) { 1021 pciehp_free_irq(ctrl); 1022 return -1; 1023 } 1024 return 0; 1025 } 1026 1027 static void pcie_shutdown_notification(struct controller *ctrl) 1028 { 1029 pcie_disable_notification(ctrl); 1030 pciehp_free_irq(ctrl); 1031 } 1032 1033 static void make_slot_name(struct slot *slot) 1034 { 1035 if (pciehp_slot_with_bus) 1036 snprintf(slot->name, SLOT_NAME_SIZE, "%04d_%04d", 1037 slot->bus, slot->number); 1038 else 1039 snprintf(slot->name, SLOT_NAME_SIZE, "%d", slot->number); 1040 } 1041 1042 static int pcie_init_slot(struct controller *ctrl) 1043 { 1044 struct slot *slot; 1045 1046 slot = kzalloc(sizeof(*slot), GFP_KERNEL); 1047 if (!slot) 1048 return -ENOMEM; 1049 1050 slot->hp_slot = 0; 1051 slot->ctrl = ctrl; 1052 slot->bus = ctrl->pci_dev->subordinate->number; 1053 slot->device = ctrl->slot_device_offset + slot->hp_slot; 1054 slot->hpc_ops = ctrl->hpc_ops; 1055 slot->number = ctrl->first_slot; 1056 make_slot_name(slot); 1057 mutex_init(&slot->lock); 1058 INIT_DELAYED_WORK(&slot->work, pciehp_queue_pushbutton_work); 1059 list_add(&slot->slot_list, &ctrl->slot_list); 1060 return 0; 1061 } 1062 1063 static void pcie_cleanup_slot(struct controller *ctrl) 1064 { 1065 struct slot *slot; 1066 slot = list_first_entry(&ctrl->slot_list, struct slot, slot_list); 1067 list_del(&slot->slot_list); 1068 cancel_delayed_work(&slot->work); 1069 flush_scheduled_work(); 1070 flush_workqueue(pciehp_wq); 1071 kfree(slot); 1072 } 1073 1074 static inline void dbg_ctrl(struct controller *ctrl) 1075 { 1076 int i; 1077 u16 reg16; 1078 struct pci_dev *pdev = ctrl->pci_dev; 1079 1080 if (!pciehp_debug) 1081 return; 1082 1083 dbg("Hotplug Controller:\n"); 1084 dbg(" Seg/Bus/Dev/Func/IRQ : %s IRQ %d\n", pci_name(pdev), pdev->irq); 1085 dbg(" Vendor ID : 0x%04x\n", pdev->vendor); 1086 dbg(" Device ID : 0x%04x\n", pdev->device); 1087 dbg(" Subsystem ID : 0x%04x\n", pdev->subsystem_device); 1088 dbg(" Subsystem Vendor ID : 0x%04x\n", pdev->subsystem_vendor); 1089 dbg(" PCIe Cap offset : 0x%02x\n", ctrl->cap_base); 1090 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 1091 if (!pci_resource_len(pdev, i)) 1092 continue; 1093 dbg(" PCI resource [%d] : 0x%llx@0x%llx\n", i, 1094 (unsigned long long)pci_resource_len(pdev, i), 1095 (unsigned long long)pci_resource_start(pdev, i)); 1096 } 1097 dbg("Slot Capabilities : 0x%08x\n", ctrl->slot_cap); 1098 dbg(" Physical Slot Number : %d\n", ctrl->first_slot); 1099 dbg(" Attention Button : %3s\n", ATTN_BUTTN(ctrl) ? "yes" : "no"); 1100 dbg(" Power Controller : %3s\n", POWER_CTRL(ctrl) ? "yes" : "no"); 1101 dbg(" MRL Sensor : %3s\n", MRL_SENS(ctrl) ? "yes" : "no"); 1102 dbg(" Attention Indicator : %3s\n", ATTN_LED(ctrl) ? "yes" : "no"); 1103 dbg(" Power Indicator : %3s\n", PWR_LED(ctrl) ? "yes" : "no"); 1104 dbg(" Hot-Plug Surprise : %3s\n", HP_SUPR_RM(ctrl) ? "yes" : "no"); 1105 dbg(" EMI Present : %3s\n", EMI(ctrl) ? "yes" : "no"); 1106 dbg(" Comamnd Completed : %3s\n", NO_CMD_CMPL(ctrl)? "no" : "yes"); 1107 pciehp_readw(ctrl, SLOTSTATUS, ®16); 1108 dbg("Slot Status : 0x%04x\n", reg16); 1109 pciehp_readw(ctrl, SLOTCTRL, ®16); 1110 dbg("Slot Control : 0x%04x\n", reg16); 1111 } 1112 1113 struct controller *pcie_init(struct pcie_device *dev) 1114 { 1115 struct controller *ctrl; 1116 u32 slot_cap; 1117 struct pci_dev *pdev = dev->port; 1118 1119 ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL); 1120 if (!ctrl) { 1121 err("%s : out of memory\n", __func__); 1122 goto abort; 1123 } 1124 INIT_LIST_HEAD(&ctrl->slot_list); 1125 1126 ctrl->pci_dev = pdev; 1127 ctrl->cap_base = pci_find_capability(pdev, PCI_CAP_ID_EXP); 1128 if (!ctrl->cap_base) { 1129 err("%s: Cannot find PCI Express capability\n", __func__); 1130 goto abort; 1131 } 1132 if (pciehp_readl(ctrl, SLOTCAP, &slot_cap)) { 1133 err("%s: Cannot read SLOTCAP register\n", __func__); 1134 goto abort; 1135 } 1136 1137 ctrl->slot_cap = slot_cap; 1138 ctrl->first_slot = slot_cap >> 19; 1139 ctrl->slot_device_offset = 0; 1140 ctrl->num_slots = 1; 1141 ctrl->hpc_ops = &pciehp_hpc_ops; 1142 mutex_init(&ctrl->crit_sect); 1143 mutex_init(&ctrl->ctrl_lock); 1144 init_waitqueue_head(&ctrl->queue); 1145 dbg_ctrl(ctrl); 1146 /* 1147 * Controller doesn't notify of command completion if the "No 1148 * Command Completed Support" bit is set in Slot Capability 1149 * register or the controller supports none of power 1150 * controller, attention led, power led and EMI. 1151 */ 1152 if (NO_CMD_CMPL(ctrl) || 1153 !(POWER_CTRL(ctrl) | ATTN_LED(ctrl) | PWR_LED(ctrl) | EMI(ctrl))) 1154 ctrl->no_cmd_complete = 1; 1155 1156 /* Clear all remaining event bits in Slot Status register */ 1157 if (pciehp_writew(ctrl, SLOTSTATUS, 0x1f)) 1158 goto abort_ctrl; 1159 1160 /* Disable sotfware notification */ 1161 pcie_disable_notification(ctrl); 1162 1163 /* 1164 * If this is the first controller to be initialized, 1165 * initialize the pciehp work queue 1166 */ 1167 if (atomic_add_return(1, &pciehp_num_controllers) == 1) { 1168 pciehp_wq = create_singlethread_workqueue("pciehpd"); 1169 if (!pciehp_wq) 1170 goto abort_ctrl; 1171 } 1172 1173 info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", 1174 pdev->vendor, pdev->device, 1175 pdev->subsystem_vendor, pdev->subsystem_device); 1176 1177 if (pcie_init_slot(ctrl)) 1178 goto abort_ctrl; 1179 1180 if (pcie_init_notification(ctrl)) 1181 goto abort_slot; 1182 1183 return ctrl; 1184 1185 abort_slot: 1186 pcie_cleanup_slot(ctrl); 1187 abort_ctrl: 1188 kfree(ctrl); 1189 abort: 1190 return NULL; 1191 } 1192 1193 void pcie_release_ctrl(struct controller *ctrl) 1194 { 1195 pcie_shutdown_notification(ctrl); 1196 pcie_cleanup_slot(ctrl); 1197 /* 1198 * If this is the last controller to be released, destroy the 1199 * pciehp work queue 1200 */ 1201 if (atomic_dec_and_test(&pciehp_num_controllers)) 1202 destroy_workqueue(pciehp_wq); 1203 kfree(ctrl); 1204 } 1205