1 /* 2 * PCI Express PCI Hot Plug Driver 3 * 4 * Copyright (C) 1995,2001 Compaq Computer Corporation 5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com) 6 * Copyright (C) 2001 IBM Corp. 7 * Copyright (C) 2003-2004 Intel Corporation 8 * 9 * All rights reserved. 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or (at 14 * your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 19 * NON INFRINGEMENT. See the GNU General Public License for more 20 * details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 25 * 26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com> 27 * 28 */ 29 30 #include <linux/kernel.h> 31 #include <linux/module.h> 32 #include <linux/types.h> 33 #include <linux/signal.h> 34 #include <linux/jiffies.h> 35 #include <linux/timer.h> 36 #include <linux/pci.h> 37 #include <linux/interrupt.h> 38 #include <linux/time.h> 39 #include <linux/slab.h> 40 41 #include "../pci.h" 42 #include "pciehp.h" 43 44 static inline struct pci_dev *ctrl_dev(struct controller *ctrl) 45 { 46 return ctrl->pcie->port; 47 } 48 49 static irqreturn_t pcie_isr(int irq, void *dev_id); 50 static void start_int_poll_timer(struct controller *ctrl, int sec); 51 52 /* This is the interrupt polling timeout function. */ 53 static void int_poll_timeout(unsigned long data) 54 { 55 struct controller *ctrl = (struct controller *)data; 56 57 /* Poll for interrupt events. regs == NULL => polling */ 58 pcie_isr(0, ctrl); 59 60 init_timer(&ctrl->poll_timer); 61 if (!pciehp_poll_time) 62 pciehp_poll_time = 2; /* default polling interval is 2 sec */ 63 64 start_int_poll_timer(ctrl, pciehp_poll_time); 65 } 66 67 /* This function starts the interrupt polling timer. */ 68 static void start_int_poll_timer(struct controller *ctrl, int sec) 69 { 70 /* Clamp to sane value */ 71 if ((sec <= 0) || (sec > 60)) 72 sec = 2; 73 74 ctrl->poll_timer.function = &int_poll_timeout; 75 ctrl->poll_timer.data = (unsigned long)ctrl; 76 ctrl->poll_timer.expires = jiffies + sec * HZ; 77 add_timer(&ctrl->poll_timer); 78 } 79 80 static inline int pciehp_request_irq(struct controller *ctrl) 81 { 82 int retval, irq = ctrl->pcie->irq; 83 84 /* Install interrupt polling timer. Start with 10 sec delay */ 85 if (pciehp_poll_mode) { 86 init_timer(&ctrl->poll_timer); 87 start_int_poll_timer(ctrl, 10); 88 return 0; 89 } 90 91 /* Installs the interrupt handler */ 92 retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl); 93 if (retval) 94 ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n", 95 irq); 96 return retval; 97 } 98 99 static inline void pciehp_free_irq(struct controller *ctrl) 100 { 101 if (pciehp_poll_mode) 102 del_timer_sync(&ctrl->poll_timer); 103 else 104 free_irq(ctrl->pcie->irq, ctrl); 105 } 106 107 static int pcie_poll_cmd(struct controller *ctrl) 108 { 109 struct pci_dev *pdev = ctrl_dev(ctrl); 110 u16 slot_status; 111 int timeout = 1000; 112 113 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); 114 if (slot_status & PCI_EXP_SLTSTA_CC) { 115 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, 116 PCI_EXP_SLTSTA_CC); 117 return 1; 118 } 119 while (timeout > 0) { 120 msleep(10); 121 timeout -= 10; 122 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); 123 if (slot_status & PCI_EXP_SLTSTA_CC) { 124 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, 125 PCI_EXP_SLTSTA_CC); 126 return 1; 127 } 128 } 129 return 0; /* timeout */ 130 } 131 132 static void pcie_wait_cmd(struct controller *ctrl, int poll) 133 { 134 unsigned int msecs = pciehp_poll_mode ? 2500 : 1000; 135 unsigned long timeout = msecs_to_jiffies(msecs); 136 int rc; 137 138 if (poll) 139 rc = pcie_poll_cmd(ctrl); 140 else 141 rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout); 142 if (!rc) 143 ctrl_dbg(ctrl, "Command not completed in 1000 msec\n"); 144 } 145 146 /** 147 * pcie_write_cmd - Issue controller command 148 * @ctrl: controller to which the command is issued 149 * @cmd: command value written to slot control register 150 * @mask: bitmask of slot control register to be modified 151 */ 152 static void pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask) 153 { 154 struct pci_dev *pdev = ctrl_dev(ctrl); 155 u16 slot_status; 156 u16 slot_ctrl; 157 158 mutex_lock(&ctrl->ctrl_lock); 159 160 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); 161 if (slot_status & PCI_EXP_SLTSTA_CC) { 162 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, 163 PCI_EXP_SLTSTA_CC); 164 if (!ctrl->no_cmd_complete) { 165 /* 166 * After 1 sec and CMD_COMPLETED still not set, just 167 * proceed forward to issue the next command according 168 * to spec. Just print out the error message. 169 */ 170 ctrl_dbg(ctrl, "CMD_COMPLETED not clear after 1 sec\n"); 171 } else if (!NO_CMD_CMPL(ctrl)) { 172 /* 173 * This controller seems to notify of command completed 174 * event even though it supports none of power 175 * controller, attention led, power led and EMI. 176 */ 177 ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Need to " 178 "wait for command completed event.\n"); 179 ctrl->no_cmd_complete = 0; 180 } else { 181 ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Maybe " 182 "the controller is broken.\n"); 183 } 184 } 185 186 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl); 187 slot_ctrl &= ~mask; 188 slot_ctrl |= (cmd & mask); 189 ctrl->cmd_busy = 1; 190 smp_mb(); 191 pcie_capability_write_word(pdev, PCI_EXP_SLTCTL, slot_ctrl); 192 193 /* 194 * Wait for command completion. 195 */ 196 if (!ctrl->no_cmd_complete) { 197 int poll = 0; 198 /* 199 * if hotplug interrupt is not enabled or command 200 * completed interrupt is not enabled, we need to poll 201 * command completed event. 202 */ 203 if (!(slot_ctrl & PCI_EXP_SLTCTL_HPIE) || 204 !(slot_ctrl & PCI_EXP_SLTCTL_CCIE)) 205 poll = 1; 206 pcie_wait_cmd(ctrl, poll); 207 } 208 mutex_unlock(&ctrl->ctrl_lock); 209 } 210 211 bool pciehp_check_link_active(struct controller *ctrl) 212 { 213 struct pci_dev *pdev = ctrl_dev(ctrl); 214 u16 lnk_status; 215 bool ret; 216 217 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status); 218 ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA); 219 220 if (ret) 221 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status); 222 223 return ret; 224 } 225 226 static void __pcie_wait_link_active(struct controller *ctrl, bool active) 227 { 228 int timeout = 1000; 229 230 if (pciehp_check_link_active(ctrl) == active) 231 return; 232 while (timeout > 0) { 233 msleep(10); 234 timeout -= 10; 235 if (pciehp_check_link_active(ctrl) == active) 236 return; 237 } 238 ctrl_dbg(ctrl, "Data Link Layer Link Active not %s in 1000 msec\n", 239 active ? "set" : "cleared"); 240 } 241 242 static void pcie_wait_link_active(struct controller *ctrl) 243 { 244 __pcie_wait_link_active(ctrl, true); 245 } 246 247 static bool pci_bus_check_dev(struct pci_bus *bus, int devfn) 248 { 249 u32 l; 250 int count = 0; 251 int delay = 1000, step = 20; 252 bool found = false; 253 254 do { 255 found = pci_bus_read_dev_vendor_id(bus, devfn, &l, 0); 256 count++; 257 258 if (found) 259 break; 260 261 msleep(step); 262 delay -= step; 263 } while (delay > 0); 264 265 if (count > 1 && pciehp_debug) 266 printk(KERN_DEBUG "pci %04x:%02x:%02x.%d id reading try %d times with interval %d ms to get %08x\n", 267 pci_domain_nr(bus), bus->number, PCI_SLOT(devfn), 268 PCI_FUNC(devfn), count, step, l); 269 270 return found; 271 } 272 273 int pciehp_check_link_status(struct controller *ctrl) 274 { 275 struct pci_dev *pdev = ctrl_dev(ctrl); 276 bool found; 277 u16 lnk_status; 278 279 /* 280 * Data Link Layer Link Active Reporting must be capable for 281 * hot-plug capable downstream port. But old controller might 282 * not implement it. In this case, we wait for 1000 ms. 283 */ 284 if (ctrl->link_active_reporting) 285 pcie_wait_link_active(ctrl); 286 else 287 msleep(1000); 288 289 /* wait 100ms before read pci conf, and try in 1s */ 290 msleep(100); 291 found = pci_bus_check_dev(ctrl->pcie->port->subordinate, 292 PCI_DEVFN(0, 0)); 293 294 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status); 295 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status); 296 if ((lnk_status & PCI_EXP_LNKSTA_LT) || 297 !(lnk_status & PCI_EXP_LNKSTA_NLW)) { 298 ctrl_err(ctrl, "Link Training Error occurs \n"); 299 return -1; 300 } 301 302 pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status); 303 304 if (!found) 305 return -1; 306 307 return 0; 308 } 309 310 static int __pciehp_link_set(struct controller *ctrl, bool enable) 311 { 312 struct pci_dev *pdev = ctrl_dev(ctrl); 313 u16 lnk_ctrl; 314 315 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &lnk_ctrl); 316 317 if (enable) 318 lnk_ctrl &= ~PCI_EXP_LNKCTL_LD; 319 else 320 lnk_ctrl |= PCI_EXP_LNKCTL_LD; 321 322 pcie_capability_write_word(pdev, PCI_EXP_LNKCTL, lnk_ctrl); 323 ctrl_dbg(ctrl, "%s: lnk_ctrl = %x\n", __func__, lnk_ctrl); 324 return 0; 325 } 326 327 static int pciehp_link_enable(struct controller *ctrl) 328 { 329 return __pciehp_link_set(ctrl, true); 330 } 331 332 void pciehp_get_attention_status(struct slot *slot, u8 *status) 333 { 334 struct controller *ctrl = slot->ctrl; 335 struct pci_dev *pdev = ctrl_dev(ctrl); 336 u16 slot_ctrl; 337 338 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl); 339 ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__, 340 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl); 341 342 switch (slot_ctrl & PCI_EXP_SLTCTL_AIC) { 343 case PCI_EXP_SLTCTL_ATTN_IND_ON: 344 *status = 1; /* On */ 345 break; 346 case PCI_EXP_SLTCTL_ATTN_IND_BLINK: 347 *status = 2; /* Blink */ 348 break; 349 case PCI_EXP_SLTCTL_ATTN_IND_OFF: 350 *status = 0; /* Off */ 351 break; 352 default: 353 *status = 0xFF; 354 break; 355 } 356 } 357 358 void pciehp_get_power_status(struct slot *slot, u8 *status) 359 { 360 struct controller *ctrl = slot->ctrl; 361 struct pci_dev *pdev = ctrl_dev(ctrl); 362 u16 slot_ctrl; 363 364 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl); 365 ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__, 366 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl); 367 368 switch (slot_ctrl & PCI_EXP_SLTCTL_PCC) { 369 case PCI_EXP_SLTCTL_PWR_ON: 370 *status = 1; /* On */ 371 break; 372 case PCI_EXP_SLTCTL_PWR_OFF: 373 *status = 0; /* Off */ 374 break; 375 default: 376 *status = 0xFF; 377 break; 378 } 379 } 380 381 void pciehp_get_latch_status(struct slot *slot, u8 *status) 382 { 383 struct pci_dev *pdev = ctrl_dev(slot->ctrl); 384 u16 slot_status; 385 386 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); 387 *status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS); 388 } 389 390 void pciehp_get_adapter_status(struct slot *slot, u8 *status) 391 { 392 struct pci_dev *pdev = ctrl_dev(slot->ctrl); 393 u16 slot_status; 394 395 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); 396 *status = !!(slot_status & PCI_EXP_SLTSTA_PDS); 397 } 398 399 int pciehp_query_power_fault(struct slot *slot) 400 { 401 struct pci_dev *pdev = ctrl_dev(slot->ctrl); 402 u16 slot_status; 403 404 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); 405 return !!(slot_status & PCI_EXP_SLTSTA_PFD); 406 } 407 408 void pciehp_set_attention_status(struct slot *slot, u8 value) 409 { 410 struct controller *ctrl = slot->ctrl; 411 u16 slot_cmd; 412 413 if (!ATTN_LED(ctrl)) 414 return; 415 416 switch (value) { 417 case 0 : /* turn off */ 418 slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_OFF; 419 break; 420 case 1: /* turn on */ 421 slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_ON; 422 break; 423 case 2: /* turn blink */ 424 slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_BLINK; 425 break; 426 default: 427 return; 428 } 429 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 430 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); 431 pcie_write_cmd(ctrl, slot_cmd, PCI_EXP_SLTCTL_AIC); 432 } 433 434 void pciehp_green_led_on(struct slot *slot) 435 { 436 struct controller *ctrl = slot->ctrl; 437 438 if (!PWR_LED(ctrl)) 439 return; 440 441 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_IND_ON, PCI_EXP_SLTCTL_PIC); 442 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 443 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 444 PCI_EXP_SLTCTL_PWR_IND_ON); 445 } 446 447 void pciehp_green_led_off(struct slot *slot) 448 { 449 struct controller *ctrl = slot->ctrl; 450 451 if (!PWR_LED(ctrl)) 452 return; 453 454 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_IND_OFF, PCI_EXP_SLTCTL_PIC); 455 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 456 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 457 PCI_EXP_SLTCTL_PWR_IND_OFF); 458 } 459 460 void pciehp_green_led_blink(struct slot *slot) 461 { 462 struct controller *ctrl = slot->ctrl; 463 464 if (!PWR_LED(ctrl)) 465 return; 466 467 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_IND_BLINK, PCI_EXP_SLTCTL_PIC); 468 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 469 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 470 PCI_EXP_SLTCTL_PWR_IND_BLINK); 471 } 472 473 int pciehp_power_on_slot(struct slot * slot) 474 { 475 struct controller *ctrl = slot->ctrl; 476 struct pci_dev *pdev = ctrl_dev(ctrl); 477 u16 slot_status; 478 int retval; 479 480 /* Clear sticky power-fault bit from previous power failures */ 481 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); 482 if (slot_status & PCI_EXP_SLTSTA_PFD) 483 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, 484 PCI_EXP_SLTSTA_PFD); 485 ctrl->power_fault_detected = 0; 486 487 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_ON, PCI_EXP_SLTCTL_PCC); 488 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 489 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 490 PCI_EXP_SLTCTL_PWR_ON); 491 492 retval = pciehp_link_enable(ctrl); 493 if (retval) 494 ctrl_err(ctrl, "%s: Can not enable the link!\n", __func__); 495 496 return retval; 497 } 498 499 void pciehp_power_off_slot(struct slot * slot) 500 { 501 struct controller *ctrl = slot->ctrl; 502 503 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_OFF, PCI_EXP_SLTCTL_PCC); 504 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 505 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 506 PCI_EXP_SLTCTL_PWR_OFF); 507 } 508 509 static irqreturn_t pcie_isr(int irq, void *dev_id) 510 { 511 struct controller *ctrl = (struct controller *)dev_id; 512 struct pci_dev *pdev = ctrl_dev(ctrl); 513 struct slot *slot = ctrl->slot; 514 u16 detected, intr_loc; 515 516 /* 517 * In order to guarantee that all interrupt events are 518 * serviced, we need to re-inspect Slot Status register after 519 * clearing what is presumed to be the last pending interrupt. 520 */ 521 intr_loc = 0; 522 do { 523 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &detected); 524 525 detected &= (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD | 526 PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC | 527 PCI_EXP_SLTSTA_CC | PCI_EXP_SLTSTA_DLLSC); 528 detected &= ~intr_loc; 529 intr_loc |= detected; 530 if (!intr_loc) 531 return IRQ_NONE; 532 if (detected) 533 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, 534 intr_loc); 535 } while (detected); 536 537 ctrl_dbg(ctrl, "%s: intr_loc %x\n", __func__, intr_loc); 538 539 /* Check Command Complete Interrupt Pending */ 540 if (intr_loc & PCI_EXP_SLTSTA_CC) { 541 ctrl->cmd_busy = 0; 542 smp_mb(); 543 wake_up(&ctrl->queue); 544 } 545 546 if (!(intr_loc & ~PCI_EXP_SLTSTA_CC)) 547 return IRQ_HANDLED; 548 549 /* Check MRL Sensor Changed */ 550 if (intr_loc & PCI_EXP_SLTSTA_MRLSC) 551 pciehp_handle_switch_change(slot); 552 553 /* Check Attention Button Pressed */ 554 if (intr_loc & PCI_EXP_SLTSTA_ABP) 555 pciehp_handle_attention_button(slot); 556 557 /* Check Presence Detect Changed */ 558 if (intr_loc & PCI_EXP_SLTSTA_PDC) 559 pciehp_handle_presence_change(slot); 560 561 /* Check Power Fault Detected */ 562 if ((intr_loc & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) { 563 ctrl->power_fault_detected = 1; 564 pciehp_handle_power_fault(slot); 565 } 566 567 if (intr_loc & PCI_EXP_SLTSTA_DLLSC) 568 pciehp_handle_linkstate_change(slot); 569 570 return IRQ_HANDLED; 571 } 572 573 void pcie_enable_notification(struct controller *ctrl) 574 { 575 u16 cmd, mask; 576 577 /* 578 * TBD: Power fault detected software notification support. 579 * 580 * Power fault detected software notification is not enabled 581 * now, because it caused power fault detected interrupt storm 582 * on some machines. On those machines, power fault detected 583 * bit in the slot status register was set again immediately 584 * when it is cleared in the interrupt service routine, and 585 * next power fault detected interrupt was notified again. 586 */ 587 588 /* 589 * Always enable link events: thus link-up and link-down shall 590 * always be treated as hotplug and unplug respectively. Enable 591 * presence detect only if Attention Button is not present. 592 */ 593 cmd = PCI_EXP_SLTCTL_DLLSCE; 594 if (ATTN_BUTTN(ctrl)) 595 cmd |= PCI_EXP_SLTCTL_ABPE; 596 else 597 cmd |= PCI_EXP_SLTCTL_PDCE; 598 if (MRL_SENS(ctrl)) 599 cmd |= PCI_EXP_SLTCTL_MRLSCE; 600 if (!pciehp_poll_mode) 601 cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE; 602 603 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE | 604 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE | 605 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE | 606 PCI_EXP_SLTCTL_DLLSCE); 607 608 pcie_write_cmd(ctrl, cmd, mask); 609 } 610 611 static void pcie_disable_notification(struct controller *ctrl) 612 { 613 u16 mask; 614 615 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE | 616 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE | 617 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE | 618 PCI_EXP_SLTCTL_DLLSCE); 619 pcie_write_cmd(ctrl, 0, mask); 620 } 621 622 /* 623 * pciehp has a 1:1 bus:slot relationship so we ultimately want a secondary 624 * bus reset of the bridge, but at the same time we want to ensure that it is 625 * not seen as a hot-unplug, followed by the hot-plug of the device. Thus, 626 * disable link state notification and presence detection change notification 627 * momentarily, if we see that they could interfere. Also, clear any spurious 628 * events after. 629 */ 630 int pciehp_reset_slot(struct slot *slot, int probe) 631 { 632 struct controller *ctrl = slot->ctrl; 633 struct pci_dev *pdev = ctrl_dev(ctrl); 634 u16 stat_mask = 0, ctrl_mask = 0; 635 636 if (probe) 637 return 0; 638 639 if (!ATTN_BUTTN(ctrl)) { 640 ctrl_mask |= PCI_EXP_SLTCTL_PDCE; 641 stat_mask |= PCI_EXP_SLTSTA_PDC; 642 } 643 ctrl_mask |= PCI_EXP_SLTCTL_DLLSCE; 644 stat_mask |= PCI_EXP_SLTSTA_DLLSC; 645 646 pcie_write_cmd(ctrl, 0, ctrl_mask); 647 if (pciehp_poll_mode) 648 del_timer_sync(&ctrl->poll_timer); 649 650 pci_reset_bridge_secondary_bus(ctrl->pcie->port); 651 652 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, stat_mask); 653 pcie_write_cmd(ctrl, ctrl_mask, ctrl_mask); 654 if (pciehp_poll_mode) 655 int_poll_timeout(ctrl->poll_timer.data); 656 657 return 0; 658 } 659 660 int pcie_init_notification(struct controller *ctrl) 661 { 662 if (pciehp_request_irq(ctrl)) 663 return -1; 664 pcie_enable_notification(ctrl); 665 ctrl->notification_enabled = 1; 666 return 0; 667 } 668 669 static void pcie_shutdown_notification(struct controller *ctrl) 670 { 671 if (ctrl->notification_enabled) { 672 pcie_disable_notification(ctrl); 673 pciehp_free_irq(ctrl); 674 ctrl->notification_enabled = 0; 675 } 676 } 677 678 static int pcie_init_slot(struct controller *ctrl) 679 { 680 struct slot *slot; 681 682 slot = kzalloc(sizeof(*slot), GFP_KERNEL); 683 if (!slot) 684 return -ENOMEM; 685 686 slot->wq = alloc_workqueue("pciehp-%u", 0, 0, PSN(ctrl)); 687 if (!slot->wq) 688 goto abort; 689 690 slot->ctrl = ctrl; 691 mutex_init(&slot->lock); 692 mutex_init(&slot->hotplug_lock); 693 INIT_DELAYED_WORK(&slot->work, pciehp_queue_pushbutton_work); 694 ctrl->slot = slot; 695 return 0; 696 abort: 697 kfree(slot); 698 return -ENOMEM; 699 } 700 701 static void pcie_cleanup_slot(struct controller *ctrl) 702 { 703 struct slot *slot = ctrl->slot; 704 cancel_delayed_work(&slot->work); 705 destroy_workqueue(slot->wq); 706 kfree(slot); 707 } 708 709 static inline void dbg_ctrl(struct controller *ctrl) 710 { 711 int i; 712 u16 reg16; 713 struct pci_dev *pdev = ctrl->pcie->port; 714 715 if (!pciehp_debug) 716 return; 717 718 ctrl_info(ctrl, "Hotplug Controller:\n"); 719 ctrl_info(ctrl, " Seg/Bus/Dev/Func/IRQ : %s IRQ %d\n", 720 pci_name(pdev), pdev->irq); 721 ctrl_info(ctrl, " Vendor ID : 0x%04x\n", pdev->vendor); 722 ctrl_info(ctrl, " Device ID : 0x%04x\n", pdev->device); 723 ctrl_info(ctrl, " Subsystem ID : 0x%04x\n", 724 pdev->subsystem_device); 725 ctrl_info(ctrl, " Subsystem Vendor ID : 0x%04x\n", 726 pdev->subsystem_vendor); 727 ctrl_info(ctrl, " PCIe Cap offset : 0x%02x\n", 728 pci_pcie_cap(pdev)); 729 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 730 if (!pci_resource_len(pdev, i)) 731 continue; 732 ctrl_info(ctrl, " PCI resource [%d] : %pR\n", 733 i, &pdev->resource[i]); 734 } 735 ctrl_info(ctrl, "Slot Capabilities : 0x%08x\n", ctrl->slot_cap); 736 ctrl_info(ctrl, " Physical Slot Number : %d\n", PSN(ctrl)); 737 ctrl_info(ctrl, " Attention Button : %3s\n", 738 ATTN_BUTTN(ctrl) ? "yes" : "no"); 739 ctrl_info(ctrl, " Power Controller : %3s\n", 740 POWER_CTRL(ctrl) ? "yes" : "no"); 741 ctrl_info(ctrl, " MRL Sensor : %3s\n", 742 MRL_SENS(ctrl) ? "yes" : "no"); 743 ctrl_info(ctrl, " Attention Indicator : %3s\n", 744 ATTN_LED(ctrl) ? "yes" : "no"); 745 ctrl_info(ctrl, " Power Indicator : %3s\n", 746 PWR_LED(ctrl) ? "yes" : "no"); 747 ctrl_info(ctrl, " Hot-Plug Surprise : %3s\n", 748 HP_SUPR_RM(ctrl) ? "yes" : "no"); 749 ctrl_info(ctrl, " EMI Present : %3s\n", 750 EMI(ctrl) ? "yes" : "no"); 751 ctrl_info(ctrl, " Command Completed : %3s\n", 752 NO_CMD_CMPL(ctrl) ? "no" : "yes"); 753 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, ®16); 754 ctrl_info(ctrl, "Slot Status : 0x%04x\n", reg16); 755 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, ®16); 756 ctrl_info(ctrl, "Slot Control : 0x%04x\n", reg16); 757 } 758 759 #define FLAG(x,y) (((x) & (y)) ? '+' : '-') 760 761 struct controller *pcie_init(struct pcie_device *dev) 762 { 763 struct controller *ctrl; 764 u32 slot_cap, link_cap; 765 struct pci_dev *pdev = dev->port; 766 767 ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL); 768 if (!ctrl) { 769 dev_err(&dev->device, "%s: Out of memory\n", __func__); 770 goto abort; 771 } 772 ctrl->pcie = dev; 773 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap); 774 ctrl->slot_cap = slot_cap; 775 mutex_init(&ctrl->ctrl_lock); 776 init_waitqueue_head(&ctrl->queue); 777 dbg_ctrl(ctrl); 778 /* 779 * Controller doesn't notify of command completion if the "No 780 * Command Completed Support" bit is set in Slot Capability 781 * register or the controller supports none of power 782 * controller, attention led, power led and EMI. 783 */ 784 if (NO_CMD_CMPL(ctrl) || 785 !(POWER_CTRL(ctrl) | ATTN_LED(ctrl) | PWR_LED(ctrl) | EMI(ctrl))) 786 ctrl->no_cmd_complete = 1; 787 788 /* Check if Data Link Layer Link Active Reporting is implemented */ 789 pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &link_cap); 790 if (link_cap & PCI_EXP_LNKCAP_DLLLARC) { 791 ctrl_dbg(ctrl, "Link Active Reporting supported\n"); 792 ctrl->link_active_reporting = 1; 793 } 794 795 /* Clear all remaining event bits in Slot Status register */ 796 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, 797 PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD | 798 PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC | 799 PCI_EXP_SLTSTA_CC); 800 801 /* Disable software notification */ 802 pcie_disable_notification(ctrl); 803 804 ctrl_info(ctrl, "Slot #%d AttnBtn%c AttnInd%c PwrInd%c PwrCtrl%c MRL%c Interlock%c NoCompl%c LLActRep%c\n", 805 (slot_cap & PCI_EXP_SLTCAP_PSN) >> 19, 806 FLAG(slot_cap, PCI_EXP_SLTCAP_ABP), 807 FLAG(slot_cap, PCI_EXP_SLTCAP_AIP), 808 FLAG(slot_cap, PCI_EXP_SLTCAP_PIP), 809 FLAG(slot_cap, PCI_EXP_SLTCAP_PCP), 810 FLAG(slot_cap, PCI_EXP_SLTCAP_MRLSP), 811 FLAG(slot_cap, PCI_EXP_SLTCAP_EIP), 812 FLAG(slot_cap, PCI_EXP_SLTCAP_NCCS), 813 FLAG(link_cap, PCI_EXP_LNKCAP_DLLLARC)); 814 815 if (pcie_init_slot(ctrl)) 816 goto abort_ctrl; 817 818 return ctrl; 819 820 abort_ctrl: 821 kfree(ctrl); 822 abort: 823 return NULL; 824 } 825 826 void pciehp_release_ctrl(struct controller *ctrl) 827 { 828 pcie_shutdown_notification(ctrl); 829 pcie_cleanup_slot(ctrl); 830 kfree(ctrl); 831 } 832