1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * PCI Express PCI Hot Plug Driver 4 * 5 * Copyright (C) 1995,2001 Compaq Computer Corporation 6 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com) 7 * Copyright (C) 2001 IBM Corp. 8 * Copyright (C) 2003-2004 Intel Corporation 9 * 10 * All rights reserved. 11 * 12 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com> 13 */ 14 15 #define dev_fmt(fmt) "pciehp: " fmt 16 17 #include <linux/dmi.h> 18 #include <linux/kernel.h> 19 #include <linux/types.h> 20 #include <linux/jiffies.h> 21 #include <linux/kthread.h> 22 #include <linux/pci.h> 23 #include <linux/pm_runtime.h> 24 #include <linux/interrupt.h> 25 #include <linux/slab.h> 26 27 #include "../pci.h" 28 #include "pciehp.h" 29 30 static const struct dmi_system_id inband_presence_disabled_dmi_table[] = { 31 /* 32 * Match all Dell systems, as some Dell systems have inband 33 * presence disabled on NVMe slots (but don't support the bit to 34 * report it). Setting inband presence disabled should have no 35 * negative effect, except on broken hotplug slots that never 36 * assert presence detect--and those will still work, they will 37 * just have a bit of extra delay before being probed. 38 */ 39 { 40 .ident = "Dell System", 41 .matches = { 42 DMI_MATCH(DMI_OEM_STRING, "Dell System"), 43 }, 44 }, 45 {} 46 }; 47 48 static inline struct pci_dev *ctrl_dev(struct controller *ctrl) 49 { 50 return ctrl->pcie->port; 51 } 52 53 static irqreturn_t pciehp_isr(int irq, void *dev_id); 54 static irqreturn_t pciehp_ist(int irq, void *dev_id); 55 static int pciehp_poll(void *data); 56 57 static inline int pciehp_request_irq(struct controller *ctrl) 58 { 59 int retval, irq = ctrl->pcie->irq; 60 61 if (pciehp_poll_mode) { 62 ctrl->poll_thread = kthread_run(&pciehp_poll, ctrl, 63 "pciehp_poll-%s", 64 slot_name(ctrl)); 65 return PTR_ERR_OR_ZERO(ctrl->poll_thread); 66 } 67 68 /* Installs the interrupt handler */ 69 retval = request_threaded_irq(irq, pciehp_isr, pciehp_ist, 70 IRQF_SHARED, "pciehp", ctrl); 71 if (retval) 72 ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n", 73 irq); 74 return retval; 75 } 76 77 static inline void pciehp_free_irq(struct controller *ctrl) 78 { 79 if (pciehp_poll_mode) 80 kthread_stop(ctrl->poll_thread); 81 else 82 free_irq(ctrl->pcie->irq, ctrl); 83 } 84 85 static int pcie_poll_cmd(struct controller *ctrl, int timeout) 86 { 87 struct pci_dev *pdev = ctrl_dev(ctrl); 88 u16 slot_status; 89 90 do { 91 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); 92 if (slot_status == (u16) ~0) { 93 ctrl_info(ctrl, "%s: no response from device\n", 94 __func__); 95 return 0; 96 } 97 98 if (slot_status & PCI_EXP_SLTSTA_CC) { 99 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, 100 PCI_EXP_SLTSTA_CC); 101 return 1; 102 } 103 msleep(10); 104 timeout -= 10; 105 } while (timeout >= 0); 106 return 0; /* timeout */ 107 } 108 109 static void pcie_wait_cmd(struct controller *ctrl) 110 { 111 unsigned int msecs = pciehp_poll_mode ? 2500 : 1000; 112 unsigned long duration = msecs_to_jiffies(msecs); 113 unsigned long cmd_timeout = ctrl->cmd_started + duration; 114 unsigned long now, timeout; 115 int rc; 116 117 /* 118 * If the controller does not generate notifications for command 119 * completions, we never need to wait between writes. 120 */ 121 if (NO_CMD_CMPL(ctrl)) 122 return; 123 124 if (!ctrl->cmd_busy) 125 return; 126 127 /* 128 * Even if the command has already timed out, we want to call 129 * pcie_poll_cmd() so it can clear PCI_EXP_SLTSTA_CC. 130 */ 131 now = jiffies; 132 if (time_before_eq(cmd_timeout, now)) 133 timeout = 1; 134 else 135 timeout = cmd_timeout - now; 136 137 if (ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE && 138 ctrl->slot_ctrl & PCI_EXP_SLTCTL_CCIE) 139 rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout); 140 else 141 rc = pcie_poll_cmd(ctrl, jiffies_to_msecs(timeout)); 142 143 if (!rc) 144 ctrl_info(ctrl, "Timeout on hotplug command %#06x (issued %u msec ago)\n", 145 ctrl->slot_ctrl, 146 jiffies_to_msecs(jiffies - ctrl->cmd_started)); 147 } 148 149 #define CC_ERRATUM_MASK (PCI_EXP_SLTCTL_PCC | \ 150 PCI_EXP_SLTCTL_PIC | \ 151 PCI_EXP_SLTCTL_AIC | \ 152 PCI_EXP_SLTCTL_EIC) 153 154 static void pcie_do_write_cmd(struct controller *ctrl, u16 cmd, 155 u16 mask, bool wait) 156 { 157 struct pci_dev *pdev = ctrl_dev(ctrl); 158 u16 slot_ctrl_orig, slot_ctrl; 159 160 mutex_lock(&ctrl->ctrl_lock); 161 162 /* 163 * Always wait for any previous command that might still be in progress 164 */ 165 pcie_wait_cmd(ctrl); 166 167 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl); 168 if (slot_ctrl == (u16) ~0) { 169 ctrl_info(ctrl, "%s: no response from device\n", __func__); 170 goto out; 171 } 172 173 slot_ctrl_orig = slot_ctrl; 174 slot_ctrl &= ~mask; 175 slot_ctrl |= (cmd & mask); 176 ctrl->cmd_busy = 1; 177 smp_mb(); 178 ctrl->slot_ctrl = slot_ctrl; 179 pcie_capability_write_word(pdev, PCI_EXP_SLTCTL, slot_ctrl); 180 ctrl->cmd_started = jiffies; 181 182 /* 183 * Controllers with the Intel CF118 and similar errata advertise 184 * Command Completed support, but they only set Command Completed 185 * if we change the "Control" bits for power, power indicator, 186 * attention indicator, or interlock. If we only change the 187 * "Enable" bits, they never set the Command Completed bit. 188 */ 189 if (pdev->broken_cmd_compl && 190 (slot_ctrl_orig & CC_ERRATUM_MASK) == (slot_ctrl & CC_ERRATUM_MASK)) 191 ctrl->cmd_busy = 0; 192 193 /* 194 * Optionally wait for the hardware to be ready for a new command, 195 * indicating completion of the above issued command. 196 */ 197 if (wait) 198 pcie_wait_cmd(ctrl); 199 200 out: 201 mutex_unlock(&ctrl->ctrl_lock); 202 } 203 204 /** 205 * pcie_write_cmd - Issue controller command 206 * @ctrl: controller to which the command is issued 207 * @cmd: command value written to slot control register 208 * @mask: bitmask of slot control register to be modified 209 */ 210 static void pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask) 211 { 212 pcie_do_write_cmd(ctrl, cmd, mask, true); 213 } 214 215 /* Same as above without waiting for the hardware to latch */ 216 static void pcie_write_cmd_nowait(struct controller *ctrl, u16 cmd, u16 mask) 217 { 218 pcie_do_write_cmd(ctrl, cmd, mask, false); 219 } 220 221 /** 222 * pciehp_check_link_active() - Is the link active 223 * @ctrl: PCIe hotplug controller 224 * 225 * Check whether the downstream link is currently active. Note it is 226 * possible that the card is removed immediately after this so the 227 * caller may need to take it into account. 228 * 229 * If the hotplug controller itself is not available anymore returns 230 * %-ENODEV. 231 */ 232 int pciehp_check_link_active(struct controller *ctrl) 233 { 234 struct pci_dev *pdev = ctrl_dev(ctrl); 235 u16 lnk_status; 236 int ret; 237 238 ret = pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status); 239 if (ret == PCIBIOS_DEVICE_NOT_FOUND || lnk_status == (u16)~0) 240 return -ENODEV; 241 242 ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA); 243 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status); 244 245 return ret; 246 } 247 248 static bool pci_bus_check_dev(struct pci_bus *bus, int devfn) 249 { 250 u32 l; 251 int count = 0; 252 int delay = 1000, step = 20; 253 bool found = false; 254 255 do { 256 found = pci_bus_read_dev_vendor_id(bus, devfn, &l, 0); 257 count++; 258 259 if (found) 260 break; 261 262 msleep(step); 263 delay -= step; 264 } while (delay > 0); 265 266 if (count > 1) 267 pr_debug("pci %04x:%02x:%02x.%d id reading try %d times with interval %d ms to get %08x\n", 268 pci_domain_nr(bus), bus->number, PCI_SLOT(devfn), 269 PCI_FUNC(devfn), count, step, l); 270 271 return found; 272 } 273 274 static void pcie_wait_for_presence(struct pci_dev *pdev) 275 { 276 int timeout = 1250; 277 u16 slot_status; 278 279 do { 280 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); 281 if (slot_status & PCI_EXP_SLTSTA_PDS) 282 return; 283 msleep(10); 284 timeout -= 10; 285 } while (timeout > 0); 286 287 pci_info(pdev, "Timeout waiting for Presence Detect\n"); 288 } 289 290 int pciehp_check_link_status(struct controller *ctrl) 291 { 292 struct pci_dev *pdev = ctrl_dev(ctrl); 293 bool found; 294 u16 lnk_status; 295 296 if (!pcie_wait_for_link(pdev, true)) 297 return -1; 298 299 if (ctrl->inband_presence_disabled) 300 pcie_wait_for_presence(pdev); 301 302 found = pci_bus_check_dev(ctrl->pcie->port->subordinate, 303 PCI_DEVFN(0, 0)); 304 305 /* ignore link or presence changes up to this point */ 306 if (found) 307 atomic_and(~(PCI_EXP_SLTSTA_DLLSC | PCI_EXP_SLTSTA_PDC), 308 &ctrl->pending_events); 309 310 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status); 311 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status); 312 if ((lnk_status & PCI_EXP_LNKSTA_LT) || 313 !(lnk_status & PCI_EXP_LNKSTA_NLW)) { 314 ctrl_err(ctrl, "link training error: status %#06x\n", 315 lnk_status); 316 return -1; 317 } 318 319 pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status); 320 321 if (!found) 322 return -1; 323 324 return 0; 325 } 326 327 static int __pciehp_link_set(struct controller *ctrl, bool enable) 328 { 329 struct pci_dev *pdev = ctrl_dev(ctrl); 330 u16 lnk_ctrl; 331 332 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &lnk_ctrl); 333 334 if (enable) 335 lnk_ctrl &= ~PCI_EXP_LNKCTL_LD; 336 else 337 lnk_ctrl |= PCI_EXP_LNKCTL_LD; 338 339 pcie_capability_write_word(pdev, PCI_EXP_LNKCTL, lnk_ctrl); 340 ctrl_dbg(ctrl, "%s: lnk_ctrl = %x\n", __func__, lnk_ctrl); 341 return 0; 342 } 343 344 static int pciehp_link_enable(struct controller *ctrl) 345 { 346 return __pciehp_link_set(ctrl, true); 347 } 348 349 int pciehp_get_raw_indicator_status(struct hotplug_slot *hotplug_slot, 350 u8 *status) 351 { 352 struct controller *ctrl = to_ctrl(hotplug_slot); 353 struct pci_dev *pdev = ctrl_dev(ctrl); 354 u16 slot_ctrl; 355 356 pci_config_pm_runtime_get(pdev); 357 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl); 358 pci_config_pm_runtime_put(pdev); 359 *status = (slot_ctrl & (PCI_EXP_SLTCTL_AIC | PCI_EXP_SLTCTL_PIC)) >> 6; 360 return 0; 361 } 362 363 int pciehp_get_attention_status(struct hotplug_slot *hotplug_slot, u8 *status) 364 { 365 struct controller *ctrl = to_ctrl(hotplug_slot); 366 struct pci_dev *pdev = ctrl_dev(ctrl); 367 u16 slot_ctrl; 368 369 pci_config_pm_runtime_get(pdev); 370 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl); 371 pci_config_pm_runtime_put(pdev); 372 ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__, 373 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl); 374 375 switch (slot_ctrl & PCI_EXP_SLTCTL_AIC) { 376 case PCI_EXP_SLTCTL_ATTN_IND_ON: 377 *status = 1; /* On */ 378 break; 379 case PCI_EXP_SLTCTL_ATTN_IND_BLINK: 380 *status = 2; /* Blink */ 381 break; 382 case PCI_EXP_SLTCTL_ATTN_IND_OFF: 383 *status = 0; /* Off */ 384 break; 385 default: 386 *status = 0xFF; 387 break; 388 } 389 390 return 0; 391 } 392 393 void pciehp_get_power_status(struct controller *ctrl, u8 *status) 394 { 395 struct pci_dev *pdev = ctrl_dev(ctrl); 396 u16 slot_ctrl; 397 398 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl); 399 ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__, 400 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl); 401 402 switch (slot_ctrl & PCI_EXP_SLTCTL_PCC) { 403 case PCI_EXP_SLTCTL_PWR_ON: 404 *status = 1; /* On */ 405 break; 406 case PCI_EXP_SLTCTL_PWR_OFF: 407 *status = 0; /* Off */ 408 break; 409 default: 410 *status = 0xFF; 411 break; 412 } 413 } 414 415 void pciehp_get_latch_status(struct controller *ctrl, u8 *status) 416 { 417 struct pci_dev *pdev = ctrl_dev(ctrl); 418 u16 slot_status; 419 420 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); 421 *status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS); 422 } 423 424 /** 425 * pciehp_card_present() - Is the card present 426 * @ctrl: PCIe hotplug controller 427 * 428 * Function checks whether the card is currently present in the slot and 429 * in that case returns true. Note it is possible that the card is 430 * removed immediately after the check so the caller may need to take 431 * this into account. 432 * 433 * It the hotplug controller itself is not available anymore returns 434 * %-ENODEV. 435 */ 436 int pciehp_card_present(struct controller *ctrl) 437 { 438 struct pci_dev *pdev = ctrl_dev(ctrl); 439 u16 slot_status; 440 int ret; 441 442 ret = pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); 443 if (ret == PCIBIOS_DEVICE_NOT_FOUND || slot_status == (u16)~0) 444 return -ENODEV; 445 446 return !!(slot_status & PCI_EXP_SLTSTA_PDS); 447 } 448 449 /** 450 * pciehp_card_present_or_link_active() - whether given slot is occupied 451 * @ctrl: PCIe hotplug controller 452 * 453 * Unlike pciehp_card_present(), which determines presence solely from the 454 * Presence Detect State bit, this helper also returns true if the Link Active 455 * bit is set. This is a concession to broken hotplug ports which hardwire 456 * Presence Detect State to zero, such as Wilocity's [1ae9:0200]. 457 * 458 * Returns: %1 if the slot is occupied and %0 if it is not. If the hotplug 459 * port is not present anymore returns %-ENODEV. 460 */ 461 int pciehp_card_present_or_link_active(struct controller *ctrl) 462 { 463 int ret; 464 465 ret = pciehp_card_present(ctrl); 466 if (ret) 467 return ret; 468 469 return pciehp_check_link_active(ctrl); 470 } 471 472 int pciehp_query_power_fault(struct controller *ctrl) 473 { 474 struct pci_dev *pdev = ctrl_dev(ctrl); 475 u16 slot_status; 476 477 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); 478 return !!(slot_status & PCI_EXP_SLTSTA_PFD); 479 } 480 481 int pciehp_set_raw_indicator_status(struct hotplug_slot *hotplug_slot, 482 u8 status) 483 { 484 struct controller *ctrl = to_ctrl(hotplug_slot); 485 struct pci_dev *pdev = ctrl_dev(ctrl); 486 487 pci_config_pm_runtime_get(pdev); 488 pcie_write_cmd_nowait(ctrl, status << 6, 489 PCI_EXP_SLTCTL_AIC | PCI_EXP_SLTCTL_PIC); 490 pci_config_pm_runtime_put(pdev); 491 return 0; 492 } 493 494 /** 495 * pciehp_set_indicators() - set attention indicator, power indicator, or both 496 * @ctrl: PCIe hotplug controller 497 * @pwr: one of: 498 * PCI_EXP_SLTCTL_PWR_IND_ON 499 * PCI_EXP_SLTCTL_PWR_IND_BLINK 500 * PCI_EXP_SLTCTL_PWR_IND_OFF 501 * @attn: one of: 502 * PCI_EXP_SLTCTL_ATTN_IND_ON 503 * PCI_EXP_SLTCTL_ATTN_IND_BLINK 504 * PCI_EXP_SLTCTL_ATTN_IND_OFF 505 * 506 * Either @pwr or @attn can also be INDICATOR_NOOP to leave that indicator 507 * unchanged. 508 */ 509 void pciehp_set_indicators(struct controller *ctrl, int pwr, int attn) 510 { 511 u16 cmd = 0, mask = 0; 512 513 if (PWR_LED(ctrl) && pwr != INDICATOR_NOOP) { 514 cmd |= (pwr & PCI_EXP_SLTCTL_PIC); 515 mask |= PCI_EXP_SLTCTL_PIC; 516 } 517 518 if (ATTN_LED(ctrl) && attn != INDICATOR_NOOP) { 519 cmd |= (attn & PCI_EXP_SLTCTL_AIC); 520 mask |= PCI_EXP_SLTCTL_AIC; 521 } 522 523 if (cmd) { 524 pcie_write_cmd_nowait(ctrl, cmd, mask); 525 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 526 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, cmd); 527 } 528 } 529 530 int pciehp_power_on_slot(struct controller *ctrl) 531 { 532 struct pci_dev *pdev = ctrl_dev(ctrl); 533 u16 slot_status; 534 int retval; 535 536 /* Clear power-fault bit from previous power failures */ 537 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); 538 if (slot_status & PCI_EXP_SLTSTA_PFD) 539 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, 540 PCI_EXP_SLTSTA_PFD); 541 ctrl->power_fault_detected = 0; 542 543 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_ON, PCI_EXP_SLTCTL_PCC); 544 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 545 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 546 PCI_EXP_SLTCTL_PWR_ON); 547 548 retval = pciehp_link_enable(ctrl); 549 if (retval) 550 ctrl_err(ctrl, "%s: Can not enable the link!\n", __func__); 551 552 return retval; 553 } 554 555 void pciehp_power_off_slot(struct controller *ctrl) 556 { 557 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_OFF, PCI_EXP_SLTCTL_PCC); 558 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 559 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 560 PCI_EXP_SLTCTL_PWR_OFF); 561 } 562 563 static irqreturn_t pciehp_isr(int irq, void *dev_id) 564 { 565 struct controller *ctrl = (struct controller *)dev_id; 566 struct pci_dev *pdev = ctrl_dev(ctrl); 567 struct device *parent = pdev->dev.parent; 568 u16 status, events = 0; 569 570 /* 571 * Interrupts only occur in D3hot or shallower and only if enabled 572 * in the Slot Control register (PCIe r4.0, sec 6.7.3.4). 573 */ 574 if (pdev->current_state == PCI_D3cold || 575 (!(ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE) && !pciehp_poll_mode)) 576 return IRQ_NONE; 577 578 /* 579 * Keep the port accessible by holding a runtime PM ref on its parent. 580 * Defer resume of the parent to the IRQ thread if it's suspended. 581 * Mask the interrupt until then. 582 */ 583 if (parent) { 584 pm_runtime_get_noresume(parent); 585 if (!pm_runtime_active(parent)) { 586 pm_runtime_put(parent); 587 disable_irq_nosync(irq); 588 atomic_or(RERUN_ISR, &ctrl->pending_events); 589 return IRQ_WAKE_THREAD; 590 } 591 } 592 593 read_status: 594 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &status); 595 if (status == (u16) ~0) { 596 ctrl_info(ctrl, "%s: no response from device\n", __func__); 597 if (parent) 598 pm_runtime_put(parent); 599 return IRQ_NONE; 600 } 601 602 /* 603 * Slot Status contains plain status bits as well as event 604 * notification bits; right now we only want the event bits. 605 */ 606 status &= PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD | 607 PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_CC | 608 PCI_EXP_SLTSTA_DLLSC; 609 610 /* 611 * If we've already reported a power fault, don't report it again 612 * until we've done something to handle it. 613 */ 614 if (ctrl->power_fault_detected) 615 status &= ~PCI_EXP_SLTSTA_PFD; 616 617 events |= status; 618 if (!events) { 619 if (parent) 620 pm_runtime_put(parent); 621 return IRQ_NONE; 622 } 623 624 if (status) { 625 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, events); 626 627 /* 628 * In MSI mode, all event bits must be zero before the port 629 * will send a new interrupt (PCIe Base Spec r5.0 sec 6.7.3.4). 630 * So re-read the Slot Status register in case a bit was set 631 * between read and write. 632 */ 633 if (pci_dev_msi_enabled(pdev) && !pciehp_poll_mode) 634 goto read_status; 635 } 636 637 ctrl_dbg(ctrl, "pending interrupts %#06x from Slot Status\n", events); 638 if (parent) 639 pm_runtime_put(parent); 640 641 /* 642 * Command Completed notifications are not deferred to the 643 * IRQ thread because it may be waiting for their arrival. 644 */ 645 if (events & PCI_EXP_SLTSTA_CC) { 646 ctrl->cmd_busy = 0; 647 smp_mb(); 648 wake_up(&ctrl->queue); 649 650 if (events == PCI_EXP_SLTSTA_CC) 651 return IRQ_HANDLED; 652 653 events &= ~PCI_EXP_SLTSTA_CC; 654 } 655 656 if (pdev->ignore_hotplug) { 657 ctrl_dbg(ctrl, "ignoring hotplug event %#06x\n", events); 658 return IRQ_HANDLED; 659 } 660 661 /* Save pending events for consumption by IRQ thread. */ 662 atomic_or(events, &ctrl->pending_events); 663 return IRQ_WAKE_THREAD; 664 } 665 666 static irqreturn_t pciehp_ist(int irq, void *dev_id) 667 { 668 struct controller *ctrl = (struct controller *)dev_id; 669 struct pci_dev *pdev = ctrl_dev(ctrl); 670 irqreturn_t ret; 671 u32 events; 672 673 ctrl->ist_running = true; 674 pci_config_pm_runtime_get(pdev); 675 676 /* rerun pciehp_isr() if the port was inaccessible on interrupt */ 677 if (atomic_fetch_and(~RERUN_ISR, &ctrl->pending_events) & RERUN_ISR) { 678 ret = pciehp_isr(irq, dev_id); 679 enable_irq(irq); 680 if (ret != IRQ_WAKE_THREAD) 681 goto out; 682 } 683 684 synchronize_hardirq(irq); 685 events = atomic_xchg(&ctrl->pending_events, 0); 686 if (!events) { 687 ret = IRQ_NONE; 688 goto out; 689 } 690 691 /* Check Attention Button Pressed */ 692 if (events & PCI_EXP_SLTSTA_ABP) { 693 ctrl_info(ctrl, "Slot(%s): Attention button pressed\n", 694 slot_name(ctrl)); 695 pciehp_handle_button_press(ctrl); 696 } 697 698 /* Check Power Fault Detected */ 699 if ((events & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) { 700 ctrl->power_fault_detected = 1; 701 ctrl_err(ctrl, "Slot(%s): Power fault\n", slot_name(ctrl)); 702 pciehp_set_indicators(ctrl, PCI_EXP_SLTCTL_PWR_IND_OFF, 703 PCI_EXP_SLTCTL_ATTN_IND_ON); 704 } 705 706 /* 707 * Disable requests have higher priority than Presence Detect Changed 708 * or Data Link Layer State Changed events. 709 */ 710 down_read(&ctrl->reset_lock); 711 if (events & DISABLE_SLOT) 712 pciehp_handle_disable_request(ctrl); 713 else if (events & (PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_DLLSC)) 714 pciehp_handle_presence_or_link_change(ctrl, events); 715 up_read(&ctrl->reset_lock); 716 717 ret = IRQ_HANDLED; 718 out: 719 pci_config_pm_runtime_put(pdev); 720 ctrl->ist_running = false; 721 wake_up(&ctrl->requester); 722 return ret; 723 } 724 725 static int pciehp_poll(void *data) 726 { 727 struct controller *ctrl = data; 728 729 schedule_timeout_idle(10 * HZ); /* start with 10 sec delay */ 730 731 while (!kthread_should_stop()) { 732 /* poll for interrupt events or user requests */ 733 while (pciehp_isr(IRQ_NOTCONNECTED, ctrl) == IRQ_WAKE_THREAD || 734 atomic_read(&ctrl->pending_events)) 735 pciehp_ist(IRQ_NOTCONNECTED, ctrl); 736 737 if (pciehp_poll_time <= 0 || pciehp_poll_time > 60) 738 pciehp_poll_time = 2; /* clamp to sane value */ 739 740 schedule_timeout_idle(pciehp_poll_time * HZ); 741 } 742 743 return 0; 744 } 745 746 static void pcie_enable_notification(struct controller *ctrl) 747 { 748 u16 cmd, mask; 749 750 /* 751 * TBD: Power fault detected software notification support. 752 * 753 * Power fault detected software notification is not enabled 754 * now, because it caused power fault detected interrupt storm 755 * on some machines. On those machines, power fault detected 756 * bit in the slot status register was set again immediately 757 * when it is cleared in the interrupt service routine, and 758 * next power fault detected interrupt was notified again. 759 */ 760 761 /* 762 * Always enable link events: thus link-up and link-down shall 763 * always be treated as hotplug and unplug respectively. Enable 764 * presence detect only if Attention Button is not present. 765 */ 766 cmd = PCI_EXP_SLTCTL_DLLSCE; 767 if (ATTN_BUTTN(ctrl)) 768 cmd |= PCI_EXP_SLTCTL_ABPE; 769 else 770 cmd |= PCI_EXP_SLTCTL_PDCE; 771 if (!pciehp_poll_mode) 772 cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE; 773 774 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE | 775 PCI_EXP_SLTCTL_PFDE | 776 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE | 777 PCI_EXP_SLTCTL_DLLSCE); 778 779 pcie_write_cmd_nowait(ctrl, cmd, mask); 780 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 781 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, cmd); 782 } 783 784 static void pcie_disable_notification(struct controller *ctrl) 785 { 786 u16 mask; 787 788 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE | 789 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE | 790 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE | 791 PCI_EXP_SLTCTL_DLLSCE); 792 pcie_write_cmd(ctrl, 0, mask); 793 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 794 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0); 795 } 796 797 void pcie_clear_hotplug_events(struct controller *ctrl) 798 { 799 pcie_capability_write_word(ctrl_dev(ctrl), PCI_EXP_SLTSTA, 800 PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_DLLSC); 801 } 802 803 void pcie_enable_interrupt(struct controller *ctrl) 804 { 805 u16 mask; 806 807 mask = PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_DLLSCE; 808 pcie_write_cmd(ctrl, mask, mask); 809 } 810 811 void pcie_disable_interrupt(struct controller *ctrl) 812 { 813 u16 mask; 814 815 /* 816 * Mask hot-plug interrupt to prevent it triggering immediately 817 * when the link goes inactive (we still get PME when any of the 818 * enabled events is detected). Same goes with Link Layer State 819 * changed event which generates PME immediately when the link goes 820 * inactive so mask it as well. 821 */ 822 mask = PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_DLLSCE; 823 pcie_write_cmd(ctrl, 0, mask); 824 } 825 826 /* 827 * pciehp has a 1:1 bus:slot relationship so we ultimately want a secondary 828 * bus reset of the bridge, but at the same time we want to ensure that it is 829 * not seen as a hot-unplug, followed by the hot-plug of the device. Thus, 830 * disable link state notification and presence detection change notification 831 * momentarily, if we see that they could interfere. Also, clear any spurious 832 * events after. 833 */ 834 int pciehp_reset_slot(struct hotplug_slot *hotplug_slot, int probe) 835 { 836 struct controller *ctrl = to_ctrl(hotplug_slot); 837 struct pci_dev *pdev = ctrl_dev(ctrl); 838 u16 stat_mask = 0, ctrl_mask = 0; 839 int rc; 840 841 if (probe) 842 return 0; 843 844 down_write(&ctrl->reset_lock); 845 846 if (!ATTN_BUTTN(ctrl)) { 847 ctrl_mask |= PCI_EXP_SLTCTL_PDCE; 848 stat_mask |= PCI_EXP_SLTSTA_PDC; 849 } 850 ctrl_mask |= PCI_EXP_SLTCTL_DLLSCE; 851 stat_mask |= PCI_EXP_SLTSTA_DLLSC; 852 853 pcie_write_cmd(ctrl, 0, ctrl_mask); 854 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 855 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0); 856 857 rc = pci_bridge_secondary_bus_reset(ctrl->pcie->port); 858 859 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, stat_mask); 860 pcie_write_cmd_nowait(ctrl, ctrl_mask, ctrl_mask); 861 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 862 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, ctrl_mask); 863 864 up_write(&ctrl->reset_lock); 865 return rc; 866 } 867 868 int pcie_init_notification(struct controller *ctrl) 869 { 870 if (pciehp_request_irq(ctrl)) 871 return -1; 872 pcie_enable_notification(ctrl); 873 ctrl->notification_enabled = 1; 874 return 0; 875 } 876 877 void pcie_shutdown_notification(struct controller *ctrl) 878 { 879 if (ctrl->notification_enabled) { 880 pcie_disable_notification(ctrl); 881 pciehp_free_irq(ctrl); 882 ctrl->notification_enabled = 0; 883 } 884 } 885 886 static inline void dbg_ctrl(struct controller *ctrl) 887 { 888 struct pci_dev *pdev = ctrl->pcie->port; 889 u16 reg16; 890 891 ctrl_dbg(ctrl, "Slot Capabilities : 0x%08x\n", ctrl->slot_cap); 892 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, ®16); 893 ctrl_dbg(ctrl, "Slot Status : 0x%04x\n", reg16); 894 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, ®16); 895 ctrl_dbg(ctrl, "Slot Control : 0x%04x\n", reg16); 896 } 897 898 #define FLAG(x, y) (((x) & (y)) ? '+' : '-') 899 900 struct controller *pcie_init(struct pcie_device *dev) 901 { 902 struct controller *ctrl; 903 u32 slot_cap, slot_cap2, link_cap; 904 u8 poweron; 905 struct pci_dev *pdev = dev->port; 906 struct pci_bus *subordinate = pdev->subordinate; 907 908 ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL); 909 if (!ctrl) 910 return NULL; 911 912 ctrl->pcie = dev; 913 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap); 914 915 if (pdev->hotplug_user_indicators) 916 slot_cap &= ~(PCI_EXP_SLTCAP_AIP | PCI_EXP_SLTCAP_PIP); 917 918 /* 919 * We assume no Thunderbolt controllers support Command Complete events, 920 * but some controllers falsely claim they do. 921 */ 922 if (pdev->is_thunderbolt) 923 slot_cap |= PCI_EXP_SLTCAP_NCCS; 924 925 ctrl->slot_cap = slot_cap; 926 mutex_init(&ctrl->ctrl_lock); 927 mutex_init(&ctrl->state_lock); 928 init_rwsem(&ctrl->reset_lock); 929 init_waitqueue_head(&ctrl->requester); 930 init_waitqueue_head(&ctrl->queue); 931 INIT_DELAYED_WORK(&ctrl->button_work, pciehp_queue_pushbutton_work); 932 dbg_ctrl(ctrl); 933 934 down_read(&pci_bus_sem); 935 ctrl->state = list_empty(&subordinate->devices) ? OFF_STATE : ON_STATE; 936 up_read(&pci_bus_sem); 937 938 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP2, &slot_cap2); 939 if (slot_cap2 & PCI_EXP_SLTCAP2_IBPD) { 940 pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_IBPD_DISABLE, 941 PCI_EXP_SLTCTL_IBPD_DISABLE); 942 ctrl->inband_presence_disabled = 1; 943 } 944 945 if (dmi_first_match(inband_presence_disabled_dmi_table)) 946 ctrl->inband_presence_disabled = 1; 947 948 /* Check if Data Link Layer Link Active Reporting is implemented */ 949 pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &link_cap); 950 951 /* Clear all remaining event bits in Slot Status register. */ 952 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, 953 PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD | 954 PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_CC | 955 PCI_EXP_SLTSTA_DLLSC | PCI_EXP_SLTSTA_PDC); 956 957 ctrl_info(ctrl, "Slot #%d AttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surprise%c Interlock%c NoCompl%c IbPresDis%c LLActRep%c%s\n", 958 (slot_cap & PCI_EXP_SLTCAP_PSN) >> 19, 959 FLAG(slot_cap, PCI_EXP_SLTCAP_ABP), 960 FLAG(slot_cap, PCI_EXP_SLTCAP_PCP), 961 FLAG(slot_cap, PCI_EXP_SLTCAP_MRLSP), 962 FLAG(slot_cap, PCI_EXP_SLTCAP_AIP), 963 FLAG(slot_cap, PCI_EXP_SLTCAP_PIP), 964 FLAG(slot_cap, PCI_EXP_SLTCAP_HPC), 965 FLAG(slot_cap, PCI_EXP_SLTCAP_HPS), 966 FLAG(slot_cap, PCI_EXP_SLTCAP_EIP), 967 FLAG(slot_cap, PCI_EXP_SLTCAP_NCCS), 968 FLAG(slot_cap2, PCI_EXP_SLTCAP2_IBPD), 969 FLAG(link_cap, PCI_EXP_LNKCAP_DLLLARC), 970 pdev->broken_cmd_compl ? " (with Cmd Compl erratum)" : ""); 971 972 /* 973 * If empty slot's power status is on, turn power off. The IRQ isn't 974 * requested yet, so avoid triggering a notification with this command. 975 */ 976 if (POWER_CTRL(ctrl)) { 977 pciehp_get_power_status(ctrl, &poweron); 978 if (!pciehp_card_present_or_link_active(ctrl) && poweron) { 979 pcie_disable_notification(ctrl); 980 pciehp_power_off_slot(ctrl); 981 } 982 } 983 984 return ctrl; 985 } 986 987 void pciehp_release_ctrl(struct controller *ctrl) 988 { 989 cancel_delayed_work_sync(&ctrl->button_work); 990 kfree(ctrl); 991 } 992 993 static void quirk_cmd_compl(struct pci_dev *pdev) 994 { 995 u32 slot_cap; 996 997 if (pci_is_pcie(pdev)) { 998 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap); 999 if (slot_cap & PCI_EXP_SLTCAP_HPC && 1000 !(slot_cap & PCI_EXP_SLTCAP_NCCS)) 1001 pdev->broken_cmd_compl = 1; 1002 } 1003 } 1004 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 1005 PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl); 1006 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_QCOM, 0x0400, 1007 PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl); 1008 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_QCOM, 0x0401, 1009 PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl); 1010 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_HXT, 0x0401, 1011 PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl); 1012