1 /* 2 * PCI Express PCI Hot Plug Driver 3 * 4 * Copyright (C) 1995,2001 Compaq Computer Corporation 5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com) 6 * Copyright (C) 2001 IBM Corp. 7 * Copyright (C) 2003-2004 Intel Corporation 8 * 9 * All rights reserved. 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or (at 14 * your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 19 * NON INFRINGEMENT. See the GNU General Public License for more 20 * details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 25 * 26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com> 27 * 28 */ 29 30 #include <linux/kernel.h> 31 #include <linux/module.h> 32 #include <linux/types.h> 33 #include <linux/signal.h> 34 #include <linux/jiffies.h> 35 #include <linux/timer.h> 36 #include <linux/pci.h> 37 #include <linux/interrupt.h> 38 #include <linux/time.h> 39 #include <linux/slab.h> 40 41 #include "../pci.h" 42 #include "pciehp.h" 43 44 static inline struct pci_dev *ctrl_dev(struct controller *ctrl) 45 { 46 return ctrl->pcie->port; 47 } 48 49 static irqreturn_t pcie_isr(int irq, void *dev_id); 50 static void start_int_poll_timer(struct controller *ctrl, int sec); 51 52 /* This is the interrupt polling timeout function. */ 53 static void int_poll_timeout(struct timer_list *t) 54 { 55 struct controller *ctrl = from_timer(ctrl, t, poll_timer); 56 57 /* Poll for interrupt events. regs == NULL => polling */ 58 pcie_isr(0, ctrl); 59 60 if (!pciehp_poll_time) 61 pciehp_poll_time = 2; /* default polling interval is 2 sec */ 62 63 start_int_poll_timer(ctrl, pciehp_poll_time); 64 } 65 66 /* This function starts the interrupt polling timer. */ 67 static void start_int_poll_timer(struct controller *ctrl, int sec) 68 { 69 /* Clamp to sane value */ 70 if ((sec <= 0) || (sec > 60)) 71 sec = 2; 72 73 ctrl->poll_timer.expires = jiffies + sec * HZ; 74 add_timer(&ctrl->poll_timer); 75 } 76 77 static inline int pciehp_request_irq(struct controller *ctrl) 78 { 79 int retval, irq = ctrl->pcie->irq; 80 81 /* Install interrupt polling timer. Start with 10 sec delay */ 82 if (pciehp_poll_mode) { 83 timer_setup(&ctrl->poll_timer, int_poll_timeout, 0); 84 start_int_poll_timer(ctrl, 10); 85 return 0; 86 } 87 88 /* Installs the interrupt handler */ 89 retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl); 90 if (retval) 91 ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n", 92 irq); 93 return retval; 94 } 95 96 static inline void pciehp_free_irq(struct controller *ctrl) 97 { 98 if (pciehp_poll_mode) 99 del_timer_sync(&ctrl->poll_timer); 100 else 101 free_irq(ctrl->pcie->irq, ctrl); 102 } 103 104 static int pcie_poll_cmd(struct controller *ctrl, int timeout) 105 { 106 struct pci_dev *pdev = ctrl_dev(ctrl); 107 u16 slot_status; 108 109 while (true) { 110 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); 111 if (slot_status == (u16) ~0) { 112 ctrl_info(ctrl, "%s: no response from device\n", 113 __func__); 114 return 0; 115 } 116 117 if (slot_status & PCI_EXP_SLTSTA_CC) { 118 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, 119 PCI_EXP_SLTSTA_CC); 120 return 1; 121 } 122 if (timeout < 0) 123 break; 124 msleep(10); 125 timeout -= 10; 126 } 127 return 0; /* timeout */ 128 } 129 130 static void pcie_wait_cmd(struct controller *ctrl) 131 { 132 unsigned int msecs = pciehp_poll_mode ? 2500 : 1000; 133 unsigned long duration = msecs_to_jiffies(msecs); 134 unsigned long cmd_timeout = ctrl->cmd_started + duration; 135 unsigned long now, timeout; 136 int rc; 137 138 /* 139 * If the controller does not generate notifications for command 140 * completions, we never need to wait between writes. 141 */ 142 if (NO_CMD_CMPL(ctrl)) 143 return; 144 145 if (!ctrl->cmd_busy) 146 return; 147 148 /* 149 * Even if the command has already timed out, we want to call 150 * pcie_poll_cmd() so it can clear PCI_EXP_SLTSTA_CC. 151 */ 152 now = jiffies; 153 if (time_before_eq(cmd_timeout, now)) 154 timeout = 1; 155 else 156 timeout = cmd_timeout - now; 157 158 if (ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE && 159 ctrl->slot_ctrl & PCI_EXP_SLTCTL_CCIE) 160 rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout); 161 else 162 rc = pcie_poll_cmd(ctrl, jiffies_to_msecs(timeout)); 163 164 /* 165 * Controllers with errata like Intel CF118 don't generate 166 * completion notifications unless the power/indicator/interlock 167 * control bits are changed. On such controllers, we'll emit this 168 * timeout message when we wait for completion of commands that 169 * don't change those bits, e.g., commands that merely enable 170 * interrupts. 171 */ 172 if (!rc) 173 ctrl_info(ctrl, "Timeout on hotplug command %#06x (issued %u msec ago)\n", 174 ctrl->slot_ctrl, 175 jiffies_to_msecs(jiffies - ctrl->cmd_started)); 176 } 177 178 static void pcie_do_write_cmd(struct controller *ctrl, u16 cmd, 179 u16 mask, bool wait) 180 { 181 struct pci_dev *pdev = ctrl_dev(ctrl); 182 u16 slot_ctrl; 183 184 mutex_lock(&ctrl->ctrl_lock); 185 186 /* 187 * Always wait for any previous command that might still be in progress 188 */ 189 pcie_wait_cmd(ctrl); 190 191 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl); 192 if (slot_ctrl == (u16) ~0) { 193 ctrl_info(ctrl, "%s: no response from device\n", __func__); 194 goto out; 195 } 196 197 slot_ctrl &= ~mask; 198 slot_ctrl |= (cmd & mask); 199 ctrl->cmd_busy = 1; 200 smp_mb(); 201 pcie_capability_write_word(pdev, PCI_EXP_SLTCTL, slot_ctrl); 202 ctrl->cmd_started = jiffies; 203 ctrl->slot_ctrl = slot_ctrl; 204 205 /* 206 * Optionally wait for the hardware to be ready for a new command, 207 * indicating completion of the above issued command. 208 */ 209 if (wait) 210 pcie_wait_cmd(ctrl); 211 212 out: 213 mutex_unlock(&ctrl->ctrl_lock); 214 } 215 216 /** 217 * pcie_write_cmd - Issue controller command 218 * @ctrl: controller to which the command is issued 219 * @cmd: command value written to slot control register 220 * @mask: bitmask of slot control register to be modified 221 */ 222 static void pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask) 223 { 224 pcie_do_write_cmd(ctrl, cmd, mask, true); 225 } 226 227 /* Same as above without waiting for the hardware to latch */ 228 static void pcie_write_cmd_nowait(struct controller *ctrl, u16 cmd, u16 mask) 229 { 230 pcie_do_write_cmd(ctrl, cmd, mask, false); 231 } 232 233 bool pciehp_check_link_active(struct controller *ctrl) 234 { 235 struct pci_dev *pdev = ctrl_dev(ctrl); 236 u16 lnk_status; 237 bool ret; 238 239 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status); 240 ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA); 241 242 if (ret) 243 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status); 244 245 return ret; 246 } 247 248 static void __pcie_wait_link_active(struct controller *ctrl, bool active) 249 { 250 int timeout = 1000; 251 252 if (pciehp_check_link_active(ctrl) == active) 253 return; 254 while (timeout > 0) { 255 msleep(10); 256 timeout -= 10; 257 if (pciehp_check_link_active(ctrl) == active) 258 return; 259 } 260 ctrl_dbg(ctrl, "Data Link Layer Link Active not %s in 1000 msec\n", 261 active ? "set" : "cleared"); 262 } 263 264 static void pcie_wait_link_active(struct controller *ctrl) 265 { 266 __pcie_wait_link_active(ctrl, true); 267 } 268 269 static bool pci_bus_check_dev(struct pci_bus *bus, int devfn) 270 { 271 u32 l; 272 int count = 0; 273 int delay = 1000, step = 20; 274 bool found = false; 275 276 do { 277 found = pci_bus_read_dev_vendor_id(bus, devfn, &l, 0); 278 count++; 279 280 if (found) 281 break; 282 283 msleep(step); 284 delay -= step; 285 } while (delay > 0); 286 287 if (count > 1 && pciehp_debug) 288 printk(KERN_DEBUG "pci %04x:%02x:%02x.%d id reading try %d times with interval %d ms to get %08x\n", 289 pci_domain_nr(bus), bus->number, PCI_SLOT(devfn), 290 PCI_FUNC(devfn), count, step, l); 291 292 return found; 293 } 294 295 int pciehp_check_link_status(struct controller *ctrl) 296 { 297 struct pci_dev *pdev = ctrl_dev(ctrl); 298 bool found; 299 u16 lnk_status; 300 301 /* 302 * Data Link Layer Link Active Reporting must be capable for 303 * hot-plug capable downstream port. But old controller might 304 * not implement it. In this case, we wait for 1000 ms. 305 */ 306 if (ctrl->link_active_reporting) 307 pcie_wait_link_active(ctrl); 308 else 309 msleep(1000); 310 311 /* wait 100ms before read pci conf, and try in 1s */ 312 msleep(100); 313 found = pci_bus_check_dev(ctrl->pcie->port->subordinate, 314 PCI_DEVFN(0, 0)); 315 316 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status); 317 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status); 318 if ((lnk_status & PCI_EXP_LNKSTA_LT) || 319 !(lnk_status & PCI_EXP_LNKSTA_NLW)) { 320 ctrl_err(ctrl, "link training error: status %#06x\n", 321 lnk_status); 322 return -1; 323 } 324 325 pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status); 326 327 if (!found) 328 return -1; 329 330 return 0; 331 } 332 333 static int __pciehp_link_set(struct controller *ctrl, bool enable) 334 { 335 struct pci_dev *pdev = ctrl_dev(ctrl); 336 u16 lnk_ctrl; 337 338 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &lnk_ctrl); 339 340 if (enable) 341 lnk_ctrl &= ~PCI_EXP_LNKCTL_LD; 342 else 343 lnk_ctrl |= PCI_EXP_LNKCTL_LD; 344 345 pcie_capability_write_word(pdev, PCI_EXP_LNKCTL, lnk_ctrl); 346 ctrl_dbg(ctrl, "%s: lnk_ctrl = %x\n", __func__, lnk_ctrl); 347 return 0; 348 } 349 350 static int pciehp_link_enable(struct controller *ctrl) 351 { 352 return __pciehp_link_set(ctrl, true); 353 } 354 355 int pciehp_get_raw_indicator_status(struct hotplug_slot *hotplug_slot, 356 u8 *status) 357 { 358 struct slot *slot = hotplug_slot->private; 359 struct pci_dev *pdev = ctrl_dev(slot->ctrl); 360 u16 slot_ctrl; 361 362 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl); 363 *status = (slot_ctrl & (PCI_EXP_SLTCTL_AIC | PCI_EXP_SLTCTL_PIC)) >> 6; 364 return 0; 365 } 366 367 void pciehp_get_attention_status(struct slot *slot, u8 *status) 368 { 369 struct controller *ctrl = slot->ctrl; 370 struct pci_dev *pdev = ctrl_dev(ctrl); 371 u16 slot_ctrl; 372 373 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl); 374 ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__, 375 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl); 376 377 switch (slot_ctrl & PCI_EXP_SLTCTL_AIC) { 378 case PCI_EXP_SLTCTL_ATTN_IND_ON: 379 *status = 1; /* On */ 380 break; 381 case PCI_EXP_SLTCTL_ATTN_IND_BLINK: 382 *status = 2; /* Blink */ 383 break; 384 case PCI_EXP_SLTCTL_ATTN_IND_OFF: 385 *status = 0; /* Off */ 386 break; 387 default: 388 *status = 0xFF; 389 break; 390 } 391 } 392 393 void pciehp_get_power_status(struct slot *slot, u8 *status) 394 { 395 struct controller *ctrl = slot->ctrl; 396 struct pci_dev *pdev = ctrl_dev(ctrl); 397 u16 slot_ctrl; 398 399 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl); 400 ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__, 401 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl); 402 403 switch (slot_ctrl & PCI_EXP_SLTCTL_PCC) { 404 case PCI_EXP_SLTCTL_PWR_ON: 405 *status = 1; /* On */ 406 break; 407 case PCI_EXP_SLTCTL_PWR_OFF: 408 *status = 0; /* Off */ 409 break; 410 default: 411 *status = 0xFF; 412 break; 413 } 414 } 415 416 void pciehp_get_latch_status(struct slot *slot, u8 *status) 417 { 418 struct pci_dev *pdev = ctrl_dev(slot->ctrl); 419 u16 slot_status; 420 421 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); 422 *status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS); 423 } 424 425 void pciehp_get_adapter_status(struct slot *slot, u8 *status) 426 { 427 struct pci_dev *pdev = ctrl_dev(slot->ctrl); 428 u16 slot_status; 429 430 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); 431 *status = !!(slot_status & PCI_EXP_SLTSTA_PDS); 432 } 433 434 int pciehp_query_power_fault(struct slot *slot) 435 { 436 struct pci_dev *pdev = ctrl_dev(slot->ctrl); 437 u16 slot_status; 438 439 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); 440 return !!(slot_status & PCI_EXP_SLTSTA_PFD); 441 } 442 443 int pciehp_set_raw_indicator_status(struct hotplug_slot *hotplug_slot, 444 u8 status) 445 { 446 struct slot *slot = hotplug_slot->private; 447 struct controller *ctrl = slot->ctrl; 448 449 pcie_write_cmd_nowait(ctrl, status << 6, 450 PCI_EXP_SLTCTL_AIC | PCI_EXP_SLTCTL_PIC); 451 return 0; 452 } 453 454 void pciehp_set_attention_status(struct slot *slot, u8 value) 455 { 456 struct controller *ctrl = slot->ctrl; 457 u16 slot_cmd; 458 459 if (!ATTN_LED(ctrl)) 460 return; 461 462 switch (value) { 463 case 0: /* turn off */ 464 slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_OFF; 465 break; 466 case 1: /* turn on */ 467 slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_ON; 468 break; 469 case 2: /* turn blink */ 470 slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_BLINK; 471 break; 472 default: 473 return; 474 } 475 pcie_write_cmd_nowait(ctrl, slot_cmd, PCI_EXP_SLTCTL_AIC); 476 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 477 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); 478 } 479 480 void pciehp_green_led_on(struct slot *slot) 481 { 482 struct controller *ctrl = slot->ctrl; 483 484 if (!PWR_LED(ctrl)) 485 return; 486 487 pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_ON, 488 PCI_EXP_SLTCTL_PIC); 489 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 490 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 491 PCI_EXP_SLTCTL_PWR_IND_ON); 492 } 493 494 void pciehp_green_led_off(struct slot *slot) 495 { 496 struct controller *ctrl = slot->ctrl; 497 498 if (!PWR_LED(ctrl)) 499 return; 500 501 pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_OFF, 502 PCI_EXP_SLTCTL_PIC); 503 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 504 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 505 PCI_EXP_SLTCTL_PWR_IND_OFF); 506 } 507 508 void pciehp_green_led_blink(struct slot *slot) 509 { 510 struct controller *ctrl = slot->ctrl; 511 512 if (!PWR_LED(ctrl)) 513 return; 514 515 pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_BLINK, 516 PCI_EXP_SLTCTL_PIC); 517 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 518 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 519 PCI_EXP_SLTCTL_PWR_IND_BLINK); 520 } 521 522 int pciehp_power_on_slot(struct slot *slot) 523 { 524 struct controller *ctrl = slot->ctrl; 525 struct pci_dev *pdev = ctrl_dev(ctrl); 526 u16 slot_status; 527 int retval; 528 529 /* Clear sticky power-fault bit from previous power failures */ 530 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); 531 if (slot_status & PCI_EXP_SLTSTA_PFD) 532 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, 533 PCI_EXP_SLTSTA_PFD); 534 ctrl->power_fault_detected = 0; 535 536 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_ON, PCI_EXP_SLTCTL_PCC); 537 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 538 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 539 PCI_EXP_SLTCTL_PWR_ON); 540 541 retval = pciehp_link_enable(ctrl); 542 if (retval) 543 ctrl_err(ctrl, "%s: Can not enable the link!\n", __func__); 544 545 return retval; 546 } 547 548 void pciehp_power_off_slot(struct slot *slot) 549 { 550 struct controller *ctrl = slot->ctrl; 551 552 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_OFF, PCI_EXP_SLTCTL_PCC); 553 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 554 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 555 PCI_EXP_SLTCTL_PWR_OFF); 556 } 557 558 static irqreturn_t pciehp_isr(int irq, void *dev_id) 559 { 560 struct controller *ctrl = (struct controller *)dev_id; 561 struct pci_dev *pdev = ctrl_dev(ctrl); 562 struct pci_bus *subordinate = pdev->subordinate; 563 struct pci_dev *dev; 564 struct slot *slot = ctrl->slot; 565 u16 status, events; 566 u8 present; 567 bool link; 568 569 /* Interrupts cannot originate from a controller that's asleep */ 570 if (pdev->current_state == PCI_D3cold) 571 return IRQ_NONE; 572 573 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &status); 574 if (status == (u16) ~0) { 575 ctrl_info(ctrl, "%s: no response from device\n", __func__); 576 return IRQ_NONE; 577 } 578 579 /* 580 * Slot Status contains plain status bits as well as event 581 * notification bits; right now we only want the event bits. 582 */ 583 events = status & (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD | 584 PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_CC | 585 PCI_EXP_SLTSTA_DLLSC); 586 587 /* 588 * If we've already reported a power fault, don't report it again 589 * until we've done something to handle it. 590 */ 591 if (ctrl->power_fault_detected) 592 events &= ~PCI_EXP_SLTSTA_PFD; 593 594 if (!events) 595 return IRQ_NONE; 596 597 /* Capture link status before clearing interrupts */ 598 if (events & PCI_EXP_SLTSTA_DLLSC) 599 link = pciehp_check_link_active(ctrl); 600 601 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, events); 602 ctrl_dbg(ctrl, "pending interrupts %#06x from Slot Status\n", events); 603 604 /* Check Command Complete Interrupt Pending */ 605 if (events & PCI_EXP_SLTSTA_CC) { 606 ctrl->cmd_busy = 0; 607 smp_mb(); 608 wake_up(&ctrl->queue); 609 } 610 611 if (subordinate) { 612 list_for_each_entry(dev, &subordinate->devices, bus_list) { 613 if (dev->ignore_hotplug) { 614 ctrl_dbg(ctrl, "ignoring hotplug event %#06x (%s requested no hotplug)\n", 615 events, pci_name(dev)); 616 return IRQ_HANDLED; 617 } 618 } 619 } 620 621 /* Check Attention Button Pressed */ 622 if (events & PCI_EXP_SLTSTA_ABP) { 623 ctrl_info(ctrl, "Slot(%s): Attention button pressed\n", 624 slot_name(slot)); 625 pciehp_queue_interrupt_event(slot, INT_BUTTON_PRESS); 626 } 627 628 /* 629 * Check Link Status Changed at higher precedence than Presence 630 * Detect Changed. The PDS value may be set to "card present" from 631 * out-of-band detection, which may be in conflict with a Link Down 632 * and cause the wrong event to queue. 633 */ 634 if (events & PCI_EXP_SLTSTA_DLLSC) { 635 ctrl_info(ctrl, "Slot(%s): Link %s\n", slot_name(slot), 636 link ? "Up" : "Down"); 637 pciehp_queue_interrupt_event(slot, link ? INT_LINK_UP : 638 INT_LINK_DOWN); 639 } else if (events & PCI_EXP_SLTSTA_PDC) { 640 present = !!(status & PCI_EXP_SLTSTA_PDS); 641 ctrl_info(ctrl, "Slot(%s): Card %spresent\n", slot_name(slot), 642 present ? "" : "not "); 643 pciehp_queue_interrupt_event(slot, present ? INT_PRESENCE_ON : 644 INT_PRESENCE_OFF); 645 } 646 647 /* Check Power Fault Detected */ 648 if ((events & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) { 649 ctrl->power_fault_detected = 1; 650 ctrl_err(ctrl, "Slot(%s): Power fault\n", slot_name(slot)); 651 pciehp_queue_interrupt_event(slot, INT_POWER_FAULT); 652 } 653 654 return IRQ_HANDLED; 655 } 656 657 static irqreturn_t pcie_isr(int irq, void *dev_id) 658 { 659 irqreturn_t rc, handled = IRQ_NONE; 660 661 /* 662 * To guarantee that all interrupt events are serviced, we need to 663 * re-inspect Slot Status register after clearing what is presumed 664 * to be the last pending interrupt. 665 */ 666 do { 667 rc = pciehp_isr(irq, dev_id); 668 if (rc == IRQ_HANDLED) 669 handled = IRQ_HANDLED; 670 } while (rc == IRQ_HANDLED); 671 672 /* Return IRQ_HANDLED if we handled one or more events */ 673 return handled; 674 } 675 676 void pcie_enable_notification(struct controller *ctrl) 677 { 678 u16 cmd, mask; 679 680 /* 681 * TBD: Power fault detected software notification support. 682 * 683 * Power fault detected software notification is not enabled 684 * now, because it caused power fault detected interrupt storm 685 * on some machines. On those machines, power fault detected 686 * bit in the slot status register was set again immediately 687 * when it is cleared in the interrupt service routine, and 688 * next power fault detected interrupt was notified again. 689 */ 690 691 /* 692 * Always enable link events: thus link-up and link-down shall 693 * always be treated as hotplug and unplug respectively. Enable 694 * presence detect only if Attention Button is not present. 695 */ 696 cmd = PCI_EXP_SLTCTL_DLLSCE; 697 if (ATTN_BUTTN(ctrl)) 698 cmd |= PCI_EXP_SLTCTL_ABPE; 699 else 700 cmd |= PCI_EXP_SLTCTL_PDCE; 701 if (!pciehp_poll_mode) 702 cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE; 703 704 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE | 705 PCI_EXP_SLTCTL_PFDE | 706 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE | 707 PCI_EXP_SLTCTL_DLLSCE); 708 709 pcie_write_cmd_nowait(ctrl, cmd, mask); 710 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 711 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, cmd); 712 } 713 714 static void pcie_disable_notification(struct controller *ctrl) 715 { 716 u16 mask; 717 718 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE | 719 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE | 720 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE | 721 PCI_EXP_SLTCTL_DLLSCE); 722 pcie_write_cmd(ctrl, 0, mask); 723 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 724 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0); 725 } 726 727 /* 728 * pciehp has a 1:1 bus:slot relationship so we ultimately want a secondary 729 * bus reset of the bridge, but at the same time we want to ensure that it is 730 * not seen as a hot-unplug, followed by the hot-plug of the device. Thus, 731 * disable link state notification and presence detection change notification 732 * momentarily, if we see that they could interfere. Also, clear any spurious 733 * events after. 734 */ 735 int pciehp_reset_slot(struct slot *slot, int probe) 736 { 737 struct controller *ctrl = slot->ctrl; 738 struct pci_dev *pdev = ctrl_dev(ctrl); 739 u16 stat_mask = 0, ctrl_mask = 0; 740 741 if (probe) 742 return 0; 743 744 if (!ATTN_BUTTN(ctrl)) { 745 ctrl_mask |= PCI_EXP_SLTCTL_PDCE; 746 stat_mask |= PCI_EXP_SLTSTA_PDC; 747 } 748 ctrl_mask |= PCI_EXP_SLTCTL_DLLSCE; 749 stat_mask |= PCI_EXP_SLTSTA_DLLSC; 750 751 pcie_write_cmd(ctrl, 0, ctrl_mask); 752 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 753 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0); 754 if (pciehp_poll_mode) 755 del_timer_sync(&ctrl->poll_timer); 756 757 pci_reset_bridge_secondary_bus(ctrl->pcie->port); 758 759 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, stat_mask); 760 pcie_write_cmd_nowait(ctrl, ctrl_mask, ctrl_mask); 761 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 762 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, ctrl_mask); 763 if (pciehp_poll_mode) 764 int_poll_timeout(&ctrl->poll_timer); 765 return 0; 766 } 767 768 int pcie_init_notification(struct controller *ctrl) 769 { 770 if (pciehp_request_irq(ctrl)) 771 return -1; 772 pcie_enable_notification(ctrl); 773 ctrl->notification_enabled = 1; 774 return 0; 775 } 776 777 static void pcie_shutdown_notification(struct controller *ctrl) 778 { 779 if (ctrl->notification_enabled) { 780 pcie_disable_notification(ctrl); 781 pciehp_free_irq(ctrl); 782 ctrl->notification_enabled = 0; 783 } 784 } 785 786 static int pcie_init_slot(struct controller *ctrl) 787 { 788 struct slot *slot; 789 790 slot = kzalloc(sizeof(*slot), GFP_KERNEL); 791 if (!slot) 792 return -ENOMEM; 793 794 slot->wq = alloc_ordered_workqueue("pciehp-%u", 0, PSN(ctrl)); 795 if (!slot->wq) 796 goto abort; 797 798 slot->ctrl = ctrl; 799 mutex_init(&slot->lock); 800 mutex_init(&slot->hotplug_lock); 801 INIT_DELAYED_WORK(&slot->work, pciehp_queue_pushbutton_work); 802 ctrl->slot = slot; 803 return 0; 804 abort: 805 kfree(slot); 806 return -ENOMEM; 807 } 808 809 static void pcie_cleanup_slot(struct controller *ctrl) 810 { 811 struct slot *slot = ctrl->slot; 812 cancel_delayed_work(&slot->work); 813 destroy_workqueue(slot->wq); 814 kfree(slot); 815 } 816 817 static inline void dbg_ctrl(struct controller *ctrl) 818 { 819 struct pci_dev *pdev = ctrl->pcie->port; 820 u16 reg16; 821 822 if (!pciehp_debug) 823 return; 824 825 ctrl_info(ctrl, "Slot Capabilities : 0x%08x\n", ctrl->slot_cap); 826 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, ®16); 827 ctrl_info(ctrl, "Slot Status : 0x%04x\n", reg16); 828 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, ®16); 829 ctrl_info(ctrl, "Slot Control : 0x%04x\n", reg16); 830 } 831 832 #define FLAG(x, y) (((x) & (y)) ? '+' : '-') 833 834 struct controller *pcie_init(struct pcie_device *dev) 835 { 836 struct controller *ctrl; 837 u32 slot_cap, link_cap; 838 struct pci_dev *pdev = dev->port; 839 840 ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL); 841 if (!ctrl) { 842 dev_err(&dev->device, "%s: Out of memory\n", __func__); 843 goto abort; 844 } 845 ctrl->pcie = dev; 846 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap); 847 848 if (pdev->hotplug_user_indicators) 849 slot_cap &= ~(PCI_EXP_SLTCAP_AIP | PCI_EXP_SLTCAP_PIP); 850 851 ctrl->slot_cap = slot_cap; 852 mutex_init(&ctrl->ctrl_lock); 853 init_waitqueue_head(&ctrl->queue); 854 dbg_ctrl(ctrl); 855 856 /* Check if Data Link Layer Link Active Reporting is implemented */ 857 pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &link_cap); 858 if (link_cap & PCI_EXP_LNKCAP_DLLLARC) 859 ctrl->link_active_reporting = 1; 860 861 /* 862 * Clear all remaining event bits in Slot Status register except 863 * Presence Detect Changed. We want to make sure possible 864 * hotplug event is triggered when the interrupt is unmasked so 865 * that we don't lose that event. 866 */ 867 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, 868 PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD | 869 PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_CC | 870 PCI_EXP_SLTSTA_DLLSC); 871 872 ctrl_info(ctrl, "Slot #%d AttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surprise%c Interlock%c NoCompl%c LLActRep%c\n", 873 (slot_cap & PCI_EXP_SLTCAP_PSN) >> 19, 874 FLAG(slot_cap, PCI_EXP_SLTCAP_ABP), 875 FLAG(slot_cap, PCI_EXP_SLTCAP_PCP), 876 FLAG(slot_cap, PCI_EXP_SLTCAP_MRLSP), 877 FLAG(slot_cap, PCI_EXP_SLTCAP_AIP), 878 FLAG(slot_cap, PCI_EXP_SLTCAP_PIP), 879 FLAG(slot_cap, PCI_EXP_SLTCAP_HPC), 880 FLAG(slot_cap, PCI_EXP_SLTCAP_HPS), 881 FLAG(slot_cap, PCI_EXP_SLTCAP_EIP), 882 FLAG(slot_cap, PCI_EXP_SLTCAP_NCCS), 883 FLAG(link_cap, PCI_EXP_LNKCAP_DLLLARC)); 884 885 if (pcie_init_slot(ctrl)) 886 goto abort_ctrl; 887 888 return ctrl; 889 890 abort_ctrl: 891 kfree(ctrl); 892 abort: 893 return NULL; 894 } 895 896 void pciehp_release_ctrl(struct controller *ctrl) 897 { 898 pcie_shutdown_notification(ctrl); 899 pcie_cleanup_slot(ctrl); 900 kfree(ctrl); 901 } 902