1 /* 2 * PCI Express PCI Hot Plug Driver 3 * 4 * Copyright (C) 1995,2001 Compaq Computer Corporation 5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com) 6 * Copyright (C) 2001 IBM Corp. 7 * Copyright (C) 2003-2004 Intel Corporation 8 * 9 * All rights reserved. 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or (at 14 * your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 19 * NON INFRINGEMENT. See the GNU General Public License for more 20 * details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 25 * 26 * Send feedback to <greg@kroah.com>,<dely.l.sy@intel.com> 27 * 28 */ 29 30 #include <linux/config.h> 31 #include <linux/kernel.h> 32 #include <linux/module.h> 33 #include <linux/types.h> 34 #include <linux/slab.h> 35 #include <linux/vmalloc.h> 36 #include <linux/interrupt.h> 37 #include <linux/spinlock.h> 38 #include <linux/pci.h> 39 #include <asm/system.h> 40 #include "../pci.h" 41 #include "pciehp.h" 42 43 #ifdef DEBUG 44 #define DBG_K_TRACE_ENTRY ((unsigned int)0x00000001) /* On function entry */ 45 #define DBG_K_TRACE_EXIT ((unsigned int)0x00000002) /* On function exit */ 46 #define DBG_K_INFO ((unsigned int)0x00000004) /* Info messages */ 47 #define DBG_K_ERROR ((unsigned int)0x00000008) /* Error messages */ 48 #define DBG_K_TRACE (DBG_K_TRACE_ENTRY|DBG_K_TRACE_EXIT) 49 #define DBG_K_STANDARD (DBG_K_INFO|DBG_K_ERROR|DBG_K_TRACE) 50 /* Redefine this flagword to set debug level */ 51 #define DEBUG_LEVEL DBG_K_STANDARD 52 53 #define DEFINE_DBG_BUFFER char __dbg_str_buf[256]; 54 55 #define DBG_PRINT( dbg_flags, args... ) \ 56 do { \ 57 if ( DEBUG_LEVEL & ( dbg_flags ) ) \ 58 { \ 59 int len; \ 60 len = sprintf( __dbg_str_buf, "%s:%d: %s: ", \ 61 __FILE__, __LINE__, __FUNCTION__ ); \ 62 sprintf( __dbg_str_buf + len, args ); \ 63 printk( KERN_NOTICE "%s\n", __dbg_str_buf ); \ 64 } \ 65 } while (0) 66 67 #define DBG_ENTER_ROUTINE DBG_PRINT (DBG_K_TRACE_ENTRY, "%s", "[Entry]"); 68 #define DBG_LEAVE_ROUTINE DBG_PRINT (DBG_K_TRACE_EXIT, "%s", "[Exit]"); 69 #else 70 #define DEFINE_DBG_BUFFER 71 #define DBG_ENTER_ROUTINE 72 #define DBG_LEAVE_ROUTINE 73 #endif /* DEBUG */ 74 75 struct ctrl_reg { 76 u8 cap_id; 77 u8 nxt_ptr; 78 u16 cap_reg; 79 u32 dev_cap; 80 u16 dev_ctrl; 81 u16 dev_status; 82 u32 lnk_cap; 83 u16 lnk_ctrl; 84 u16 lnk_status; 85 u32 slot_cap; 86 u16 slot_ctrl; 87 u16 slot_status; 88 u16 root_ctrl; 89 u16 rsvp; 90 u32 root_status; 91 } __attribute__ ((packed)); 92 93 /* offsets to the controller registers based on the above structure layout */ 94 enum ctrl_offsets { 95 PCIECAPID = offsetof(struct ctrl_reg, cap_id), 96 NXTCAPPTR = offsetof(struct ctrl_reg, nxt_ptr), 97 CAPREG = offsetof(struct ctrl_reg, cap_reg), 98 DEVCAP = offsetof(struct ctrl_reg, dev_cap), 99 DEVCTRL = offsetof(struct ctrl_reg, dev_ctrl), 100 DEVSTATUS = offsetof(struct ctrl_reg, dev_status), 101 LNKCAP = offsetof(struct ctrl_reg, lnk_cap), 102 LNKCTRL = offsetof(struct ctrl_reg, lnk_ctrl), 103 LNKSTATUS = offsetof(struct ctrl_reg, lnk_status), 104 SLOTCAP = offsetof(struct ctrl_reg, slot_cap), 105 SLOTCTRL = offsetof(struct ctrl_reg, slot_ctrl), 106 SLOTSTATUS = offsetof(struct ctrl_reg, slot_status), 107 ROOTCTRL = offsetof(struct ctrl_reg, root_ctrl), 108 ROOTSTATUS = offsetof(struct ctrl_reg, root_status), 109 }; 110 static int pcie_cap_base = 0; /* Base of the PCI Express capability item structure */ 111 112 #define PCIE_CAP_ID ( pcie_cap_base + PCIECAPID ) 113 #define NXT_CAP_PTR ( pcie_cap_base + NXTCAPPTR ) 114 #define CAP_REG ( pcie_cap_base + CAPREG ) 115 #define DEV_CAP ( pcie_cap_base + DEVCAP ) 116 #define DEV_CTRL ( pcie_cap_base + DEVCTRL ) 117 #define DEV_STATUS ( pcie_cap_base + DEVSTATUS ) 118 #define LNK_CAP ( pcie_cap_base + LNKCAP ) 119 #define LNK_CTRL ( pcie_cap_base + LNKCTRL ) 120 #define LNK_STATUS ( pcie_cap_base + LNKSTATUS ) 121 #define SLOT_CAP ( pcie_cap_base + SLOTCAP ) 122 #define SLOT_CTRL ( pcie_cap_base + SLOTCTRL ) 123 #define SLOT_STATUS ( pcie_cap_base + SLOTSTATUS ) 124 #define ROOT_CTRL ( pcie_cap_base + ROOTCTRL ) 125 #define ROOT_STATUS ( pcie_cap_base + ROOTSTATUS ) 126 127 #define hp_register_read_word(pdev, reg , value) \ 128 pci_read_config_word(pdev, reg, &value) 129 130 #define hp_register_read_dword(pdev, reg , value) \ 131 pci_read_config_dword(pdev, reg, &value) 132 133 #define hp_register_write_word(pdev, reg , value) \ 134 pci_write_config_word(pdev, reg, value) 135 136 #define hp_register_dwrite_word(pdev, reg , value) \ 137 pci_write_config_dword(pdev, reg, value) 138 139 /* Field definitions in PCI Express Capabilities Register */ 140 #define CAP_VER 0x000F 141 #define DEV_PORT_TYPE 0x00F0 142 #define SLOT_IMPL 0x0100 143 #define MSG_NUM 0x3E00 144 145 /* Device or Port Type */ 146 #define NAT_ENDPT 0x00 147 #define LEG_ENDPT 0x01 148 #define ROOT_PORT 0x04 149 #define UP_STREAM 0x05 150 #define DN_STREAM 0x06 151 #define PCIE_PCI_BRDG 0x07 152 #define PCI_PCIE_BRDG 0x10 153 154 /* Field definitions in Device Capabilities Register */ 155 #define DATTN_BUTTN_PRSN 0x1000 156 #define DATTN_LED_PRSN 0x2000 157 #define DPWR_LED_PRSN 0x4000 158 159 /* Field definitions in Link Capabilities Register */ 160 #define MAX_LNK_SPEED 0x000F 161 #define MAX_LNK_WIDTH 0x03F0 162 163 /* Link Width Encoding */ 164 #define LNK_X1 0x01 165 #define LNK_X2 0x02 166 #define LNK_X4 0x04 167 #define LNK_X8 0x08 168 #define LNK_X12 0x0C 169 #define LNK_X16 0x10 170 #define LNK_X32 0x20 171 172 /*Field definitions of Link Status Register */ 173 #define LNK_SPEED 0x000F 174 #define NEG_LINK_WD 0x03F0 175 #define LNK_TRN_ERR 0x0400 176 #define LNK_TRN 0x0800 177 #define SLOT_CLK_CONF 0x1000 178 179 /* Field definitions in Slot Capabilities Register */ 180 #define ATTN_BUTTN_PRSN 0x00000001 181 #define PWR_CTRL_PRSN 0x00000002 182 #define MRL_SENS_PRSN 0x00000004 183 #define ATTN_LED_PRSN 0x00000008 184 #define PWR_LED_PRSN 0x00000010 185 #define HP_SUPR_RM_SUP 0x00000020 186 #define HP_CAP 0x00000040 187 #define SLOT_PWR_VALUE 0x000003F8 188 #define SLOT_PWR_LIMIT 0x00000C00 189 #define PSN 0xFFF80000 /* PSN: Physical Slot Number */ 190 191 /* Field definitions in Slot Control Register */ 192 #define ATTN_BUTTN_ENABLE 0x0001 193 #define PWR_FAULT_DETECT_ENABLE 0x0002 194 #define MRL_DETECT_ENABLE 0x0004 195 #define PRSN_DETECT_ENABLE 0x0008 196 #define CMD_CMPL_INTR_ENABLE 0x0010 197 #define HP_INTR_ENABLE 0x0020 198 #define ATTN_LED_CTRL 0x00C0 199 #define PWR_LED_CTRL 0x0300 200 #define PWR_CTRL 0x0400 201 202 /* Attention indicator and Power indicator states */ 203 #define LED_ON 0x01 204 #define LED_BLINK 0x10 205 #define LED_OFF 0x11 206 207 /* Power Control Command */ 208 #define POWER_ON 0 209 #define POWER_OFF 0x0400 210 211 /* Field definitions in Slot Status Register */ 212 #define ATTN_BUTTN_PRESSED 0x0001 213 #define PWR_FAULT_DETECTED 0x0002 214 #define MRL_SENS_CHANGED 0x0004 215 #define PRSN_DETECT_CHANGED 0x0008 216 #define CMD_COMPLETED 0x0010 217 #define MRL_STATE 0x0020 218 #define PRSN_STATE 0x0040 219 220 struct php_ctlr_state_s { 221 struct php_ctlr_state_s *pnext; 222 struct pci_dev *pci_dev; 223 unsigned int irq; 224 unsigned long flags; /* spinlock's */ 225 u32 slot_device_offset; 226 u32 num_slots; 227 struct timer_list int_poll_timer; /* Added for poll event */ 228 php_intr_callback_t attention_button_callback; 229 php_intr_callback_t switch_change_callback; 230 php_intr_callback_t presence_change_callback; 231 php_intr_callback_t power_fault_callback; 232 void *callback_instance_id; 233 struct ctrl_reg *creg; /* Ptr to controller register space */ 234 }; 235 236 237 static spinlock_t hpc_event_lock; 238 239 DEFINE_DBG_BUFFER /* Debug string buffer for entire HPC defined here */ 240 static struct php_ctlr_state_s *php_ctlr_list_head; /* HPC state linked list */ 241 static int ctlr_seq_num = 0; /* Controller sequence # */ 242 static spinlock_t list_lock; 243 244 static irqreturn_t pcie_isr(int IRQ, void *dev_id, struct pt_regs *regs); 245 246 static void start_int_poll_timer(struct php_ctlr_state_s *php_ctlr, int seconds); 247 248 /* This is the interrupt polling timeout function. */ 249 static void int_poll_timeout(unsigned long lphp_ctlr) 250 { 251 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *)lphp_ctlr; 252 253 DBG_ENTER_ROUTINE 254 255 if ( !php_ctlr ) { 256 err("%s: Invalid HPC controller handle!\n", __FUNCTION__); 257 return; 258 } 259 260 /* Poll for interrupt events. regs == NULL => polling */ 261 pcie_isr( 0, (void *)php_ctlr, NULL ); 262 263 init_timer(&php_ctlr->int_poll_timer); 264 265 if (!pciehp_poll_time) 266 pciehp_poll_time = 2; /* reset timer to poll in 2 secs if user doesn't specify at module installation*/ 267 268 start_int_poll_timer(php_ctlr, pciehp_poll_time); 269 270 return; 271 } 272 273 /* This function starts the interrupt polling timer. */ 274 static void start_int_poll_timer(struct php_ctlr_state_s *php_ctlr, int seconds) 275 { 276 if (!php_ctlr) { 277 err("%s: Invalid HPC controller handle!\n", __FUNCTION__); 278 return; 279 } 280 281 if ( ( seconds <= 0 ) || ( seconds > 60 ) ) 282 seconds = 2; /* Clamp to sane value */ 283 284 php_ctlr->int_poll_timer.function = &int_poll_timeout; 285 php_ctlr->int_poll_timer.data = (unsigned long)php_ctlr; /* Instance data */ 286 php_ctlr->int_poll_timer.expires = jiffies + seconds * HZ; 287 add_timer(&php_ctlr->int_poll_timer); 288 289 return; 290 } 291 292 static int pcie_write_cmd(struct slot *slot, u16 cmd) 293 { 294 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; 295 int retval = 0; 296 u16 slot_status; 297 298 DBG_ENTER_ROUTINE 299 300 dbg("%s : Enter\n", __FUNCTION__); 301 if (!php_ctlr) { 302 err("%s: Invalid HPC controller handle!\n", __FUNCTION__); 303 return -1; 304 } 305 306 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS, slot_status); 307 if (retval) { 308 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__); 309 return retval; 310 } 311 dbg("%s : hp_register_read_word SLOT_STATUS %x\n", __FUNCTION__, slot_status); 312 313 if ((slot_status & CMD_COMPLETED) == CMD_COMPLETED ) { 314 /* After 1 sec and CMD_COMPLETED still not set, just proceed forward to issue 315 the next command according to spec. Just print out the error message */ 316 dbg("%s : CMD_COMPLETED not clear after 1 sec.\n", __FUNCTION__); 317 } 318 319 dbg("%s: Before hp_register_write_word SLOT_CTRL %x\n", __FUNCTION__, cmd); 320 retval = hp_register_write_word(php_ctlr->pci_dev, SLOT_CTRL, cmd | CMD_CMPL_INTR_ENABLE); 321 if (retval) { 322 err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__); 323 return retval; 324 } 325 dbg("%s : hp_register_write_word SLOT_CTRL %x\n", __FUNCTION__, cmd | CMD_CMPL_INTR_ENABLE); 326 dbg("%s : Exit\n", __FUNCTION__); 327 328 DBG_LEAVE_ROUTINE 329 return retval; 330 } 331 332 static int hpc_check_lnk_status(struct controller *ctrl) 333 { 334 struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle; 335 u16 lnk_status; 336 int retval = 0; 337 338 DBG_ENTER_ROUTINE 339 340 if (!php_ctlr) { 341 err("%s: Invalid HPC controller handle!\n", __FUNCTION__); 342 return -1; 343 } 344 345 retval = hp_register_read_word(php_ctlr->pci_dev, LNK_STATUS, lnk_status); 346 347 if (retval) { 348 err("%s : hp_register_read_word LNK_STATUS failed\n", __FUNCTION__); 349 return retval; 350 } 351 352 dbg("%s: lnk_status = %x\n", __FUNCTION__, lnk_status); 353 if ( (lnk_status & LNK_TRN) || (lnk_status & LNK_TRN_ERR) || 354 !(lnk_status & NEG_LINK_WD)) { 355 err("%s : Link Training Error occurs \n", __FUNCTION__); 356 retval = -1; 357 return retval; 358 } 359 360 DBG_LEAVE_ROUTINE 361 return retval; 362 } 363 364 365 static int hpc_get_attention_status(struct slot *slot, u8 *status) 366 { 367 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; 368 u16 slot_ctrl; 369 u8 atten_led_state; 370 int retval = 0; 371 372 DBG_ENTER_ROUTINE 373 374 if (!php_ctlr) { 375 err("%s: Invalid HPC controller handle!\n", __FUNCTION__); 376 return -1; 377 } 378 379 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL, slot_ctrl); 380 381 if (retval) { 382 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__); 383 return retval; 384 } 385 386 dbg("%s: SLOT_CTRL %x, value read %x\n", __FUNCTION__,SLOT_CTRL, slot_ctrl); 387 388 atten_led_state = (slot_ctrl & ATTN_LED_CTRL) >> 6; 389 390 switch (atten_led_state) { 391 case 0: 392 *status = 0xFF; /* Reserved */ 393 break; 394 case 1: 395 *status = 1; /* On */ 396 break; 397 case 2: 398 *status = 2; /* Blink */ 399 break; 400 case 3: 401 *status = 0; /* Off */ 402 break; 403 default: 404 *status = 0xFF; 405 break; 406 } 407 408 DBG_LEAVE_ROUTINE 409 return 0; 410 } 411 412 static int hpc_get_power_status(struct slot * slot, u8 *status) 413 { 414 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; 415 u16 slot_ctrl; 416 u8 pwr_state; 417 int retval = 0; 418 419 DBG_ENTER_ROUTINE 420 421 if (!php_ctlr) { 422 err("%s: Invalid HPC controller handle!\n", __FUNCTION__); 423 return -1; 424 } 425 426 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL, slot_ctrl); 427 428 if (retval) { 429 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__); 430 return retval; 431 } 432 dbg("%s: SLOT_CTRL %x value read %x\n", __FUNCTION__, SLOT_CTRL, slot_ctrl); 433 434 pwr_state = (slot_ctrl & PWR_CTRL) >> 10; 435 436 switch (pwr_state) { 437 case 0: 438 *status = 1; 439 break; 440 case 1: 441 *status = 0; 442 break; 443 default: 444 *status = 0xFF; 445 break; 446 } 447 448 DBG_LEAVE_ROUTINE 449 return retval; 450 } 451 452 453 static int hpc_get_latch_status(struct slot *slot, u8 *status) 454 { 455 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; 456 u16 slot_status; 457 int retval = 0; 458 459 DBG_ENTER_ROUTINE 460 461 if (!php_ctlr) { 462 err("%s: Invalid HPC controller handle!\n", __FUNCTION__); 463 return -1; 464 } 465 466 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS, slot_status); 467 468 if (retval) { 469 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__); 470 return retval; 471 } 472 473 *status = (((slot_status & MRL_STATE) >> 5) == 0) ? 0 : 1; 474 475 DBG_LEAVE_ROUTINE 476 return 0; 477 } 478 479 static int hpc_get_adapter_status(struct slot *slot, u8 *status) 480 { 481 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; 482 u16 slot_status; 483 u8 card_state; 484 int retval = 0; 485 486 DBG_ENTER_ROUTINE 487 488 if (!php_ctlr) { 489 err("%s: Invalid HPC controller handle!\n", __FUNCTION__); 490 return -1; 491 } 492 493 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS, slot_status); 494 495 if (retval) { 496 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__); 497 return retval; 498 } 499 card_state = (u8)((slot_status & PRSN_STATE) >> 6); 500 *status = (card_state == 1) ? 1 : 0; 501 502 DBG_LEAVE_ROUTINE 503 return 0; 504 } 505 506 static int hpc_query_power_fault(struct slot * slot) 507 { 508 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; 509 u16 slot_status; 510 u8 pwr_fault; 511 int retval = 0; 512 u8 status; 513 514 DBG_ENTER_ROUTINE 515 516 if (!php_ctlr) { 517 err("%s: Invalid HPC controller handle!\n", __FUNCTION__); 518 return -1; 519 } 520 521 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS, slot_status); 522 523 if (retval) { 524 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__); 525 return retval; 526 } 527 pwr_fault = (u8)((slot_status & PWR_FAULT_DETECTED) >> 1); 528 status = (pwr_fault != 1) ? 1 : 0; 529 530 DBG_LEAVE_ROUTINE 531 /* Note: Logic 0 => fault */ 532 return status; 533 } 534 535 static int hpc_set_attention_status(struct slot *slot, u8 value) 536 { 537 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; 538 u16 slot_cmd = 0; 539 u16 slot_ctrl; 540 int rc = 0; 541 542 dbg("%s: \n", __FUNCTION__); 543 if (!php_ctlr) { 544 err("%s: Invalid HPC controller handle!\n", __FUNCTION__); 545 return -1; 546 } 547 548 if (slot->hp_slot >= php_ctlr->num_slots) { 549 err("%s: Invalid HPC slot number!\n", __FUNCTION__); 550 return -1; 551 } 552 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL, slot_ctrl); 553 554 if (rc) { 555 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__); 556 return rc; 557 } 558 dbg("%s : hp_register_read_word SLOT_CTRL %x\n", __FUNCTION__, slot_ctrl); 559 560 switch (value) { 561 case 0 : /* turn off */ 562 slot_cmd = (slot_ctrl & ~ATTN_LED_CTRL) | 0x00C0; 563 break; 564 case 1: /* turn on */ 565 slot_cmd = (slot_ctrl & ~ATTN_LED_CTRL) | 0x0040; 566 break; 567 case 2: /* turn blink */ 568 slot_cmd = (slot_ctrl & ~ATTN_LED_CTRL) | 0x0080; 569 break; 570 default: 571 return -1; 572 } 573 if (!pciehp_poll_mode) 574 slot_cmd = slot_cmd | HP_INTR_ENABLE; 575 576 pcie_write_cmd(slot, slot_cmd); 577 dbg("%s: SLOT_CTRL %x write cmd %x\n", __FUNCTION__, SLOT_CTRL, slot_cmd); 578 579 return rc; 580 } 581 582 583 static void hpc_set_green_led_on(struct slot *slot) 584 { 585 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; 586 u16 slot_cmd; 587 u16 slot_ctrl; 588 int rc = 0; 589 590 dbg("%s: \n", __FUNCTION__); 591 if (!php_ctlr) { 592 err("%s: Invalid HPC controller handle!\n", __FUNCTION__); 593 return ; 594 } 595 596 if (slot->hp_slot >= php_ctlr->num_slots) { 597 err("%s: Invalid HPC slot number!\n", __FUNCTION__); 598 return ; 599 } 600 601 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL, slot_ctrl); 602 603 if (rc) { 604 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__); 605 return; 606 } 607 dbg("%s : hp_register_read_word SLOT_CTRL %x\n", __FUNCTION__, slot_ctrl); 608 slot_cmd = (slot_ctrl & ~PWR_LED_CTRL) | 0x0100; 609 if (!pciehp_poll_mode) 610 slot_cmd = slot_cmd | HP_INTR_ENABLE; 611 612 pcie_write_cmd(slot, slot_cmd); 613 614 dbg("%s: SLOT_CTRL %x write cmd %x\n",__FUNCTION__, SLOT_CTRL, slot_cmd); 615 return; 616 } 617 618 static void hpc_set_green_led_off(struct slot *slot) 619 { 620 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; 621 u16 slot_cmd; 622 u16 slot_ctrl; 623 int rc = 0; 624 625 dbg("%s: \n", __FUNCTION__); 626 if (!php_ctlr) { 627 err("%s: Invalid HPC controller handle!\n", __FUNCTION__); 628 return ; 629 } 630 631 if (slot->hp_slot >= php_ctlr->num_slots) { 632 err("%s: Invalid HPC slot number!\n", __FUNCTION__); 633 return ; 634 } 635 636 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL, slot_ctrl); 637 638 if (rc) { 639 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__); 640 return; 641 } 642 dbg("%s : hp_register_read_word SLOT_CTRL %x\n", __FUNCTION__, slot_ctrl); 643 644 slot_cmd = (slot_ctrl & ~PWR_LED_CTRL) | 0x0300; 645 646 if (!pciehp_poll_mode) 647 slot_cmd = slot_cmd | HP_INTR_ENABLE; 648 pcie_write_cmd(slot, slot_cmd); 649 dbg("%s: SLOT_CTRL %x write cmd %x\n", __FUNCTION__, SLOT_CTRL, slot_cmd); 650 651 return; 652 } 653 654 static void hpc_set_green_led_blink(struct slot *slot) 655 { 656 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; 657 u16 slot_cmd; 658 u16 slot_ctrl; 659 int rc = 0; 660 661 dbg("%s: \n", __FUNCTION__); 662 if (!php_ctlr) { 663 err("%s: Invalid HPC controller handle!\n", __FUNCTION__); 664 return ; 665 } 666 667 if (slot->hp_slot >= php_ctlr->num_slots) { 668 err("%s: Invalid HPC slot number!\n", __FUNCTION__); 669 return ; 670 } 671 672 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL, slot_ctrl); 673 674 if (rc) { 675 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__); 676 return; 677 } 678 dbg("%s : hp_register_read_word SLOT_CTRL %x\n", __FUNCTION__, slot_ctrl); 679 680 slot_cmd = (slot_ctrl & ~PWR_LED_CTRL) | 0x0200; 681 682 if (!pciehp_poll_mode) 683 slot_cmd = slot_cmd | HP_INTR_ENABLE; 684 pcie_write_cmd(slot, slot_cmd); 685 686 dbg("%s: SLOT_CTRL %x write cmd %x\n",__FUNCTION__, SLOT_CTRL, slot_cmd); 687 return; 688 } 689 690 int pcie_get_ctlr_slot_config(struct controller *ctrl, 691 int *num_ctlr_slots, /* number of slots in this HPC; only 1 in PCIE */ 692 int *first_device_num, /* PCI dev num of the first slot in this PCIE */ 693 int *physical_slot_num, /* phy slot num of the first slot in this PCIE */ 694 u8 *ctrlcap) 695 { 696 struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle; 697 u32 slot_cap; 698 int rc = 0; 699 700 DBG_ENTER_ROUTINE 701 702 if (!php_ctlr) { 703 err("%s: Invalid HPC controller handle!\n", __FUNCTION__); 704 return -1; 705 } 706 707 *first_device_num = 0; 708 *num_ctlr_slots = 1; 709 710 rc = hp_register_read_dword(php_ctlr->pci_dev, SLOT_CAP, slot_cap); 711 712 if (rc) { 713 err("%s : hp_register_read_dword SLOT_CAP failed\n", __FUNCTION__); 714 return -1; 715 } 716 717 *physical_slot_num = slot_cap >> 19; 718 dbg("%s: PSN %d \n", __FUNCTION__, *physical_slot_num); 719 720 *ctrlcap = slot_cap & 0x0000007f; 721 722 DBG_LEAVE_ROUTINE 723 return 0; 724 } 725 726 static void hpc_release_ctlr(struct controller *ctrl) 727 { 728 struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle; 729 struct php_ctlr_state_s *p, *p_prev; 730 731 DBG_ENTER_ROUTINE 732 733 if (!php_ctlr) { 734 err("%s: Invalid HPC controller handle!\n", __FUNCTION__); 735 return ; 736 } 737 738 if (pciehp_poll_mode) { 739 del_timer(&php_ctlr->int_poll_timer); 740 } else { 741 if (php_ctlr->irq) { 742 free_irq(php_ctlr->irq, ctrl); 743 php_ctlr->irq = 0; 744 if (!pcie_mch_quirk) 745 pci_disable_msi(php_ctlr->pci_dev); 746 } 747 } 748 if (php_ctlr->pci_dev) 749 php_ctlr->pci_dev = NULL; 750 751 spin_lock(&list_lock); 752 p = php_ctlr_list_head; 753 p_prev = NULL; 754 while (p) { 755 if (p == php_ctlr) { 756 if (p_prev) 757 p_prev->pnext = p->pnext; 758 else 759 php_ctlr_list_head = p->pnext; 760 break; 761 } else { 762 p_prev = p; 763 p = p->pnext; 764 } 765 } 766 spin_unlock(&list_lock); 767 768 kfree(php_ctlr); 769 770 DBG_LEAVE_ROUTINE 771 772 } 773 774 static int hpc_power_on_slot(struct slot * slot) 775 { 776 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; 777 u16 slot_cmd; 778 u16 slot_ctrl; 779 780 int retval = 0; 781 782 DBG_ENTER_ROUTINE 783 dbg("%s: \n", __FUNCTION__); 784 785 if (!php_ctlr) { 786 err("%s: Invalid HPC controller handle!\n", __FUNCTION__); 787 return -1; 788 } 789 790 dbg("%s: slot->hp_slot %x\n", __FUNCTION__, slot->hp_slot); 791 if (slot->hp_slot >= php_ctlr->num_slots) { 792 err("%s: Invalid HPC slot number!\n", __FUNCTION__); 793 return -1; 794 } 795 796 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL, slot_ctrl); 797 798 if (retval) { 799 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__); 800 return retval; 801 } 802 dbg("%s: SLOT_CTRL %x, value read %xn", __FUNCTION__, SLOT_CTRL, 803 slot_ctrl); 804 805 slot_cmd = (slot_ctrl & ~PWR_CTRL) | POWER_ON; 806 807 if (!pciehp_poll_mode) 808 slot_cmd = slot_cmd | HP_INTR_ENABLE; 809 810 retval = pcie_write_cmd(slot, slot_cmd); 811 812 if (retval) { 813 err("%s: Write %x command failed!\n", __FUNCTION__, slot_cmd); 814 return -1; 815 } 816 dbg("%s: SLOT_CTRL %x write cmd %x\n",__FUNCTION__, SLOT_CTRL, slot_cmd); 817 818 DBG_LEAVE_ROUTINE 819 820 return retval; 821 } 822 823 static int hpc_power_off_slot(struct slot * slot) 824 { 825 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; 826 u16 slot_cmd; 827 u16 slot_ctrl; 828 829 int retval = 0; 830 831 DBG_ENTER_ROUTINE 832 dbg("%s: \n", __FUNCTION__); 833 834 if (!php_ctlr) { 835 err("%s: Invalid HPC controller handle!\n", __FUNCTION__); 836 return -1; 837 } 838 839 dbg("%s: slot->hp_slot %x\n", __FUNCTION__, slot->hp_slot); 840 slot->hp_slot = 0; 841 if (slot->hp_slot >= php_ctlr->num_slots) { 842 err("%s: Invalid HPC slot number!\n", __FUNCTION__); 843 return -1; 844 } 845 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL, slot_ctrl); 846 847 if (retval) { 848 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__); 849 return retval; 850 } 851 dbg("%s: SLOT_CTRL %x, value read %x\n", __FUNCTION__, SLOT_CTRL, 852 slot_ctrl); 853 854 slot_cmd = (slot_ctrl & ~PWR_CTRL) | POWER_OFF; 855 856 if (!pciehp_poll_mode) 857 slot_cmd = slot_cmd | HP_INTR_ENABLE; 858 859 retval = pcie_write_cmd(slot, slot_cmd); 860 861 if (retval) { 862 err("%s: Write command failed!\n", __FUNCTION__); 863 return -1; 864 } 865 dbg("%s: SLOT_CTRL %x write cmd %x\n",__FUNCTION__, SLOT_CTRL, slot_cmd); 866 867 DBG_LEAVE_ROUTINE 868 869 return retval; 870 } 871 872 static irqreturn_t pcie_isr(int IRQ, void *dev_id, struct pt_regs *regs) 873 { 874 struct controller *ctrl = NULL; 875 struct php_ctlr_state_s *php_ctlr; 876 u8 schedule_flag = 0; 877 u16 slot_status, intr_detect, intr_loc; 878 u16 temp_word; 879 int hp_slot = 0; /* only 1 slot per PCI Express port */ 880 int rc = 0; 881 882 if (!dev_id) 883 return IRQ_NONE; 884 885 if (!pciehp_poll_mode) { 886 ctrl = dev_id; 887 php_ctlr = ctrl->hpc_ctlr_handle; 888 } else { 889 php_ctlr = dev_id; 890 ctrl = (struct controller *)php_ctlr->callback_instance_id; 891 } 892 893 if (!ctrl) { 894 dbg("%s: dev_id %p ctlr == NULL\n", __FUNCTION__, (void*) dev_id); 895 return IRQ_NONE; 896 } 897 898 if (!php_ctlr) { 899 dbg("%s: php_ctlr == NULL\n", __FUNCTION__); 900 return IRQ_NONE; 901 } 902 903 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS, slot_status); 904 if (rc) { 905 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__); 906 return IRQ_NONE; 907 } 908 909 intr_detect = ( ATTN_BUTTN_PRESSED | PWR_FAULT_DETECTED | MRL_SENS_CHANGED | 910 PRSN_DETECT_CHANGED | CMD_COMPLETED ); 911 912 intr_loc = slot_status & intr_detect; 913 914 /* Check to see if it was our interrupt */ 915 if ( !intr_loc ) 916 return IRQ_NONE; 917 918 dbg("%s: intr_loc %x\n", __FUNCTION__, intr_loc); 919 /* Mask Hot-plug Interrupt Enable */ 920 if (!pciehp_poll_mode) { 921 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL, temp_word); 922 if (rc) { 923 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__); 924 return IRQ_NONE; 925 } 926 927 dbg("%s: Set Mask Hot-plug Interrupt Enable\n", __FUNCTION__); 928 dbg("%s: hp_register_read_word SLOT_CTRL with value %x\n", __FUNCTION__, temp_word); 929 temp_word = (temp_word & ~HP_INTR_ENABLE & ~CMD_CMPL_INTR_ENABLE) | 0x00; 930 931 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_CTRL, temp_word); 932 if (rc) { 933 err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__); 934 return IRQ_NONE; 935 } 936 dbg("%s: hp_register_write_word SLOT_CTRL with value %x\n", __FUNCTION__, temp_word); 937 938 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS, slot_status); 939 if (rc) { 940 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__); 941 return IRQ_NONE; 942 } 943 dbg("%s: hp_register_read_word SLOT_STATUS with value %x\n", __FUNCTION__, slot_status); 944 945 /* Clear command complete interrupt caused by this write */ 946 temp_word = 0x1f; 947 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS, temp_word); 948 if (rc) { 949 err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__); 950 return IRQ_NONE; 951 } 952 dbg("%s: hp_register_write_word SLOT_STATUS with value %x\n", __FUNCTION__, temp_word); 953 } 954 955 if (intr_loc & CMD_COMPLETED) { 956 /* 957 * Command Complete Interrupt Pending 958 */ 959 dbg("%s: In Command Complete Interrupt Pending\n", __FUNCTION__); 960 wake_up_interruptible(&ctrl->queue); 961 } 962 963 if ((php_ctlr->switch_change_callback) && (intr_loc & MRL_SENS_CHANGED)) 964 schedule_flag += php_ctlr->switch_change_callback( 965 hp_slot, php_ctlr->callback_instance_id); 966 if ((php_ctlr->attention_button_callback) && (intr_loc & ATTN_BUTTN_PRESSED)) 967 schedule_flag += php_ctlr->attention_button_callback( 968 hp_slot, php_ctlr->callback_instance_id); 969 if ((php_ctlr->presence_change_callback) && (intr_loc & PRSN_DETECT_CHANGED)) 970 schedule_flag += php_ctlr->presence_change_callback( 971 hp_slot , php_ctlr->callback_instance_id); 972 if ((php_ctlr->power_fault_callback) && (intr_loc & PWR_FAULT_DETECTED)) 973 schedule_flag += php_ctlr->power_fault_callback( 974 hp_slot, php_ctlr->callback_instance_id); 975 976 /* Clear all events after serving them */ 977 temp_word = 0x1F; 978 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS, temp_word); 979 if (rc) { 980 err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__); 981 return IRQ_NONE; 982 } 983 /* Unmask Hot-plug Interrupt Enable */ 984 if (!pciehp_poll_mode) { 985 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL, temp_word); 986 if (rc) { 987 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__); 988 return IRQ_NONE; 989 } 990 991 dbg("%s: Unmask Hot-plug Interrupt Enable\n", __FUNCTION__); 992 dbg("%s: hp_register_read_word SLOT_CTRL with value %x\n", __FUNCTION__, temp_word); 993 temp_word = (temp_word & ~HP_INTR_ENABLE) | HP_INTR_ENABLE; 994 995 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_CTRL, temp_word); 996 if (rc) { 997 err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__); 998 return IRQ_NONE; 999 } 1000 dbg("%s: hp_register_write_word SLOT_CTRL with value %x\n", __FUNCTION__, temp_word); 1001 1002 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS, slot_status); 1003 if (rc) { 1004 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__); 1005 return IRQ_NONE; 1006 } 1007 dbg("%s: hp_register_read_word SLOT_STATUS with value %x\n", __FUNCTION__, slot_status); 1008 1009 /* Clear command complete interrupt caused by this write */ 1010 temp_word = 0x1F; 1011 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS, temp_word); 1012 if (rc) { 1013 err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__); 1014 return IRQ_NONE; 1015 } 1016 dbg("%s: hp_register_write_word SLOT_STATUS with value %x\n", __FUNCTION__, temp_word); 1017 } 1018 1019 return IRQ_HANDLED; 1020 } 1021 1022 static int hpc_get_max_lnk_speed (struct slot *slot, enum pci_bus_speed *value) 1023 { 1024 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; 1025 enum pcie_link_speed lnk_speed; 1026 u32 lnk_cap; 1027 int retval = 0; 1028 1029 DBG_ENTER_ROUTINE 1030 1031 if (!php_ctlr) { 1032 err("%s: Invalid HPC controller handle!\n", __FUNCTION__); 1033 return -1; 1034 } 1035 1036 if (slot->hp_slot >= php_ctlr->num_slots) { 1037 err("%s: Invalid HPC slot number!\n", __FUNCTION__); 1038 return -1; 1039 } 1040 1041 retval = hp_register_read_dword(php_ctlr->pci_dev, LNK_CAP, lnk_cap); 1042 1043 if (retval) { 1044 err("%s : hp_register_read_dword LNK_CAP failed\n", __FUNCTION__); 1045 return retval; 1046 } 1047 1048 switch (lnk_cap & 0x000F) { 1049 case 1: 1050 lnk_speed = PCIE_2PT5GB; 1051 break; 1052 default: 1053 lnk_speed = PCIE_LNK_SPEED_UNKNOWN; 1054 break; 1055 } 1056 1057 *value = lnk_speed; 1058 dbg("Max link speed = %d\n", lnk_speed); 1059 DBG_LEAVE_ROUTINE 1060 return retval; 1061 } 1062 1063 static int hpc_get_max_lnk_width (struct slot *slot, enum pcie_link_width *value) 1064 { 1065 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; 1066 enum pcie_link_width lnk_wdth; 1067 u32 lnk_cap; 1068 int retval = 0; 1069 1070 DBG_ENTER_ROUTINE 1071 1072 if (!php_ctlr) { 1073 err("%s: Invalid HPC controller handle!\n", __FUNCTION__); 1074 return -1; 1075 } 1076 1077 if (slot->hp_slot >= php_ctlr->num_slots) { 1078 err("%s: Invalid HPC slot number!\n", __FUNCTION__); 1079 return -1; 1080 } 1081 1082 retval = hp_register_read_dword(php_ctlr->pci_dev, LNK_CAP, lnk_cap); 1083 1084 if (retval) { 1085 err("%s : hp_register_read_dword LNK_CAP failed\n", __FUNCTION__); 1086 return retval; 1087 } 1088 1089 switch ((lnk_cap & 0x03F0) >> 4){ 1090 case 0: 1091 lnk_wdth = PCIE_LNK_WIDTH_RESRV; 1092 break; 1093 case 1: 1094 lnk_wdth = PCIE_LNK_X1; 1095 break; 1096 case 2: 1097 lnk_wdth = PCIE_LNK_X2; 1098 break; 1099 case 4: 1100 lnk_wdth = PCIE_LNK_X4; 1101 break; 1102 case 8: 1103 lnk_wdth = PCIE_LNK_X8; 1104 break; 1105 case 12: 1106 lnk_wdth = PCIE_LNK_X12; 1107 break; 1108 case 16: 1109 lnk_wdth = PCIE_LNK_X16; 1110 break; 1111 case 32: 1112 lnk_wdth = PCIE_LNK_X32; 1113 break; 1114 default: 1115 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; 1116 break; 1117 } 1118 1119 *value = lnk_wdth; 1120 dbg("Max link width = %d\n", lnk_wdth); 1121 DBG_LEAVE_ROUTINE 1122 return retval; 1123 } 1124 1125 static int hpc_get_cur_lnk_speed (struct slot *slot, enum pci_bus_speed *value) 1126 { 1127 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; 1128 enum pcie_link_speed lnk_speed = PCI_SPEED_UNKNOWN; 1129 int retval = 0; 1130 u16 lnk_status; 1131 1132 DBG_ENTER_ROUTINE 1133 1134 if (!php_ctlr) { 1135 err("%s: Invalid HPC controller handle!\n", __FUNCTION__); 1136 return -1; 1137 } 1138 1139 if (slot->hp_slot >= php_ctlr->num_slots) { 1140 err("%s: Invalid HPC slot number!\n", __FUNCTION__); 1141 return -1; 1142 } 1143 1144 retval = hp_register_read_word(php_ctlr->pci_dev, LNK_STATUS, lnk_status); 1145 1146 if (retval) { 1147 err("%s : hp_register_read_word LNK_STATUS failed\n", __FUNCTION__); 1148 return retval; 1149 } 1150 1151 switch (lnk_status & 0x0F) { 1152 case 1: 1153 lnk_speed = PCIE_2PT5GB; 1154 break; 1155 default: 1156 lnk_speed = PCIE_LNK_SPEED_UNKNOWN; 1157 break; 1158 } 1159 1160 *value = lnk_speed; 1161 dbg("Current link speed = %d\n", lnk_speed); 1162 DBG_LEAVE_ROUTINE 1163 return retval; 1164 } 1165 1166 static int hpc_get_cur_lnk_width (struct slot *slot, enum pcie_link_width *value) 1167 { 1168 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; 1169 enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; 1170 int retval = 0; 1171 u16 lnk_status; 1172 1173 DBG_ENTER_ROUTINE 1174 1175 if (!php_ctlr) { 1176 err("%s: Invalid HPC controller handle!\n", __FUNCTION__); 1177 return -1; 1178 } 1179 1180 if (slot->hp_slot >= php_ctlr->num_slots) { 1181 err("%s: Invalid HPC slot number!\n", __FUNCTION__); 1182 return -1; 1183 } 1184 1185 retval = hp_register_read_word(php_ctlr->pci_dev, LNK_STATUS, lnk_status); 1186 1187 if (retval) { 1188 err("%s : hp_register_read_word LNK_STATUS failed\n", __FUNCTION__); 1189 return retval; 1190 } 1191 1192 switch ((lnk_status & 0x03F0) >> 4){ 1193 case 0: 1194 lnk_wdth = PCIE_LNK_WIDTH_RESRV; 1195 break; 1196 case 1: 1197 lnk_wdth = PCIE_LNK_X1; 1198 break; 1199 case 2: 1200 lnk_wdth = PCIE_LNK_X2; 1201 break; 1202 case 4: 1203 lnk_wdth = PCIE_LNK_X4; 1204 break; 1205 case 8: 1206 lnk_wdth = PCIE_LNK_X8; 1207 break; 1208 case 12: 1209 lnk_wdth = PCIE_LNK_X12; 1210 break; 1211 case 16: 1212 lnk_wdth = PCIE_LNK_X16; 1213 break; 1214 case 32: 1215 lnk_wdth = PCIE_LNK_X32; 1216 break; 1217 default: 1218 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; 1219 break; 1220 } 1221 1222 *value = lnk_wdth; 1223 dbg("Current link width = %d\n", lnk_wdth); 1224 DBG_LEAVE_ROUTINE 1225 return retval; 1226 } 1227 1228 static struct hpc_ops pciehp_hpc_ops = { 1229 .power_on_slot = hpc_power_on_slot, 1230 .power_off_slot = hpc_power_off_slot, 1231 .set_attention_status = hpc_set_attention_status, 1232 .get_power_status = hpc_get_power_status, 1233 .get_attention_status = hpc_get_attention_status, 1234 .get_latch_status = hpc_get_latch_status, 1235 .get_adapter_status = hpc_get_adapter_status, 1236 1237 .get_max_bus_speed = hpc_get_max_lnk_speed, 1238 .get_cur_bus_speed = hpc_get_cur_lnk_speed, 1239 .get_max_lnk_width = hpc_get_max_lnk_width, 1240 .get_cur_lnk_width = hpc_get_cur_lnk_width, 1241 1242 .query_power_fault = hpc_query_power_fault, 1243 .green_led_on = hpc_set_green_led_on, 1244 .green_led_off = hpc_set_green_led_off, 1245 .green_led_blink = hpc_set_green_led_blink, 1246 1247 .release_ctlr = hpc_release_ctlr, 1248 .check_lnk_status = hpc_check_lnk_status, 1249 }; 1250 1251 int pcie_init(struct controller * ctrl, 1252 struct pcie_device *dev, 1253 php_intr_callback_t attention_button_callback, 1254 php_intr_callback_t switch_change_callback, 1255 php_intr_callback_t presence_change_callback, 1256 php_intr_callback_t power_fault_callback) 1257 { 1258 struct php_ctlr_state_s *php_ctlr, *p; 1259 void *instance_id = ctrl; 1260 int rc; 1261 static int first = 1; 1262 u16 temp_word; 1263 u16 cap_reg; 1264 u16 intr_enable = 0; 1265 u32 slot_cap; 1266 int cap_base, saved_cap_base; 1267 u16 slot_status, slot_ctrl; 1268 struct pci_dev *pdev; 1269 1270 DBG_ENTER_ROUTINE 1271 1272 spin_lock_init(&list_lock); 1273 php_ctlr = (struct php_ctlr_state_s *) kmalloc(sizeof(struct php_ctlr_state_s), GFP_KERNEL); 1274 1275 if (!php_ctlr) { /* allocate controller state data */ 1276 err("%s: HPC controller memory allocation error!\n", __FUNCTION__); 1277 goto abort; 1278 } 1279 1280 memset(php_ctlr, 0, sizeof(struct php_ctlr_state_s)); 1281 1282 pdev = dev->port; 1283 php_ctlr->pci_dev = pdev; /* save pci_dev in context */ 1284 1285 dbg("%s: pdev->vendor %x pdev->device %x\n", __FUNCTION__, 1286 pdev->vendor, pdev->device); 1287 1288 saved_cap_base = pcie_cap_base; 1289 1290 if ((cap_base = pci_find_capability(pdev, PCI_CAP_ID_EXP)) == 0) { 1291 dbg("%s: Can't find PCI_CAP_ID_EXP (0x10)\n", __FUNCTION__); 1292 goto abort_free_ctlr; 1293 } 1294 1295 pcie_cap_base = cap_base; 1296 1297 dbg("%s: pcie_cap_base %x\n", __FUNCTION__, pcie_cap_base); 1298 1299 rc = hp_register_read_word(pdev, CAP_REG, cap_reg); 1300 if (rc) { 1301 err("%s : hp_register_read_word CAP_REG failed\n", __FUNCTION__); 1302 goto abort_free_ctlr; 1303 } 1304 dbg("%s: CAP_REG offset %x cap_reg %x\n", __FUNCTION__, CAP_REG, cap_reg); 1305 1306 if (((cap_reg & SLOT_IMPL) == 0) || ((cap_reg & DEV_PORT_TYPE) != 0x0040)){ 1307 dbg("%s : This is not a root port or the port is not connected to a slot\n", __FUNCTION__); 1308 goto abort_free_ctlr; 1309 } 1310 1311 rc = hp_register_read_dword(php_ctlr->pci_dev, SLOT_CAP, slot_cap); 1312 if (rc) { 1313 err("%s : hp_register_read_word CAP_REG failed\n", __FUNCTION__); 1314 goto abort_free_ctlr; 1315 } 1316 dbg("%s: SLOT_CAP offset %x slot_cap %x\n", __FUNCTION__, SLOT_CAP, slot_cap); 1317 1318 if (!(slot_cap & HP_CAP)) { 1319 dbg("%s : This slot is not hot-plug capable\n", __FUNCTION__); 1320 goto abort_free_ctlr; 1321 } 1322 /* For debugging purpose */ 1323 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS, slot_status); 1324 if (rc) { 1325 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__); 1326 goto abort_free_ctlr; 1327 } 1328 dbg("%s: SLOT_STATUS offset %x slot_status %x\n", __FUNCTION__, SLOT_STATUS, slot_status); 1329 1330 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL, slot_ctrl); 1331 if (rc) { 1332 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__); 1333 goto abort_free_ctlr; 1334 } 1335 dbg("%s: SLOT_CTRL offset %x slot_ctrl %x\n", __FUNCTION__, SLOT_CTRL, slot_ctrl); 1336 1337 if (first) { 1338 spin_lock_init(&hpc_event_lock); 1339 first = 0; 1340 } 1341 1342 dbg("pdev = %p: b:d:f:irq=0x%x:%x:%x:%x\n", pdev, pdev->bus->number, 1343 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), dev->irq); 1344 for ( rc = 0; rc < DEVICE_COUNT_RESOURCE; rc++) 1345 if (pci_resource_len(pdev, rc) > 0) 1346 dbg("pci resource[%d] start=0x%lx(len=0x%lx)\n", rc, 1347 pci_resource_start(pdev, rc), pci_resource_len(pdev, rc)); 1348 1349 info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", pdev->vendor, pdev->device, 1350 pdev->subsystem_vendor, pdev->subsystem_device); 1351 1352 if (pci_enable_device(pdev)) 1353 goto abort_free_ctlr; 1354 1355 init_MUTEX(&ctrl->crit_sect); 1356 /* setup wait queue */ 1357 init_waitqueue_head(&ctrl->queue); 1358 1359 /* find the IRQ */ 1360 php_ctlr->irq = dev->irq; 1361 dbg("HPC interrupt = %d\n", php_ctlr->irq); 1362 1363 /* Save interrupt callback info */ 1364 php_ctlr->attention_button_callback = attention_button_callback; 1365 php_ctlr->switch_change_callback = switch_change_callback; 1366 php_ctlr->presence_change_callback = presence_change_callback; 1367 php_ctlr->power_fault_callback = power_fault_callback; 1368 php_ctlr->callback_instance_id = instance_id; 1369 1370 /* return PCI Controller Info */ 1371 php_ctlr->slot_device_offset = 0; 1372 php_ctlr->num_slots = 1; 1373 1374 /* Mask Hot-plug Interrupt Enable */ 1375 rc = hp_register_read_word(pdev, SLOT_CTRL, temp_word); 1376 if (rc) { 1377 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__); 1378 goto abort_free_ctlr; 1379 } 1380 1381 dbg("%s: SLOT_CTRL %x value read %x\n", __FUNCTION__, SLOT_CTRL, temp_word); 1382 temp_word = (temp_word & ~HP_INTR_ENABLE & ~CMD_CMPL_INTR_ENABLE) | 0x00; 1383 1384 rc = hp_register_write_word(pdev, SLOT_CTRL, temp_word); 1385 if (rc) { 1386 err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__); 1387 goto abort_free_ctlr; 1388 } 1389 dbg("%s : Mask HPIE hp_register_write_word SLOT_CTRL %x\n", __FUNCTION__, temp_word); 1390 1391 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS, slot_status); 1392 if (rc) { 1393 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__); 1394 goto abort_free_ctlr; 1395 } 1396 dbg("%s: Mask HPIE SLOT_STATUS offset %x reads slot_status %x\n", __FUNCTION__, SLOT_STATUS, slot_status); 1397 1398 temp_word = 0x1F; /* Clear all events */ 1399 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS, temp_word); 1400 if (rc) { 1401 err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__); 1402 goto abort_free_ctlr; 1403 } 1404 dbg("%s: SLOT_STATUS offset %x writes slot_status %x\n", __FUNCTION__, SLOT_STATUS, temp_word); 1405 1406 if (pciehp_poll_mode) {/* Install interrupt polling code */ 1407 /* Install and start the interrupt polling timer */ 1408 init_timer(&php_ctlr->int_poll_timer); 1409 start_int_poll_timer( php_ctlr, 10 ); /* start with 10 second delay */ 1410 } else { 1411 /* Installs the interrupt handler */ 1412 rc = request_irq(php_ctlr->irq, pcie_isr, SA_SHIRQ, MY_NAME, (void *) ctrl); 1413 dbg("%s: request_irq %d for hpc%d (returns %d)\n", __FUNCTION__, php_ctlr->irq, ctlr_seq_num, rc); 1414 if (rc) { 1415 err("Can't get irq %d for the hotplug controller\n", php_ctlr->irq); 1416 goto abort_free_ctlr; 1417 } 1418 } 1419 1420 rc = hp_register_read_word(pdev, SLOT_CTRL, temp_word); 1421 if (rc) { 1422 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__); 1423 goto abort_free_ctlr; 1424 } 1425 dbg("%s: SLOT_CTRL %x value read %x\n", __FUNCTION__, SLOT_CTRL, temp_word); 1426 dbg("%s: slot_cap %x\n", __FUNCTION__, slot_cap); 1427 1428 intr_enable = intr_enable | PRSN_DETECT_ENABLE; 1429 1430 if (ATTN_BUTTN(slot_cap)) 1431 intr_enable = intr_enable | ATTN_BUTTN_ENABLE; 1432 1433 if (POWER_CTRL(slot_cap)) 1434 intr_enable = intr_enable | PWR_FAULT_DETECT_ENABLE; 1435 1436 if (MRL_SENS(slot_cap)) 1437 intr_enable = intr_enable | MRL_DETECT_ENABLE; 1438 1439 temp_word = (temp_word & ~intr_enable) | intr_enable; 1440 1441 if (pciehp_poll_mode) { 1442 temp_word = (temp_word & ~HP_INTR_ENABLE) | 0x0; 1443 } else { 1444 temp_word = (temp_word & ~HP_INTR_ENABLE) | HP_INTR_ENABLE; 1445 } 1446 dbg("%s: temp_word %x\n", __FUNCTION__, temp_word); 1447 1448 /* Unmask Hot-plug Interrupt Enable for the interrupt notification mechanism case */ 1449 rc = hp_register_write_word(pdev, SLOT_CTRL, temp_word); 1450 if (rc) { 1451 err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__); 1452 goto abort_free_ctlr; 1453 } 1454 dbg("%s : Unmask HPIE hp_register_write_word SLOT_CTRL with %x\n", __FUNCTION__, temp_word); 1455 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS, slot_status); 1456 if (rc) { 1457 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__); 1458 goto abort_free_ctlr; 1459 } 1460 dbg("%s: Unmask HPIE SLOT_STATUS offset %x reads slot_status %x\n", __FUNCTION__, 1461 SLOT_STATUS, slot_status); 1462 1463 temp_word = 0x1F; /* Clear all events */ 1464 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS, temp_word); 1465 if (rc) { 1466 err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__); 1467 goto abort_free_ctlr; 1468 } 1469 dbg("%s: SLOT_STATUS offset %x writes slot_status %x\n", __FUNCTION__, SLOT_STATUS, temp_word); 1470 1471 /* Add this HPC instance into the HPC list */ 1472 spin_lock(&list_lock); 1473 if (php_ctlr_list_head == 0) { 1474 php_ctlr_list_head = php_ctlr; 1475 p = php_ctlr_list_head; 1476 p->pnext = NULL; 1477 } else { 1478 p = php_ctlr_list_head; 1479 1480 while (p->pnext) 1481 p = p->pnext; 1482 1483 p->pnext = php_ctlr; 1484 } 1485 spin_unlock(&list_lock); 1486 1487 ctlr_seq_num++; 1488 ctrl->hpc_ctlr_handle = php_ctlr; 1489 ctrl->hpc_ops = &pciehp_hpc_ops; 1490 1491 DBG_LEAVE_ROUTINE 1492 return 0; 1493 1494 /* We end up here for the many possible ways to fail this API. */ 1495 abort_free_ctlr: 1496 pcie_cap_base = saved_cap_base; 1497 kfree(php_ctlr); 1498 abort: 1499 DBG_LEAVE_ROUTINE 1500 return -1; 1501 } 1502