1 /* 2 * IBM Hot Plug Controller Driver 3 * 4 * Written By: Jyoti Shah, IBM Corporation 5 * 6 * Copyright (C) 2001-2003 IBM Corp. 7 * 8 * All rights reserved. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or (at 13 * your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, but 16 * WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 18 * NON INFRINGEMENT. See the GNU General Public License for more 19 * details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 24 * 25 * Send feedback to <gregkh@us.ibm.com> 26 * <jshah@us.ibm.com> 27 * 28 */ 29 30 #include <linux/wait.h> 31 #include <linux/time.h> 32 #include <linux/delay.h> 33 #include <linux/module.h> 34 #include <linux/pci.h> 35 #include <linux/init.h> 36 #include <linux/mutex.h> 37 #include <linux/sched.h> 38 #include <linux/semaphore.h> 39 #include <linux/kthread.h> 40 #include "ibmphp.h" 41 42 static int to_debug = 0; 43 #define debug_polling(fmt, arg...) do { if (to_debug) debug (fmt, arg); } while (0) 44 45 //---------------------------------------------------------------------------- 46 // timeout values 47 //---------------------------------------------------------------------------- 48 #define CMD_COMPLETE_TOUT_SEC 60 // give HPC 60 sec to finish cmd 49 #define HPC_CTLR_WORKING_TOUT 60 // give HPC 60 sec to finish cmd 50 #define HPC_GETACCESS_TIMEOUT 60 // seconds 51 #define POLL_INTERVAL_SEC 2 // poll HPC every 2 seconds 52 #define POLL_LATCH_CNT 5 // poll latch 5 times, then poll slots 53 54 //---------------------------------------------------------------------------- 55 // Winnipeg Architected Register Offsets 56 //---------------------------------------------------------------------------- 57 #define WPG_I2CMBUFL_OFFSET 0x08 // I2C Message Buffer Low 58 #define WPG_I2CMOSUP_OFFSET 0x10 // I2C Master Operation Setup Reg 59 #define WPG_I2CMCNTL_OFFSET 0x20 // I2C Master Control Register 60 #define WPG_I2CPARM_OFFSET 0x40 // I2C Parameter Register 61 #define WPG_I2CSTAT_OFFSET 0x70 // I2C Status Register 62 63 //---------------------------------------------------------------------------- 64 // Winnipeg Store Type commands (Add this commands to the register offset) 65 //---------------------------------------------------------------------------- 66 #define WPG_I2C_AND 0x1000 // I2C AND operation 67 #define WPG_I2C_OR 0x2000 // I2C OR operation 68 69 //---------------------------------------------------------------------------- 70 // Command set for I2C Master Operation Setup Register 71 //---------------------------------------------------------------------------- 72 #define WPG_READATADDR_MASK 0x00010000 // read,bytes,I2C shifted,index 73 #define WPG_WRITEATADDR_MASK 0x40010000 // write,bytes,I2C shifted,index 74 #define WPG_READDIRECT_MASK 0x10010000 75 #define WPG_WRITEDIRECT_MASK 0x60010000 76 77 78 //---------------------------------------------------------------------------- 79 // bit masks for I2C Master Control Register 80 //---------------------------------------------------------------------------- 81 #define WPG_I2CMCNTL_STARTOP_MASK 0x00000002 // Start the Operation 82 83 //---------------------------------------------------------------------------- 84 // 85 //---------------------------------------------------------------------------- 86 #define WPG_I2C_IOREMAP_SIZE 0x2044 // size of linear address interval 87 88 //---------------------------------------------------------------------------- 89 // command index 90 //---------------------------------------------------------------------------- 91 #define WPG_1ST_SLOT_INDEX 0x01 // index - 1st slot for ctlr 92 #define WPG_CTLR_INDEX 0x0F // index - ctlr 93 #define WPG_1ST_EXTSLOT_INDEX 0x10 // index - 1st ext slot for ctlr 94 #define WPG_1ST_BUS_INDEX 0x1F // index - 1st bus for ctlr 95 96 //---------------------------------------------------------------------------- 97 // macro utilities 98 //---------------------------------------------------------------------------- 99 // if bits 20,22,25,26,27,29,30 are OFF return 1 100 #define HPC_I2CSTATUS_CHECK(s) ((u8)((s & 0x00000A76) ? 0 : 1)) 101 102 //---------------------------------------------------------------------------- 103 // global variables 104 //---------------------------------------------------------------------------- 105 static struct mutex sem_hpcaccess; // lock access to HPC 106 static struct semaphore semOperations; // lock all operations and 107 // access to data structures 108 static struct semaphore sem_exit; // make sure polling thread goes away 109 static struct task_struct *ibmphp_poll_thread; 110 //---------------------------------------------------------------------------- 111 // local function prototypes 112 //---------------------------------------------------------------------------- 113 static u8 i2c_ctrl_read (struct controller *, void __iomem *, u8); 114 static u8 i2c_ctrl_write (struct controller *, void __iomem *, u8, u8); 115 static u8 hpc_writecmdtoindex (u8, u8); 116 static u8 hpc_readcmdtoindex (u8, u8); 117 static void get_hpc_access (void); 118 static void free_hpc_access (void); 119 static int poll_hpc(void *data); 120 static int process_changeinstatus (struct slot *, struct slot *); 121 static int process_changeinlatch (u8, u8, struct controller *); 122 static int hpc_wait_ctlr_notworking (int, struct controller *, void __iomem *, u8 *); 123 //---------------------------------------------------------------------------- 124 125 126 /*---------------------------------------------------------------------- 127 * Name: ibmphp_hpc_initvars 128 * 129 * Action: initialize semaphores and variables 130 *---------------------------------------------------------------------*/ 131 void __init ibmphp_hpc_initvars (void) 132 { 133 debug ("%s - Entry\n", __func__); 134 135 mutex_init(&sem_hpcaccess); 136 sema_init(&semOperations, 1); 137 sema_init(&sem_exit, 0); 138 to_debug = 0; 139 140 debug ("%s - Exit\n", __func__); 141 } 142 143 /*---------------------------------------------------------------------- 144 * Name: i2c_ctrl_read 145 * 146 * Action: read from HPC over I2C 147 * 148 *---------------------------------------------------------------------*/ 149 static u8 i2c_ctrl_read (struct controller *ctlr_ptr, void __iomem *WPGBbar, u8 index) 150 { 151 u8 status; 152 int i; 153 void __iomem *wpg_addr; // base addr + offset 154 unsigned long wpg_data; // data to/from WPG LOHI format 155 unsigned long ultemp; 156 unsigned long data; // actual data HILO format 157 158 debug_polling ("%s - Entry WPGBbar[%p] index[%x] \n", __func__, WPGBbar, index); 159 160 //-------------------------------------------------------------------- 161 // READ - step 1 162 // read at address, byte length, I2C address (shifted), index 163 // or read direct, byte length, index 164 if (ctlr_ptr->ctlr_type == 0x02) { 165 data = WPG_READATADDR_MASK; 166 // fill in I2C address 167 ultemp = (unsigned long)ctlr_ptr->u.wpeg_ctlr.i2c_addr; 168 ultemp = ultemp >> 1; 169 data |= (ultemp << 8); 170 171 // fill in index 172 data |= (unsigned long)index; 173 } else if (ctlr_ptr->ctlr_type == 0x04) { 174 data = WPG_READDIRECT_MASK; 175 176 // fill in index 177 ultemp = (unsigned long)index; 178 ultemp = ultemp << 8; 179 data |= ultemp; 180 } else { 181 err ("this controller type is not supported \n"); 182 return HPC_ERROR; 183 } 184 185 wpg_data = swab32 (data); // swap data before writing 186 wpg_addr = WPGBbar + WPG_I2CMOSUP_OFFSET; 187 writel (wpg_data, wpg_addr); 188 189 //-------------------------------------------------------------------- 190 // READ - step 2 : clear the message buffer 191 data = 0x00000000; 192 wpg_data = swab32 (data); 193 wpg_addr = WPGBbar + WPG_I2CMBUFL_OFFSET; 194 writel (wpg_data, wpg_addr); 195 196 //-------------------------------------------------------------------- 197 // READ - step 3 : issue start operation, I2C master control bit 30:ON 198 // 2020 : [20] OR operation at [20] offset 0x20 199 data = WPG_I2CMCNTL_STARTOP_MASK; 200 wpg_data = swab32 (data); 201 wpg_addr = WPGBbar + WPG_I2CMCNTL_OFFSET + WPG_I2C_OR; 202 writel (wpg_data, wpg_addr); 203 204 //-------------------------------------------------------------------- 205 // READ - step 4 : wait until start operation bit clears 206 i = CMD_COMPLETE_TOUT_SEC; 207 while (i) { 208 msleep(10); 209 wpg_addr = WPGBbar + WPG_I2CMCNTL_OFFSET; 210 wpg_data = readl (wpg_addr); 211 data = swab32 (wpg_data); 212 if (!(data & WPG_I2CMCNTL_STARTOP_MASK)) 213 break; 214 i--; 215 } 216 if (i == 0) { 217 debug ("%s - Error : WPG timeout\n", __func__); 218 return HPC_ERROR; 219 } 220 //-------------------------------------------------------------------- 221 // READ - step 5 : read I2C status register 222 i = CMD_COMPLETE_TOUT_SEC; 223 while (i) { 224 msleep(10); 225 wpg_addr = WPGBbar + WPG_I2CSTAT_OFFSET; 226 wpg_data = readl (wpg_addr); 227 data = swab32 (wpg_data); 228 if (HPC_I2CSTATUS_CHECK (data)) 229 break; 230 i--; 231 } 232 if (i == 0) { 233 debug ("ctrl_read - Exit Error:I2C timeout\n"); 234 return HPC_ERROR; 235 } 236 237 //-------------------------------------------------------------------- 238 // READ - step 6 : get DATA 239 wpg_addr = WPGBbar + WPG_I2CMBUFL_OFFSET; 240 wpg_data = readl (wpg_addr); 241 data = swab32 (wpg_data); 242 243 status = (u8) data; 244 245 debug_polling ("%s - Exit index[%x] status[%x]\n", __func__, index, status); 246 247 return (status); 248 } 249 250 /*---------------------------------------------------------------------- 251 * Name: i2c_ctrl_write 252 * 253 * Action: write to HPC over I2C 254 * 255 * Return 0 or error codes 256 *---------------------------------------------------------------------*/ 257 static u8 i2c_ctrl_write (struct controller *ctlr_ptr, void __iomem *WPGBbar, u8 index, u8 cmd) 258 { 259 u8 rc; 260 void __iomem *wpg_addr; // base addr + offset 261 unsigned long wpg_data; // data to/from WPG LOHI format 262 unsigned long ultemp; 263 unsigned long data; // actual data HILO format 264 int i; 265 266 debug_polling ("%s - Entry WPGBbar[%p] index[%x] cmd[%x]\n", __func__, WPGBbar, index, cmd); 267 268 rc = 0; 269 //-------------------------------------------------------------------- 270 // WRITE - step 1 271 // write at address, byte length, I2C address (shifted), index 272 // or write direct, byte length, index 273 data = 0x00000000; 274 275 if (ctlr_ptr->ctlr_type == 0x02) { 276 data = WPG_WRITEATADDR_MASK; 277 // fill in I2C address 278 ultemp = (unsigned long)ctlr_ptr->u.wpeg_ctlr.i2c_addr; 279 ultemp = ultemp >> 1; 280 data |= (ultemp << 8); 281 282 // fill in index 283 data |= (unsigned long)index; 284 } else if (ctlr_ptr->ctlr_type == 0x04) { 285 data = WPG_WRITEDIRECT_MASK; 286 287 // fill in index 288 ultemp = (unsigned long)index; 289 ultemp = ultemp << 8; 290 data |= ultemp; 291 } else { 292 err ("this controller type is not supported \n"); 293 return HPC_ERROR; 294 } 295 296 wpg_data = swab32 (data); // swap data before writing 297 wpg_addr = WPGBbar + WPG_I2CMOSUP_OFFSET; 298 writel (wpg_data, wpg_addr); 299 300 //-------------------------------------------------------------------- 301 // WRITE - step 2 : clear the message buffer 302 data = 0x00000000 | (unsigned long)cmd; 303 wpg_data = swab32 (data); 304 wpg_addr = WPGBbar + WPG_I2CMBUFL_OFFSET; 305 writel (wpg_data, wpg_addr); 306 307 //-------------------------------------------------------------------- 308 // WRITE - step 3 : issue start operation,I2C master control bit 30:ON 309 // 2020 : [20] OR operation at [20] offset 0x20 310 data = WPG_I2CMCNTL_STARTOP_MASK; 311 wpg_data = swab32 (data); 312 wpg_addr = WPGBbar + WPG_I2CMCNTL_OFFSET + WPG_I2C_OR; 313 writel (wpg_data, wpg_addr); 314 315 //-------------------------------------------------------------------- 316 // WRITE - step 4 : wait until start operation bit clears 317 i = CMD_COMPLETE_TOUT_SEC; 318 while (i) { 319 msleep(10); 320 wpg_addr = WPGBbar + WPG_I2CMCNTL_OFFSET; 321 wpg_data = readl (wpg_addr); 322 data = swab32 (wpg_data); 323 if (!(data & WPG_I2CMCNTL_STARTOP_MASK)) 324 break; 325 i--; 326 } 327 if (i == 0) { 328 debug ("%s - Exit Error:WPG timeout\n", __func__); 329 rc = HPC_ERROR; 330 } 331 332 //-------------------------------------------------------------------- 333 // WRITE - step 5 : read I2C status register 334 i = CMD_COMPLETE_TOUT_SEC; 335 while (i) { 336 msleep(10); 337 wpg_addr = WPGBbar + WPG_I2CSTAT_OFFSET; 338 wpg_data = readl (wpg_addr); 339 data = swab32 (wpg_data); 340 if (HPC_I2CSTATUS_CHECK (data)) 341 break; 342 i--; 343 } 344 if (i == 0) { 345 debug ("ctrl_read - Error : I2C timeout\n"); 346 rc = HPC_ERROR; 347 } 348 349 debug_polling ("%s Exit rc[%x]\n", __func__, rc); 350 return (rc); 351 } 352 353 //------------------------------------------------------------ 354 // Read from ISA type HPC 355 //------------------------------------------------------------ 356 static u8 isa_ctrl_read (struct controller *ctlr_ptr, u8 offset) 357 { 358 u16 start_address; 359 u16 end_address; 360 u8 data; 361 362 start_address = ctlr_ptr->u.isa_ctlr.io_start; 363 end_address = ctlr_ptr->u.isa_ctlr.io_end; 364 data = inb (start_address + offset); 365 return data; 366 } 367 368 //-------------------------------------------------------------- 369 // Write to ISA type HPC 370 //-------------------------------------------------------------- 371 static void isa_ctrl_write (struct controller *ctlr_ptr, u8 offset, u8 data) 372 { 373 u16 start_address; 374 u16 port_address; 375 376 start_address = ctlr_ptr->u.isa_ctlr.io_start; 377 port_address = start_address + (u16) offset; 378 outb (data, port_address); 379 } 380 381 static u8 pci_ctrl_read (struct controller *ctrl, u8 offset) 382 { 383 u8 data = 0x00; 384 debug ("inside pci_ctrl_read\n"); 385 if (ctrl->ctrl_dev) 386 pci_read_config_byte (ctrl->ctrl_dev, HPC_PCI_OFFSET + offset, &data); 387 return data; 388 } 389 390 static u8 pci_ctrl_write (struct controller *ctrl, u8 offset, u8 data) 391 { 392 u8 rc = -ENODEV; 393 debug ("inside pci_ctrl_write\n"); 394 if (ctrl->ctrl_dev) { 395 pci_write_config_byte (ctrl->ctrl_dev, HPC_PCI_OFFSET + offset, data); 396 rc = 0; 397 } 398 return rc; 399 } 400 401 static u8 ctrl_read (struct controller *ctlr, void __iomem *base, u8 offset) 402 { 403 u8 rc; 404 switch (ctlr->ctlr_type) { 405 case 0: 406 rc = isa_ctrl_read (ctlr, offset); 407 break; 408 case 1: 409 rc = pci_ctrl_read (ctlr, offset); 410 break; 411 case 2: 412 case 4: 413 rc = i2c_ctrl_read (ctlr, base, offset); 414 break; 415 default: 416 return -ENODEV; 417 } 418 return rc; 419 } 420 421 static u8 ctrl_write (struct controller *ctlr, void __iomem *base, u8 offset, u8 data) 422 { 423 u8 rc = 0; 424 switch (ctlr->ctlr_type) { 425 case 0: 426 isa_ctrl_write(ctlr, offset, data); 427 break; 428 case 1: 429 rc = pci_ctrl_write (ctlr, offset, data); 430 break; 431 case 2: 432 case 4: 433 rc = i2c_ctrl_write(ctlr, base, offset, data); 434 break; 435 default: 436 return -ENODEV; 437 } 438 return rc; 439 } 440 /*---------------------------------------------------------------------- 441 * Name: hpc_writecmdtoindex() 442 * 443 * Action: convert a write command to proper index within a controller 444 * 445 * Return index, HPC_ERROR 446 *---------------------------------------------------------------------*/ 447 static u8 hpc_writecmdtoindex (u8 cmd, u8 index) 448 { 449 u8 rc; 450 451 switch (cmd) { 452 case HPC_CTLR_ENABLEIRQ: // 0x00.N.15 453 case HPC_CTLR_CLEARIRQ: // 0x06.N.15 454 case HPC_CTLR_RESET: // 0x07.N.15 455 case HPC_CTLR_IRQSTEER: // 0x08.N.15 456 case HPC_CTLR_DISABLEIRQ: // 0x01.N.15 457 case HPC_ALLSLOT_ON: // 0x11.N.15 458 case HPC_ALLSLOT_OFF: // 0x12.N.15 459 rc = 0x0F; 460 break; 461 462 case HPC_SLOT_OFF: // 0x02.Y.0-14 463 case HPC_SLOT_ON: // 0x03.Y.0-14 464 case HPC_SLOT_ATTNOFF: // 0x04.N.0-14 465 case HPC_SLOT_ATTNON: // 0x05.N.0-14 466 case HPC_SLOT_BLINKLED: // 0x13.N.0-14 467 rc = index; 468 break; 469 470 case HPC_BUS_33CONVMODE: 471 case HPC_BUS_66CONVMODE: 472 case HPC_BUS_66PCIXMODE: 473 case HPC_BUS_100PCIXMODE: 474 case HPC_BUS_133PCIXMODE: 475 rc = index + WPG_1ST_BUS_INDEX - 1; 476 break; 477 478 default: 479 err ("hpc_writecmdtoindex - Error invalid cmd[%x]\n", cmd); 480 rc = HPC_ERROR; 481 } 482 483 return rc; 484 } 485 486 /*---------------------------------------------------------------------- 487 * Name: hpc_readcmdtoindex() 488 * 489 * Action: convert a read command to proper index within a controller 490 * 491 * Return index, HPC_ERROR 492 *---------------------------------------------------------------------*/ 493 static u8 hpc_readcmdtoindex (u8 cmd, u8 index) 494 { 495 u8 rc; 496 497 switch (cmd) { 498 case READ_CTLRSTATUS: 499 rc = 0x0F; 500 break; 501 case READ_SLOTSTATUS: 502 case READ_ALLSTAT: 503 rc = index; 504 break; 505 case READ_EXTSLOTSTATUS: 506 rc = index + WPG_1ST_EXTSLOT_INDEX; 507 break; 508 case READ_BUSSTATUS: 509 rc = index + WPG_1ST_BUS_INDEX - 1; 510 break; 511 case READ_SLOTLATCHLOWREG: 512 rc = 0x28; 513 break; 514 case READ_REVLEVEL: 515 rc = 0x25; 516 break; 517 case READ_HPCOPTIONS: 518 rc = 0x27; 519 break; 520 default: 521 rc = HPC_ERROR; 522 } 523 return rc; 524 } 525 526 /*---------------------------------------------------------------------- 527 * Name: HPCreadslot() 528 * 529 * Action: issue a READ command to HPC 530 * 531 * Input: pslot - cannot be NULL for READ_ALLSTAT 532 * pstatus - can be NULL for READ_ALLSTAT 533 * 534 * Return 0 or error codes 535 *---------------------------------------------------------------------*/ 536 int ibmphp_hpc_readslot (struct slot *pslot, u8 cmd, u8 *pstatus) 537 { 538 void __iomem *wpg_bbar = NULL; 539 struct controller *ctlr_ptr; 540 struct list_head *pslotlist; 541 u8 index, status; 542 int rc = 0; 543 int busindex; 544 545 debug_polling ("%s - Entry pslot[%p] cmd[%x] pstatus[%p]\n", __func__, pslot, cmd, pstatus); 546 547 if ((pslot == NULL) 548 || ((pstatus == NULL) && (cmd != READ_ALLSTAT) && (cmd != READ_BUSSTATUS))) { 549 rc = -EINVAL; 550 err ("%s - Error invalid pointer, rc[%d]\n", __func__, rc); 551 return rc; 552 } 553 554 if (cmd == READ_BUSSTATUS) { 555 busindex = ibmphp_get_bus_index (pslot->bus); 556 if (busindex < 0) { 557 rc = -EINVAL; 558 err ("%s - Exit Error:invalid bus, rc[%d]\n", __func__, rc); 559 return rc; 560 } else 561 index = (u8) busindex; 562 } else 563 index = pslot->ctlr_index; 564 565 index = hpc_readcmdtoindex (cmd, index); 566 567 if (index == HPC_ERROR) { 568 rc = -EINVAL; 569 err ("%s - Exit Error:invalid index, rc[%d]\n", __func__, rc); 570 return rc; 571 } 572 573 ctlr_ptr = pslot->ctrl; 574 575 get_hpc_access (); 576 577 //-------------------------------------------------------------------- 578 // map physical address to logical address 579 //-------------------------------------------------------------------- 580 if ((ctlr_ptr->ctlr_type == 2) || (ctlr_ptr->ctlr_type == 4)) 581 wpg_bbar = ioremap (ctlr_ptr->u.wpeg_ctlr.wpegbbar, WPG_I2C_IOREMAP_SIZE); 582 583 //-------------------------------------------------------------------- 584 // check controller status before reading 585 //-------------------------------------------------------------------- 586 rc = hpc_wait_ctlr_notworking (HPC_CTLR_WORKING_TOUT, ctlr_ptr, wpg_bbar, &status); 587 if (!rc) { 588 switch (cmd) { 589 case READ_ALLSTAT: 590 // update the slot structure 591 pslot->ctrl->status = status; 592 pslot->status = ctrl_read (ctlr_ptr, wpg_bbar, index); 593 rc = hpc_wait_ctlr_notworking (HPC_CTLR_WORKING_TOUT, ctlr_ptr, wpg_bbar, 594 &status); 595 if (!rc) 596 pslot->ext_status = ctrl_read (ctlr_ptr, wpg_bbar, index + WPG_1ST_EXTSLOT_INDEX); 597 598 break; 599 600 case READ_SLOTSTATUS: 601 // DO NOT update the slot structure 602 *pstatus = ctrl_read (ctlr_ptr, wpg_bbar, index); 603 break; 604 605 case READ_EXTSLOTSTATUS: 606 // DO NOT update the slot structure 607 *pstatus = ctrl_read (ctlr_ptr, wpg_bbar, index); 608 break; 609 610 case READ_CTLRSTATUS: 611 // DO NOT update the slot structure 612 *pstatus = status; 613 break; 614 615 case READ_BUSSTATUS: 616 pslot->busstatus = ctrl_read (ctlr_ptr, wpg_bbar, index); 617 break; 618 case READ_REVLEVEL: 619 *pstatus = ctrl_read (ctlr_ptr, wpg_bbar, index); 620 break; 621 case READ_HPCOPTIONS: 622 *pstatus = ctrl_read (ctlr_ptr, wpg_bbar, index); 623 break; 624 case READ_SLOTLATCHLOWREG: 625 // DO NOT update the slot structure 626 *pstatus = ctrl_read (ctlr_ptr, wpg_bbar, index); 627 break; 628 629 // Not used 630 case READ_ALLSLOT: 631 list_for_each (pslotlist, &ibmphp_slot_head) { 632 pslot = list_entry (pslotlist, struct slot, ibm_slot_list); 633 index = pslot->ctlr_index; 634 rc = hpc_wait_ctlr_notworking (HPC_CTLR_WORKING_TOUT, ctlr_ptr, 635 wpg_bbar, &status); 636 if (!rc) { 637 pslot->status = ctrl_read (ctlr_ptr, wpg_bbar, index); 638 rc = hpc_wait_ctlr_notworking (HPC_CTLR_WORKING_TOUT, 639 ctlr_ptr, wpg_bbar, &status); 640 if (!rc) 641 pslot->ext_status = 642 ctrl_read (ctlr_ptr, wpg_bbar, 643 index + WPG_1ST_EXTSLOT_INDEX); 644 } else { 645 err ("%s - Error ctrl_read failed\n", __func__); 646 rc = -EINVAL; 647 break; 648 } 649 } 650 break; 651 default: 652 rc = -EINVAL; 653 break; 654 } 655 } 656 //-------------------------------------------------------------------- 657 // cleanup 658 //-------------------------------------------------------------------- 659 660 // remove physical to logical address mapping 661 if ((ctlr_ptr->ctlr_type == 2) || (ctlr_ptr->ctlr_type == 4)) 662 iounmap (wpg_bbar); 663 664 free_hpc_access (); 665 666 debug_polling ("%s - Exit rc[%d]\n", __func__, rc); 667 return rc; 668 } 669 670 /*---------------------------------------------------------------------- 671 * Name: ibmphp_hpc_writeslot() 672 * 673 * Action: issue a WRITE command to HPC 674 *---------------------------------------------------------------------*/ 675 int ibmphp_hpc_writeslot (struct slot *pslot, u8 cmd) 676 { 677 void __iomem *wpg_bbar = NULL; 678 struct controller *ctlr_ptr; 679 u8 index, status; 680 int busindex; 681 u8 done; 682 int rc = 0; 683 int timeout; 684 685 debug_polling ("%s - Entry pslot[%p] cmd[%x]\n", __func__, pslot, cmd); 686 if (pslot == NULL) { 687 rc = -EINVAL; 688 err ("%s - Error Exit rc[%d]\n", __func__, rc); 689 return rc; 690 } 691 692 if ((cmd == HPC_BUS_33CONVMODE) || (cmd == HPC_BUS_66CONVMODE) || 693 (cmd == HPC_BUS_66PCIXMODE) || (cmd == HPC_BUS_100PCIXMODE) || 694 (cmd == HPC_BUS_133PCIXMODE)) { 695 busindex = ibmphp_get_bus_index (pslot->bus); 696 if (busindex < 0) { 697 rc = -EINVAL; 698 err ("%s - Exit Error:invalid bus, rc[%d]\n", __func__, rc); 699 return rc; 700 } else 701 index = (u8) busindex; 702 } else 703 index = pslot->ctlr_index; 704 705 index = hpc_writecmdtoindex (cmd, index); 706 707 if (index == HPC_ERROR) { 708 rc = -EINVAL; 709 err ("%s - Error Exit rc[%d]\n", __func__, rc); 710 return rc; 711 } 712 713 ctlr_ptr = pslot->ctrl; 714 715 get_hpc_access (); 716 717 //-------------------------------------------------------------------- 718 // map physical address to logical address 719 //-------------------------------------------------------------------- 720 if ((ctlr_ptr->ctlr_type == 2) || (ctlr_ptr->ctlr_type == 4)) { 721 wpg_bbar = ioremap (ctlr_ptr->u.wpeg_ctlr.wpegbbar, WPG_I2C_IOREMAP_SIZE); 722 723 debug ("%s - ctlr id[%x] physical[%lx] logical[%lx] i2c[%x]\n", __func__, 724 ctlr_ptr->ctlr_id, (ulong) (ctlr_ptr->u.wpeg_ctlr.wpegbbar), (ulong) wpg_bbar, 725 ctlr_ptr->u.wpeg_ctlr.i2c_addr); 726 } 727 //-------------------------------------------------------------------- 728 // check controller status before writing 729 //-------------------------------------------------------------------- 730 rc = hpc_wait_ctlr_notworking (HPC_CTLR_WORKING_TOUT, ctlr_ptr, wpg_bbar, &status); 731 if (!rc) { 732 733 ctrl_write (ctlr_ptr, wpg_bbar, index, cmd); 734 735 //-------------------------------------------------------------------- 736 // check controller is still not working on the command 737 //-------------------------------------------------------------------- 738 timeout = CMD_COMPLETE_TOUT_SEC; 739 done = 0; 740 while (!done) { 741 rc = hpc_wait_ctlr_notworking (HPC_CTLR_WORKING_TOUT, ctlr_ptr, wpg_bbar, 742 &status); 743 if (!rc) { 744 if (NEEDTOCHECK_CMDSTATUS (cmd)) { 745 if (CTLR_FINISHED (status) == HPC_CTLR_FINISHED_YES) 746 done = 1; 747 } else 748 done = 1; 749 } 750 if (!done) { 751 msleep(1000); 752 if (timeout < 1) { 753 done = 1; 754 err ("%s - Error command complete timeout\n", __func__); 755 rc = -EFAULT; 756 } else 757 timeout--; 758 } 759 } 760 ctlr_ptr->status = status; 761 } 762 // cleanup 763 764 // remove physical to logical address mapping 765 if ((ctlr_ptr->ctlr_type == 2) || (ctlr_ptr->ctlr_type == 4)) 766 iounmap (wpg_bbar); 767 free_hpc_access (); 768 769 debug_polling ("%s - Exit rc[%d]\n", __func__, rc); 770 return rc; 771 } 772 773 /*---------------------------------------------------------------------- 774 * Name: get_hpc_access() 775 * 776 * Action: make sure only one process can access HPC at one time 777 *---------------------------------------------------------------------*/ 778 static void get_hpc_access (void) 779 { 780 mutex_lock(&sem_hpcaccess); 781 } 782 783 /*---------------------------------------------------------------------- 784 * Name: free_hpc_access() 785 *---------------------------------------------------------------------*/ 786 void free_hpc_access (void) 787 { 788 mutex_unlock(&sem_hpcaccess); 789 } 790 791 /*---------------------------------------------------------------------- 792 * Name: ibmphp_lock_operations() 793 * 794 * Action: make sure only one process can change the data structure 795 *---------------------------------------------------------------------*/ 796 void ibmphp_lock_operations (void) 797 { 798 down (&semOperations); 799 to_debug = 1; 800 } 801 802 /*---------------------------------------------------------------------- 803 * Name: ibmphp_unlock_operations() 804 *---------------------------------------------------------------------*/ 805 void ibmphp_unlock_operations (void) 806 { 807 debug ("%s - Entry\n", __func__); 808 up (&semOperations); 809 to_debug = 0; 810 debug ("%s - Exit\n", __func__); 811 } 812 813 /*---------------------------------------------------------------------- 814 * Name: poll_hpc() 815 *---------------------------------------------------------------------*/ 816 #define POLL_LATCH_REGISTER 0 817 #define POLL_SLOTS 1 818 #define POLL_SLEEP 2 819 static int poll_hpc(void *data) 820 { 821 struct slot myslot; 822 struct slot *pslot = NULL; 823 struct list_head *pslotlist; 824 int rc; 825 int poll_state = POLL_LATCH_REGISTER; 826 u8 oldlatchlow = 0x00; 827 u8 curlatchlow = 0x00; 828 int poll_count = 0; 829 u8 ctrl_count = 0x00; 830 831 debug ("%s - Entry\n", __func__); 832 833 while (!kthread_should_stop()) { 834 /* try to get the lock to do some kind of hardware access */ 835 down (&semOperations); 836 837 switch (poll_state) { 838 case POLL_LATCH_REGISTER: 839 oldlatchlow = curlatchlow; 840 ctrl_count = 0x00; 841 list_for_each (pslotlist, &ibmphp_slot_head) { 842 if (ctrl_count >= ibmphp_get_total_controllers()) 843 break; 844 pslot = list_entry (pslotlist, struct slot, ibm_slot_list); 845 if (pslot->ctrl->ctlr_relative_id == ctrl_count) { 846 ctrl_count++; 847 if (READ_SLOT_LATCH (pslot->ctrl)) { 848 rc = ibmphp_hpc_readslot (pslot, 849 READ_SLOTLATCHLOWREG, 850 &curlatchlow); 851 if (oldlatchlow != curlatchlow) 852 process_changeinlatch (oldlatchlow, 853 curlatchlow, 854 pslot->ctrl); 855 } 856 } 857 } 858 ++poll_count; 859 poll_state = POLL_SLEEP; 860 break; 861 case POLL_SLOTS: 862 list_for_each (pslotlist, &ibmphp_slot_head) { 863 pslot = list_entry (pslotlist, struct slot, ibm_slot_list); 864 // make a copy of the old status 865 memcpy ((void *) &myslot, (void *) pslot, 866 sizeof (struct slot)); 867 rc = ibmphp_hpc_readslot (pslot, READ_ALLSTAT, NULL); 868 if ((myslot.status != pslot->status) 869 || (myslot.ext_status != pslot->ext_status)) 870 process_changeinstatus (pslot, &myslot); 871 } 872 ctrl_count = 0x00; 873 list_for_each (pslotlist, &ibmphp_slot_head) { 874 if (ctrl_count >= ibmphp_get_total_controllers()) 875 break; 876 pslot = list_entry (pslotlist, struct slot, ibm_slot_list); 877 if (pslot->ctrl->ctlr_relative_id == ctrl_count) { 878 ctrl_count++; 879 if (READ_SLOT_LATCH (pslot->ctrl)) 880 rc = ibmphp_hpc_readslot (pslot, 881 READ_SLOTLATCHLOWREG, 882 &curlatchlow); 883 } 884 } 885 ++poll_count; 886 poll_state = POLL_SLEEP; 887 break; 888 case POLL_SLEEP: 889 /* don't sleep with a lock on the hardware */ 890 up (&semOperations); 891 msleep(POLL_INTERVAL_SEC * 1000); 892 893 if (kthread_should_stop()) 894 goto out_sleep; 895 896 down (&semOperations); 897 898 if (poll_count >= POLL_LATCH_CNT) { 899 poll_count = 0; 900 poll_state = POLL_SLOTS; 901 } else 902 poll_state = POLL_LATCH_REGISTER; 903 break; 904 } 905 /* give up the hardware semaphore */ 906 up (&semOperations); 907 /* sleep for a short time just for good measure */ 908 out_sleep: 909 msleep(100); 910 } 911 up (&sem_exit); 912 debug ("%s - Exit\n", __func__); 913 return 0; 914 } 915 916 917 /*---------------------------------------------------------------------- 918 * Name: process_changeinstatus 919 * 920 * Action: compare old and new slot status, process the change in status 921 * 922 * Input: pointer to slot struct, old slot struct 923 * 924 * Return 0 or error codes 925 * Value: 926 * 927 * Side 928 * Effects: None. 929 * 930 * Notes: 931 *---------------------------------------------------------------------*/ 932 static int process_changeinstatus (struct slot *pslot, struct slot *poldslot) 933 { 934 u8 status; 935 int rc = 0; 936 u8 disable = 0; 937 u8 update = 0; 938 939 debug ("process_changeinstatus - Entry pslot[%p], poldslot[%p]\n", pslot, poldslot); 940 941 // bit 0 - HPC_SLOT_POWER 942 if ((pslot->status & 0x01) != (poldslot->status & 0x01)) 943 update = 1; 944 945 // bit 1 - HPC_SLOT_CONNECT 946 // ignore 947 948 // bit 2 - HPC_SLOT_ATTN 949 if ((pslot->status & 0x04) != (poldslot->status & 0x04)) 950 update = 1; 951 952 // bit 3 - HPC_SLOT_PRSNT2 953 // bit 4 - HPC_SLOT_PRSNT1 954 if (((pslot->status & 0x08) != (poldslot->status & 0x08)) 955 || ((pslot->status & 0x10) != (poldslot->status & 0x10))) 956 update = 1; 957 958 // bit 5 - HPC_SLOT_PWRGD 959 if ((pslot->status & 0x20) != (poldslot->status & 0x20)) 960 // OFF -> ON: ignore, ON -> OFF: disable slot 961 if ((poldslot->status & 0x20) && (SLOT_CONNECT (poldslot->status) == HPC_SLOT_CONNECTED) && (SLOT_PRESENT (poldslot->status))) 962 disable = 1; 963 964 // bit 6 - HPC_SLOT_BUS_SPEED 965 // ignore 966 967 // bit 7 - HPC_SLOT_LATCH 968 if ((pslot->status & 0x80) != (poldslot->status & 0x80)) { 969 update = 1; 970 // OPEN -> CLOSE 971 if (pslot->status & 0x80) { 972 if (SLOT_PWRGD (pslot->status)) { 973 // power goes on and off after closing latch 974 // check again to make sure power is still ON 975 msleep(1000); 976 rc = ibmphp_hpc_readslot (pslot, READ_SLOTSTATUS, &status); 977 if (SLOT_PWRGD (status)) 978 update = 1; 979 else // overwrite power in pslot to OFF 980 pslot->status &= ~HPC_SLOT_POWER; 981 } 982 } 983 // CLOSE -> OPEN 984 else if ((SLOT_PWRGD (poldslot->status) == HPC_SLOT_PWRGD_GOOD) 985 && (SLOT_CONNECT (poldslot->status) == HPC_SLOT_CONNECTED) && (SLOT_PRESENT (poldslot->status))) { 986 disable = 1; 987 } 988 // else - ignore 989 } 990 // bit 4 - HPC_SLOT_BLINK_ATTN 991 if ((pslot->ext_status & 0x08) != (poldslot->ext_status & 0x08)) 992 update = 1; 993 994 if (disable) { 995 debug ("process_changeinstatus - disable slot\n"); 996 pslot->flag = 0; 997 rc = ibmphp_do_disable_slot (pslot); 998 } 999 1000 if (update || disable) 1001 ibmphp_update_slot_info (pslot); 1002 1003 debug ("%s - Exit rc[%d] disable[%x] update[%x]\n", __func__, rc, disable, update); 1004 1005 return rc; 1006 } 1007 1008 /*---------------------------------------------------------------------- 1009 * Name: process_changeinlatch 1010 * 1011 * Action: compare old and new latch reg status, process the change 1012 * 1013 * Input: old and current latch register status 1014 * 1015 * Return 0 or error codes 1016 * Value: 1017 *---------------------------------------------------------------------*/ 1018 static int process_changeinlatch (u8 old, u8 new, struct controller *ctrl) 1019 { 1020 struct slot myslot, *pslot; 1021 u8 i; 1022 u8 mask; 1023 int rc = 0; 1024 1025 debug ("%s - Entry old[%x], new[%x]\n", __func__, old, new); 1026 // bit 0 reserved, 0 is LSB, check bit 1-6 for 6 slots 1027 1028 for (i = ctrl->starting_slot_num; i <= ctrl->ending_slot_num; i++) { 1029 mask = 0x01 << i; 1030 if ((mask & old) != (mask & new)) { 1031 pslot = ibmphp_get_slot_from_physical_num (i); 1032 if (pslot) { 1033 memcpy ((void *) &myslot, (void *) pslot, sizeof (struct slot)); 1034 rc = ibmphp_hpc_readslot (pslot, READ_ALLSTAT, NULL); 1035 debug ("%s - call process_changeinstatus for slot[%d]\n", __func__, i); 1036 process_changeinstatus (pslot, &myslot); 1037 } else { 1038 rc = -EINVAL; 1039 err ("%s - Error bad pointer for slot[%d]\n", __func__, i); 1040 } 1041 } 1042 } 1043 debug ("%s - Exit rc[%d]\n", __func__, rc); 1044 return rc; 1045 } 1046 1047 /*---------------------------------------------------------------------- 1048 * Name: ibmphp_hpc_start_poll_thread 1049 * 1050 * Action: start polling thread 1051 *---------------------------------------------------------------------*/ 1052 int __init ibmphp_hpc_start_poll_thread (void) 1053 { 1054 debug ("%s - Entry\n", __func__); 1055 1056 ibmphp_poll_thread = kthread_run(poll_hpc, NULL, "hpc_poll"); 1057 if (IS_ERR(ibmphp_poll_thread)) { 1058 err ("%s - Error, thread not started\n", __func__); 1059 return PTR_ERR(ibmphp_poll_thread); 1060 } 1061 return 0; 1062 } 1063 1064 /*---------------------------------------------------------------------- 1065 * Name: ibmphp_hpc_stop_poll_thread 1066 * 1067 * Action: stop polling thread and cleanup 1068 *---------------------------------------------------------------------*/ 1069 void __exit ibmphp_hpc_stop_poll_thread (void) 1070 { 1071 debug ("%s - Entry\n", __func__); 1072 1073 kthread_stop(ibmphp_poll_thread); 1074 debug ("before locking operations \n"); 1075 ibmphp_lock_operations (); 1076 debug ("after locking operations \n"); 1077 1078 // wait for poll thread to exit 1079 debug ("before sem_exit down \n"); 1080 down (&sem_exit); 1081 debug ("after sem_exit down \n"); 1082 1083 // cleanup 1084 debug ("before free_hpc_access \n"); 1085 free_hpc_access (); 1086 debug ("after free_hpc_access \n"); 1087 ibmphp_unlock_operations (); 1088 debug ("after unlock operations \n"); 1089 up (&sem_exit); 1090 debug ("after sem exit up\n"); 1091 1092 debug ("%s - Exit\n", __func__); 1093 } 1094 1095 /*---------------------------------------------------------------------- 1096 * Name: hpc_wait_ctlr_notworking 1097 * 1098 * Action: wait until the controller is in a not working state 1099 * 1100 * Return 0, HPC_ERROR 1101 * Value: 1102 *---------------------------------------------------------------------*/ 1103 static int hpc_wait_ctlr_notworking (int timeout, struct controller *ctlr_ptr, void __iomem *wpg_bbar, 1104 u8 *pstatus) 1105 { 1106 int rc = 0; 1107 u8 done = 0; 1108 1109 debug_polling ("hpc_wait_ctlr_notworking - Entry timeout[%d]\n", timeout); 1110 1111 while (!done) { 1112 *pstatus = ctrl_read (ctlr_ptr, wpg_bbar, WPG_CTLR_INDEX); 1113 if (*pstatus == HPC_ERROR) { 1114 rc = HPC_ERROR; 1115 done = 1; 1116 } 1117 if (CTLR_WORKING (*pstatus) == HPC_CTLR_WORKING_NO) 1118 done = 1; 1119 if (!done) { 1120 msleep(1000); 1121 if (timeout < 1) { 1122 done = 1; 1123 err ("HPCreadslot - Error ctlr timeout\n"); 1124 rc = HPC_ERROR; 1125 } else 1126 timeout--; 1127 } 1128 } 1129 debug_polling ("hpc_wait_ctlr_notworking - Exit rc[%x] status[%x]\n", rc, *pstatus); 1130 return rc; 1131 } 1132