1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 #ifndef __IBMPHP_H 3 #define __IBMPHP_H 4 5 /* 6 * IBM Hot Plug Controller Driver 7 * 8 * Written By: Jyoti Shah, Tong Yu, Irene Zubarev, IBM Corporation 9 * 10 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com) 11 * Copyright (C) 2001-2003 IBM Corp. 12 * 13 * All rights reserved. 14 * 15 * Send feedback to <gregkh@us.ibm.com> 16 * 17 */ 18 19 #include <linux/pci_hotplug.h> 20 21 extern int ibmphp_debug; 22 23 #if !defined(MODULE) 24 #define MY_NAME "ibmphpd" 25 #else 26 #define MY_NAME THIS_MODULE->name 27 #endif 28 #define debug(fmt, arg...) do { if (ibmphp_debug == 1) printk(KERN_DEBUG "%s: " fmt, MY_NAME, ## arg); } while (0) 29 #define debug_pci(fmt, arg...) do { if (ibmphp_debug) printk(KERN_DEBUG "%s: " fmt, MY_NAME, ## arg); } while (0) 30 #define err(format, arg...) printk(KERN_ERR "%s: " format, MY_NAME, ## arg) 31 #define info(format, arg...) printk(KERN_INFO "%s: " format, MY_NAME, ## arg) 32 #define warn(format, arg...) printk(KERN_WARNING "%s: " format, MY_NAME, ## arg) 33 34 35 /* EBDA stuff */ 36 37 /*********************************************************** 38 * SLOT CAPABILITY * 39 ***********************************************************/ 40 41 #define EBDA_SLOT_133_MAX 0x20 42 #define EBDA_SLOT_100_MAX 0x10 43 #define EBDA_SLOT_66_MAX 0x02 44 #define EBDA_SLOT_PCIX_CAP 0x08 45 46 47 /************************************************************ 48 * RESOURCE TYPE * 49 ************************************************************/ 50 51 #define EBDA_RSRC_TYPE_MASK 0x03 52 #define EBDA_IO_RSRC_TYPE 0x00 53 #define EBDA_MEM_RSRC_TYPE 0x01 54 #define EBDA_PFM_RSRC_TYPE 0x03 55 #define EBDA_RES_RSRC_TYPE 0x02 56 57 58 /************************************************************* 59 * IO RESTRICTION TYPE * 60 *************************************************************/ 61 62 #define EBDA_IO_RESTRI_MASK 0x0c 63 #define EBDA_NO_RESTRI 0x00 64 #define EBDA_AVO_VGA_ADDR 0x04 65 #define EBDA_AVO_VGA_ADDR_AND_ALIA 0x08 66 #define EBDA_AVO_ISA_ADDR 0x0c 67 68 69 /************************************************************** 70 * DEVICE TYPE DEF * 71 **************************************************************/ 72 73 #define EBDA_DEV_TYPE_MASK 0x10 74 #define EBDA_PCI_DEV 0x10 75 #define EBDA_NON_PCI_DEV 0x00 76 77 78 /*************************************************************** 79 * PRIMARY DEF DEFINITION * 80 ***************************************************************/ 81 82 #define EBDA_PRI_DEF_MASK 0x20 83 #define EBDA_PRI_PCI_BUS_INFO 0x20 84 #define EBDA_NORM_DEV_RSRC_INFO 0x00 85 86 87 //-------------------------------------------------------------- 88 // RIO TABLE DATA STRUCTURE 89 //-------------------------------------------------------------- 90 91 struct rio_table_hdr { 92 u8 ver_num; 93 u8 scal_count; 94 u8 riodev_count; 95 u16 offset; 96 }; 97 98 //------------------------------------------------------------- 99 // SCALABILITY DETAIL 100 //------------------------------------------------------------- 101 102 struct scal_detail { 103 u8 node_id; 104 u32 cbar; 105 u8 port0_node_connect; 106 u8 port0_port_connect; 107 u8 port1_node_connect; 108 u8 port1_port_connect; 109 u8 port2_node_connect; 110 u8 port2_port_connect; 111 u8 chassis_num; 112 // struct list_head scal_detail_list; 113 }; 114 115 //-------------------------------------------------------------- 116 // RIO DETAIL 117 //-------------------------------------------------------------- 118 119 struct rio_detail { 120 u8 rio_node_id; 121 u32 bbar; 122 u8 rio_type; 123 u8 owner_id; 124 u8 port0_node_connect; 125 u8 port0_port_connect; 126 u8 port1_node_connect; 127 u8 port1_port_connect; 128 u8 first_slot_num; 129 u8 status; 130 u8 wpindex; 131 u8 chassis_num; 132 struct list_head rio_detail_list; 133 }; 134 135 struct opt_rio { 136 u8 rio_type; 137 u8 chassis_num; 138 u8 first_slot_num; 139 u8 middle_num; 140 struct list_head opt_rio_list; 141 }; 142 143 struct opt_rio_lo { 144 u8 rio_type; 145 u8 chassis_num; 146 u8 first_slot_num; 147 u8 middle_num; 148 u8 pack_count; 149 struct list_head opt_rio_lo_list; 150 }; 151 152 /**************************************************************** 153 * HPC DESCRIPTOR NODE * 154 ****************************************************************/ 155 156 struct ebda_hpc_list { 157 u8 format; 158 u16 num_ctlrs; 159 short phys_addr; 160 // struct list_head ebda_hpc_list; 161 }; 162 /***************************************************************** 163 * IN HPC DATA STRUCTURE, THE ASSOCIATED SLOT AND BUS * 164 * STRUCTURE * 165 *****************************************************************/ 166 167 struct ebda_hpc_slot { 168 u8 slot_num; 169 u32 slot_bus_num; 170 u8 ctl_index; 171 u8 slot_cap; 172 }; 173 174 struct ebda_hpc_bus { 175 u32 bus_num; 176 u8 slots_at_33_conv; 177 u8 slots_at_66_conv; 178 u8 slots_at_66_pcix; 179 u8 slots_at_100_pcix; 180 u8 slots_at_133_pcix; 181 }; 182 183 184 /******************************************************************** 185 * THREE TYPE OF HOT PLUG CONTROLLER * 186 ********************************************************************/ 187 188 struct isa_ctlr_access { 189 u16 io_start; 190 u16 io_end; 191 }; 192 193 struct pci_ctlr_access { 194 u8 bus; 195 u8 dev_fun; 196 }; 197 198 struct wpeg_i2c_ctlr_access { 199 ulong wpegbbar; 200 u8 i2c_addr; 201 }; 202 203 #define HPC_DEVICE_ID 0x0246 204 #define HPC_SUBSYSTEM_ID 0x0247 205 #define HPC_PCI_OFFSET 0x40 206 /************************************************************************* 207 * RSTC DESCRIPTOR NODE * 208 *************************************************************************/ 209 210 struct ebda_rsrc_list { 211 u8 format; 212 u16 num_entries; 213 u16 phys_addr; 214 struct ebda_rsrc_list *next; 215 }; 216 217 218 /*************************************************************************** 219 * PCI RSRC NODE * 220 ***************************************************************************/ 221 222 struct ebda_pci_rsrc { 223 u8 rsrc_type; 224 u8 bus_num; 225 u8 dev_fun; 226 u32 start_addr; 227 u32 end_addr; 228 u8 marked; /* for NVRAM */ 229 struct list_head ebda_pci_rsrc_list; 230 }; 231 232 233 /*********************************************************** 234 * BUS_INFO DATE STRUCTURE * 235 ***********************************************************/ 236 237 struct bus_info { 238 u8 slot_min; 239 u8 slot_max; 240 u8 slot_count; 241 u8 busno; 242 u8 controller_id; 243 u8 current_speed; 244 u8 current_bus_mode; 245 u8 index; 246 u8 slots_at_33_conv; 247 u8 slots_at_66_conv; 248 u8 slots_at_66_pcix; 249 u8 slots_at_100_pcix; 250 u8 slots_at_133_pcix; 251 struct list_head bus_info_list; 252 }; 253 254 255 /*********************************************************** 256 * GLOBAL VARIABLES * 257 ***********************************************************/ 258 extern struct list_head ibmphp_ebda_pci_rsrc_head; 259 extern struct list_head ibmphp_slot_head; 260 /*********************************************************** 261 * FUNCTION PROTOTYPES * 262 ***********************************************************/ 263 264 void ibmphp_free_ebda_hpc_queue(void); 265 int ibmphp_access_ebda(void); 266 struct slot *ibmphp_get_slot_from_physical_num(u8); 267 int ibmphp_get_total_hp_slots(void); 268 void ibmphp_free_ibm_slot(struct slot *); 269 void ibmphp_free_bus_info_queue(void); 270 void ibmphp_free_ebda_pci_rsrc_queue(void); 271 struct bus_info *ibmphp_find_same_bus_num(u32); 272 int ibmphp_get_bus_index(u8); 273 u16 ibmphp_get_total_controllers(void); 274 int ibmphp_register_pci(void); 275 276 /* passed parameters */ 277 #define MEM 0 278 #define IO 1 279 #define PFMEM 2 280 281 /* bit masks */ 282 #define RESTYPE 0x03 283 #define IOMASK 0x00 /* will need to take its complement */ 284 #define MMASK 0x01 285 #define PFMASK 0x03 286 #define PCIDEVMASK 0x10 /* we should always have PCI devices */ 287 #define PRIMARYBUSMASK 0x20 288 289 /* pci specific defines */ 290 #define PCI_VENDOR_ID_NOTVALID 0xFFFF 291 #define PCI_HEADER_TYPE_MULTIDEVICE 0x80 292 #define PCI_HEADER_TYPE_MULTIBRIDGE 0x81 293 294 #define LATENCY 0x64 295 #define CACHE 64 296 #define DEVICEENABLE 0x015F /* CPQ has 0x0157 */ 297 298 #define IOBRIDGE 0x1000 /* 4k */ 299 #define MEMBRIDGE 0x100000 /* 1M */ 300 301 /* irqs */ 302 #define SCSI_IRQ 0x09 303 #define LAN_IRQ 0x0A 304 #define OTHER_IRQ 0x0B 305 306 /* Data Structures */ 307 308 /* type is of the form x x xx xx 309 * | | | |_ 00 - I/O, 01 - Memory, 11 - PFMemory 310 * | | - 00 - No Restrictions, 01 - Avoid VGA, 10 - Avoid 311 * | | VGA and their aliases, 11 - Avoid ISA 312 * | - 1 - PCI device, 0 - non pci device 313 * - 1 - Primary PCI Bus Information (0 if Normal device) 314 * the IO restrictions [2:3] are only for primary buses 315 */ 316 317 318 /* we need this struct because there could be several resource blocks 319 * allocated per primary bus in the EBDA 320 */ 321 struct range_node { 322 int rangeno; 323 u32 start; 324 u32 end; 325 struct range_node *next; 326 }; 327 328 struct bus_node { 329 u8 busno; 330 int noIORanges; 331 struct range_node *rangeIO; 332 int noMemRanges; 333 struct range_node *rangeMem; 334 int noPFMemRanges; 335 struct range_node *rangePFMem; 336 int needIOUpdate; 337 int needMemUpdate; 338 int needPFMemUpdate; 339 struct resource_node *firstIO; /* first IO resource on the Bus */ 340 struct resource_node *firstMem; /* first memory resource on the Bus */ 341 struct resource_node *firstPFMem; /* first prefetchable memory resource on the Bus */ 342 struct resource_node *firstPFMemFromMem; /* when run out of pfmem available, taking from Mem */ 343 struct list_head bus_list; 344 }; 345 346 struct resource_node { 347 int rangeno; 348 u8 busno; 349 u8 devfunc; 350 u32 start; 351 u32 end; 352 u32 len; 353 int type; /* MEM, IO, PFMEM */ 354 u8 fromMem; /* this is to indicate that the range is from 355 * from the Memory bucket rather than from PFMem */ 356 struct resource_node *next; 357 struct resource_node *nextRange; /* for the other mem range on bus */ 358 }; 359 360 struct res_needed { 361 u32 mem; 362 u32 pfmem; 363 u32 io; 364 u8 not_correct; /* needed for return */ 365 int devices[32]; /* for device numbers behind this bridge */ 366 }; 367 368 /* functions */ 369 370 int ibmphp_rsrc_init(void); 371 int ibmphp_add_resource(struct resource_node *); 372 int ibmphp_remove_resource(struct resource_node *); 373 int ibmphp_find_resource(struct bus_node *, u32, struct resource_node **, int); 374 int ibmphp_check_resource(struct resource_node *, u8); 375 int ibmphp_remove_bus(struct bus_node *, u8); 376 void ibmphp_free_resources(void); 377 int ibmphp_add_pfmem_from_mem(struct resource_node *); 378 struct bus_node *ibmphp_find_res_bus(u8); 379 void ibmphp_print_test(void); /* for debugging purposes */ 380 381 int ibmphp_hpc_readslot(struct slot *, u8, u8 *); 382 int ibmphp_hpc_writeslot(struct slot *, u8); 383 void ibmphp_lock_operations(void); 384 void ibmphp_unlock_operations(void); 385 int ibmphp_hpc_start_poll_thread(void); 386 void ibmphp_hpc_stop_poll_thread(void); 387 388 //---------------------------------------------------------------------------- 389 390 391 //---------------------------------------------------------------------------- 392 // HPC return codes 393 //---------------------------------------------------------------------------- 394 #define HPC_ERROR 0xFF 395 396 //----------------------------------------------------------------------------- 397 // BUS INFO 398 //----------------------------------------------------------------------------- 399 #define BUS_SPEED 0x30 400 #define BUS_MODE 0x40 401 #define BUS_MODE_PCIX 0x01 402 #define BUS_MODE_PCI 0x00 403 #define BUS_SPEED_2 0x20 404 #define BUS_SPEED_1 0x10 405 #define BUS_SPEED_33 0x00 406 #define BUS_SPEED_66 0x01 407 #define BUS_SPEED_100 0x02 408 #define BUS_SPEED_133 0x03 409 #define BUS_SPEED_66PCIX 0x04 410 #define BUS_SPEED_66UNKNOWN 0x05 411 #define BUS_STATUS_AVAILABLE 0x01 412 #define BUS_CONTROL_AVAILABLE 0x02 413 #define SLOT_LATCH_REGS_SUPPORTED 0x10 414 415 #define PRGM_MODEL_REV_LEVEL 0xF0 416 #define MAX_ADAPTER_NONE 0x09 417 418 //---------------------------------------------------------------------------- 419 // HPC 'write' operations/commands 420 //---------------------------------------------------------------------------- 421 // Command Code State Write to reg 422 // Machine at index 423 //------------------------- ---- ------- ------------ 424 #define HPC_CTLR_ENABLEIRQ 0x00 // N 15 425 #define HPC_CTLR_DISABLEIRQ 0x01 // N 15 426 #define HPC_SLOT_OFF 0x02 // Y 0-14 427 #define HPC_SLOT_ON 0x03 // Y 0-14 428 #define HPC_SLOT_ATTNOFF 0x04 // N 0-14 429 #define HPC_SLOT_ATTNON 0x05 // N 0-14 430 #define HPC_CTLR_CLEARIRQ 0x06 // N 15 431 #define HPC_CTLR_RESET 0x07 // Y 15 432 #define HPC_CTLR_IRQSTEER 0x08 // N 15 433 #define HPC_BUS_33CONVMODE 0x09 // Y 31-34 434 #define HPC_BUS_66CONVMODE 0x0A // Y 31-34 435 #define HPC_BUS_66PCIXMODE 0x0B // Y 31-34 436 #define HPC_BUS_100PCIXMODE 0x0C // Y 31-34 437 #define HPC_BUS_133PCIXMODE 0x0D // Y 31-34 438 #define HPC_ALLSLOT_OFF 0x11 // Y 15 439 #define HPC_ALLSLOT_ON 0x12 // Y 15 440 #define HPC_SLOT_BLINKLED 0x13 // N 0-14 441 442 //---------------------------------------------------------------------------- 443 // read commands 444 //---------------------------------------------------------------------------- 445 #define READ_SLOTSTATUS 0x01 446 #define READ_EXTSLOTSTATUS 0x02 447 #define READ_BUSSTATUS 0x03 448 #define READ_CTLRSTATUS 0x04 449 #define READ_ALLSTAT 0x05 450 #define READ_ALLSLOT 0x06 451 #define READ_SLOTLATCHLOWREG 0x07 452 #define READ_REVLEVEL 0x08 453 #define READ_HPCOPTIONS 0x09 454 //---------------------------------------------------------------------------- 455 // slot status 456 //---------------------------------------------------------------------------- 457 #define HPC_SLOT_POWER 0x01 458 #define HPC_SLOT_CONNECT 0x02 459 #define HPC_SLOT_ATTN 0x04 460 #define HPC_SLOT_PRSNT2 0x08 461 #define HPC_SLOT_PRSNT1 0x10 462 #define HPC_SLOT_PWRGD 0x20 463 #define HPC_SLOT_BUS_SPEED 0x40 464 #define HPC_SLOT_LATCH 0x80 465 466 //---------------------------------------------------------------------------- 467 // HPC_SLOT_POWER status return codes 468 //---------------------------------------------------------------------------- 469 #define HPC_SLOT_POWER_OFF 0x00 470 #define HPC_SLOT_POWER_ON 0x01 471 472 //---------------------------------------------------------------------------- 473 // HPC_SLOT_CONNECT status return codes 474 //---------------------------------------------------------------------------- 475 #define HPC_SLOT_CONNECTED 0x00 476 #define HPC_SLOT_DISCONNECTED 0x01 477 478 //---------------------------------------------------------------------------- 479 // HPC_SLOT_ATTN status return codes 480 //---------------------------------------------------------------------------- 481 #define HPC_SLOT_ATTN_OFF 0x00 482 #define HPC_SLOT_ATTN_ON 0x01 483 #define HPC_SLOT_ATTN_BLINK 0x02 484 485 //---------------------------------------------------------------------------- 486 // HPC_SLOT_PRSNT status return codes 487 //---------------------------------------------------------------------------- 488 #define HPC_SLOT_EMPTY 0x00 489 #define HPC_SLOT_PRSNT_7 0x01 490 #define HPC_SLOT_PRSNT_15 0x02 491 #define HPC_SLOT_PRSNT_25 0x03 492 493 //---------------------------------------------------------------------------- 494 // HPC_SLOT_PWRGD status return codes 495 //---------------------------------------------------------------------------- 496 #define HPC_SLOT_PWRGD_FAULT_NONE 0x00 497 #define HPC_SLOT_PWRGD_GOOD 0x01 498 499 //---------------------------------------------------------------------------- 500 // HPC_SLOT_BUS_SPEED status return codes 501 //---------------------------------------------------------------------------- 502 #define HPC_SLOT_BUS_SPEED_OK 0x00 503 #define HPC_SLOT_BUS_SPEED_MISM 0x01 504 505 //---------------------------------------------------------------------------- 506 // HPC_SLOT_LATCH status return codes 507 //---------------------------------------------------------------------------- 508 #define HPC_SLOT_LATCH_OPEN 0x01 // NOTE : in PCI spec bit off = open 509 #define HPC_SLOT_LATCH_CLOSED 0x00 // NOTE : in PCI spec bit on = closed 510 511 512 //---------------------------------------------------------------------------- 513 // extended slot status 514 //---------------------------------------------------------------------------- 515 #define HPC_SLOT_PCIX 0x01 516 #define HPC_SLOT_SPEED1 0x02 517 #define HPC_SLOT_SPEED2 0x04 518 #define HPC_SLOT_BLINK_ATTN 0x08 519 #define HPC_SLOT_RSRVD1 0x10 520 #define HPC_SLOT_RSRVD2 0x20 521 #define HPC_SLOT_BUS_MODE 0x40 522 #define HPC_SLOT_RSRVD3 0x80 523 524 //---------------------------------------------------------------------------- 525 // HPC_XSLOT_PCIX_CAP status return codes 526 //---------------------------------------------------------------------------- 527 #define HPC_SLOT_PCIX_NO 0x00 528 #define HPC_SLOT_PCIX_YES 0x01 529 530 //---------------------------------------------------------------------------- 531 // HPC_XSLOT_SPEED status return codes 532 //---------------------------------------------------------------------------- 533 #define HPC_SLOT_SPEED_33 0x00 534 #define HPC_SLOT_SPEED_66 0x01 535 #define HPC_SLOT_SPEED_133 0x02 536 537 //---------------------------------------------------------------------------- 538 // HPC_XSLOT_ATTN_BLINK status return codes 539 //---------------------------------------------------------------------------- 540 #define HPC_SLOT_ATTN_BLINK_OFF 0x00 541 #define HPC_SLOT_ATTN_BLINK_ON 0x01 542 543 //---------------------------------------------------------------------------- 544 // HPC_XSLOT_BUS_MODE status return codes 545 //---------------------------------------------------------------------------- 546 #define HPC_SLOT_BUS_MODE_OK 0x00 547 #define HPC_SLOT_BUS_MODE_MISM 0x01 548 549 //---------------------------------------------------------------------------- 550 // Controller status 551 //---------------------------------------------------------------------------- 552 #define HPC_CTLR_WORKING 0x01 553 #define HPC_CTLR_FINISHED 0x02 554 #define HPC_CTLR_RESULT0 0x04 555 #define HPC_CTLR_RESULT1 0x08 556 #define HPC_CTLR_RESULE2 0x10 557 #define HPC_CTLR_RESULT3 0x20 558 #define HPC_CTLR_IRQ_ROUTG 0x40 559 #define HPC_CTLR_IRQ_PENDG 0x80 560 561 //---------------------------------------------------------------------------- 562 // HPC_CTLR_WORKING status return codes 563 //---------------------------------------------------------------------------- 564 #define HPC_CTLR_WORKING_NO 0x00 565 #define HPC_CTLR_WORKING_YES 0x01 566 567 //---------------------------------------------------------------------------- 568 // HPC_CTLR_FINISHED status return codes 569 //---------------------------------------------------------------------------- 570 #define HPC_CTLR_FINISHED_NO 0x00 571 #define HPC_CTLR_FINISHED_YES 0x01 572 573 //---------------------------------------------------------------------------- 574 // HPC_CTLR_RESULT status return codes 575 //---------------------------------------------------------------------------- 576 #define HPC_CTLR_RESULT_SUCCESS 0x00 577 #define HPC_CTLR_RESULT_FAILED 0x01 578 #define HPC_CTLR_RESULT_RSVD 0x02 579 #define HPC_CTLR_RESULT_NORESP 0x03 580 581 582 //---------------------------------------------------------------------------- 583 // macro for slot info 584 //---------------------------------------------------------------------------- 585 #define SLOT_POWER(s) ((u8) ((s & HPC_SLOT_POWER) \ 586 ? HPC_SLOT_POWER_ON : HPC_SLOT_POWER_OFF)) 587 588 #define SLOT_CONNECT(s) ((u8) ((s & HPC_SLOT_CONNECT) \ 589 ? HPC_SLOT_DISCONNECTED : HPC_SLOT_CONNECTED)) 590 591 #define SLOT_ATTN(s, es) ((u8) ((es & HPC_SLOT_BLINK_ATTN) \ 592 ? HPC_SLOT_ATTN_BLINK \ 593 : ((s & HPC_SLOT_ATTN) ? HPC_SLOT_ATTN_ON : HPC_SLOT_ATTN_OFF))) 594 595 #define SLOT_PRESENT(s) ((u8) ((s & HPC_SLOT_PRSNT1) \ 596 ? ((s & HPC_SLOT_PRSNT2) ? HPC_SLOT_EMPTY : HPC_SLOT_PRSNT_15) \ 597 : ((s & HPC_SLOT_PRSNT2) ? HPC_SLOT_PRSNT_25 : HPC_SLOT_PRSNT_7))) 598 599 #define SLOT_PWRGD(s) ((u8) ((s & HPC_SLOT_PWRGD) \ 600 ? HPC_SLOT_PWRGD_GOOD : HPC_SLOT_PWRGD_FAULT_NONE)) 601 602 #define SLOT_BUS_SPEED(s) ((u8) ((s & HPC_SLOT_BUS_SPEED) \ 603 ? HPC_SLOT_BUS_SPEED_MISM : HPC_SLOT_BUS_SPEED_OK)) 604 605 #define SLOT_LATCH(s) ((u8) ((s & HPC_SLOT_LATCH) \ 606 ? HPC_SLOT_LATCH_CLOSED : HPC_SLOT_LATCH_OPEN)) 607 608 #define SLOT_PCIX(es) ((u8) ((es & HPC_SLOT_PCIX) \ 609 ? HPC_SLOT_PCIX_YES : HPC_SLOT_PCIX_NO)) 610 611 #define SLOT_SPEED(es) ((u8) ((es & HPC_SLOT_SPEED2) \ 612 ? ((es & HPC_SLOT_SPEED1) ? HPC_SLOT_SPEED_133 \ 613 : HPC_SLOT_SPEED_66) \ 614 : HPC_SLOT_SPEED_33)) 615 616 #define SLOT_BUS_MODE(es) ((u8) ((es & HPC_SLOT_BUS_MODE) \ 617 ? HPC_SLOT_BUS_MODE_MISM : HPC_SLOT_BUS_MODE_OK)) 618 619 //-------------------------------------------------------------------------- 620 // macro for bus info 621 //--------------------------------------------------------------------------- 622 #define CURRENT_BUS_SPEED(s) ((u8) (s & BUS_SPEED_2) \ 623 ? ((s & BUS_SPEED_1) ? BUS_SPEED_133 : BUS_SPEED_100) \ 624 : ((s & BUS_SPEED_1) ? BUS_SPEED_66 : BUS_SPEED_33)) 625 626 #define CURRENT_BUS_MODE(s) ((u8) (s & BUS_MODE) ? BUS_MODE_PCIX : BUS_MODE_PCI) 627 628 #define READ_BUS_STATUS(s) ((u8) (s->options & BUS_STATUS_AVAILABLE)) 629 630 #define READ_BUS_MODE(s) ((s->revision & PRGM_MODEL_REV_LEVEL) >= 0x20) 631 632 #define SET_BUS_STATUS(s) ((u8) (s->options & BUS_CONTROL_AVAILABLE)) 633 634 #define READ_SLOT_LATCH(s) ((u8) (s->options & SLOT_LATCH_REGS_SUPPORTED)) 635 636 //---------------------------------------------------------------------------- 637 // macro for controller info 638 //---------------------------------------------------------------------------- 639 #define CTLR_WORKING(c) ((u8) ((c & HPC_CTLR_WORKING) \ 640 ? HPC_CTLR_WORKING_YES : HPC_CTLR_WORKING_NO)) 641 #define CTLR_FINISHED(c) ((u8) ((c & HPC_CTLR_FINISHED) \ 642 ? HPC_CTLR_FINISHED_YES : HPC_CTLR_FINISHED_NO)) 643 #define CTLR_RESULT(c) ((u8) ((c & HPC_CTLR_RESULT1) \ 644 ? ((c & HPC_CTLR_RESULT0) ? HPC_CTLR_RESULT_NORESP \ 645 : HPC_CTLR_RESULT_RSVD) \ 646 : ((c & HPC_CTLR_RESULT0) ? HPC_CTLR_RESULT_FAILED \ 647 : HPC_CTLR_RESULT_SUCCESS))) 648 649 // command that affect the state machine of HPC 650 #define NEEDTOCHECK_CMDSTATUS(c) ((c == HPC_SLOT_OFF) || \ 651 (c == HPC_SLOT_ON) || \ 652 (c == HPC_CTLR_RESET) || \ 653 (c == HPC_BUS_33CONVMODE) || \ 654 (c == HPC_BUS_66CONVMODE) || \ 655 (c == HPC_BUS_66PCIXMODE) || \ 656 (c == HPC_BUS_100PCIXMODE) || \ 657 (c == HPC_BUS_133PCIXMODE) || \ 658 (c == HPC_ALLSLOT_OFF) || \ 659 (c == HPC_ALLSLOT_ON)) 660 661 662 /* Core part of the driver */ 663 664 #define ENABLE 1 665 #define DISABLE 0 666 667 #define CARD_INFO 0x07 668 #define PCIX133 0x07 669 #define PCIX66 0x05 670 #define PCI66 0x04 671 672 extern struct pci_bus *ibmphp_pci_bus; 673 674 /* Variables */ 675 676 struct pci_func { 677 struct pci_dev *dev; /* from the OS */ 678 u8 busno; 679 u8 device; 680 u8 function; 681 struct resource_node *io[6]; 682 struct resource_node *mem[6]; 683 struct resource_node *pfmem[6]; 684 struct pci_func *next; 685 int devices[32]; /* for bridge config */ 686 u8 irq[4]; /* for interrupt config */ 687 u8 bus; /* flag for unconfiguring, to say if PPB */ 688 }; 689 690 struct slot { 691 u8 bus; 692 u8 device; 693 u8 number; 694 u8 real_physical_slot_num; 695 u32 capabilities; 696 u8 supported_speed; 697 u8 supported_bus_mode; 698 u8 flag; /* this is for disable slot and polling */ 699 u8 ctlr_index; 700 struct hotplug_slot hotplug_slot; 701 struct controller *ctrl; 702 struct pci_func *func; 703 u8 irq[4]; 704 int bit_mode; /* 0 = 32, 1 = 64 */ 705 struct bus_info *bus_on; 706 struct list_head ibm_slot_list; 707 u8 status; 708 u8 ext_status; 709 u8 busstatus; 710 }; 711 712 struct controller { 713 struct ebda_hpc_slot *slots; 714 struct ebda_hpc_bus *buses; 715 struct pci_dev *ctrl_dev; /* in case where controller is PCI */ 716 u8 starting_slot_num; /* starting and ending slot #'s this ctrl controls*/ 717 u8 ending_slot_num; 718 u8 revision; 719 u8 options; /* which options HPC supports */ 720 u8 status; 721 u8 ctlr_id; 722 u8 slot_count; 723 u8 bus_count; 724 u8 ctlr_relative_id; 725 u32 irq; 726 union { 727 struct isa_ctlr_access isa_ctlr; 728 struct pci_ctlr_access pci_ctlr; 729 struct wpeg_i2c_ctlr_access wpeg_ctlr; 730 } u; 731 u8 ctlr_type; 732 struct list_head ebda_hpc_list; 733 }; 734 735 /* Functions */ 736 737 int ibmphp_init_devno(struct slot **); /* This function is called from EBDA, so we need it not be static */ 738 int ibmphp_do_disable_slot(struct slot *slot_cur); 739 int ibmphp_update_slot_info(struct slot *); /* This function is called from HPC, so we need it to not be be static */ 740 int ibmphp_configure_card(struct pci_func *, u8); 741 int ibmphp_unconfigure_card(struct slot **, int); 742 extern const struct hotplug_slot_ops ibmphp_hotplug_slot_ops; 743 744 static inline struct slot *to_slot(struct hotplug_slot *hotplug_slot) 745 { 746 return container_of(hotplug_slot, struct slot, hotplug_slot); 747 } 748 749 #endif //__IBMPHP_H 750 751