1 /* SPDX-License-Identifier: GPL-2.0+ */
2 #ifndef __IBMPHP_H
3 #define __IBMPHP_H
4
5 /*
6 * IBM Hot Plug Controller Driver
7 *
8 * Written By: Jyoti Shah, Tong Yu, Irene Zubarev, IBM Corporation
9 *
10 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
11 * Copyright (C) 2001-2003 IBM Corp.
12 *
13 * All rights reserved.
14 *
15 * Send feedback to <gregkh@us.ibm.com>
16 *
17 */
18
19 #include <linux/pci_hotplug.h>
20
21 extern int ibmphp_debug;
22
23 #if !defined(MODULE)
24 #define MY_NAME "ibmphpd"
25 #else
26 #define MY_NAME THIS_MODULE->name
27 #endif
28 #define debug(fmt, arg...) do { if (ibmphp_debug == 1) printk(KERN_DEBUG "%s: " fmt, MY_NAME, ## arg); } while (0)
29 #define debug_pci(fmt, arg...) do { if (ibmphp_debug) printk(KERN_DEBUG "%s: " fmt, MY_NAME, ## arg); } while (0)
30 #define err(format, arg...) printk(KERN_ERR "%s: " format, MY_NAME, ## arg)
31 #define info(format, arg...) printk(KERN_INFO "%s: " format, MY_NAME, ## arg)
32 #define warn(format, arg...) printk(KERN_WARNING "%s: " format, MY_NAME, ## arg)
33
34
35 /* EBDA stuff */
36
37 /***********************************************************
38 * SLOT CAPABILITY *
39 ***********************************************************/
40
41 #define EBDA_SLOT_133_MAX 0x20
42 #define EBDA_SLOT_100_MAX 0x10
43 #define EBDA_SLOT_66_MAX 0x02
44 #define EBDA_SLOT_PCIX_CAP 0x08
45
46
47 /************************************************************
48 * RESOURCE TYPE *
49 ************************************************************/
50
51 #define EBDA_RSRC_TYPE_MASK 0x03
52 #define EBDA_IO_RSRC_TYPE 0x00
53 #define EBDA_MEM_RSRC_TYPE 0x01
54 #define EBDA_PFM_RSRC_TYPE 0x03
55 #define EBDA_RES_RSRC_TYPE 0x02
56
57
58 /*************************************************************
59 * IO RESTRICTION TYPE *
60 *************************************************************/
61
62 #define EBDA_IO_RESTRI_MASK 0x0c
63 #define EBDA_NO_RESTRI 0x00
64 #define EBDA_AVO_VGA_ADDR 0x04
65 #define EBDA_AVO_VGA_ADDR_AND_ALIA 0x08
66 #define EBDA_AVO_ISA_ADDR 0x0c
67
68
69 /**************************************************************
70 * DEVICE TYPE DEF *
71 **************************************************************/
72
73 #define EBDA_DEV_TYPE_MASK 0x10
74 #define EBDA_PCI_DEV 0x10
75 #define EBDA_NON_PCI_DEV 0x00
76
77
78 /***************************************************************
79 * PRIMARY DEF DEFINITION *
80 ***************************************************************/
81
82 #define EBDA_PRI_DEF_MASK 0x20
83 #define EBDA_PRI_PCI_BUS_INFO 0x20
84 #define EBDA_NORM_DEV_RSRC_INFO 0x00
85
86
87 //--------------------------------------------------------------
88 // RIO TABLE DATA STRUCTURE
89 //--------------------------------------------------------------
90
91 struct rio_table_hdr {
92 u8 ver_num;
93 u8 scal_count;
94 u8 riodev_count;
95 u16 offset;
96 };
97
98 //-------------------------------------------------------------
99 // SCALABILITY DETAIL
100 //-------------------------------------------------------------
101
102 struct scal_detail {
103 u8 node_id;
104 u32 cbar;
105 u8 port0_node_connect;
106 u8 port0_port_connect;
107 u8 port1_node_connect;
108 u8 port1_port_connect;
109 u8 port2_node_connect;
110 u8 port2_port_connect;
111 u8 chassis_num;
112 // struct list_head scal_detail_list;
113 };
114
115 //--------------------------------------------------------------
116 // RIO DETAIL
117 //--------------------------------------------------------------
118
119 struct rio_detail {
120 u8 rio_node_id;
121 u32 bbar;
122 u8 rio_type;
123 u8 owner_id;
124 u8 port0_node_connect;
125 u8 port0_port_connect;
126 u8 port1_node_connect;
127 u8 port1_port_connect;
128 u8 first_slot_num;
129 u8 status;
130 u8 wpindex;
131 u8 chassis_num;
132 struct list_head rio_detail_list;
133 };
134
135 struct opt_rio {
136 u8 rio_type;
137 u8 chassis_num;
138 u8 first_slot_num;
139 u8 middle_num;
140 struct list_head opt_rio_list;
141 };
142
143 struct opt_rio_lo {
144 u8 rio_type;
145 u8 chassis_num;
146 u8 first_slot_num;
147 u8 middle_num;
148 u8 pack_count;
149 struct list_head opt_rio_lo_list;
150 };
151
152 /****************************************************************
153 * HPC DESCRIPTOR NODE *
154 ****************************************************************/
155
156 struct ebda_hpc_list {
157 u8 format;
158 u16 num_ctlrs;
159 short phys_addr;
160 // struct list_head ebda_hpc_list;
161 };
162 /*****************************************************************
163 * IN HPC DATA STRUCTURE, THE ASSOCIATED SLOT AND BUS *
164 * STRUCTURE *
165 *****************************************************************/
166
167 struct ebda_hpc_slot {
168 u8 slot_num;
169 u32 slot_bus_num;
170 u8 ctl_index;
171 u8 slot_cap;
172 };
173
174 struct ebda_hpc_bus {
175 u32 bus_num;
176 u8 slots_at_33_conv;
177 u8 slots_at_66_conv;
178 u8 slots_at_66_pcix;
179 u8 slots_at_100_pcix;
180 u8 slots_at_133_pcix;
181 };
182
183
184 /********************************************************************
185 * THREE TYPE OF HOT PLUG CONTROLLER *
186 ********************************************************************/
187
188 struct isa_ctlr_access {
189 u16 io_start;
190 u16 io_end;
191 };
192
193 struct pci_ctlr_access {
194 u8 bus;
195 u8 dev_fun;
196 };
197
198 struct wpeg_i2c_ctlr_access {
199 ulong wpegbbar;
200 u8 i2c_addr;
201 };
202
203 #define HPC_DEVICE_ID 0x0246
204 #define HPC_SUBSYSTEM_ID 0x0247
205 #define HPC_PCI_OFFSET 0x40
206 /*************************************************************************
207 * RSTC DESCRIPTOR NODE *
208 *************************************************************************/
209
210 struct ebda_rsrc_list {
211 u8 format;
212 u16 num_entries;
213 u16 phys_addr;
214 struct ebda_rsrc_list *next;
215 };
216
217
218 /***************************************************************************
219 * PCI RSRC NODE *
220 ***************************************************************************/
221
222 struct ebda_pci_rsrc {
223 u8 rsrc_type;
224 u8 bus_num;
225 u8 dev_fun;
226 u32 start_addr;
227 u32 end_addr;
228 u8 marked; /* for NVRAM */
229 struct list_head ebda_pci_rsrc_list;
230 };
231
232
233 /***********************************************************
234 * BUS_INFO DATE STRUCTURE *
235 ***********************************************************/
236
237 struct bus_info {
238 u8 slot_min;
239 u8 slot_max;
240 u8 slot_count;
241 u8 busno;
242 u8 controller_id;
243 u8 current_speed;
244 u8 current_bus_mode;
245 u8 index;
246 u8 slots_at_33_conv;
247 u8 slots_at_66_conv;
248 u8 slots_at_66_pcix;
249 u8 slots_at_100_pcix;
250 u8 slots_at_133_pcix;
251 struct list_head bus_info_list;
252 };
253
254
255 /***********************************************************
256 * GLOBAL VARIABLES *
257 ***********************************************************/
258 extern struct list_head ibmphp_ebda_pci_rsrc_head;
259 extern struct list_head ibmphp_slot_head;
260 /***********************************************************
261 * FUNCTION PROTOTYPES *
262 ***********************************************************/
263
264 void ibmphp_free_ebda_hpc_queue(void);
265 int ibmphp_access_ebda(void);
266 struct slot *ibmphp_get_slot_from_physical_num(u8);
267 void ibmphp_free_bus_info_queue(void);
268 void ibmphp_free_ebda_pci_rsrc_queue(void);
269 struct bus_info *ibmphp_find_same_bus_num(u32);
270 int ibmphp_get_bus_index(u8);
271 u16 ibmphp_get_total_controllers(void);
272 int ibmphp_register_pci(void);
273
274 /* passed parameters */
275 #define MEM 0
276 #define IO 1
277 #define PFMEM 2
278
279 /* bit masks */
280 #define RESTYPE 0x03
281 #define IOMASK 0x00 /* will need to take its complement */
282 #define MMASK 0x01
283 #define PFMASK 0x03
284 #define PCIDEVMASK 0x10 /* we should always have PCI devices */
285 #define PRIMARYBUSMASK 0x20
286
287 /* pci specific defines */
288 #define PCI_VENDOR_ID_NOTVALID 0xFFFF
289 #define PCI_HEADER_TYPE_MULTIDEVICE 0x80
290 #define PCI_HEADER_TYPE_MULTIBRIDGE 0x81
291
292 #define LATENCY 0x64
293 #define CACHE 64
294 #define DEVICEENABLE 0x015F /* CPQ has 0x0157 */
295
296 #define IOBRIDGE 0x1000 /* 4k */
297 #define MEMBRIDGE 0x100000 /* 1M */
298
299 /* irqs */
300 #define SCSI_IRQ 0x09
301 #define LAN_IRQ 0x0A
302 #define OTHER_IRQ 0x0B
303
304 /* Data Structures */
305
306 /* type is of the form x x xx xx
307 * | | | |_ 00 - I/O, 01 - Memory, 11 - PFMemory
308 * | | - 00 - No Restrictions, 01 - Avoid VGA, 10 - Avoid
309 * | | VGA and their aliases, 11 - Avoid ISA
310 * | - 1 - PCI device, 0 - non pci device
311 * - 1 - Primary PCI Bus Information (0 if Normal device)
312 * the IO restrictions [2:3] are only for primary buses
313 */
314
315
316 /* we need this struct because there could be several resource blocks
317 * allocated per primary bus in the EBDA
318 */
319 struct range_node {
320 int rangeno;
321 u32 start;
322 u32 end;
323 struct range_node *next;
324 };
325
326 struct bus_node {
327 u8 busno;
328 int noIORanges;
329 struct range_node *rangeIO;
330 int noMemRanges;
331 struct range_node *rangeMem;
332 int noPFMemRanges;
333 struct range_node *rangePFMem;
334 int needIOUpdate;
335 int needMemUpdate;
336 int needPFMemUpdate;
337 struct resource_node *firstIO; /* first IO resource on the Bus */
338 struct resource_node *firstMem; /* first memory resource on the Bus */
339 struct resource_node *firstPFMem; /* first prefetchable memory resource on the Bus */
340 struct resource_node *firstPFMemFromMem; /* when run out of pfmem available, taking from Mem */
341 struct list_head bus_list;
342 };
343
344 struct resource_node {
345 int rangeno;
346 u8 busno;
347 u8 devfunc;
348 u32 start;
349 u32 end;
350 u32 len;
351 int type; /* MEM, IO, PFMEM */
352 u8 fromMem; /* this is to indicate that the range is from
353 * the Memory bucket rather than from PFMem */
354 struct resource_node *next;
355 struct resource_node *nextRange; /* for the other mem range on bus */
356 };
357
358 struct res_needed {
359 u32 mem;
360 u32 pfmem;
361 u32 io;
362 u8 not_correct; /* needed for return */
363 int devices[32]; /* for device numbers behind this bridge */
364 };
365
366 /* functions */
367
368 int ibmphp_rsrc_init(void);
369 int ibmphp_add_resource(struct resource_node *);
370 int ibmphp_remove_resource(struct resource_node *);
371 int ibmphp_find_resource(struct bus_node *, u32, struct resource_node **, int);
372 int ibmphp_check_resource(struct resource_node *, u8);
373 int ibmphp_remove_bus(struct bus_node *, u8);
374 void ibmphp_free_resources(void);
375 int ibmphp_add_pfmem_from_mem(struct resource_node *);
376 struct bus_node *ibmphp_find_res_bus(u8);
377 void ibmphp_print_test(void); /* for debugging purposes */
378
379 int ibmphp_hpc_readslot(struct slot *, u8, u8 *);
380 int ibmphp_hpc_writeslot(struct slot *, u8);
381 void ibmphp_lock_operations(void);
382 void ibmphp_unlock_operations(void);
383 int ibmphp_hpc_start_poll_thread(void);
384 void ibmphp_hpc_stop_poll_thread(void);
385
386 //----------------------------------------------------------------------------
387
388
389 //----------------------------------------------------------------------------
390 // HPC return codes
391 //----------------------------------------------------------------------------
392 #define HPC_ERROR 0xFF
393
394 //-----------------------------------------------------------------------------
395 // BUS INFO
396 //-----------------------------------------------------------------------------
397 #define BUS_SPEED 0x30
398 #define BUS_MODE 0x40
399 #define BUS_MODE_PCIX 0x01
400 #define BUS_MODE_PCI 0x00
401 #define BUS_SPEED_2 0x20
402 #define BUS_SPEED_1 0x10
403 #define BUS_SPEED_33 0x00
404 #define BUS_SPEED_66 0x01
405 #define BUS_SPEED_100 0x02
406 #define BUS_SPEED_133 0x03
407 #define BUS_SPEED_66PCIX 0x04
408 #define BUS_SPEED_66UNKNOWN 0x05
409 #define BUS_STATUS_AVAILABLE 0x01
410 #define BUS_CONTROL_AVAILABLE 0x02
411 #define SLOT_LATCH_REGS_SUPPORTED 0x10
412
413 #define PRGM_MODEL_REV_LEVEL 0xF0
414 #define MAX_ADAPTER_NONE 0x09
415
416 //----------------------------------------------------------------------------
417 // HPC 'write' operations/commands
418 //----------------------------------------------------------------------------
419 // Command Code State Write to reg
420 // Machine at index
421 //------------------------- ---- ------- ------------
422 #define HPC_CTLR_ENABLEIRQ 0x00 // N 15
423 #define HPC_CTLR_DISABLEIRQ 0x01 // N 15
424 #define HPC_SLOT_OFF 0x02 // Y 0-14
425 #define HPC_SLOT_ON 0x03 // Y 0-14
426 #define HPC_SLOT_ATTNOFF 0x04 // N 0-14
427 #define HPC_SLOT_ATTNON 0x05 // N 0-14
428 #define HPC_CTLR_CLEARIRQ 0x06 // N 15
429 #define HPC_CTLR_RESET 0x07 // Y 15
430 #define HPC_CTLR_IRQSTEER 0x08 // N 15
431 #define HPC_BUS_33CONVMODE 0x09 // Y 31-34
432 #define HPC_BUS_66CONVMODE 0x0A // Y 31-34
433 #define HPC_BUS_66PCIXMODE 0x0B // Y 31-34
434 #define HPC_BUS_100PCIXMODE 0x0C // Y 31-34
435 #define HPC_BUS_133PCIXMODE 0x0D // Y 31-34
436 #define HPC_ALLSLOT_OFF 0x11 // Y 15
437 #define HPC_ALLSLOT_ON 0x12 // Y 15
438 #define HPC_SLOT_BLINKLED 0x13 // N 0-14
439
440 //----------------------------------------------------------------------------
441 // read commands
442 //----------------------------------------------------------------------------
443 #define READ_SLOTSTATUS 0x01
444 #define READ_EXTSLOTSTATUS 0x02
445 #define READ_BUSSTATUS 0x03
446 #define READ_CTLRSTATUS 0x04
447 #define READ_ALLSTAT 0x05
448 #define READ_ALLSLOT 0x06
449 #define READ_SLOTLATCHLOWREG 0x07
450 #define READ_REVLEVEL 0x08
451 #define READ_HPCOPTIONS 0x09
452 //----------------------------------------------------------------------------
453 // slot status
454 //----------------------------------------------------------------------------
455 #define HPC_SLOT_POWER 0x01
456 #define HPC_SLOT_CONNECT 0x02
457 #define HPC_SLOT_ATTN 0x04
458 #define HPC_SLOT_PRSNT2 0x08
459 #define HPC_SLOT_PRSNT1 0x10
460 #define HPC_SLOT_PWRGD 0x20
461 #define HPC_SLOT_BUS_SPEED 0x40
462 #define HPC_SLOT_LATCH 0x80
463
464 //----------------------------------------------------------------------------
465 // HPC_SLOT_POWER status return codes
466 //----------------------------------------------------------------------------
467 #define HPC_SLOT_POWER_OFF 0x00
468 #define HPC_SLOT_POWER_ON 0x01
469
470 //----------------------------------------------------------------------------
471 // HPC_SLOT_CONNECT status return codes
472 //----------------------------------------------------------------------------
473 #define HPC_SLOT_CONNECTED 0x00
474 #define HPC_SLOT_DISCONNECTED 0x01
475
476 //----------------------------------------------------------------------------
477 // HPC_SLOT_ATTN status return codes
478 //----------------------------------------------------------------------------
479 #define HPC_SLOT_ATTN_OFF 0x00
480 #define HPC_SLOT_ATTN_ON 0x01
481 #define HPC_SLOT_ATTN_BLINK 0x02
482
483 //----------------------------------------------------------------------------
484 // HPC_SLOT_PRSNT status return codes
485 //----------------------------------------------------------------------------
486 #define HPC_SLOT_EMPTY 0x00
487 #define HPC_SLOT_PRSNT_7 0x01
488 #define HPC_SLOT_PRSNT_15 0x02
489 #define HPC_SLOT_PRSNT_25 0x03
490
491 //----------------------------------------------------------------------------
492 // HPC_SLOT_PWRGD status return codes
493 //----------------------------------------------------------------------------
494 #define HPC_SLOT_PWRGD_FAULT_NONE 0x00
495 #define HPC_SLOT_PWRGD_GOOD 0x01
496
497 //----------------------------------------------------------------------------
498 // HPC_SLOT_BUS_SPEED status return codes
499 //----------------------------------------------------------------------------
500 #define HPC_SLOT_BUS_SPEED_OK 0x00
501 #define HPC_SLOT_BUS_SPEED_MISM 0x01
502
503 //----------------------------------------------------------------------------
504 // HPC_SLOT_LATCH status return codes
505 //----------------------------------------------------------------------------
506 #define HPC_SLOT_LATCH_OPEN 0x01 // NOTE : in PCI spec bit off = open
507 #define HPC_SLOT_LATCH_CLOSED 0x00 // NOTE : in PCI spec bit on = closed
508
509
510 //----------------------------------------------------------------------------
511 // extended slot status
512 //----------------------------------------------------------------------------
513 #define HPC_SLOT_PCIX 0x01
514 #define HPC_SLOT_SPEED1 0x02
515 #define HPC_SLOT_SPEED2 0x04
516 #define HPC_SLOT_BLINK_ATTN 0x08
517 #define HPC_SLOT_RSRVD1 0x10
518 #define HPC_SLOT_RSRVD2 0x20
519 #define HPC_SLOT_BUS_MODE 0x40
520 #define HPC_SLOT_RSRVD3 0x80
521
522 //----------------------------------------------------------------------------
523 // HPC_XSLOT_PCIX_CAP status return codes
524 //----------------------------------------------------------------------------
525 #define HPC_SLOT_PCIX_NO 0x00
526 #define HPC_SLOT_PCIX_YES 0x01
527
528 //----------------------------------------------------------------------------
529 // HPC_XSLOT_SPEED status return codes
530 //----------------------------------------------------------------------------
531 #define HPC_SLOT_SPEED_33 0x00
532 #define HPC_SLOT_SPEED_66 0x01
533 #define HPC_SLOT_SPEED_133 0x02
534
535 //----------------------------------------------------------------------------
536 // HPC_XSLOT_ATTN_BLINK status return codes
537 //----------------------------------------------------------------------------
538 #define HPC_SLOT_ATTN_BLINK_OFF 0x00
539 #define HPC_SLOT_ATTN_BLINK_ON 0x01
540
541 //----------------------------------------------------------------------------
542 // HPC_XSLOT_BUS_MODE status return codes
543 //----------------------------------------------------------------------------
544 #define HPC_SLOT_BUS_MODE_OK 0x00
545 #define HPC_SLOT_BUS_MODE_MISM 0x01
546
547 //----------------------------------------------------------------------------
548 // Controller status
549 //----------------------------------------------------------------------------
550 #define HPC_CTLR_WORKING 0x01
551 #define HPC_CTLR_FINISHED 0x02
552 #define HPC_CTLR_RESULT0 0x04
553 #define HPC_CTLR_RESULT1 0x08
554 #define HPC_CTLR_RESULE2 0x10
555 #define HPC_CTLR_RESULT3 0x20
556 #define HPC_CTLR_IRQ_ROUTG 0x40
557 #define HPC_CTLR_IRQ_PENDG 0x80
558
559 //----------------------------------------------------------------------------
560 // HPC_CTLR_WORKING status return codes
561 //----------------------------------------------------------------------------
562 #define HPC_CTLR_WORKING_NO 0x00
563 #define HPC_CTLR_WORKING_YES 0x01
564
565 //----------------------------------------------------------------------------
566 // HPC_CTLR_FINISHED status return codes
567 //----------------------------------------------------------------------------
568 #define HPC_CTLR_FINISHED_NO 0x00
569 #define HPC_CTLR_FINISHED_YES 0x01
570
571 //----------------------------------------------------------------------------
572 // HPC_CTLR_RESULT status return codes
573 //----------------------------------------------------------------------------
574 #define HPC_CTLR_RESULT_SUCCESS 0x00
575 #define HPC_CTLR_RESULT_FAILED 0x01
576 #define HPC_CTLR_RESULT_RSVD 0x02
577 #define HPC_CTLR_RESULT_NORESP 0x03
578
579
580 //----------------------------------------------------------------------------
581 // macro for slot info
582 //----------------------------------------------------------------------------
583 #define SLOT_POWER(s) ((u8) ((s & HPC_SLOT_POWER) \
584 ? HPC_SLOT_POWER_ON : HPC_SLOT_POWER_OFF))
585
586 #define SLOT_CONNECT(s) ((u8) ((s & HPC_SLOT_CONNECT) \
587 ? HPC_SLOT_DISCONNECTED : HPC_SLOT_CONNECTED))
588
589 #define SLOT_ATTN(s, es) ((u8) ((es & HPC_SLOT_BLINK_ATTN) \
590 ? HPC_SLOT_ATTN_BLINK \
591 : ((s & HPC_SLOT_ATTN) ? HPC_SLOT_ATTN_ON : HPC_SLOT_ATTN_OFF)))
592
593 #define SLOT_PRESENT(s) ((u8) ((s & HPC_SLOT_PRSNT1) \
594 ? ((s & HPC_SLOT_PRSNT2) ? HPC_SLOT_EMPTY : HPC_SLOT_PRSNT_15) \
595 : ((s & HPC_SLOT_PRSNT2) ? HPC_SLOT_PRSNT_25 : HPC_SLOT_PRSNT_7)))
596
597 #define SLOT_PWRGD(s) ((u8) ((s & HPC_SLOT_PWRGD) \
598 ? HPC_SLOT_PWRGD_GOOD : HPC_SLOT_PWRGD_FAULT_NONE))
599
600 #define SLOT_BUS_SPEED(s) ((u8) ((s & HPC_SLOT_BUS_SPEED) \
601 ? HPC_SLOT_BUS_SPEED_MISM : HPC_SLOT_BUS_SPEED_OK))
602
603 #define SLOT_LATCH(s) ((u8) ((s & HPC_SLOT_LATCH) \
604 ? HPC_SLOT_LATCH_CLOSED : HPC_SLOT_LATCH_OPEN))
605
606 #define SLOT_PCIX(es) ((u8) ((es & HPC_SLOT_PCIX) \
607 ? HPC_SLOT_PCIX_YES : HPC_SLOT_PCIX_NO))
608
609 #define SLOT_SPEED(es) ((u8) ((es & HPC_SLOT_SPEED2) \
610 ? ((es & HPC_SLOT_SPEED1) ? HPC_SLOT_SPEED_133 \
611 : HPC_SLOT_SPEED_66) \
612 : HPC_SLOT_SPEED_33))
613
614 #define SLOT_BUS_MODE(es) ((u8) ((es & HPC_SLOT_BUS_MODE) \
615 ? HPC_SLOT_BUS_MODE_MISM : HPC_SLOT_BUS_MODE_OK))
616
617 //--------------------------------------------------------------------------
618 // macro for bus info
619 //---------------------------------------------------------------------------
620 #define CURRENT_BUS_SPEED(s) ((u8) (s & BUS_SPEED_2) \
621 ? ((s & BUS_SPEED_1) ? BUS_SPEED_133 : BUS_SPEED_100) \
622 : ((s & BUS_SPEED_1) ? BUS_SPEED_66 : BUS_SPEED_33))
623
624 #define CURRENT_BUS_MODE(s) ((u8) (s & BUS_MODE) ? BUS_MODE_PCIX : BUS_MODE_PCI)
625
626 #define READ_BUS_STATUS(s) ((u8) (s->options & BUS_STATUS_AVAILABLE))
627
628 #define READ_BUS_MODE(s) ((s->revision & PRGM_MODEL_REV_LEVEL) >= 0x20)
629
630 #define SET_BUS_STATUS(s) ((u8) (s->options & BUS_CONTROL_AVAILABLE))
631
632 #define READ_SLOT_LATCH(s) ((u8) (s->options & SLOT_LATCH_REGS_SUPPORTED))
633
634 //----------------------------------------------------------------------------
635 // macro for controller info
636 //----------------------------------------------------------------------------
637 #define CTLR_WORKING(c) ((u8) ((c & HPC_CTLR_WORKING) \
638 ? HPC_CTLR_WORKING_YES : HPC_CTLR_WORKING_NO))
639 #define CTLR_FINISHED(c) ((u8) ((c & HPC_CTLR_FINISHED) \
640 ? HPC_CTLR_FINISHED_YES : HPC_CTLR_FINISHED_NO))
641 #define CTLR_RESULT(c) ((u8) ((c & HPC_CTLR_RESULT1) \
642 ? ((c & HPC_CTLR_RESULT0) ? HPC_CTLR_RESULT_NORESP \
643 : HPC_CTLR_RESULT_RSVD) \
644 : ((c & HPC_CTLR_RESULT0) ? HPC_CTLR_RESULT_FAILED \
645 : HPC_CTLR_RESULT_SUCCESS)))
646
647 // command that affect the state machine of HPC
648 #define NEEDTOCHECK_CMDSTATUS(c) ((c == HPC_SLOT_OFF) || \
649 (c == HPC_SLOT_ON) || \
650 (c == HPC_CTLR_RESET) || \
651 (c == HPC_BUS_33CONVMODE) || \
652 (c == HPC_BUS_66CONVMODE) || \
653 (c == HPC_BUS_66PCIXMODE) || \
654 (c == HPC_BUS_100PCIXMODE) || \
655 (c == HPC_BUS_133PCIXMODE) || \
656 (c == HPC_ALLSLOT_OFF) || \
657 (c == HPC_ALLSLOT_ON))
658
659
660 /* Core part of the driver */
661
662 #define ENABLE 1
663 #define DISABLE 0
664
665 #define CARD_INFO 0x07
666 #define PCIX133 0x07
667 #define PCIX66 0x05
668 #define PCI66 0x04
669
670 extern struct pci_bus *ibmphp_pci_bus;
671
672 /* Variables */
673
674 struct pci_func {
675 struct pci_dev *dev; /* from the OS */
676 u8 busno;
677 u8 device;
678 u8 function;
679 struct resource_node *io[6];
680 struct resource_node *mem[6];
681 struct resource_node *pfmem[6];
682 struct pci_func *next;
683 int devices[32]; /* for bridge config */
684 u8 irq[4]; /* for interrupt config */
685 u8 bus; /* flag for unconfiguring, to say if PPB */
686 };
687
688 struct slot {
689 u8 bus;
690 u8 device;
691 u8 number;
692 u8 real_physical_slot_num;
693 u32 capabilities;
694 u8 supported_speed;
695 u8 supported_bus_mode;
696 u8 flag; /* this is for disable slot and polling */
697 u8 ctlr_index;
698 struct hotplug_slot hotplug_slot;
699 struct controller *ctrl;
700 struct pci_func *func;
701 u8 irq[4];
702 int bit_mode; /* 0 = 32, 1 = 64 */
703 struct bus_info *bus_on;
704 struct list_head ibm_slot_list;
705 u8 status;
706 u8 ext_status;
707 u8 busstatus;
708 };
709
710 struct controller {
711 struct ebda_hpc_slot *slots;
712 struct ebda_hpc_bus *buses;
713 struct pci_dev *ctrl_dev; /* in case where controller is PCI */
714 u8 starting_slot_num; /* starting and ending slot #'s this ctrl controls*/
715 u8 ending_slot_num;
716 u8 revision;
717 u8 options; /* which options HPC supports */
718 u8 status;
719 u8 ctlr_id;
720 u8 slot_count;
721 u8 bus_count;
722 u8 ctlr_relative_id;
723 u32 irq;
724 union {
725 struct isa_ctlr_access isa_ctlr;
726 struct pci_ctlr_access pci_ctlr;
727 struct wpeg_i2c_ctlr_access wpeg_ctlr;
728 } u;
729 u8 ctlr_type;
730 struct list_head ebda_hpc_list;
731 };
732
733 /* Functions */
734
735 int ibmphp_init_devno(struct slot **); /* This function is called from EBDA, so we need it not be static */
736 int ibmphp_do_disable_slot(struct slot *slot_cur);
737 int ibmphp_update_slot_info(struct slot *); /* This function is called from HPC, so we need it to not be static */
738 int ibmphp_configure_card(struct pci_func *, u8);
739 int ibmphp_unconfigure_card(struct slot **, int);
740 extern const struct hotplug_slot_ops ibmphp_hotplug_slot_ops;
741
to_slot(struct hotplug_slot * hotplug_slot)742 static inline struct slot *to_slot(struct hotplug_slot *hotplug_slot)
743 {
744 return container_of(hotplug_slot, struct slot, hotplug_slot);
745 }
746
747 #endif //__IBMPHP_H
748
749