1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * PCI EPF driver for MHI Endpoint devices 4 * 5 * Copyright (C) 2023 Linaro Ltd. 6 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> 7 */ 8 9 #include <linux/mhi_ep.h> 10 #include <linux/module.h> 11 #include <linux/platform_device.h> 12 #include <linux/pci-epc.h> 13 #include <linux/pci-epf.h> 14 15 #define MHI_VERSION_1_0 0x01000000 16 17 #define to_epf_mhi(cntrl) container_of(cntrl, struct pci_epf_mhi, cntrl) 18 19 struct pci_epf_mhi_ep_info { 20 const struct mhi_ep_cntrl_config *config; 21 struct pci_epf_header *epf_header; 22 enum pci_barno bar_num; 23 u32 epf_flags; 24 u32 msi_count; 25 u32 mru; 26 }; 27 28 #define MHI_EP_CHANNEL_CONFIG(ch_num, ch_name, direction) \ 29 { \ 30 .num = ch_num, \ 31 .name = ch_name, \ 32 .dir = direction, \ 33 } 34 35 #define MHI_EP_CHANNEL_CONFIG_UL(ch_num, ch_name) \ 36 MHI_EP_CHANNEL_CONFIG(ch_num, ch_name, DMA_TO_DEVICE) 37 38 #define MHI_EP_CHANNEL_CONFIG_DL(ch_num, ch_name) \ 39 MHI_EP_CHANNEL_CONFIG(ch_num, ch_name, DMA_FROM_DEVICE) 40 41 static const struct mhi_ep_channel_config mhi_v1_channels[] = { 42 MHI_EP_CHANNEL_CONFIG_UL(0, "LOOPBACK"), 43 MHI_EP_CHANNEL_CONFIG_DL(1, "LOOPBACK"), 44 MHI_EP_CHANNEL_CONFIG_UL(2, "SAHARA"), 45 MHI_EP_CHANNEL_CONFIG_DL(3, "SAHARA"), 46 MHI_EP_CHANNEL_CONFIG_UL(4, "DIAG"), 47 MHI_EP_CHANNEL_CONFIG_DL(5, "DIAG"), 48 MHI_EP_CHANNEL_CONFIG_UL(6, "SSR"), 49 MHI_EP_CHANNEL_CONFIG_DL(7, "SSR"), 50 MHI_EP_CHANNEL_CONFIG_UL(8, "QDSS"), 51 MHI_EP_CHANNEL_CONFIG_DL(9, "QDSS"), 52 MHI_EP_CHANNEL_CONFIG_UL(10, "EFS"), 53 MHI_EP_CHANNEL_CONFIG_DL(11, "EFS"), 54 MHI_EP_CHANNEL_CONFIG_UL(12, "MBIM"), 55 MHI_EP_CHANNEL_CONFIG_DL(13, "MBIM"), 56 MHI_EP_CHANNEL_CONFIG_UL(14, "QMI"), 57 MHI_EP_CHANNEL_CONFIG_DL(15, "QMI"), 58 MHI_EP_CHANNEL_CONFIG_UL(16, "QMI"), 59 MHI_EP_CHANNEL_CONFIG_DL(17, "QMI"), 60 MHI_EP_CHANNEL_CONFIG_UL(18, "IP-CTRL-1"), 61 MHI_EP_CHANNEL_CONFIG_DL(19, "IP-CTRL-1"), 62 MHI_EP_CHANNEL_CONFIG_UL(20, "IPCR"), 63 MHI_EP_CHANNEL_CONFIG_DL(21, "IPCR"), 64 MHI_EP_CHANNEL_CONFIG_UL(32, "DUN"), 65 MHI_EP_CHANNEL_CONFIG_DL(33, "DUN"), 66 MHI_EP_CHANNEL_CONFIG_UL(46, "IP_SW0"), 67 MHI_EP_CHANNEL_CONFIG_DL(47, "IP_SW0"), 68 }; 69 70 static const struct mhi_ep_cntrl_config mhi_v1_config = { 71 .max_channels = 128, 72 .num_channels = ARRAY_SIZE(mhi_v1_channels), 73 .ch_cfg = mhi_v1_channels, 74 .mhi_version = MHI_VERSION_1_0, 75 }; 76 77 static struct pci_epf_header sdx55_header = { 78 .vendorid = PCI_VENDOR_ID_QCOM, 79 .deviceid = 0x0306, 80 .baseclass_code = PCI_BASE_CLASS_COMMUNICATION, 81 .subclass_code = PCI_CLASS_COMMUNICATION_MODEM & 0xff, 82 .interrupt_pin = PCI_INTERRUPT_INTA, 83 }; 84 85 static const struct pci_epf_mhi_ep_info sdx55_info = { 86 .config = &mhi_v1_config, 87 .epf_header = &sdx55_header, 88 .bar_num = BAR_0, 89 .epf_flags = PCI_BASE_ADDRESS_MEM_TYPE_32, 90 .msi_count = 32, 91 .mru = 0x8000, 92 }; 93 94 struct pci_epf_mhi { 95 const struct pci_epf_mhi_ep_info *info; 96 struct mhi_ep_cntrl mhi_cntrl; 97 struct pci_epf *epf; 98 struct mutex lock; 99 void __iomem *mmio; 100 resource_size_t mmio_phys; 101 u32 mmio_size; 102 int irq; 103 }; 104 105 static int __pci_epf_mhi_alloc_map(struct mhi_ep_cntrl *mhi_cntrl, u64 pci_addr, 106 phys_addr_t *paddr, void __iomem **vaddr, 107 size_t offset, size_t size) 108 { 109 struct pci_epf_mhi *epf_mhi = to_epf_mhi(mhi_cntrl); 110 struct pci_epf *epf = epf_mhi->epf; 111 struct pci_epc *epc = epf->epc; 112 int ret; 113 114 *vaddr = pci_epc_mem_alloc_addr(epc, paddr, size + offset); 115 if (!*vaddr) 116 return -ENOMEM; 117 118 ret = pci_epc_map_addr(epc, epf->func_no, epf->vfunc_no, *paddr, 119 pci_addr - offset, size + offset); 120 if (ret) { 121 pci_epc_mem_free_addr(epc, *paddr, *vaddr, size + offset); 122 return ret; 123 } 124 125 *paddr = *paddr + offset; 126 *vaddr = *vaddr + offset; 127 128 return 0; 129 } 130 131 static int pci_epf_mhi_alloc_map(struct mhi_ep_cntrl *mhi_cntrl, u64 pci_addr, 132 phys_addr_t *paddr, void __iomem **vaddr, 133 size_t size) 134 { 135 struct pci_epf_mhi *epf_mhi = to_epf_mhi(mhi_cntrl); 136 struct pci_epc *epc = epf_mhi->epf->epc; 137 size_t offset = pci_addr & (epc->mem->window.page_size - 1); 138 139 return __pci_epf_mhi_alloc_map(mhi_cntrl, pci_addr, paddr, vaddr, 140 offset, size); 141 } 142 143 static void __pci_epf_mhi_unmap_free(struct mhi_ep_cntrl *mhi_cntrl, 144 u64 pci_addr, phys_addr_t paddr, 145 void __iomem *vaddr, size_t offset, 146 size_t size) 147 { 148 struct pci_epf_mhi *epf_mhi = to_epf_mhi(mhi_cntrl); 149 struct pci_epf *epf = epf_mhi->epf; 150 struct pci_epc *epc = epf->epc; 151 152 pci_epc_unmap_addr(epc, epf->func_no, epf->vfunc_no, paddr - offset); 153 pci_epc_mem_free_addr(epc, paddr - offset, vaddr - offset, 154 size + offset); 155 } 156 157 static void pci_epf_mhi_unmap_free(struct mhi_ep_cntrl *mhi_cntrl, u64 pci_addr, 158 phys_addr_t paddr, void __iomem *vaddr, 159 size_t size) 160 { 161 struct pci_epf_mhi *epf_mhi = to_epf_mhi(mhi_cntrl); 162 struct pci_epf *epf = epf_mhi->epf; 163 struct pci_epc *epc = epf->epc; 164 size_t offset = pci_addr & (epc->mem->window.page_size - 1); 165 166 __pci_epf_mhi_unmap_free(mhi_cntrl, pci_addr, paddr, vaddr, offset, 167 size); 168 } 169 170 static void pci_epf_mhi_raise_irq(struct mhi_ep_cntrl *mhi_cntrl, u32 vector) 171 { 172 struct pci_epf_mhi *epf_mhi = to_epf_mhi(mhi_cntrl); 173 struct pci_epf *epf = epf_mhi->epf; 174 struct pci_epc *epc = epf->epc; 175 176 /* 177 * MHI supplies 0 based MSI vectors but the API expects the vector 178 * number to start from 1, so we need to increment the vector by 1. 179 */ 180 pci_epc_raise_irq(epc, epf->func_no, epf->vfunc_no, PCI_EPC_IRQ_MSI, 181 vector + 1); 182 } 183 184 static int pci_epf_mhi_read_from_host(struct mhi_ep_cntrl *mhi_cntrl, u64 from, 185 void *to, size_t size) 186 { 187 struct pci_epf_mhi *epf_mhi = to_epf_mhi(mhi_cntrl); 188 size_t offset = from % SZ_4K; 189 void __iomem *tre_buf; 190 phys_addr_t tre_phys; 191 int ret; 192 193 mutex_lock(&epf_mhi->lock); 194 195 ret = __pci_epf_mhi_alloc_map(mhi_cntrl, from, &tre_phys, &tre_buf, 196 offset, size); 197 if (ret) { 198 mutex_unlock(&epf_mhi->lock); 199 return ret; 200 } 201 202 memcpy_fromio(to, tre_buf, size); 203 204 __pci_epf_mhi_unmap_free(mhi_cntrl, from, tre_phys, tre_buf, offset, 205 size); 206 207 mutex_unlock(&epf_mhi->lock); 208 209 return 0; 210 } 211 212 static int pci_epf_mhi_write_to_host(struct mhi_ep_cntrl *mhi_cntrl, 213 void *from, u64 to, size_t size) 214 { 215 struct pci_epf_mhi *epf_mhi = to_epf_mhi(mhi_cntrl); 216 size_t offset = to % SZ_4K; 217 void __iomem *tre_buf; 218 phys_addr_t tre_phys; 219 int ret; 220 221 mutex_lock(&epf_mhi->lock); 222 223 ret = __pci_epf_mhi_alloc_map(mhi_cntrl, to, &tre_phys, &tre_buf, 224 offset, size); 225 if (ret) { 226 mutex_unlock(&epf_mhi->lock); 227 return ret; 228 } 229 230 memcpy_toio(tre_buf, from, size); 231 232 __pci_epf_mhi_unmap_free(mhi_cntrl, to, tre_phys, tre_buf, offset, 233 size); 234 235 mutex_unlock(&epf_mhi->lock); 236 237 return 0; 238 } 239 240 static int pci_epf_mhi_core_init(struct pci_epf *epf) 241 { 242 struct pci_epf_mhi *epf_mhi = epf_get_drvdata(epf); 243 const struct pci_epf_mhi_ep_info *info = epf_mhi->info; 244 struct pci_epf_bar *epf_bar = &epf->bar[info->bar_num]; 245 struct pci_epc *epc = epf->epc; 246 struct device *dev = &epf->dev; 247 int ret; 248 249 epf_bar->phys_addr = epf_mhi->mmio_phys; 250 epf_bar->size = epf_mhi->mmio_size; 251 epf_bar->barno = info->bar_num; 252 epf_bar->flags = info->epf_flags; 253 ret = pci_epc_set_bar(epc, epf->func_no, epf->vfunc_no, epf_bar); 254 if (ret) { 255 dev_err(dev, "Failed to set BAR: %d\n", ret); 256 return ret; 257 } 258 259 ret = pci_epc_set_msi(epc, epf->func_no, epf->vfunc_no, 260 order_base_2(info->msi_count)); 261 if (ret) { 262 dev_err(dev, "Failed to set MSI configuration: %d\n", ret); 263 return ret; 264 } 265 266 ret = pci_epc_write_header(epc, epf->func_no, epf->vfunc_no, 267 epf->header); 268 if (ret) { 269 dev_err(dev, "Failed to set Configuration header: %d\n", ret); 270 return ret; 271 } 272 273 return 0; 274 } 275 276 static int pci_epf_mhi_link_up(struct pci_epf *epf) 277 { 278 struct pci_epf_mhi *epf_mhi = epf_get_drvdata(epf); 279 const struct pci_epf_mhi_ep_info *info = epf_mhi->info; 280 struct mhi_ep_cntrl *mhi_cntrl = &epf_mhi->mhi_cntrl; 281 struct pci_epc *epc = epf->epc; 282 struct device *dev = &epf->dev; 283 int ret; 284 285 mhi_cntrl->mmio = epf_mhi->mmio; 286 mhi_cntrl->irq = epf_mhi->irq; 287 mhi_cntrl->mru = info->mru; 288 289 /* Assign the struct dev of PCI EP as MHI controller device */ 290 mhi_cntrl->cntrl_dev = epc->dev.parent; 291 mhi_cntrl->raise_irq = pci_epf_mhi_raise_irq; 292 mhi_cntrl->alloc_map = pci_epf_mhi_alloc_map; 293 mhi_cntrl->unmap_free = pci_epf_mhi_unmap_free; 294 mhi_cntrl->read_from_host = pci_epf_mhi_read_from_host; 295 mhi_cntrl->write_to_host = pci_epf_mhi_write_to_host; 296 297 /* Register the MHI EP controller */ 298 ret = mhi_ep_register_controller(mhi_cntrl, info->config); 299 if (ret) { 300 dev_err(dev, "Failed to register MHI EP controller: %d\n", ret); 301 return ret; 302 } 303 304 return 0; 305 } 306 307 static int pci_epf_mhi_link_down(struct pci_epf *epf) 308 { 309 struct pci_epf_mhi *epf_mhi = epf_get_drvdata(epf); 310 struct mhi_ep_cntrl *mhi_cntrl = &epf_mhi->mhi_cntrl; 311 312 if (mhi_cntrl->mhi_dev) { 313 mhi_ep_power_down(mhi_cntrl); 314 mhi_ep_unregister_controller(mhi_cntrl); 315 } 316 317 return 0; 318 } 319 320 static int pci_epf_mhi_bme(struct pci_epf *epf) 321 { 322 struct pci_epf_mhi *epf_mhi = epf_get_drvdata(epf); 323 struct mhi_ep_cntrl *mhi_cntrl = &epf_mhi->mhi_cntrl; 324 struct device *dev = &epf->dev; 325 int ret; 326 327 /* 328 * Power up the MHI EP stack if link is up and stack is in power down 329 * state. 330 */ 331 if (!mhi_cntrl->enabled && mhi_cntrl->mhi_dev) { 332 ret = mhi_ep_power_up(mhi_cntrl); 333 if (ret) { 334 dev_err(dev, "Failed to power up MHI EP: %d\n", ret); 335 mhi_ep_unregister_controller(mhi_cntrl); 336 } 337 } 338 339 return 0; 340 } 341 342 static int pci_epf_mhi_bind(struct pci_epf *epf) 343 { 344 struct pci_epf_mhi *epf_mhi = epf_get_drvdata(epf); 345 struct pci_epc *epc = epf->epc; 346 struct platform_device *pdev = to_platform_device(epc->dev.parent); 347 struct resource *res; 348 int ret; 349 350 /* Get MMIO base address from Endpoint controller */ 351 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mmio"); 352 epf_mhi->mmio_phys = res->start; 353 epf_mhi->mmio_size = resource_size(res); 354 355 epf_mhi->mmio = ioremap(epf_mhi->mmio_phys, epf_mhi->mmio_size); 356 if (!epf_mhi->mmio) 357 return -ENOMEM; 358 359 ret = platform_get_irq_byname(pdev, "doorbell"); 360 if (ret < 0) { 361 iounmap(epf_mhi->mmio); 362 return ret; 363 } 364 365 epf_mhi->irq = ret; 366 367 return 0; 368 } 369 370 static void pci_epf_mhi_unbind(struct pci_epf *epf) 371 { 372 struct pci_epf_mhi *epf_mhi = epf_get_drvdata(epf); 373 const struct pci_epf_mhi_ep_info *info = epf_mhi->info; 374 struct pci_epf_bar *epf_bar = &epf->bar[info->bar_num]; 375 struct mhi_ep_cntrl *mhi_cntrl = &epf_mhi->mhi_cntrl; 376 struct pci_epc *epc = epf->epc; 377 378 /* 379 * Forcefully power down the MHI EP stack. Only way to bring the MHI EP 380 * stack back to working state after successive bind is by getting BME 381 * from host. 382 */ 383 if (mhi_cntrl->mhi_dev) { 384 mhi_ep_power_down(mhi_cntrl); 385 mhi_ep_unregister_controller(mhi_cntrl); 386 } 387 388 iounmap(epf_mhi->mmio); 389 pci_epc_clear_bar(epc, epf->func_no, epf->vfunc_no, epf_bar); 390 } 391 392 static struct pci_epc_event_ops pci_epf_mhi_event_ops = { 393 .core_init = pci_epf_mhi_core_init, 394 .link_up = pci_epf_mhi_link_up, 395 .link_down = pci_epf_mhi_link_down, 396 .bme = pci_epf_mhi_bme, 397 }; 398 399 static int pci_epf_mhi_probe(struct pci_epf *epf, 400 const struct pci_epf_device_id *id) 401 { 402 struct pci_epf_mhi_ep_info *info = 403 (struct pci_epf_mhi_ep_info *)id->driver_data; 404 struct pci_epf_mhi *epf_mhi; 405 struct device *dev = &epf->dev; 406 407 epf_mhi = devm_kzalloc(dev, sizeof(*epf_mhi), GFP_KERNEL); 408 if (!epf_mhi) 409 return -ENOMEM; 410 411 epf->header = info->epf_header; 412 epf_mhi->info = info; 413 epf_mhi->epf = epf; 414 415 epf->event_ops = &pci_epf_mhi_event_ops; 416 417 mutex_init(&epf_mhi->lock); 418 419 epf_set_drvdata(epf, epf_mhi); 420 421 return 0; 422 } 423 424 static const struct pci_epf_device_id pci_epf_mhi_ids[] = { 425 { 426 .name = "sdx55", .driver_data = (kernel_ulong_t)&sdx55_info, 427 }, 428 {}, 429 }; 430 431 static struct pci_epf_ops pci_epf_mhi_ops = { 432 .unbind = pci_epf_mhi_unbind, 433 .bind = pci_epf_mhi_bind, 434 }; 435 436 static struct pci_epf_driver pci_epf_mhi_driver = { 437 .driver.name = "pci_epf_mhi", 438 .probe = pci_epf_mhi_probe, 439 .id_table = pci_epf_mhi_ids, 440 .ops = &pci_epf_mhi_ops, 441 .owner = THIS_MODULE, 442 }; 443 444 static int __init pci_epf_mhi_init(void) 445 { 446 return pci_epf_register_driver(&pci_epf_mhi_driver); 447 } 448 module_init(pci_epf_mhi_init); 449 450 static void __exit pci_epf_mhi_exit(void) 451 { 452 pci_epf_unregister_driver(&pci_epf_mhi_driver); 453 } 454 module_exit(pci_epf_mhi_exit); 455 456 MODULE_DESCRIPTION("PCI EPF driver for MHI Endpoint devices"); 457 MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>"); 458 MODULE_LICENSE("GPL"); 459