1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Volume Management Device driver 4 * Copyright (c) 2015, Intel Corporation. 5 */ 6 7 #include <linux/device.h> 8 #include <linux/interrupt.h> 9 #include <linux/irq.h> 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/msi.h> 13 #include <linux/pci.h> 14 #include <linux/srcu.h> 15 #include <linux/rculist.h> 16 #include <linux/rcupdate.h> 17 18 #include <asm/irqdomain.h> 19 #include <asm/device.h> 20 #include <asm/msi.h> 21 #include <asm/msidef.h> 22 23 #define VMD_CFGBAR 0 24 #define VMD_MEMBAR1 2 25 #define VMD_MEMBAR2 4 26 27 #define PCI_REG_VMCAP 0x40 28 #define BUS_RESTRICT_CAP(vmcap) (vmcap & 0x1) 29 #define PCI_REG_VMCONFIG 0x44 30 #define BUS_RESTRICT_CFG(vmcfg) ((vmcfg >> 8) & 0x3) 31 #define PCI_REG_VMLOCK 0x70 32 #define MB2_SHADOW_EN(vmlock) (vmlock & 0x2) 33 34 #define MB2_SHADOW_OFFSET 0x2000 35 #define MB2_SHADOW_SIZE 16 36 37 enum vmd_features { 38 /* 39 * Device may contain registers which hint the physical location of the 40 * membars, in order to allow proper address translation during 41 * resource assignment to enable guest virtualization 42 */ 43 VMD_FEAT_HAS_MEMBAR_SHADOW = (1 << 0), 44 45 /* 46 * Device may provide root port configuration information which limits 47 * bus numbering 48 */ 49 VMD_FEAT_HAS_BUS_RESTRICTIONS = (1 << 1), 50 }; 51 52 /* 53 * Lock for manipulating VMD IRQ lists. 54 */ 55 static DEFINE_RAW_SPINLOCK(list_lock); 56 57 /** 58 * struct vmd_irq - private data to map driver IRQ to the VMD shared vector 59 * @node: list item for parent traversal. 60 * @irq: back pointer to parent. 61 * @enabled: true if driver enabled IRQ 62 * @virq: the virtual IRQ value provided to the requesting driver. 63 * 64 * Every MSI/MSI-X IRQ requested for a device in a VMD domain will be mapped to 65 * a VMD IRQ using this structure. 66 */ 67 struct vmd_irq { 68 struct list_head node; 69 struct vmd_irq_list *irq; 70 bool enabled; 71 unsigned int virq; 72 }; 73 74 /** 75 * struct vmd_irq_list - list of driver requested IRQs mapping to a VMD vector 76 * @irq_list: the list of irq's the VMD one demuxes to. 77 * @srcu: SRCU struct for local synchronization. 78 * @count: number of child IRQs assigned to this vector; used to track 79 * sharing. 80 */ 81 struct vmd_irq_list { 82 struct list_head irq_list; 83 struct srcu_struct srcu; 84 unsigned int count; 85 }; 86 87 struct vmd_dev { 88 struct pci_dev *dev; 89 90 spinlock_t cfg_lock; 91 char __iomem *cfgbar; 92 93 int msix_count; 94 struct vmd_irq_list *irqs; 95 96 struct pci_sysdata sysdata; 97 struct resource resources[3]; 98 struct irq_domain *irq_domain; 99 struct pci_bus *bus; 100 u8 busn_start; 101 }; 102 103 static inline struct vmd_dev *vmd_from_bus(struct pci_bus *bus) 104 { 105 return container_of(bus->sysdata, struct vmd_dev, sysdata); 106 } 107 108 static inline unsigned int index_from_irqs(struct vmd_dev *vmd, 109 struct vmd_irq_list *irqs) 110 { 111 return irqs - vmd->irqs; 112 } 113 114 /* 115 * Drivers managing a device in a VMD domain allocate their own IRQs as before, 116 * but the MSI entry for the hardware it's driving will be programmed with a 117 * destination ID for the VMD MSI-X table. The VMD muxes interrupts in its 118 * domain into one of its own, and the VMD driver de-muxes these for the 119 * handlers sharing that VMD IRQ. The vmd irq_domain provides the operations 120 * and irq_chip to set this up. 121 */ 122 static void vmd_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) 123 { 124 struct vmd_irq *vmdirq = data->chip_data; 125 struct vmd_irq_list *irq = vmdirq->irq; 126 struct vmd_dev *vmd = irq_data_get_irq_handler_data(data); 127 128 msg->address_hi = MSI_ADDR_BASE_HI; 129 msg->address_lo = MSI_ADDR_BASE_LO | 130 MSI_ADDR_DEST_ID(index_from_irqs(vmd, irq)); 131 msg->data = 0; 132 } 133 134 /* 135 * We rely on MSI_FLAG_USE_DEF_CHIP_OPS to set the IRQ mask/unmask ops. 136 */ 137 static void vmd_irq_enable(struct irq_data *data) 138 { 139 struct vmd_irq *vmdirq = data->chip_data; 140 unsigned long flags; 141 142 raw_spin_lock_irqsave(&list_lock, flags); 143 WARN_ON(vmdirq->enabled); 144 list_add_tail_rcu(&vmdirq->node, &vmdirq->irq->irq_list); 145 vmdirq->enabled = true; 146 raw_spin_unlock_irqrestore(&list_lock, flags); 147 148 data->chip->irq_unmask(data); 149 } 150 151 static void vmd_irq_disable(struct irq_data *data) 152 { 153 struct vmd_irq *vmdirq = data->chip_data; 154 unsigned long flags; 155 156 data->chip->irq_mask(data); 157 158 raw_spin_lock_irqsave(&list_lock, flags); 159 if (vmdirq->enabled) { 160 list_del_rcu(&vmdirq->node); 161 vmdirq->enabled = false; 162 } 163 raw_spin_unlock_irqrestore(&list_lock, flags); 164 } 165 166 /* 167 * XXX: Stubbed until we develop acceptable way to not create conflicts with 168 * other devices sharing the same vector. 169 */ 170 static int vmd_irq_set_affinity(struct irq_data *data, 171 const struct cpumask *dest, bool force) 172 { 173 return -EINVAL; 174 } 175 176 static struct irq_chip vmd_msi_controller = { 177 .name = "VMD-MSI", 178 .irq_enable = vmd_irq_enable, 179 .irq_disable = vmd_irq_disable, 180 .irq_compose_msi_msg = vmd_compose_msi_msg, 181 .irq_set_affinity = vmd_irq_set_affinity, 182 }; 183 184 static irq_hw_number_t vmd_get_hwirq(struct msi_domain_info *info, 185 msi_alloc_info_t *arg) 186 { 187 return 0; 188 } 189 190 /* 191 * XXX: We can be even smarter selecting the best IRQ once we solve the 192 * affinity problem. 193 */ 194 static struct vmd_irq_list *vmd_next_irq(struct vmd_dev *vmd, struct msi_desc *desc) 195 { 196 int i, best = 1; 197 unsigned long flags; 198 199 if (vmd->msix_count == 1) 200 return &vmd->irqs[0]; 201 202 /* 203 * White list for fast-interrupt handlers. All others will share the 204 * "slow" interrupt vector. 205 */ 206 switch (msi_desc_to_pci_dev(desc)->class) { 207 case PCI_CLASS_STORAGE_EXPRESS: 208 break; 209 default: 210 return &vmd->irqs[0]; 211 } 212 213 raw_spin_lock_irqsave(&list_lock, flags); 214 for (i = 1; i < vmd->msix_count; i++) 215 if (vmd->irqs[i].count < vmd->irqs[best].count) 216 best = i; 217 vmd->irqs[best].count++; 218 raw_spin_unlock_irqrestore(&list_lock, flags); 219 220 return &vmd->irqs[best]; 221 } 222 223 static int vmd_msi_init(struct irq_domain *domain, struct msi_domain_info *info, 224 unsigned int virq, irq_hw_number_t hwirq, 225 msi_alloc_info_t *arg) 226 { 227 struct msi_desc *desc = arg->desc; 228 struct vmd_dev *vmd = vmd_from_bus(msi_desc_to_pci_dev(desc)->bus); 229 struct vmd_irq *vmdirq = kzalloc(sizeof(*vmdirq), GFP_KERNEL); 230 unsigned int index, vector; 231 232 if (!vmdirq) 233 return -ENOMEM; 234 235 INIT_LIST_HEAD(&vmdirq->node); 236 vmdirq->irq = vmd_next_irq(vmd, desc); 237 vmdirq->virq = virq; 238 index = index_from_irqs(vmd, vmdirq->irq); 239 vector = pci_irq_vector(vmd->dev, index); 240 241 irq_domain_set_info(domain, virq, vector, info->chip, vmdirq, 242 handle_untracked_irq, vmd, NULL); 243 return 0; 244 } 245 246 static void vmd_msi_free(struct irq_domain *domain, 247 struct msi_domain_info *info, unsigned int virq) 248 { 249 struct vmd_irq *vmdirq = irq_get_chip_data(virq); 250 unsigned long flags; 251 252 synchronize_srcu(&vmdirq->irq->srcu); 253 254 /* XXX: Potential optimization to rebalance */ 255 raw_spin_lock_irqsave(&list_lock, flags); 256 vmdirq->irq->count--; 257 raw_spin_unlock_irqrestore(&list_lock, flags); 258 259 kfree(vmdirq); 260 } 261 262 static int vmd_msi_prepare(struct irq_domain *domain, struct device *dev, 263 int nvec, msi_alloc_info_t *arg) 264 { 265 struct pci_dev *pdev = to_pci_dev(dev); 266 struct vmd_dev *vmd = vmd_from_bus(pdev->bus); 267 268 if (nvec > vmd->msix_count) 269 return vmd->msix_count; 270 271 memset(arg, 0, sizeof(*arg)); 272 return 0; 273 } 274 275 static void vmd_set_desc(msi_alloc_info_t *arg, struct msi_desc *desc) 276 { 277 arg->desc = desc; 278 } 279 280 static struct msi_domain_ops vmd_msi_domain_ops = { 281 .get_hwirq = vmd_get_hwirq, 282 .msi_init = vmd_msi_init, 283 .msi_free = vmd_msi_free, 284 .msi_prepare = vmd_msi_prepare, 285 .set_desc = vmd_set_desc, 286 }; 287 288 static struct msi_domain_info vmd_msi_domain_info = { 289 .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 290 MSI_FLAG_PCI_MSIX, 291 .ops = &vmd_msi_domain_ops, 292 .chip = &vmd_msi_controller, 293 }; 294 295 static char __iomem *vmd_cfg_addr(struct vmd_dev *vmd, struct pci_bus *bus, 296 unsigned int devfn, int reg, int len) 297 { 298 char __iomem *addr = vmd->cfgbar + 299 ((bus->number - vmd->busn_start) << 20) + 300 (devfn << 12) + reg; 301 302 if ((addr - vmd->cfgbar) + len >= 303 resource_size(&vmd->dev->resource[VMD_CFGBAR])) 304 return NULL; 305 306 return addr; 307 } 308 309 /* 310 * CPU may deadlock if config space is not serialized on some versions of this 311 * hardware, so all config space access is done under a spinlock. 312 */ 313 static int vmd_pci_read(struct pci_bus *bus, unsigned int devfn, int reg, 314 int len, u32 *value) 315 { 316 struct vmd_dev *vmd = vmd_from_bus(bus); 317 char __iomem *addr = vmd_cfg_addr(vmd, bus, devfn, reg, len); 318 unsigned long flags; 319 int ret = 0; 320 321 if (!addr) 322 return -EFAULT; 323 324 spin_lock_irqsave(&vmd->cfg_lock, flags); 325 switch (len) { 326 case 1: 327 *value = readb(addr); 328 break; 329 case 2: 330 *value = readw(addr); 331 break; 332 case 4: 333 *value = readl(addr); 334 break; 335 default: 336 ret = -EINVAL; 337 break; 338 } 339 spin_unlock_irqrestore(&vmd->cfg_lock, flags); 340 return ret; 341 } 342 343 /* 344 * VMD h/w converts non-posted config writes to posted memory writes. The 345 * read-back in this function forces the completion so it returns only after 346 * the config space was written, as expected. 347 */ 348 static int vmd_pci_write(struct pci_bus *bus, unsigned int devfn, int reg, 349 int len, u32 value) 350 { 351 struct vmd_dev *vmd = vmd_from_bus(bus); 352 char __iomem *addr = vmd_cfg_addr(vmd, bus, devfn, reg, len); 353 unsigned long flags; 354 int ret = 0; 355 356 if (!addr) 357 return -EFAULT; 358 359 spin_lock_irqsave(&vmd->cfg_lock, flags); 360 switch (len) { 361 case 1: 362 writeb(value, addr); 363 readb(addr); 364 break; 365 case 2: 366 writew(value, addr); 367 readw(addr); 368 break; 369 case 4: 370 writel(value, addr); 371 readl(addr); 372 break; 373 default: 374 ret = -EINVAL; 375 break; 376 } 377 spin_unlock_irqrestore(&vmd->cfg_lock, flags); 378 return ret; 379 } 380 381 static struct pci_ops vmd_ops = { 382 .read = vmd_pci_read, 383 .write = vmd_pci_write, 384 }; 385 386 static void vmd_attach_resources(struct vmd_dev *vmd) 387 { 388 vmd->dev->resource[VMD_MEMBAR1].child = &vmd->resources[1]; 389 vmd->dev->resource[VMD_MEMBAR2].child = &vmd->resources[2]; 390 } 391 392 static void vmd_detach_resources(struct vmd_dev *vmd) 393 { 394 vmd->dev->resource[VMD_MEMBAR1].child = NULL; 395 vmd->dev->resource[VMD_MEMBAR2].child = NULL; 396 } 397 398 /* 399 * VMD domains start at 0x10000 to not clash with ACPI _SEG domains. 400 * Per ACPI r6.0, sec 6.5.6, _SEG returns an integer, of which the lower 401 * 16 bits are the PCI Segment Group (domain) number. Other bits are 402 * currently reserved. 403 */ 404 static int vmd_find_free_domain(void) 405 { 406 int domain = 0xffff; 407 struct pci_bus *bus = NULL; 408 409 while ((bus = pci_find_next_bus(bus)) != NULL) 410 domain = max_t(int, domain, pci_domain_nr(bus)); 411 return domain + 1; 412 } 413 414 static int vmd_enable_domain(struct vmd_dev *vmd, unsigned long features) 415 { 416 struct pci_sysdata *sd = &vmd->sysdata; 417 struct fwnode_handle *fn; 418 struct resource *res; 419 u32 upper_bits; 420 unsigned long flags; 421 LIST_HEAD(resources); 422 resource_size_t offset[2] = {0}; 423 resource_size_t membar2_offset = 0x2000; 424 struct pci_bus *child; 425 426 /* 427 * Shadow registers may exist in certain VMD device ids which allow 428 * guests to correctly assign host physical addresses to the root ports 429 * and child devices. These registers will either return the host value 430 * or 0, depending on an enable bit in the VMD device. 431 */ 432 if (features & VMD_FEAT_HAS_MEMBAR_SHADOW) { 433 u32 vmlock; 434 int ret; 435 436 membar2_offset = MB2_SHADOW_OFFSET + MB2_SHADOW_SIZE; 437 ret = pci_read_config_dword(vmd->dev, PCI_REG_VMLOCK, &vmlock); 438 if (ret || vmlock == ~0) 439 return -ENODEV; 440 441 if (MB2_SHADOW_EN(vmlock)) { 442 void __iomem *membar2; 443 444 membar2 = pci_iomap(vmd->dev, VMD_MEMBAR2, 0); 445 if (!membar2) 446 return -ENOMEM; 447 offset[0] = vmd->dev->resource[VMD_MEMBAR1].start - 448 (readq(membar2 + MB2_SHADOW_OFFSET) & 449 PCI_BASE_ADDRESS_MEM_MASK); 450 offset[1] = vmd->dev->resource[VMD_MEMBAR2].start - 451 (readq(membar2 + MB2_SHADOW_OFFSET + 8) & 452 PCI_BASE_ADDRESS_MEM_MASK); 453 pci_iounmap(vmd->dev, membar2); 454 } 455 } 456 457 /* 458 * Certain VMD devices may have a root port configuration option which 459 * limits the bus range to between 0-127, 128-255, or 224-255 460 */ 461 if (features & VMD_FEAT_HAS_BUS_RESTRICTIONS) { 462 u16 reg16; 463 464 pci_read_config_word(vmd->dev, PCI_REG_VMCAP, ®16); 465 if (BUS_RESTRICT_CAP(reg16)) { 466 pci_read_config_word(vmd->dev, PCI_REG_VMCONFIG, 467 ®16); 468 469 switch (BUS_RESTRICT_CFG(reg16)) { 470 case 1: 471 vmd->busn_start = 128; 472 break; 473 case 2: 474 vmd->busn_start = 224; 475 break; 476 case 3: 477 pci_err(vmd->dev, "Unknown Bus Offset Setting\n"); 478 return -ENODEV; 479 default: 480 break; 481 } 482 } 483 } 484 485 res = &vmd->dev->resource[VMD_CFGBAR]; 486 vmd->resources[0] = (struct resource) { 487 .name = "VMD CFGBAR", 488 .start = vmd->busn_start, 489 .end = vmd->busn_start + (resource_size(res) >> 20) - 1, 490 .flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED, 491 }; 492 493 /* 494 * If the window is below 4GB, clear IORESOURCE_MEM_64 so we can 495 * put 32-bit resources in the window. 496 * 497 * There's no hardware reason why a 64-bit window *couldn't* 498 * contain a 32-bit resource, but pbus_size_mem() computes the 499 * bridge window size assuming a 64-bit window will contain no 500 * 32-bit resources. __pci_assign_resource() enforces that 501 * artificial restriction to make sure everything will fit. 502 * 503 * The only way we could use a 64-bit non-prefetchable MEMBAR is 504 * if its address is <4GB so that we can convert it to a 32-bit 505 * resource. To be visible to the host OS, all VMD endpoints must 506 * be initially configured by platform BIOS, which includes setting 507 * up these resources. We can assume the device is configured 508 * according to the platform needs. 509 */ 510 res = &vmd->dev->resource[VMD_MEMBAR1]; 511 upper_bits = upper_32_bits(res->end); 512 flags = res->flags & ~IORESOURCE_SIZEALIGN; 513 if (!upper_bits) 514 flags &= ~IORESOURCE_MEM_64; 515 vmd->resources[1] = (struct resource) { 516 .name = "VMD MEMBAR1", 517 .start = res->start, 518 .end = res->end, 519 .flags = flags, 520 .parent = res, 521 }; 522 523 res = &vmd->dev->resource[VMD_MEMBAR2]; 524 upper_bits = upper_32_bits(res->end); 525 flags = res->flags & ~IORESOURCE_SIZEALIGN; 526 if (!upper_bits) 527 flags &= ~IORESOURCE_MEM_64; 528 vmd->resources[2] = (struct resource) { 529 .name = "VMD MEMBAR2", 530 .start = res->start + membar2_offset, 531 .end = res->end, 532 .flags = flags, 533 .parent = res, 534 }; 535 536 sd->vmd_dev = vmd->dev; 537 sd->domain = vmd_find_free_domain(); 538 if (sd->domain < 0) 539 return sd->domain; 540 541 sd->node = pcibus_to_node(vmd->dev->bus); 542 543 fn = irq_domain_alloc_named_id_fwnode("VMD-MSI", vmd->sysdata.domain); 544 if (!fn) 545 return -ENODEV; 546 547 vmd->irq_domain = pci_msi_create_irq_domain(fn, &vmd_msi_domain_info, 548 x86_vector_domain); 549 irq_domain_free_fwnode(fn); 550 if (!vmd->irq_domain) 551 return -ENODEV; 552 553 pci_add_resource(&resources, &vmd->resources[0]); 554 pci_add_resource_offset(&resources, &vmd->resources[1], offset[0]); 555 pci_add_resource_offset(&resources, &vmd->resources[2], offset[1]); 556 557 vmd->bus = pci_create_root_bus(&vmd->dev->dev, vmd->busn_start, 558 &vmd_ops, sd, &resources); 559 if (!vmd->bus) { 560 pci_free_resource_list(&resources); 561 irq_domain_remove(vmd->irq_domain); 562 return -ENODEV; 563 } 564 565 vmd_attach_resources(vmd); 566 dev_set_msi_domain(&vmd->bus->dev, vmd->irq_domain); 567 568 pci_scan_child_bus(vmd->bus); 569 pci_assign_unassigned_bus_resources(vmd->bus); 570 571 /* 572 * VMD root buses are virtual and don't return true on pci_is_pcie() 573 * and will fail pcie_bus_configure_settings() early. It can instead be 574 * run on each of the real root ports. 575 */ 576 list_for_each_entry(child, &vmd->bus->children, node) 577 pcie_bus_configure_settings(child); 578 579 pci_bus_add_devices(vmd->bus); 580 581 WARN(sysfs_create_link(&vmd->dev->dev.kobj, &vmd->bus->dev.kobj, 582 "domain"), "Can't create symlink to domain\n"); 583 return 0; 584 } 585 586 static irqreturn_t vmd_irq(int irq, void *data) 587 { 588 struct vmd_irq_list *irqs = data; 589 struct vmd_irq *vmdirq; 590 int idx; 591 592 idx = srcu_read_lock(&irqs->srcu); 593 list_for_each_entry_rcu(vmdirq, &irqs->irq_list, node) 594 generic_handle_irq(vmdirq->virq); 595 srcu_read_unlock(&irqs->srcu, idx); 596 597 return IRQ_HANDLED; 598 } 599 600 static int vmd_probe(struct pci_dev *dev, const struct pci_device_id *id) 601 { 602 struct vmd_dev *vmd; 603 int i, err; 604 605 if (resource_size(&dev->resource[VMD_CFGBAR]) < (1 << 20)) 606 return -ENOMEM; 607 608 vmd = devm_kzalloc(&dev->dev, sizeof(*vmd), GFP_KERNEL); 609 if (!vmd) 610 return -ENOMEM; 611 612 vmd->dev = dev; 613 err = pcim_enable_device(dev); 614 if (err < 0) 615 return err; 616 617 vmd->cfgbar = pcim_iomap(dev, VMD_CFGBAR, 0); 618 if (!vmd->cfgbar) 619 return -ENOMEM; 620 621 pci_set_master(dev); 622 if (dma_set_mask_and_coherent(&dev->dev, DMA_BIT_MASK(64)) && 623 dma_set_mask_and_coherent(&dev->dev, DMA_BIT_MASK(32))) 624 return -ENODEV; 625 626 vmd->msix_count = pci_msix_vec_count(dev); 627 if (vmd->msix_count < 0) 628 return -ENODEV; 629 630 vmd->msix_count = pci_alloc_irq_vectors(dev, 1, vmd->msix_count, 631 PCI_IRQ_MSIX); 632 if (vmd->msix_count < 0) 633 return vmd->msix_count; 634 635 vmd->irqs = devm_kcalloc(&dev->dev, vmd->msix_count, sizeof(*vmd->irqs), 636 GFP_KERNEL); 637 if (!vmd->irqs) 638 return -ENOMEM; 639 640 for (i = 0; i < vmd->msix_count; i++) { 641 err = init_srcu_struct(&vmd->irqs[i].srcu); 642 if (err) 643 return err; 644 645 INIT_LIST_HEAD(&vmd->irqs[i].irq_list); 646 err = devm_request_irq(&dev->dev, pci_irq_vector(dev, i), 647 vmd_irq, IRQF_NO_THREAD, 648 "vmd", &vmd->irqs[i]); 649 if (err) 650 return err; 651 } 652 653 spin_lock_init(&vmd->cfg_lock); 654 pci_set_drvdata(dev, vmd); 655 err = vmd_enable_domain(vmd, (unsigned long) id->driver_data); 656 if (err) 657 return err; 658 659 dev_info(&vmd->dev->dev, "Bound to PCI domain %04x\n", 660 vmd->sysdata.domain); 661 return 0; 662 } 663 664 static void vmd_cleanup_srcu(struct vmd_dev *vmd) 665 { 666 int i; 667 668 for (i = 0; i < vmd->msix_count; i++) 669 cleanup_srcu_struct(&vmd->irqs[i].srcu); 670 } 671 672 static void vmd_remove(struct pci_dev *dev) 673 { 674 struct vmd_dev *vmd = pci_get_drvdata(dev); 675 676 sysfs_remove_link(&vmd->dev->dev.kobj, "domain"); 677 pci_stop_root_bus(vmd->bus); 678 pci_remove_root_bus(vmd->bus); 679 vmd_cleanup_srcu(vmd); 680 vmd_detach_resources(vmd); 681 irq_domain_remove(vmd->irq_domain); 682 } 683 684 #ifdef CONFIG_PM_SLEEP 685 static int vmd_suspend(struct device *dev) 686 { 687 struct pci_dev *pdev = to_pci_dev(dev); 688 struct vmd_dev *vmd = pci_get_drvdata(pdev); 689 int i; 690 691 for (i = 0; i < vmd->msix_count; i++) 692 devm_free_irq(dev, pci_irq_vector(pdev, i), &vmd->irqs[i]); 693 694 pci_save_state(pdev); 695 return 0; 696 } 697 698 static int vmd_resume(struct device *dev) 699 { 700 struct pci_dev *pdev = to_pci_dev(dev); 701 struct vmd_dev *vmd = pci_get_drvdata(pdev); 702 int err, i; 703 704 for (i = 0; i < vmd->msix_count; i++) { 705 err = devm_request_irq(dev, pci_irq_vector(pdev, i), 706 vmd_irq, IRQF_NO_THREAD, 707 "vmd", &vmd->irqs[i]); 708 if (err) 709 return err; 710 } 711 712 pci_restore_state(pdev); 713 return 0; 714 } 715 #endif 716 static SIMPLE_DEV_PM_OPS(vmd_dev_pm_ops, vmd_suspend, vmd_resume); 717 718 static const struct pci_device_id vmd_ids[] = { 719 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VMD_201D),}, 720 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VMD_28C0), 721 .driver_data = VMD_FEAT_HAS_MEMBAR_SHADOW | 722 VMD_FEAT_HAS_BUS_RESTRICTIONS,}, 723 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x467f), 724 .driver_data = VMD_FEAT_HAS_BUS_RESTRICTIONS,}, 725 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x4c3d), 726 .driver_data = VMD_FEAT_HAS_BUS_RESTRICTIONS,}, 727 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VMD_9A0B), 728 .driver_data = VMD_FEAT_HAS_BUS_RESTRICTIONS,}, 729 {0,} 730 }; 731 MODULE_DEVICE_TABLE(pci, vmd_ids); 732 733 static struct pci_driver vmd_drv = { 734 .name = "vmd", 735 .id_table = vmd_ids, 736 .probe = vmd_probe, 737 .remove = vmd_remove, 738 .driver = { 739 .pm = &vmd_dev_pm_ops, 740 }, 741 }; 742 module_pci_driver(vmd_drv); 743 744 MODULE_AUTHOR("Intel Corporation"); 745 MODULE_LICENSE("GPL v2"); 746 MODULE_VERSION("0.6"); 747