1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Volume Management Device driver 4 * Copyright (c) 2015, Intel Corporation. 5 */ 6 7 #include <linux/device.h> 8 #include <linux/interrupt.h> 9 #include <linux/irq.h> 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/msi.h> 13 #include <linux/pci.h> 14 #include <linux/pci-acpi.h> 15 #include <linux/pci-ecam.h> 16 #include <linux/srcu.h> 17 #include <linux/rculist.h> 18 #include <linux/rcupdate.h> 19 20 #include <asm/irqdomain.h> 21 22 #define VMD_CFGBAR 0 23 #define VMD_MEMBAR1 2 24 #define VMD_MEMBAR2 4 25 26 #define PCI_REG_VMCAP 0x40 27 #define BUS_RESTRICT_CAP(vmcap) (vmcap & 0x1) 28 #define PCI_REG_VMCONFIG 0x44 29 #define BUS_RESTRICT_CFG(vmcfg) ((vmcfg >> 8) & 0x3) 30 #define VMCONFIG_MSI_REMAP 0x2 31 #define PCI_REG_VMLOCK 0x70 32 #define MB2_SHADOW_EN(vmlock) (vmlock & 0x2) 33 34 #define MB2_SHADOW_OFFSET 0x2000 35 #define MB2_SHADOW_SIZE 16 36 37 enum vmd_features { 38 /* 39 * Device may contain registers which hint the physical location of the 40 * membars, in order to allow proper address translation during 41 * resource assignment to enable guest virtualization 42 */ 43 VMD_FEAT_HAS_MEMBAR_SHADOW = (1 << 0), 44 45 /* 46 * Device may provide root port configuration information which limits 47 * bus numbering 48 */ 49 VMD_FEAT_HAS_BUS_RESTRICTIONS = (1 << 1), 50 51 /* 52 * Device contains physical location shadow registers in 53 * vendor-specific capability space 54 */ 55 VMD_FEAT_HAS_MEMBAR_SHADOW_VSCAP = (1 << 2), 56 57 /* 58 * Device may use MSI-X vector 0 for software triggering and will not 59 * be used for MSI remapping 60 */ 61 VMD_FEAT_OFFSET_FIRST_VECTOR = (1 << 3), 62 63 /* 64 * Device can bypass remapping MSI-X transactions into its MSI-X table, 65 * avoiding the requirement of a VMD MSI domain for child device 66 * interrupt handling. 67 */ 68 VMD_FEAT_CAN_BYPASS_MSI_REMAP = (1 << 4), 69 70 /* 71 * Enable ASPM on the PCIE root ports and set the default LTR of the 72 * storage devices on platforms where these values are not configured by 73 * BIOS. This is needed for laptops, which require these settings for 74 * proper power management of the SoC. 75 */ 76 VMD_FEAT_BIOS_PM_QUIRK = (1 << 5), 77 }; 78 79 #define VMD_BIOS_PM_QUIRK_LTR 0x1003 /* 3145728 ns */ 80 81 #define VMD_FEATS_CLIENT (VMD_FEAT_HAS_MEMBAR_SHADOW_VSCAP | \ 82 VMD_FEAT_HAS_BUS_RESTRICTIONS | \ 83 VMD_FEAT_OFFSET_FIRST_VECTOR | \ 84 VMD_FEAT_BIOS_PM_QUIRK) 85 86 static DEFINE_IDA(vmd_instance_ida); 87 88 /* 89 * Lock for manipulating VMD IRQ lists. 90 */ 91 static DEFINE_RAW_SPINLOCK(list_lock); 92 93 /** 94 * struct vmd_irq - private data to map driver IRQ to the VMD shared vector 95 * @node: list item for parent traversal. 96 * @irq: back pointer to parent. 97 * @enabled: true if driver enabled IRQ 98 * @virq: the virtual IRQ value provided to the requesting driver. 99 * 100 * Every MSI/MSI-X IRQ requested for a device in a VMD domain will be mapped to 101 * a VMD IRQ using this structure. 102 */ 103 struct vmd_irq { 104 struct list_head node; 105 struct vmd_irq_list *irq; 106 bool enabled; 107 unsigned int virq; 108 }; 109 110 /** 111 * struct vmd_irq_list - list of driver requested IRQs mapping to a VMD vector 112 * @irq_list: the list of irq's the VMD one demuxes to. 113 * @srcu: SRCU struct for local synchronization. 114 * @count: number of child IRQs assigned to this vector; used to track 115 * sharing. 116 * @virq: The underlying VMD Linux interrupt number 117 */ 118 struct vmd_irq_list { 119 struct list_head irq_list; 120 struct srcu_struct srcu; 121 unsigned int count; 122 unsigned int virq; 123 }; 124 125 struct vmd_dev { 126 struct pci_dev *dev; 127 128 spinlock_t cfg_lock; 129 void __iomem *cfgbar; 130 131 int msix_count; 132 struct vmd_irq_list *irqs; 133 134 struct pci_sysdata sysdata; 135 struct resource resources[3]; 136 struct irq_domain *irq_domain; 137 struct pci_bus *bus; 138 u8 busn_start; 139 u8 first_vec; 140 char *name; 141 int instance; 142 }; 143 144 static inline struct vmd_dev *vmd_from_bus(struct pci_bus *bus) 145 { 146 return container_of(bus->sysdata, struct vmd_dev, sysdata); 147 } 148 149 static inline unsigned int index_from_irqs(struct vmd_dev *vmd, 150 struct vmd_irq_list *irqs) 151 { 152 return irqs - vmd->irqs; 153 } 154 155 /* 156 * Drivers managing a device in a VMD domain allocate their own IRQs as before, 157 * but the MSI entry for the hardware it's driving will be programmed with a 158 * destination ID for the VMD MSI-X table. The VMD muxes interrupts in its 159 * domain into one of its own, and the VMD driver de-muxes these for the 160 * handlers sharing that VMD IRQ. The vmd irq_domain provides the operations 161 * and irq_chip to set this up. 162 */ 163 static void vmd_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) 164 { 165 struct vmd_irq *vmdirq = data->chip_data; 166 struct vmd_irq_list *irq = vmdirq->irq; 167 struct vmd_dev *vmd = irq_data_get_irq_handler_data(data); 168 169 memset(msg, 0, sizeof(*msg)); 170 msg->address_hi = X86_MSI_BASE_ADDRESS_HIGH; 171 msg->arch_addr_lo.base_address = X86_MSI_BASE_ADDRESS_LOW; 172 msg->arch_addr_lo.destid_0_7 = index_from_irqs(vmd, irq); 173 } 174 175 /* 176 * We rely on MSI_FLAG_USE_DEF_CHIP_OPS to set the IRQ mask/unmask ops. 177 */ 178 static void vmd_irq_enable(struct irq_data *data) 179 { 180 struct vmd_irq *vmdirq = data->chip_data; 181 unsigned long flags; 182 183 raw_spin_lock_irqsave(&list_lock, flags); 184 WARN_ON(vmdirq->enabled); 185 list_add_tail_rcu(&vmdirq->node, &vmdirq->irq->irq_list); 186 vmdirq->enabled = true; 187 raw_spin_unlock_irqrestore(&list_lock, flags); 188 189 data->chip->irq_unmask(data); 190 } 191 192 static void vmd_irq_disable(struct irq_data *data) 193 { 194 struct vmd_irq *vmdirq = data->chip_data; 195 unsigned long flags; 196 197 data->chip->irq_mask(data); 198 199 raw_spin_lock_irqsave(&list_lock, flags); 200 if (vmdirq->enabled) { 201 list_del_rcu(&vmdirq->node); 202 vmdirq->enabled = false; 203 } 204 raw_spin_unlock_irqrestore(&list_lock, flags); 205 } 206 207 /* 208 * XXX: Stubbed until we develop acceptable way to not create conflicts with 209 * other devices sharing the same vector. 210 */ 211 static int vmd_irq_set_affinity(struct irq_data *data, 212 const struct cpumask *dest, bool force) 213 { 214 return -EINVAL; 215 } 216 217 static struct irq_chip vmd_msi_controller = { 218 .name = "VMD-MSI", 219 .irq_enable = vmd_irq_enable, 220 .irq_disable = vmd_irq_disable, 221 .irq_compose_msi_msg = vmd_compose_msi_msg, 222 .irq_set_affinity = vmd_irq_set_affinity, 223 }; 224 225 static irq_hw_number_t vmd_get_hwirq(struct msi_domain_info *info, 226 msi_alloc_info_t *arg) 227 { 228 return 0; 229 } 230 231 /* 232 * XXX: We can be even smarter selecting the best IRQ once we solve the 233 * affinity problem. 234 */ 235 static struct vmd_irq_list *vmd_next_irq(struct vmd_dev *vmd, struct msi_desc *desc) 236 { 237 unsigned long flags; 238 int i, best; 239 240 if (vmd->msix_count == 1 + vmd->first_vec) 241 return &vmd->irqs[vmd->first_vec]; 242 243 /* 244 * White list for fast-interrupt handlers. All others will share the 245 * "slow" interrupt vector. 246 */ 247 switch (msi_desc_to_pci_dev(desc)->class) { 248 case PCI_CLASS_STORAGE_EXPRESS: 249 break; 250 default: 251 return &vmd->irqs[vmd->first_vec]; 252 } 253 254 raw_spin_lock_irqsave(&list_lock, flags); 255 best = vmd->first_vec + 1; 256 for (i = best; i < vmd->msix_count; i++) 257 if (vmd->irqs[i].count < vmd->irqs[best].count) 258 best = i; 259 vmd->irqs[best].count++; 260 raw_spin_unlock_irqrestore(&list_lock, flags); 261 262 return &vmd->irqs[best]; 263 } 264 265 static int vmd_msi_init(struct irq_domain *domain, struct msi_domain_info *info, 266 unsigned int virq, irq_hw_number_t hwirq, 267 msi_alloc_info_t *arg) 268 { 269 struct msi_desc *desc = arg->desc; 270 struct vmd_dev *vmd = vmd_from_bus(msi_desc_to_pci_dev(desc)->bus); 271 struct vmd_irq *vmdirq = kzalloc(sizeof(*vmdirq), GFP_KERNEL); 272 273 if (!vmdirq) 274 return -ENOMEM; 275 276 INIT_LIST_HEAD(&vmdirq->node); 277 vmdirq->irq = vmd_next_irq(vmd, desc); 278 vmdirq->virq = virq; 279 280 irq_domain_set_info(domain, virq, vmdirq->irq->virq, info->chip, vmdirq, 281 handle_untracked_irq, vmd, NULL); 282 return 0; 283 } 284 285 static void vmd_msi_free(struct irq_domain *domain, 286 struct msi_domain_info *info, unsigned int virq) 287 { 288 struct vmd_irq *vmdirq = irq_get_chip_data(virq); 289 unsigned long flags; 290 291 synchronize_srcu(&vmdirq->irq->srcu); 292 293 /* XXX: Potential optimization to rebalance */ 294 raw_spin_lock_irqsave(&list_lock, flags); 295 vmdirq->irq->count--; 296 raw_spin_unlock_irqrestore(&list_lock, flags); 297 298 kfree(vmdirq); 299 } 300 301 static int vmd_msi_prepare(struct irq_domain *domain, struct device *dev, 302 int nvec, msi_alloc_info_t *arg) 303 { 304 struct pci_dev *pdev = to_pci_dev(dev); 305 struct vmd_dev *vmd = vmd_from_bus(pdev->bus); 306 307 if (nvec > vmd->msix_count) 308 return vmd->msix_count; 309 310 memset(arg, 0, sizeof(*arg)); 311 return 0; 312 } 313 314 static void vmd_set_desc(msi_alloc_info_t *arg, struct msi_desc *desc) 315 { 316 arg->desc = desc; 317 } 318 319 static struct msi_domain_ops vmd_msi_domain_ops = { 320 .get_hwirq = vmd_get_hwirq, 321 .msi_init = vmd_msi_init, 322 .msi_free = vmd_msi_free, 323 .msi_prepare = vmd_msi_prepare, 324 .set_desc = vmd_set_desc, 325 }; 326 327 static struct msi_domain_info vmd_msi_domain_info = { 328 .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 329 MSI_FLAG_PCI_MSIX, 330 .ops = &vmd_msi_domain_ops, 331 .chip = &vmd_msi_controller, 332 }; 333 334 static void vmd_set_msi_remapping(struct vmd_dev *vmd, bool enable) 335 { 336 u16 reg; 337 338 pci_read_config_word(vmd->dev, PCI_REG_VMCONFIG, ®); 339 reg = enable ? (reg & ~VMCONFIG_MSI_REMAP) : 340 (reg | VMCONFIG_MSI_REMAP); 341 pci_write_config_word(vmd->dev, PCI_REG_VMCONFIG, reg); 342 } 343 344 static int vmd_create_irq_domain(struct vmd_dev *vmd) 345 { 346 struct fwnode_handle *fn; 347 348 fn = irq_domain_alloc_named_id_fwnode("VMD-MSI", vmd->sysdata.domain); 349 if (!fn) 350 return -ENODEV; 351 352 vmd->irq_domain = pci_msi_create_irq_domain(fn, &vmd_msi_domain_info, NULL); 353 if (!vmd->irq_domain) { 354 irq_domain_free_fwnode(fn); 355 return -ENODEV; 356 } 357 358 return 0; 359 } 360 361 static void vmd_remove_irq_domain(struct vmd_dev *vmd) 362 { 363 /* 364 * Some production BIOS won't enable remapping between soft reboots. 365 * Ensure remapping is restored before unloading the driver. 366 */ 367 if (!vmd->msix_count) 368 vmd_set_msi_remapping(vmd, true); 369 370 if (vmd->irq_domain) { 371 struct fwnode_handle *fn = vmd->irq_domain->fwnode; 372 373 irq_domain_remove(vmd->irq_domain); 374 irq_domain_free_fwnode(fn); 375 } 376 } 377 378 static void __iomem *vmd_cfg_addr(struct vmd_dev *vmd, struct pci_bus *bus, 379 unsigned int devfn, int reg, int len) 380 { 381 unsigned int busnr_ecam = bus->number - vmd->busn_start; 382 u32 offset = PCIE_ECAM_OFFSET(busnr_ecam, devfn, reg); 383 384 if (offset + len >= resource_size(&vmd->dev->resource[VMD_CFGBAR])) 385 return NULL; 386 387 return vmd->cfgbar + offset; 388 } 389 390 /* 391 * CPU may deadlock if config space is not serialized on some versions of this 392 * hardware, so all config space access is done under a spinlock. 393 */ 394 static int vmd_pci_read(struct pci_bus *bus, unsigned int devfn, int reg, 395 int len, u32 *value) 396 { 397 struct vmd_dev *vmd = vmd_from_bus(bus); 398 void __iomem *addr = vmd_cfg_addr(vmd, bus, devfn, reg, len); 399 unsigned long flags; 400 int ret = 0; 401 402 if (!addr) 403 return -EFAULT; 404 405 spin_lock_irqsave(&vmd->cfg_lock, flags); 406 switch (len) { 407 case 1: 408 *value = readb(addr); 409 break; 410 case 2: 411 *value = readw(addr); 412 break; 413 case 4: 414 *value = readl(addr); 415 break; 416 default: 417 ret = -EINVAL; 418 break; 419 } 420 spin_unlock_irqrestore(&vmd->cfg_lock, flags); 421 return ret; 422 } 423 424 /* 425 * VMD h/w converts non-posted config writes to posted memory writes. The 426 * read-back in this function forces the completion so it returns only after 427 * the config space was written, as expected. 428 */ 429 static int vmd_pci_write(struct pci_bus *bus, unsigned int devfn, int reg, 430 int len, u32 value) 431 { 432 struct vmd_dev *vmd = vmd_from_bus(bus); 433 void __iomem *addr = vmd_cfg_addr(vmd, bus, devfn, reg, len); 434 unsigned long flags; 435 int ret = 0; 436 437 if (!addr) 438 return -EFAULT; 439 440 spin_lock_irqsave(&vmd->cfg_lock, flags); 441 switch (len) { 442 case 1: 443 writeb(value, addr); 444 readb(addr); 445 break; 446 case 2: 447 writew(value, addr); 448 readw(addr); 449 break; 450 case 4: 451 writel(value, addr); 452 readl(addr); 453 break; 454 default: 455 ret = -EINVAL; 456 break; 457 } 458 spin_unlock_irqrestore(&vmd->cfg_lock, flags); 459 return ret; 460 } 461 462 static struct pci_ops vmd_ops = { 463 .read = vmd_pci_read, 464 .write = vmd_pci_write, 465 }; 466 467 #ifdef CONFIG_ACPI 468 static struct acpi_device *vmd_acpi_find_companion(struct pci_dev *pci_dev) 469 { 470 struct pci_host_bridge *bridge; 471 u32 busnr, addr; 472 473 if (pci_dev->bus->ops != &vmd_ops) 474 return NULL; 475 476 bridge = pci_find_host_bridge(pci_dev->bus); 477 busnr = pci_dev->bus->number - bridge->bus->number; 478 /* 479 * The address computation below is only applicable to relative bus 480 * numbers below 32. 481 */ 482 if (busnr > 31) 483 return NULL; 484 485 addr = (busnr << 24) | ((u32)pci_dev->devfn << 16) | 0x8000FFFFU; 486 487 dev_dbg(&pci_dev->dev, "Looking for ACPI companion (address 0x%x)\n", 488 addr); 489 490 return acpi_find_child_device(ACPI_COMPANION(bridge->dev.parent), addr, 491 false); 492 } 493 494 static bool hook_installed; 495 496 static void vmd_acpi_begin(void) 497 { 498 if (pci_acpi_set_companion_lookup_hook(vmd_acpi_find_companion)) 499 return; 500 501 hook_installed = true; 502 } 503 504 static void vmd_acpi_end(void) 505 { 506 if (!hook_installed) 507 return; 508 509 pci_acpi_clear_companion_lookup_hook(); 510 hook_installed = false; 511 } 512 #else 513 static inline void vmd_acpi_begin(void) { } 514 static inline void vmd_acpi_end(void) { } 515 #endif /* CONFIG_ACPI */ 516 517 static void vmd_domain_reset(struct vmd_dev *vmd) 518 { 519 u16 bus, max_buses = resource_size(&vmd->resources[0]); 520 u8 dev, functions, fn, hdr_type; 521 char __iomem *base; 522 523 for (bus = 0; bus < max_buses; bus++) { 524 for (dev = 0; dev < 32; dev++) { 525 base = vmd->cfgbar + PCIE_ECAM_OFFSET(bus, 526 PCI_DEVFN(dev, 0), 0); 527 528 hdr_type = readb(base + PCI_HEADER_TYPE) & 529 PCI_HEADER_TYPE_MASK; 530 531 functions = (hdr_type & 0x80) ? 8 : 1; 532 for (fn = 0; fn < functions; fn++) { 533 base = vmd->cfgbar + PCIE_ECAM_OFFSET(bus, 534 PCI_DEVFN(dev, fn), 0); 535 536 hdr_type = readb(base + PCI_HEADER_TYPE) & 537 PCI_HEADER_TYPE_MASK; 538 539 if (hdr_type != PCI_HEADER_TYPE_BRIDGE || 540 (readw(base + PCI_CLASS_DEVICE) != 541 PCI_CLASS_BRIDGE_PCI)) 542 continue; 543 544 /* 545 * Temporarily disable the I/O range before updating 546 * PCI_IO_BASE. 547 */ 548 writel(0x0000ffff, base + PCI_IO_BASE_UPPER16); 549 /* Update lower 16 bits of I/O base/limit */ 550 writew(0x00f0, base + PCI_IO_BASE); 551 /* Update upper 16 bits of I/O base/limit */ 552 writel(0, base + PCI_IO_BASE_UPPER16); 553 554 /* MMIO Base/Limit */ 555 writel(0x0000fff0, base + PCI_MEMORY_BASE); 556 557 /* Prefetchable MMIO Base/Limit */ 558 writel(0, base + PCI_PREF_LIMIT_UPPER32); 559 writel(0x0000fff0, base + PCI_PREF_MEMORY_BASE); 560 writel(0xffffffff, base + PCI_PREF_BASE_UPPER32); 561 } 562 } 563 } 564 } 565 566 static void vmd_attach_resources(struct vmd_dev *vmd) 567 { 568 vmd->dev->resource[VMD_MEMBAR1].child = &vmd->resources[1]; 569 vmd->dev->resource[VMD_MEMBAR2].child = &vmd->resources[2]; 570 } 571 572 static void vmd_detach_resources(struct vmd_dev *vmd) 573 { 574 vmd->dev->resource[VMD_MEMBAR1].child = NULL; 575 vmd->dev->resource[VMD_MEMBAR2].child = NULL; 576 } 577 578 /* 579 * VMD domains start at 0x10000 to not clash with ACPI _SEG domains. 580 * Per ACPI r6.0, sec 6.5.6, _SEG returns an integer, of which the lower 581 * 16 bits are the PCI Segment Group (domain) number. Other bits are 582 * currently reserved. 583 */ 584 static int vmd_find_free_domain(void) 585 { 586 int domain = 0xffff; 587 struct pci_bus *bus = NULL; 588 589 while ((bus = pci_find_next_bus(bus)) != NULL) 590 domain = max_t(int, domain, pci_domain_nr(bus)); 591 return domain + 1; 592 } 593 594 static int vmd_get_phys_offsets(struct vmd_dev *vmd, bool native_hint, 595 resource_size_t *offset1, 596 resource_size_t *offset2) 597 { 598 struct pci_dev *dev = vmd->dev; 599 u64 phys1, phys2; 600 601 if (native_hint) { 602 u32 vmlock; 603 int ret; 604 605 ret = pci_read_config_dword(dev, PCI_REG_VMLOCK, &vmlock); 606 if (ret || PCI_POSSIBLE_ERROR(vmlock)) 607 return -ENODEV; 608 609 if (MB2_SHADOW_EN(vmlock)) { 610 void __iomem *membar2; 611 612 membar2 = pci_iomap(dev, VMD_MEMBAR2, 0); 613 if (!membar2) 614 return -ENOMEM; 615 phys1 = readq(membar2 + MB2_SHADOW_OFFSET); 616 phys2 = readq(membar2 + MB2_SHADOW_OFFSET + 8); 617 pci_iounmap(dev, membar2); 618 } else 619 return 0; 620 } else { 621 /* Hypervisor-Emulated Vendor-Specific Capability */ 622 int pos = pci_find_capability(dev, PCI_CAP_ID_VNDR); 623 u32 reg, regu; 624 625 pci_read_config_dword(dev, pos + 4, ®); 626 627 /* "SHDW" */ 628 if (pos && reg == 0x53484457) { 629 pci_read_config_dword(dev, pos + 8, ®); 630 pci_read_config_dword(dev, pos + 12, ®u); 631 phys1 = (u64) regu << 32 | reg; 632 633 pci_read_config_dword(dev, pos + 16, ®); 634 pci_read_config_dword(dev, pos + 20, ®u); 635 phys2 = (u64) regu << 32 | reg; 636 } else 637 return 0; 638 } 639 640 *offset1 = dev->resource[VMD_MEMBAR1].start - 641 (phys1 & PCI_BASE_ADDRESS_MEM_MASK); 642 *offset2 = dev->resource[VMD_MEMBAR2].start - 643 (phys2 & PCI_BASE_ADDRESS_MEM_MASK); 644 645 return 0; 646 } 647 648 static int vmd_get_bus_number_start(struct vmd_dev *vmd) 649 { 650 struct pci_dev *dev = vmd->dev; 651 u16 reg; 652 653 pci_read_config_word(dev, PCI_REG_VMCAP, ®); 654 if (BUS_RESTRICT_CAP(reg)) { 655 pci_read_config_word(dev, PCI_REG_VMCONFIG, ®); 656 657 switch (BUS_RESTRICT_CFG(reg)) { 658 case 0: 659 vmd->busn_start = 0; 660 break; 661 case 1: 662 vmd->busn_start = 128; 663 break; 664 case 2: 665 vmd->busn_start = 224; 666 break; 667 default: 668 pci_err(dev, "Unknown Bus Offset Setting (%d)\n", 669 BUS_RESTRICT_CFG(reg)); 670 return -ENODEV; 671 } 672 } 673 674 return 0; 675 } 676 677 static irqreturn_t vmd_irq(int irq, void *data) 678 { 679 struct vmd_irq_list *irqs = data; 680 struct vmd_irq *vmdirq; 681 int idx; 682 683 idx = srcu_read_lock(&irqs->srcu); 684 list_for_each_entry_rcu(vmdirq, &irqs->irq_list, node) 685 generic_handle_irq(vmdirq->virq); 686 srcu_read_unlock(&irqs->srcu, idx); 687 688 return IRQ_HANDLED; 689 } 690 691 static int vmd_alloc_irqs(struct vmd_dev *vmd) 692 { 693 struct pci_dev *dev = vmd->dev; 694 int i, err; 695 696 vmd->msix_count = pci_msix_vec_count(dev); 697 if (vmd->msix_count < 0) 698 return -ENODEV; 699 700 vmd->msix_count = pci_alloc_irq_vectors(dev, vmd->first_vec + 1, 701 vmd->msix_count, PCI_IRQ_MSIX); 702 if (vmd->msix_count < 0) 703 return vmd->msix_count; 704 705 vmd->irqs = devm_kcalloc(&dev->dev, vmd->msix_count, sizeof(*vmd->irqs), 706 GFP_KERNEL); 707 if (!vmd->irqs) 708 return -ENOMEM; 709 710 for (i = 0; i < vmd->msix_count; i++) { 711 err = init_srcu_struct(&vmd->irqs[i].srcu); 712 if (err) 713 return err; 714 715 INIT_LIST_HEAD(&vmd->irqs[i].irq_list); 716 vmd->irqs[i].virq = pci_irq_vector(dev, i); 717 err = devm_request_irq(&dev->dev, vmd->irqs[i].virq, 718 vmd_irq, IRQF_NO_THREAD, 719 vmd->name, &vmd->irqs[i]); 720 if (err) 721 return err; 722 } 723 724 return 0; 725 } 726 727 /* 728 * Since VMD is an aperture to regular PCIe root ports, only allow it to 729 * control features that the OS is allowed to control on the physical PCI bus. 730 */ 731 static void vmd_copy_host_bridge_flags(struct pci_host_bridge *root_bridge, 732 struct pci_host_bridge *vmd_bridge) 733 { 734 vmd_bridge->native_pcie_hotplug = root_bridge->native_pcie_hotplug; 735 vmd_bridge->native_shpc_hotplug = root_bridge->native_shpc_hotplug; 736 vmd_bridge->native_aer = root_bridge->native_aer; 737 vmd_bridge->native_pme = root_bridge->native_pme; 738 vmd_bridge->native_ltr = root_bridge->native_ltr; 739 vmd_bridge->native_dpc = root_bridge->native_dpc; 740 } 741 742 /* 743 * Enable ASPM and LTR settings on devices that aren't configured by BIOS. 744 */ 745 static int vmd_pm_enable_quirk(struct pci_dev *pdev, void *userdata) 746 { 747 unsigned long features = *(unsigned long *)userdata; 748 u16 ltr = VMD_BIOS_PM_QUIRK_LTR; 749 u32 ltr_reg; 750 int pos; 751 752 if (!(features & VMD_FEAT_BIOS_PM_QUIRK)) 753 return 0; 754 755 pci_enable_link_state(pdev, PCIE_LINK_STATE_ALL); 756 757 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_LTR); 758 if (!pos) 759 return 0; 760 761 /* 762 * Skip if the max snoop LTR is non-zero, indicating BIOS has set it 763 * so the LTR quirk is not needed. 764 */ 765 pci_read_config_dword(pdev, pos + PCI_LTR_MAX_SNOOP_LAT, <r_reg); 766 if (!!(ltr_reg & (PCI_LTR_VALUE_MASK | PCI_LTR_SCALE_MASK))) 767 return 0; 768 769 /* 770 * Set the default values to the maximum required by the platform to 771 * allow the deepest power management savings. Write as a DWORD where 772 * the lower word is the max snoop latency and the upper word is the 773 * max non-snoop latency. 774 */ 775 ltr_reg = (ltr << 16) | ltr; 776 pci_write_config_dword(pdev, pos + PCI_LTR_MAX_SNOOP_LAT, ltr_reg); 777 pci_info(pdev, "VMD: Default LTR value set by driver\n"); 778 779 return 0; 780 } 781 782 static int vmd_enable_domain(struct vmd_dev *vmd, unsigned long features) 783 { 784 struct pci_sysdata *sd = &vmd->sysdata; 785 struct resource *res; 786 u32 upper_bits; 787 unsigned long flags; 788 LIST_HEAD(resources); 789 resource_size_t offset[2] = {0}; 790 resource_size_t membar2_offset = 0x2000; 791 struct pci_bus *child; 792 struct pci_dev *dev; 793 int ret; 794 795 /* 796 * Shadow registers may exist in certain VMD device ids which allow 797 * guests to correctly assign host physical addresses to the root ports 798 * and child devices. These registers will either return the host value 799 * or 0, depending on an enable bit in the VMD device. 800 */ 801 if (features & VMD_FEAT_HAS_MEMBAR_SHADOW) { 802 membar2_offset = MB2_SHADOW_OFFSET + MB2_SHADOW_SIZE; 803 ret = vmd_get_phys_offsets(vmd, true, &offset[0], &offset[1]); 804 if (ret) 805 return ret; 806 } else if (features & VMD_FEAT_HAS_MEMBAR_SHADOW_VSCAP) { 807 ret = vmd_get_phys_offsets(vmd, false, &offset[0], &offset[1]); 808 if (ret) 809 return ret; 810 } 811 812 /* 813 * Certain VMD devices may have a root port configuration option which 814 * limits the bus range to between 0-127, 128-255, or 224-255 815 */ 816 if (features & VMD_FEAT_HAS_BUS_RESTRICTIONS) { 817 ret = vmd_get_bus_number_start(vmd); 818 if (ret) 819 return ret; 820 } 821 822 res = &vmd->dev->resource[VMD_CFGBAR]; 823 vmd->resources[0] = (struct resource) { 824 .name = "VMD CFGBAR", 825 .start = vmd->busn_start, 826 .end = vmd->busn_start + (resource_size(res) >> 20) - 1, 827 .flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED, 828 }; 829 830 /* 831 * If the window is below 4GB, clear IORESOURCE_MEM_64 so we can 832 * put 32-bit resources in the window. 833 * 834 * There's no hardware reason why a 64-bit window *couldn't* 835 * contain a 32-bit resource, but pbus_size_mem() computes the 836 * bridge window size assuming a 64-bit window will contain no 837 * 32-bit resources. __pci_assign_resource() enforces that 838 * artificial restriction to make sure everything will fit. 839 * 840 * The only way we could use a 64-bit non-prefetchable MEMBAR is 841 * if its address is <4GB so that we can convert it to a 32-bit 842 * resource. To be visible to the host OS, all VMD endpoints must 843 * be initially configured by platform BIOS, which includes setting 844 * up these resources. We can assume the device is configured 845 * according to the platform needs. 846 */ 847 res = &vmd->dev->resource[VMD_MEMBAR1]; 848 upper_bits = upper_32_bits(res->end); 849 flags = res->flags & ~IORESOURCE_SIZEALIGN; 850 if (!upper_bits) 851 flags &= ~IORESOURCE_MEM_64; 852 vmd->resources[1] = (struct resource) { 853 .name = "VMD MEMBAR1", 854 .start = res->start, 855 .end = res->end, 856 .flags = flags, 857 .parent = res, 858 }; 859 860 res = &vmd->dev->resource[VMD_MEMBAR2]; 861 upper_bits = upper_32_bits(res->end); 862 flags = res->flags & ~IORESOURCE_SIZEALIGN; 863 if (!upper_bits) 864 flags &= ~IORESOURCE_MEM_64; 865 vmd->resources[2] = (struct resource) { 866 .name = "VMD MEMBAR2", 867 .start = res->start + membar2_offset, 868 .end = res->end, 869 .flags = flags, 870 .parent = res, 871 }; 872 873 sd->vmd_dev = vmd->dev; 874 sd->domain = vmd_find_free_domain(); 875 if (sd->domain < 0) 876 return sd->domain; 877 878 sd->node = pcibus_to_node(vmd->dev->bus); 879 880 /* 881 * Currently MSI remapping must be enabled in guest passthrough mode 882 * due to some missing interrupt remapping plumbing. This is probably 883 * acceptable because the guest is usually CPU-limited and MSI 884 * remapping doesn't become a performance bottleneck. 885 */ 886 if (!(features & VMD_FEAT_CAN_BYPASS_MSI_REMAP) || 887 offset[0] || offset[1]) { 888 ret = vmd_alloc_irqs(vmd); 889 if (ret) 890 return ret; 891 892 vmd_set_msi_remapping(vmd, true); 893 894 ret = vmd_create_irq_domain(vmd); 895 if (ret) 896 return ret; 897 898 /* 899 * Override the IRQ domain bus token so the domain can be 900 * distinguished from a regular PCI/MSI domain. 901 */ 902 irq_domain_update_bus_token(vmd->irq_domain, DOMAIN_BUS_VMD_MSI); 903 } else { 904 vmd_set_msi_remapping(vmd, false); 905 } 906 907 pci_add_resource(&resources, &vmd->resources[0]); 908 pci_add_resource_offset(&resources, &vmd->resources[1], offset[0]); 909 pci_add_resource_offset(&resources, &vmd->resources[2], offset[1]); 910 911 vmd->bus = pci_create_root_bus(&vmd->dev->dev, vmd->busn_start, 912 &vmd_ops, sd, &resources); 913 if (!vmd->bus) { 914 pci_free_resource_list(&resources); 915 vmd_remove_irq_domain(vmd); 916 return -ENODEV; 917 } 918 919 vmd_copy_host_bridge_flags(pci_find_host_bridge(vmd->dev->bus), 920 to_pci_host_bridge(vmd->bus->bridge)); 921 922 vmd_attach_resources(vmd); 923 if (vmd->irq_domain) 924 dev_set_msi_domain(&vmd->bus->dev, vmd->irq_domain); 925 else 926 dev_set_msi_domain(&vmd->bus->dev, 927 dev_get_msi_domain(&vmd->dev->dev)); 928 929 vmd_acpi_begin(); 930 931 pci_scan_child_bus(vmd->bus); 932 vmd_domain_reset(vmd); 933 934 /* When Intel VMD is enabled, the OS does not discover the Root Ports 935 * owned by Intel VMD within the MMCFG space. pci_reset_bus() applies 936 * a reset to the parent of the PCI device supplied as argument. This 937 * is why we pass a child device, so the reset can be triggered at 938 * the Intel bridge level and propagated to all the children in the 939 * hierarchy. 940 */ 941 list_for_each_entry(child, &vmd->bus->children, node) { 942 if (!list_empty(&child->devices)) { 943 dev = list_first_entry(&child->devices, 944 struct pci_dev, bus_list); 945 ret = pci_reset_bus(dev); 946 if (ret) 947 pci_warn(dev, "can't reset device: %d\n", ret); 948 949 break; 950 } 951 } 952 953 pci_assign_unassigned_bus_resources(vmd->bus); 954 955 pci_walk_bus(vmd->bus, vmd_pm_enable_quirk, &features); 956 957 /* 958 * VMD root buses are virtual and don't return true on pci_is_pcie() 959 * and will fail pcie_bus_configure_settings() early. It can instead be 960 * run on each of the real root ports. 961 */ 962 list_for_each_entry(child, &vmd->bus->children, node) 963 pcie_bus_configure_settings(child); 964 965 pci_bus_add_devices(vmd->bus); 966 967 vmd_acpi_end(); 968 969 WARN(sysfs_create_link(&vmd->dev->dev.kobj, &vmd->bus->dev.kobj, 970 "domain"), "Can't create symlink to domain\n"); 971 return 0; 972 } 973 974 static int vmd_probe(struct pci_dev *dev, const struct pci_device_id *id) 975 { 976 unsigned long features = (unsigned long) id->driver_data; 977 struct vmd_dev *vmd; 978 int err; 979 980 if (resource_size(&dev->resource[VMD_CFGBAR]) < (1 << 20)) 981 return -ENOMEM; 982 983 vmd = devm_kzalloc(&dev->dev, sizeof(*vmd), GFP_KERNEL); 984 if (!vmd) 985 return -ENOMEM; 986 987 vmd->dev = dev; 988 vmd->instance = ida_simple_get(&vmd_instance_ida, 0, 0, GFP_KERNEL); 989 if (vmd->instance < 0) 990 return vmd->instance; 991 992 vmd->name = devm_kasprintf(&dev->dev, GFP_KERNEL, "vmd%d", 993 vmd->instance); 994 if (!vmd->name) { 995 err = -ENOMEM; 996 goto out_release_instance; 997 } 998 999 err = pcim_enable_device(dev); 1000 if (err < 0) 1001 goto out_release_instance; 1002 1003 vmd->cfgbar = pcim_iomap(dev, VMD_CFGBAR, 0); 1004 if (!vmd->cfgbar) { 1005 err = -ENOMEM; 1006 goto out_release_instance; 1007 } 1008 1009 pci_set_master(dev); 1010 if (dma_set_mask_and_coherent(&dev->dev, DMA_BIT_MASK(64)) && 1011 dma_set_mask_and_coherent(&dev->dev, DMA_BIT_MASK(32))) { 1012 err = -ENODEV; 1013 goto out_release_instance; 1014 } 1015 1016 if (features & VMD_FEAT_OFFSET_FIRST_VECTOR) 1017 vmd->first_vec = 1; 1018 1019 spin_lock_init(&vmd->cfg_lock); 1020 pci_set_drvdata(dev, vmd); 1021 err = vmd_enable_domain(vmd, features); 1022 if (err) 1023 goto out_release_instance; 1024 1025 dev_info(&vmd->dev->dev, "Bound to PCI domain %04x\n", 1026 vmd->sysdata.domain); 1027 return 0; 1028 1029 out_release_instance: 1030 ida_simple_remove(&vmd_instance_ida, vmd->instance); 1031 return err; 1032 } 1033 1034 static void vmd_cleanup_srcu(struct vmd_dev *vmd) 1035 { 1036 int i; 1037 1038 for (i = 0; i < vmd->msix_count; i++) 1039 cleanup_srcu_struct(&vmd->irqs[i].srcu); 1040 } 1041 1042 static void vmd_remove(struct pci_dev *dev) 1043 { 1044 struct vmd_dev *vmd = pci_get_drvdata(dev); 1045 1046 sysfs_remove_link(&vmd->dev->dev.kobj, "domain"); 1047 pci_stop_root_bus(vmd->bus); 1048 pci_remove_root_bus(vmd->bus); 1049 vmd_cleanup_srcu(vmd); 1050 vmd_detach_resources(vmd); 1051 vmd_remove_irq_domain(vmd); 1052 ida_simple_remove(&vmd_instance_ida, vmd->instance); 1053 } 1054 1055 static void vmd_shutdown(struct pci_dev *dev) 1056 { 1057 struct vmd_dev *vmd = pci_get_drvdata(dev); 1058 1059 vmd_remove_irq_domain(vmd); 1060 } 1061 1062 #ifdef CONFIG_PM_SLEEP 1063 static int vmd_suspend(struct device *dev) 1064 { 1065 struct pci_dev *pdev = to_pci_dev(dev); 1066 struct vmd_dev *vmd = pci_get_drvdata(pdev); 1067 int i; 1068 1069 for (i = 0; i < vmd->msix_count; i++) 1070 devm_free_irq(dev, vmd->irqs[i].virq, &vmd->irqs[i]); 1071 1072 return 0; 1073 } 1074 1075 static int vmd_resume(struct device *dev) 1076 { 1077 struct pci_dev *pdev = to_pci_dev(dev); 1078 struct vmd_dev *vmd = pci_get_drvdata(pdev); 1079 int err, i; 1080 1081 if (vmd->irq_domain) 1082 vmd_set_msi_remapping(vmd, true); 1083 else 1084 vmd_set_msi_remapping(vmd, false); 1085 1086 for (i = 0; i < vmd->msix_count; i++) { 1087 err = devm_request_irq(dev, vmd->irqs[i].virq, 1088 vmd_irq, IRQF_NO_THREAD, 1089 vmd->name, &vmd->irqs[i]); 1090 if (err) 1091 return err; 1092 } 1093 1094 return 0; 1095 } 1096 #endif 1097 static SIMPLE_DEV_PM_OPS(vmd_dev_pm_ops, vmd_suspend, vmd_resume); 1098 1099 static const struct pci_device_id vmd_ids[] = { 1100 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_VMD_201D), 1101 .driver_data = VMD_FEAT_HAS_MEMBAR_SHADOW_VSCAP,}, 1102 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_VMD_28C0), 1103 .driver_data = VMD_FEAT_HAS_MEMBAR_SHADOW | 1104 VMD_FEAT_HAS_BUS_RESTRICTIONS | 1105 VMD_FEAT_CAN_BYPASS_MSI_REMAP,}, 1106 {PCI_VDEVICE(INTEL, 0x467f), 1107 .driver_data = VMD_FEATS_CLIENT,}, 1108 {PCI_VDEVICE(INTEL, 0x4c3d), 1109 .driver_data = VMD_FEATS_CLIENT,}, 1110 {PCI_VDEVICE(INTEL, 0xa77f), 1111 .driver_data = VMD_FEATS_CLIENT,}, 1112 {PCI_VDEVICE(INTEL, 0x7d0b), 1113 .driver_data = VMD_FEATS_CLIENT,}, 1114 {PCI_VDEVICE(INTEL, 0xad0b), 1115 .driver_data = VMD_FEATS_CLIENT,}, 1116 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_VMD_9A0B), 1117 .driver_data = VMD_FEATS_CLIENT,}, 1118 {0,} 1119 }; 1120 MODULE_DEVICE_TABLE(pci, vmd_ids); 1121 1122 static struct pci_driver vmd_drv = { 1123 .name = "vmd", 1124 .id_table = vmd_ids, 1125 .probe = vmd_probe, 1126 .remove = vmd_remove, 1127 .shutdown = vmd_shutdown, 1128 .driver = { 1129 .pm = &vmd_dev_pm_ops, 1130 }, 1131 }; 1132 module_pci_driver(vmd_drv); 1133 1134 MODULE_AUTHOR("Intel Corporation"); 1135 MODULE_LICENSE("GPL v2"); 1136 MODULE_VERSION("0.6"); 1137