1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * PCIe host controller driver for NWL PCIe Bridge 4 * Based on pcie-xilinx.c, pci-tegra.c 5 * 6 * (C) Copyright 2014 - 2015, Xilinx, Inc. 7 */ 8 9 #include <linux/delay.h> 10 #include <linux/interrupt.h> 11 #include <linux/irq.h> 12 #include <linux/irqdomain.h> 13 #include <linux/kernel.h> 14 #include <linux/init.h> 15 #include <linux/msi.h> 16 #include <linux/of_address.h> 17 #include <linux/of_pci.h> 18 #include <linux/of_platform.h> 19 #include <linux/of_irq.h> 20 #include <linux/pci.h> 21 #include <linux/platform_device.h> 22 #include <linux/irqchip/chained_irq.h> 23 24 #include "../pci.h" 25 26 /* Bridge core config registers */ 27 #define BRCFG_PCIE_RX0 0x00000000 28 #define BRCFG_INTERRUPT 0x00000010 29 #define BRCFG_PCIE_RX_MSG_FILTER 0x00000020 30 31 /* Egress - Bridge translation registers */ 32 #define E_BREG_CAPABILITIES 0x00000200 33 #define E_BREG_CONTROL 0x00000208 34 #define E_BREG_BASE_LO 0x00000210 35 #define E_BREG_BASE_HI 0x00000214 36 #define E_ECAM_CAPABILITIES 0x00000220 37 #define E_ECAM_CONTROL 0x00000228 38 #define E_ECAM_BASE_LO 0x00000230 39 #define E_ECAM_BASE_HI 0x00000234 40 41 /* Ingress - address translations */ 42 #define I_MSII_CAPABILITIES 0x00000300 43 #define I_MSII_CONTROL 0x00000308 44 #define I_MSII_BASE_LO 0x00000310 45 #define I_MSII_BASE_HI 0x00000314 46 47 #define I_ISUB_CONTROL 0x000003E8 48 #define SET_ISUB_CONTROL BIT(0) 49 /* Rxed msg fifo - Interrupt status registers */ 50 #define MSGF_MISC_STATUS 0x00000400 51 #define MSGF_MISC_MASK 0x00000404 52 #define MSGF_LEG_STATUS 0x00000420 53 #define MSGF_LEG_MASK 0x00000424 54 #define MSGF_MSI_STATUS_LO 0x00000440 55 #define MSGF_MSI_STATUS_HI 0x00000444 56 #define MSGF_MSI_MASK_LO 0x00000448 57 #define MSGF_MSI_MASK_HI 0x0000044C 58 59 /* Msg filter mask bits */ 60 #define CFG_ENABLE_PM_MSG_FWD BIT(1) 61 #define CFG_ENABLE_INT_MSG_FWD BIT(2) 62 #define CFG_ENABLE_ERR_MSG_FWD BIT(3) 63 #define CFG_ENABLE_MSG_FILTER_MASK (CFG_ENABLE_PM_MSG_FWD | \ 64 CFG_ENABLE_INT_MSG_FWD | \ 65 CFG_ENABLE_ERR_MSG_FWD) 66 67 /* Misc interrupt status mask bits */ 68 #define MSGF_MISC_SR_RXMSG_AVAIL BIT(0) 69 #define MSGF_MISC_SR_RXMSG_OVER BIT(1) 70 #define MSGF_MISC_SR_SLAVE_ERR BIT(4) 71 #define MSGF_MISC_SR_MASTER_ERR BIT(5) 72 #define MSGF_MISC_SR_I_ADDR_ERR BIT(6) 73 #define MSGF_MISC_SR_E_ADDR_ERR BIT(7) 74 #define MSGF_MISC_SR_FATAL_AER BIT(16) 75 #define MSGF_MISC_SR_NON_FATAL_AER BIT(17) 76 #define MSGF_MISC_SR_CORR_AER BIT(18) 77 #define MSGF_MISC_SR_UR_DETECT BIT(20) 78 #define MSGF_MISC_SR_NON_FATAL_DEV BIT(22) 79 #define MSGF_MISC_SR_FATAL_DEV BIT(23) 80 #define MSGF_MISC_SR_LINK_DOWN BIT(24) 81 #define MSGF_MSIC_SR_LINK_AUTO_BWIDTH BIT(25) 82 #define MSGF_MSIC_SR_LINK_BWIDTH BIT(26) 83 84 #define MSGF_MISC_SR_MASKALL (MSGF_MISC_SR_RXMSG_AVAIL | \ 85 MSGF_MISC_SR_RXMSG_OVER | \ 86 MSGF_MISC_SR_SLAVE_ERR | \ 87 MSGF_MISC_SR_MASTER_ERR | \ 88 MSGF_MISC_SR_I_ADDR_ERR | \ 89 MSGF_MISC_SR_E_ADDR_ERR | \ 90 MSGF_MISC_SR_FATAL_AER | \ 91 MSGF_MISC_SR_NON_FATAL_AER | \ 92 MSGF_MISC_SR_CORR_AER | \ 93 MSGF_MISC_SR_UR_DETECT | \ 94 MSGF_MISC_SR_NON_FATAL_DEV | \ 95 MSGF_MISC_SR_FATAL_DEV | \ 96 MSGF_MISC_SR_LINK_DOWN | \ 97 MSGF_MSIC_SR_LINK_AUTO_BWIDTH | \ 98 MSGF_MSIC_SR_LINK_BWIDTH) 99 100 /* Legacy interrupt status mask bits */ 101 #define MSGF_LEG_SR_INTA BIT(0) 102 #define MSGF_LEG_SR_INTB BIT(1) 103 #define MSGF_LEG_SR_INTC BIT(2) 104 #define MSGF_LEG_SR_INTD BIT(3) 105 #define MSGF_LEG_SR_MASKALL (MSGF_LEG_SR_INTA | MSGF_LEG_SR_INTB | \ 106 MSGF_LEG_SR_INTC | MSGF_LEG_SR_INTD) 107 108 /* MSI interrupt status mask bits */ 109 #define MSGF_MSI_SR_LO_MASK GENMASK(31, 0) 110 #define MSGF_MSI_SR_HI_MASK GENMASK(31, 0) 111 112 #define MSII_PRESENT BIT(0) 113 #define MSII_ENABLE BIT(0) 114 #define MSII_STATUS_ENABLE BIT(15) 115 116 /* Bridge config interrupt mask */ 117 #define BRCFG_INTERRUPT_MASK BIT(0) 118 #define BREG_PRESENT BIT(0) 119 #define BREG_ENABLE BIT(0) 120 #define BREG_ENABLE_FORCE BIT(1) 121 122 /* E_ECAM status mask bits */ 123 #define E_ECAM_PRESENT BIT(0) 124 #define E_ECAM_CR_ENABLE BIT(0) 125 #define E_ECAM_SIZE_LOC GENMASK(20, 16) 126 #define E_ECAM_SIZE_SHIFT 16 127 #define ECAM_BUS_LOC_SHIFT 20 128 #define ECAM_DEV_LOC_SHIFT 12 129 #define NWL_ECAM_VALUE_DEFAULT 12 130 131 #define CFG_DMA_REG_BAR GENMASK(2, 0) 132 133 #define INT_PCI_MSI_NR (2 * 32) 134 135 /* Readin the PS_LINKUP */ 136 #define PS_LINKUP_OFFSET 0x00000238 137 #define PCIE_PHY_LINKUP_BIT BIT(0) 138 #define PHY_RDY_LINKUP_BIT BIT(1) 139 140 /* Parameters for the waiting for link up routine */ 141 #define LINK_WAIT_MAX_RETRIES 10 142 #define LINK_WAIT_USLEEP_MIN 90000 143 #define LINK_WAIT_USLEEP_MAX 100000 144 145 struct nwl_msi { /* MSI information */ 146 struct irq_domain *msi_domain; 147 unsigned long *bitmap; 148 struct irq_domain *dev_domain; 149 struct mutex lock; /* protect bitmap variable */ 150 int irq_msi0; 151 int irq_msi1; 152 }; 153 154 struct nwl_pcie { 155 struct device *dev; 156 void __iomem *breg_base; 157 void __iomem *pcireg_base; 158 void __iomem *ecam_base; 159 phys_addr_t phys_breg_base; /* Physical Bridge Register Base */ 160 phys_addr_t phys_pcie_reg_base; /* Physical PCIe Controller Base */ 161 phys_addr_t phys_ecam_base; /* Physical Configuration Base */ 162 u32 breg_size; 163 u32 pcie_reg_size; 164 u32 ecam_size; 165 int irq_intx; 166 int irq_misc; 167 u32 ecam_value; 168 u8 last_busno; 169 struct nwl_msi msi; 170 struct irq_domain *legacy_irq_domain; 171 raw_spinlock_t leg_mask_lock; 172 }; 173 174 static inline u32 nwl_bridge_readl(struct nwl_pcie *pcie, u32 off) 175 { 176 return readl(pcie->breg_base + off); 177 } 178 179 static inline void nwl_bridge_writel(struct nwl_pcie *pcie, u32 val, u32 off) 180 { 181 writel(val, pcie->breg_base + off); 182 } 183 184 static bool nwl_pcie_link_up(struct nwl_pcie *pcie) 185 { 186 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PCIE_PHY_LINKUP_BIT) 187 return true; 188 return false; 189 } 190 191 static bool nwl_phy_link_up(struct nwl_pcie *pcie) 192 { 193 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PHY_RDY_LINKUP_BIT) 194 return true; 195 return false; 196 } 197 198 static int nwl_wait_for_link(struct nwl_pcie *pcie) 199 { 200 struct device *dev = pcie->dev; 201 int retries; 202 203 /* check if the link is up or not */ 204 for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { 205 if (nwl_phy_link_up(pcie)) 206 return 0; 207 usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); 208 } 209 210 dev_err(dev, "PHY link never came up\n"); 211 return -ETIMEDOUT; 212 } 213 214 static bool nwl_pcie_valid_device(struct pci_bus *bus, unsigned int devfn) 215 { 216 struct nwl_pcie *pcie = bus->sysdata; 217 218 /* Check link before accessing downstream ports */ 219 if (!pci_is_root_bus(bus)) { 220 if (!nwl_pcie_link_up(pcie)) 221 return false; 222 } else if (devfn > 0) 223 /* Only one device down on each root port */ 224 return false; 225 226 return true; 227 } 228 229 /** 230 * nwl_pcie_map_bus - Get configuration base 231 * 232 * @bus: Bus structure of current bus 233 * @devfn: Device/function 234 * @where: Offset from base 235 * 236 * Return: Base address of the configuration space needed to be 237 * accessed. 238 */ 239 static void __iomem *nwl_pcie_map_bus(struct pci_bus *bus, unsigned int devfn, 240 int where) 241 { 242 struct nwl_pcie *pcie = bus->sysdata; 243 int relbus; 244 245 if (!nwl_pcie_valid_device(bus, devfn)) 246 return NULL; 247 248 relbus = (bus->number << ECAM_BUS_LOC_SHIFT) | 249 (devfn << ECAM_DEV_LOC_SHIFT); 250 251 return pcie->ecam_base + relbus + where; 252 } 253 254 /* PCIe operations */ 255 static struct pci_ops nwl_pcie_ops = { 256 .map_bus = nwl_pcie_map_bus, 257 .read = pci_generic_config_read, 258 .write = pci_generic_config_write, 259 }; 260 261 static irqreturn_t nwl_pcie_misc_handler(int irq, void *data) 262 { 263 struct nwl_pcie *pcie = data; 264 struct device *dev = pcie->dev; 265 u32 misc_stat; 266 267 /* Checking for misc interrupts */ 268 misc_stat = nwl_bridge_readl(pcie, MSGF_MISC_STATUS) & 269 MSGF_MISC_SR_MASKALL; 270 if (!misc_stat) 271 return IRQ_NONE; 272 273 if (misc_stat & MSGF_MISC_SR_RXMSG_OVER) 274 dev_err(dev, "Received Message FIFO Overflow\n"); 275 276 if (misc_stat & MSGF_MISC_SR_SLAVE_ERR) 277 dev_err(dev, "Slave error\n"); 278 279 if (misc_stat & MSGF_MISC_SR_MASTER_ERR) 280 dev_err(dev, "Master error\n"); 281 282 if (misc_stat & MSGF_MISC_SR_I_ADDR_ERR) 283 dev_err(dev, "In Misc Ingress address translation error\n"); 284 285 if (misc_stat & MSGF_MISC_SR_E_ADDR_ERR) 286 dev_err(dev, "In Misc Egress address translation error\n"); 287 288 if (misc_stat & MSGF_MISC_SR_FATAL_AER) 289 dev_err(dev, "Fatal Error in AER Capability\n"); 290 291 if (misc_stat & MSGF_MISC_SR_NON_FATAL_AER) 292 dev_err(dev, "Non-Fatal Error in AER Capability\n"); 293 294 if (misc_stat & MSGF_MISC_SR_CORR_AER) 295 dev_err(dev, "Correctable Error in AER Capability\n"); 296 297 if (misc_stat & MSGF_MISC_SR_UR_DETECT) 298 dev_err(dev, "Unsupported request Detected\n"); 299 300 if (misc_stat & MSGF_MISC_SR_NON_FATAL_DEV) 301 dev_err(dev, "Non-Fatal Error Detected\n"); 302 303 if (misc_stat & MSGF_MISC_SR_FATAL_DEV) 304 dev_err(dev, "Fatal Error Detected\n"); 305 306 if (misc_stat & MSGF_MSIC_SR_LINK_AUTO_BWIDTH) 307 dev_info(dev, "Link Autonomous Bandwidth Management Status bit set\n"); 308 309 if (misc_stat & MSGF_MSIC_SR_LINK_BWIDTH) 310 dev_info(dev, "Link Bandwidth Management Status bit set\n"); 311 312 /* Clear misc interrupt status */ 313 nwl_bridge_writel(pcie, misc_stat, MSGF_MISC_STATUS); 314 315 return IRQ_HANDLED; 316 } 317 318 static void nwl_pcie_leg_handler(struct irq_desc *desc) 319 { 320 struct irq_chip *chip = irq_desc_get_chip(desc); 321 struct nwl_pcie *pcie; 322 unsigned long status; 323 u32 bit; 324 u32 virq; 325 326 chained_irq_enter(chip, desc); 327 pcie = irq_desc_get_handler_data(desc); 328 329 while ((status = nwl_bridge_readl(pcie, MSGF_LEG_STATUS) & 330 MSGF_LEG_SR_MASKALL) != 0) { 331 for_each_set_bit(bit, &status, PCI_NUM_INTX) { 332 virq = irq_find_mapping(pcie->legacy_irq_domain, bit); 333 if (virq) 334 generic_handle_irq(virq); 335 } 336 } 337 338 chained_irq_exit(chip, desc); 339 } 340 341 static void nwl_pcie_handle_msi_irq(struct nwl_pcie *pcie, u32 status_reg) 342 { 343 struct nwl_msi *msi; 344 unsigned long status; 345 u32 bit; 346 u32 virq; 347 348 msi = &pcie->msi; 349 350 while ((status = nwl_bridge_readl(pcie, status_reg)) != 0) { 351 for_each_set_bit(bit, &status, 32) { 352 nwl_bridge_writel(pcie, 1 << bit, status_reg); 353 virq = irq_find_mapping(msi->dev_domain, bit); 354 if (virq) 355 generic_handle_irq(virq); 356 } 357 } 358 } 359 360 static void nwl_pcie_msi_handler_high(struct irq_desc *desc) 361 { 362 struct irq_chip *chip = irq_desc_get_chip(desc); 363 struct nwl_pcie *pcie = irq_desc_get_handler_data(desc); 364 365 chained_irq_enter(chip, desc); 366 nwl_pcie_handle_msi_irq(pcie, MSGF_MSI_STATUS_HI); 367 chained_irq_exit(chip, desc); 368 } 369 370 static void nwl_pcie_msi_handler_low(struct irq_desc *desc) 371 { 372 struct irq_chip *chip = irq_desc_get_chip(desc); 373 struct nwl_pcie *pcie = irq_desc_get_handler_data(desc); 374 375 chained_irq_enter(chip, desc); 376 nwl_pcie_handle_msi_irq(pcie, MSGF_MSI_STATUS_LO); 377 chained_irq_exit(chip, desc); 378 } 379 380 static void nwl_mask_leg_irq(struct irq_data *data) 381 { 382 struct irq_desc *desc = irq_to_desc(data->irq); 383 struct nwl_pcie *pcie; 384 unsigned long flags; 385 u32 mask; 386 u32 val; 387 388 pcie = irq_desc_get_chip_data(desc); 389 mask = 1 << (data->hwirq - 1); 390 raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags); 391 val = nwl_bridge_readl(pcie, MSGF_LEG_MASK); 392 nwl_bridge_writel(pcie, (val & (~mask)), MSGF_LEG_MASK); 393 raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags); 394 } 395 396 static void nwl_unmask_leg_irq(struct irq_data *data) 397 { 398 struct irq_desc *desc = irq_to_desc(data->irq); 399 struct nwl_pcie *pcie; 400 unsigned long flags; 401 u32 mask; 402 u32 val; 403 404 pcie = irq_desc_get_chip_data(desc); 405 mask = 1 << (data->hwirq - 1); 406 raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags); 407 val = nwl_bridge_readl(pcie, MSGF_LEG_MASK); 408 nwl_bridge_writel(pcie, (val | mask), MSGF_LEG_MASK); 409 raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags); 410 } 411 412 static struct irq_chip nwl_leg_irq_chip = { 413 .name = "nwl_pcie:legacy", 414 .irq_enable = nwl_unmask_leg_irq, 415 .irq_disable = nwl_mask_leg_irq, 416 .irq_mask = nwl_mask_leg_irq, 417 .irq_unmask = nwl_unmask_leg_irq, 418 }; 419 420 static int nwl_legacy_map(struct irq_domain *domain, unsigned int irq, 421 irq_hw_number_t hwirq) 422 { 423 irq_set_chip_and_handler(irq, &nwl_leg_irq_chip, handle_level_irq); 424 irq_set_chip_data(irq, domain->host_data); 425 irq_set_status_flags(irq, IRQ_LEVEL); 426 427 return 0; 428 } 429 430 static const struct irq_domain_ops legacy_domain_ops = { 431 .map = nwl_legacy_map, 432 .xlate = pci_irqd_intx_xlate, 433 }; 434 435 #ifdef CONFIG_PCI_MSI 436 static struct irq_chip nwl_msi_irq_chip = { 437 .name = "nwl_pcie:msi", 438 .irq_enable = pci_msi_unmask_irq, 439 .irq_disable = pci_msi_mask_irq, 440 .irq_mask = pci_msi_mask_irq, 441 .irq_unmask = pci_msi_unmask_irq, 442 }; 443 444 static struct msi_domain_info nwl_msi_domain_info = { 445 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 446 MSI_FLAG_MULTI_PCI_MSI), 447 .chip = &nwl_msi_irq_chip, 448 }; 449 #endif 450 451 static void nwl_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) 452 { 453 struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data); 454 phys_addr_t msi_addr = pcie->phys_pcie_reg_base; 455 456 msg->address_lo = lower_32_bits(msi_addr); 457 msg->address_hi = upper_32_bits(msi_addr); 458 msg->data = data->hwirq; 459 } 460 461 static int nwl_msi_set_affinity(struct irq_data *irq_data, 462 const struct cpumask *mask, bool force) 463 { 464 return -EINVAL; 465 } 466 467 static struct irq_chip nwl_irq_chip = { 468 .name = "Xilinx MSI", 469 .irq_compose_msi_msg = nwl_compose_msi_msg, 470 .irq_set_affinity = nwl_msi_set_affinity, 471 }; 472 473 static int nwl_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, 474 unsigned int nr_irqs, void *args) 475 { 476 struct nwl_pcie *pcie = domain->host_data; 477 struct nwl_msi *msi = &pcie->msi; 478 int bit; 479 int i; 480 481 mutex_lock(&msi->lock); 482 bit = bitmap_find_free_region(msi->bitmap, INT_PCI_MSI_NR, 483 get_count_order(nr_irqs)); 484 if (bit < 0) { 485 mutex_unlock(&msi->lock); 486 return -ENOSPC; 487 } 488 489 for (i = 0; i < nr_irqs; i++) { 490 irq_domain_set_info(domain, virq + i, bit + i, &nwl_irq_chip, 491 domain->host_data, handle_simple_irq, 492 NULL, NULL); 493 } 494 mutex_unlock(&msi->lock); 495 return 0; 496 } 497 498 static void nwl_irq_domain_free(struct irq_domain *domain, unsigned int virq, 499 unsigned int nr_irqs) 500 { 501 struct irq_data *data = irq_domain_get_irq_data(domain, virq); 502 struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data); 503 struct nwl_msi *msi = &pcie->msi; 504 505 mutex_lock(&msi->lock); 506 bitmap_release_region(msi->bitmap, data->hwirq, 507 get_count_order(nr_irqs)); 508 mutex_unlock(&msi->lock); 509 } 510 511 static const struct irq_domain_ops dev_msi_domain_ops = { 512 .alloc = nwl_irq_domain_alloc, 513 .free = nwl_irq_domain_free, 514 }; 515 516 static int nwl_pcie_init_msi_irq_domain(struct nwl_pcie *pcie) 517 { 518 #ifdef CONFIG_PCI_MSI 519 struct device *dev = pcie->dev; 520 struct fwnode_handle *fwnode = of_node_to_fwnode(dev->of_node); 521 struct nwl_msi *msi = &pcie->msi; 522 523 msi->dev_domain = irq_domain_add_linear(NULL, INT_PCI_MSI_NR, 524 &dev_msi_domain_ops, pcie); 525 if (!msi->dev_domain) { 526 dev_err(dev, "failed to create dev IRQ domain\n"); 527 return -ENOMEM; 528 } 529 msi->msi_domain = pci_msi_create_irq_domain(fwnode, 530 &nwl_msi_domain_info, 531 msi->dev_domain); 532 if (!msi->msi_domain) { 533 dev_err(dev, "failed to create msi IRQ domain\n"); 534 irq_domain_remove(msi->dev_domain); 535 return -ENOMEM; 536 } 537 #endif 538 return 0; 539 } 540 541 static int nwl_pcie_init_irq_domain(struct nwl_pcie *pcie) 542 { 543 struct device *dev = pcie->dev; 544 struct device_node *node = dev->of_node; 545 struct device_node *legacy_intc_node; 546 547 legacy_intc_node = of_get_next_child(node, NULL); 548 if (!legacy_intc_node) { 549 dev_err(dev, "No legacy intc node found\n"); 550 return -EINVAL; 551 } 552 553 pcie->legacy_irq_domain = irq_domain_add_linear(legacy_intc_node, 554 PCI_NUM_INTX, 555 &legacy_domain_ops, 556 pcie); 557 of_node_put(legacy_intc_node); 558 if (!pcie->legacy_irq_domain) { 559 dev_err(dev, "failed to create IRQ domain\n"); 560 return -ENOMEM; 561 } 562 563 raw_spin_lock_init(&pcie->leg_mask_lock); 564 nwl_pcie_init_msi_irq_domain(pcie); 565 return 0; 566 } 567 568 static int nwl_pcie_enable_msi(struct nwl_pcie *pcie) 569 { 570 struct device *dev = pcie->dev; 571 struct platform_device *pdev = to_platform_device(dev); 572 struct nwl_msi *msi = &pcie->msi; 573 unsigned long base; 574 int ret; 575 int size = BITS_TO_LONGS(INT_PCI_MSI_NR) * sizeof(long); 576 577 mutex_init(&msi->lock); 578 579 msi->bitmap = kzalloc(size, GFP_KERNEL); 580 if (!msi->bitmap) 581 return -ENOMEM; 582 583 /* Get msi_1 IRQ number */ 584 msi->irq_msi1 = platform_get_irq_byname(pdev, "msi1"); 585 if (msi->irq_msi1 < 0) { 586 ret = -EINVAL; 587 goto err; 588 } 589 590 irq_set_chained_handler_and_data(msi->irq_msi1, 591 nwl_pcie_msi_handler_high, pcie); 592 593 /* Get msi_0 IRQ number */ 594 msi->irq_msi0 = platform_get_irq_byname(pdev, "msi0"); 595 if (msi->irq_msi0 < 0) { 596 ret = -EINVAL; 597 goto err; 598 } 599 600 irq_set_chained_handler_and_data(msi->irq_msi0, 601 nwl_pcie_msi_handler_low, pcie); 602 603 /* Check for msii_present bit */ 604 ret = nwl_bridge_readl(pcie, I_MSII_CAPABILITIES) & MSII_PRESENT; 605 if (!ret) { 606 dev_err(dev, "MSI not present\n"); 607 ret = -EIO; 608 goto err; 609 } 610 611 /* Enable MSII */ 612 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) | 613 MSII_ENABLE, I_MSII_CONTROL); 614 615 /* Enable MSII status */ 616 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) | 617 MSII_STATUS_ENABLE, I_MSII_CONTROL); 618 619 /* setup AFI/FPCI range */ 620 base = pcie->phys_pcie_reg_base; 621 nwl_bridge_writel(pcie, lower_32_bits(base), I_MSII_BASE_LO); 622 nwl_bridge_writel(pcie, upper_32_bits(base), I_MSII_BASE_HI); 623 624 /* 625 * For high range MSI interrupts: disable, clear any pending, 626 * and enable 627 */ 628 nwl_bridge_writel(pcie, 0, MSGF_MSI_MASK_HI); 629 630 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_HI) & 631 MSGF_MSI_SR_HI_MASK, MSGF_MSI_STATUS_HI); 632 633 nwl_bridge_writel(pcie, MSGF_MSI_SR_HI_MASK, MSGF_MSI_MASK_HI); 634 635 /* 636 * For low range MSI interrupts: disable, clear any pending, 637 * and enable 638 */ 639 nwl_bridge_writel(pcie, 0, MSGF_MSI_MASK_LO); 640 641 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_LO) & 642 MSGF_MSI_SR_LO_MASK, MSGF_MSI_STATUS_LO); 643 644 nwl_bridge_writel(pcie, MSGF_MSI_SR_LO_MASK, MSGF_MSI_MASK_LO); 645 646 return 0; 647 err: 648 kfree(msi->bitmap); 649 msi->bitmap = NULL; 650 return ret; 651 } 652 653 static int nwl_pcie_bridge_init(struct nwl_pcie *pcie) 654 { 655 struct device *dev = pcie->dev; 656 struct platform_device *pdev = to_platform_device(dev); 657 u32 breg_val, ecam_val, first_busno = 0; 658 int err; 659 660 breg_val = nwl_bridge_readl(pcie, E_BREG_CAPABILITIES) & BREG_PRESENT; 661 if (!breg_val) { 662 dev_err(dev, "BREG is not present\n"); 663 return breg_val; 664 } 665 666 /* Write bridge_off to breg base */ 667 nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_breg_base), 668 E_BREG_BASE_LO); 669 nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_breg_base), 670 E_BREG_BASE_HI); 671 672 /* Enable BREG */ 673 nwl_bridge_writel(pcie, ~BREG_ENABLE_FORCE & BREG_ENABLE, 674 E_BREG_CONTROL); 675 676 /* Disable DMA channel registers */ 677 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_PCIE_RX0) | 678 CFG_DMA_REG_BAR, BRCFG_PCIE_RX0); 679 680 /* Enable Ingress subtractive decode translation */ 681 nwl_bridge_writel(pcie, SET_ISUB_CONTROL, I_ISUB_CONTROL); 682 683 /* Enable msg filtering details */ 684 nwl_bridge_writel(pcie, CFG_ENABLE_MSG_FILTER_MASK, 685 BRCFG_PCIE_RX_MSG_FILTER); 686 687 err = nwl_wait_for_link(pcie); 688 if (err) 689 return err; 690 691 ecam_val = nwl_bridge_readl(pcie, E_ECAM_CAPABILITIES) & E_ECAM_PRESENT; 692 if (!ecam_val) { 693 dev_err(dev, "ECAM is not present\n"); 694 return ecam_val; 695 } 696 697 /* Enable ECAM */ 698 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) | 699 E_ECAM_CR_ENABLE, E_ECAM_CONTROL); 700 701 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) | 702 (pcie->ecam_value << E_ECAM_SIZE_SHIFT), 703 E_ECAM_CONTROL); 704 705 nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_ecam_base), 706 E_ECAM_BASE_LO); 707 nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_ecam_base), 708 E_ECAM_BASE_HI); 709 710 /* Get bus range */ 711 ecam_val = nwl_bridge_readl(pcie, E_ECAM_CONTROL); 712 pcie->last_busno = (ecam_val & E_ECAM_SIZE_LOC) >> E_ECAM_SIZE_SHIFT; 713 /* Write primary, secondary and subordinate bus numbers */ 714 ecam_val = first_busno; 715 ecam_val |= (first_busno + 1) << 8; 716 ecam_val |= (pcie->last_busno << E_ECAM_SIZE_SHIFT); 717 writel(ecam_val, (pcie->ecam_base + PCI_PRIMARY_BUS)); 718 719 if (nwl_pcie_link_up(pcie)) 720 dev_info(dev, "Link is UP\n"); 721 else 722 dev_info(dev, "Link is DOWN\n"); 723 724 /* Get misc IRQ number */ 725 pcie->irq_misc = platform_get_irq_byname(pdev, "misc"); 726 if (pcie->irq_misc < 0) 727 return -EINVAL; 728 729 err = devm_request_irq(dev, pcie->irq_misc, 730 nwl_pcie_misc_handler, IRQF_SHARED, 731 "nwl_pcie:misc", pcie); 732 if (err) { 733 dev_err(dev, "fail to register misc IRQ#%d\n", 734 pcie->irq_misc); 735 return err; 736 } 737 738 /* Disable all misc interrupts */ 739 nwl_bridge_writel(pcie, (u32)~MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK); 740 741 /* Clear pending misc interrupts */ 742 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MISC_STATUS) & 743 MSGF_MISC_SR_MASKALL, MSGF_MISC_STATUS); 744 745 /* Enable all misc interrupts */ 746 nwl_bridge_writel(pcie, MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK); 747 748 749 /* Disable all legacy interrupts */ 750 nwl_bridge_writel(pcie, (u32)~MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK); 751 752 /* Clear pending legacy interrupts */ 753 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_LEG_STATUS) & 754 MSGF_LEG_SR_MASKALL, MSGF_LEG_STATUS); 755 756 /* Enable all legacy interrupts */ 757 nwl_bridge_writel(pcie, MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK); 758 759 /* Enable the bridge config interrupt */ 760 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_INTERRUPT) | 761 BRCFG_INTERRUPT_MASK, BRCFG_INTERRUPT); 762 763 return 0; 764 } 765 766 static int nwl_pcie_parse_dt(struct nwl_pcie *pcie, 767 struct platform_device *pdev) 768 { 769 struct device *dev = pcie->dev; 770 struct resource *res; 771 772 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "breg"); 773 pcie->breg_base = devm_ioremap_resource(dev, res); 774 if (IS_ERR(pcie->breg_base)) 775 return PTR_ERR(pcie->breg_base); 776 pcie->phys_breg_base = res->start; 777 778 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcireg"); 779 pcie->pcireg_base = devm_ioremap_resource(dev, res); 780 if (IS_ERR(pcie->pcireg_base)) 781 return PTR_ERR(pcie->pcireg_base); 782 pcie->phys_pcie_reg_base = res->start; 783 784 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg"); 785 pcie->ecam_base = devm_pci_remap_cfg_resource(dev, res); 786 if (IS_ERR(pcie->ecam_base)) 787 return PTR_ERR(pcie->ecam_base); 788 pcie->phys_ecam_base = res->start; 789 790 /* Get intx IRQ number */ 791 pcie->irq_intx = platform_get_irq_byname(pdev, "intx"); 792 if (pcie->irq_intx < 0) 793 return pcie->irq_intx; 794 795 irq_set_chained_handler_and_data(pcie->irq_intx, 796 nwl_pcie_leg_handler, pcie); 797 798 return 0; 799 } 800 801 static const struct of_device_id nwl_pcie_of_match[] = { 802 { .compatible = "xlnx,nwl-pcie-2.11", }, 803 {} 804 }; 805 806 static int nwl_pcie_probe(struct platform_device *pdev) 807 { 808 struct device *dev = &pdev->dev; 809 struct nwl_pcie *pcie; 810 struct pci_host_bridge *bridge; 811 int err; 812 813 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie)); 814 if (!bridge) 815 return -ENODEV; 816 817 pcie = pci_host_bridge_priv(bridge); 818 819 pcie->dev = dev; 820 pcie->ecam_value = NWL_ECAM_VALUE_DEFAULT; 821 822 err = nwl_pcie_parse_dt(pcie, pdev); 823 if (err) { 824 dev_err(dev, "Parsing DT failed\n"); 825 return err; 826 } 827 828 err = nwl_pcie_bridge_init(pcie); 829 if (err) { 830 dev_err(dev, "HW Initialization failed\n"); 831 return err; 832 } 833 834 err = nwl_pcie_init_irq_domain(pcie); 835 if (err) { 836 dev_err(dev, "Failed creating IRQ Domain\n"); 837 return err; 838 } 839 840 bridge->sysdata = pcie; 841 bridge->ops = &nwl_pcie_ops; 842 843 if (IS_ENABLED(CONFIG_PCI_MSI)) { 844 err = nwl_pcie_enable_msi(pcie); 845 if (err < 0) { 846 dev_err(dev, "failed to enable MSI support: %d\n", err); 847 return err; 848 } 849 } 850 851 return pci_host_probe(bridge); 852 } 853 854 static struct platform_driver nwl_pcie_driver = { 855 .driver = { 856 .name = "nwl-pcie", 857 .suppress_bind_attrs = true, 858 .of_match_table = nwl_pcie_of_match, 859 }, 860 .probe = nwl_pcie_probe, 861 }; 862 builtin_platform_driver(nwl_pcie_driver); 863