1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * PCIe host controller driver for NWL PCIe Bridge 4 * Based on pcie-xilinx.c, pci-tegra.c 5 * 6 * (C) Copyright 2014 - 2015, Xilinx, Inc. 7 */ 8 9 #include <linux/delay.h> 10 #include <linux/interrupt.h> 11 #include <linux/irq.h> 12 #include <linux/irqdomain.h> 13 #include <linux/kernel.h> 14 #include <linux/init.h> 15 #include <linux/msi.h> 16 #include <linux/of_address.h> 17 #include <linux/of_pci.h> 18 #include <linux/of_platform.h> 19 #include <linux/of_irq.h> 20 #include <linux/pci.h> 21 #include <linux/pci-ecam.h> 22 #include <linux/platform_device.h> 23 #include <linux/irqchip/chained_irq.h> 24 25 #include "../pci.h" 26 27 /* Bridge core config registers */ 28 #define BRCFG_PCIE_RX0 0x00000000 29 #define BRCFG_INTERRUPT 0x00000010 30 #define BRCFG_PCIE_RX_MSG_FILTER 0x00000020 31 32 /* Egress - Bridge translation registers */ 33 #define E_BREG_CAPABILITIES 0x00000200 34 #define E_BREG_CONTROL 0x00000208 35 #define E_BREG_BASE_LO 0x00000210 36 #define E_BREG_BASE_HI 0x00000214 37 #define E_ECAM_CAPABILITIES 0x00000220 38 #define E_ECAM_CONTROL 0x00000228 39 #define E_ECAM_BASE_LO 0x00000230 40 #define E_ECAM_BASE_HI 0x00000234 41 42 /* Ingress - address translations */ 43 #define I_MSII_CAPABILITIES 0x00000300 44 #define I_MSII_CONTROL 0x00000308 45 #define I_MSII_BASE_LO 0x00000310 46 #define I_MSII_BASE_HI 0x00000314 47 48 #define I_ISUB_CONTROL 0x000003E8 49 #define SET_ISUB_CONTROL BIT(0) 50 /* Rxed msg fifo - Interrupt status registers */ 51 #define MSGF_MISC_STATUS 0x00000400 52 #define MSGF_MISC_MASK 0x00000404 53 #define MSGF_LEG_STATUS 0x00000420 54 #define MSGF_LEG_MASK 0x00000424 55 #define MSGF_MSI_STATUS_LO 0x00000440 56 #define MSGF_MSI_STATUS_HI 0x00000444 57 #define MSGF_MSI_MASK_LO 0x00000448 58 #define MSGF_MSI_MASK_HI 0x0000044C 59 60 /* Msg filter mask bits */ 61 #define CFG_ENABLE_PM_MSG_FWD BIT(1) 62 #define CFG_ENABLE_INT_MSG_FWD BIT(2) 63 #define CFG_ENABLE_ERR_MSG_FWD BIT(3) 64 #define CFG_ENABLE_MSG_FILTER_MASK (CFG_ENABLE_PM_MSG_FWD | \ 65 CFG_ENABLE_INT_MSG_FWD | \ 66 CFG_ENABLE_ERR_MSG_FWD) 67 68 /* Misc interrupt status mask bits */ 69 #define MSGF_MISC_SR_RXMSG_AVAIL BIT(0) 70 #define MSGF_MISC_SR_RXMSG_OVER BIT(1) 71 #define MSGF_MISC_SR_SLAVE_ERR BIT(4) 72 #define MSGF_MISC_SR_MASTER_ERR BIT(5) 73 #define MSGF_MISC_SR_I_ADDR_ERR BIT(6) 74 #define MSGF_MISC_SR_E_ADDR_ERR BIT(7) 75 #define MSGF_MISC_SR_FATAL_AER BIT(16) 76 #define MSGF_MISC_SR_NON_FATAL_AER BIT(17) 77 #define MSGF_MISC_SR_CORR_AER BIT(18) 78 #define MSGF_MISC_SR_UR_DETECT BIT(20) 79 #define MSGF_MISC_SR_NON_FATAL_DEV BIT(22) 80 #define MSGF_MISC_SR_FATAL_DEV BIT(23) 81 #define MSGF_MISC_SR_LINK_DOWN BIT(24) 82 #define MSGF_MSIC_SR_LINK_AUTO_BWIDTH BIT(25) 83 #define MSGF_MSIC_SR_LINK_BWIDTH BIT(26) 84 85 #define MSGF_MISC_SR_MASKALL (MSGF_MISC_SR_RXMSG_AVAIL | \ 86 MSGF_MISC_SR_RXMSG_OVER | \ 87 MSGF_MISC_SR_SLAVE_ERR | \ 88 MSGF_MISC_SR_MASTER_ERR | \ 89 MSGF_MISC_SR_I_ADDR_ERR | \ 90 MSGF_MISC_SR_E_ADDR_ERR | \ 91 MSGF_MISC_SR_FATAL_AER | \ 92 MSGF_MISC_SR_NON_FATAL_AER | \ 93 MSGF_MISC_SR_CORR_AER | \ 94 MSGF_MISC_SR_UR_DETECT | \ 95 MSGF_MISC_SR_NON_FATAL_DEV | \ 96 MSGF_MISC_SR_FATAL_DEV | \ 97 MSGF_MISC_SR_LINK_DOWN | \ 98 MSGF_MSIC_SR_LINK_AUTO_BWIDTH | \ 99 MSGF_MSIC_SR_LINK_BWIDTH) 100 101 /* Legacy interrupt status mask bits */ 102 #define MSGF_LEG_SR_INTA BIT(0) 103 #define MSGF_LEG_SR_INTB BIT(1) 104 #define MSGF_LEG_SR_INTC BIT(2) 105 #define MSGF_LEG_SR_INTD BIT(3) 106 #define MSGF_LEG_SR_MASKALL (MSGF_LEG_SR_INTA | MSGF_LEG_SR_INTB | \ 107 MSGF_LEG_SR_INTC | MSGF_LEG_SR_INTD) 108 109 /* MSI interrupt status mask bits */ 110 #define MSGF_MSI_SR_LO_MASK GENMASK(31, 0) 111 #define MSGF_MSI_SR_HI_MASK GENMASK(31, 0) 112 113 #define MSII_PRESENT BIT(0) 114 #define MSII_ENABLE BIT(0) 115 #define MSII_STATUS_ENABLE BIT(15) 116 117 /* Bridge config interrupt mask */ 118 #define BRCFG_INTERRUPT_MASK BIT(0) 119 #define BREG_PRESENT BIT(0) 120 #define BREG_ENABLE BIT(0) 121 #define BREG_ENABLE_FORCE BIT(1) 122 123 /* E_ECAM status mask bits */ 124 #define E_ECAM_PRESENT BIT(0) 125 #define E_ECAM_CR_ENABLE BIT(0) 126 #define E_ECAM_SIZE_LOC GENMASK(20, 16) 127 #define E_ECAM_SIZE_SHIFT 16 128 #define NWL_ECAM_VALUE_DEFAULT 12 129 130 #define CFG_DMA_REG_BAR GENMASK(2, 0) 131 132 #define INT_PCI_MSI_NR (2 * 32) 133 134 /* Readin the PS_LINKUP */ 135 #define PS_LINKUP_OFFSET 0x00000238 136 #define PCIE_PHY_LINKUP_BIT BIT(0) 137 #define PHY_RDY_LINKUP_BIT BIT(1) 138 139 /* Parameters for the waiting for link up routine */ 140 #define LINK_WAIT_MAX_RETRIES 10 141 #define LINK_WAIT_USLEEP_MIN 90000 142 #define LINK_WAIT_USLEEP_MAX 100000 143 144 struct nwl_msi { /* MSI information */ 145 struct irq_domain *msi_domain; 146 unsigned long *bitmap; 147 struct irq_domain *dev_domain; 148 struct mutex lock; /* protect bitmap variable */ 149 int irq_msi0; 150 int irq_msi1; 151 }; 152 153 struct nwl_pcie { 154 struct device *dev; 155 void __iomem *breg_base; 156 void __iomem *pcireg_base; 157 void __iomem *ecam_base; 158 phys_addr_t phys_breg_base; /* Physical Bridge Register Base */ 159 phys_addr_t phys_pcie_reg_base; /* Physical PCIe Controller Base */ 160 phys_addr_t phys_ecam_base; /* Physical Configuration Base */ 161 u32 breg_size; 162 u32 pcie_reg_size; 163 u32 ecam_size; 164 int irq_intx; 165 int irq_misc; 166 u32 ecam_value; 167 u8 last_busno; 168 struct nwl_msi msi; 169 struct irq_domain *legacy_irq_domain; 170 raw_spinlock_t leg_mask_lock; 171 }; 172 173 static inline u32 nwl_bridge_readl(struct nwl_pcie *pcie, u32 off) 174 { 175 return readl(pcie->breg_base + off); 176 } 177 178 static inline void nwl_bridge_writel(struct nwl_pcie *pcie, u32 val, u32 off) 179 { 180 writel(val, pcie->breg_base + off); 181 } 182 183 static bool nwl_pcie_link_up(struct nwl_pcie *pcie) 184 { 185 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PCIE_PHY_LINKUP_BIT) 186 return true; 187 return false; 188 } 189 190 static bool nwl_phy_link_up(struct nwl_pcie *pcie) 191 { 192 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PHY_RDY_LINKUP_BIT) 193 return true; 194 return false; 195 } 196 197 static int nwl_wait_for_link(struct nwl_pcie *pcie) 198 { 199 struct device *dev = pcie->dev; 200 int retries; 201 202 /* check if the link is up or not */ 203 for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { 204 if (nwl_phy_link_up(pcie)) 205 return 0; 206 usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); 207 } 208 209 dev_err(dev, "PHY link never came up\n"); 210 return -ETIMEDOUT; 211 } 212 213 static bool nwl_pcie_valid_device(struct pci_bus *bus, unsigned int devfn) 214 { 215 struct nwl_pcie *pcie = bus->sysdata; 216 217 /* Check link before accessing downstream ports */ 218 if (!pci_is_root_bus(bus)) { 219 if (!nwl_pcie_link_up(pcie)) 220 return false; 221 } else if (devfn > 0) 222 /* Only one device down on each root port */ 223 return false; 224 225 return true; 226 } 227 228 /** 229 * nwl_pcie_map_bus - Get configuration base 230 * 231 * @bus: Bus structure of current bus 232 * @devfn: Device/function 233 * @where: Offset from base 234 * 235 * Return: Base address of the configuration space needed to be 236 * accessed. 237 */ 238 static void __iomem *nwl_pcie_map_bus(struct pci_bus *bus, unsigned int devfn, 239 int where) 240 { 241 struct nwl_pcie *pcie = bus->sysdata; 242 243 if (!nwl_pcie_valid_device(bus, devfn)) 244 return NULL; 245 246 return pcie->ecam_base + PCIE_ECAM_OFFSET(bus->number, devfn, where); 247 } 248 249 /* PCIe operations */ 250 static struct pci_ops nwl_pcie_ops = { 251 .map_bus = nwl_pcie_map_bus, 252 .read = pci_generic_config_read, 253 .write = pci_generic_config_write, 254 }; 255 256 static irqreturn_t nwl_pcie_misc_handler(int irq, void *data) 257 { 258 struct nwl_pcie *pcie = data; 259 struct device *dev = pcie->dev; 260 u32 misc_stat; 261 262 /* Checking for misc interrupts */ 263 misc_stat = nwl_bridge_readl(pcie, MSGF_MISC_STATUS) & 264 MSGF_MISC_SR_MASKALL; 265 if (!misc_stat) 266 return IRQ_NONE; 267 268 if (misc_stat & MSGF_MISC_SR_RXMSG_OVER) 269 dev_err(dev, "Received Message FIFO Overflow\n"); 270 271 if (misc_stat & MSGF_MISC_SR_SLAVE_ERR) 272 dev_err(dev, "Slave error\n"); 273 274 if (misc_stat & MSGF_MISC_SR_MASTER_ERR) 275 dev_err(dev, "Master error\n"); 276 277 if (misc_stat & MSGF_MISC_SR_I_ADDR_ERR) 278 dev_err(dev, "In Misc Ingress address translation error\n"); 279 280 if (misc_stat & MSGF_MISC_SR_E_ADDR_ERR) 281 dev_err(dev, "In Misc Egress address translation error\n"); 282 283 if (misc_stat & MSGF_MISC_SR_FATAL_AER) 284 dev_err(dev, "Fatal Error in AER Capability\n"); 285 286 if (misc_stat & MSGF_MISC_SR_NON_FATAL_AER) 287 dev_err(dev, "Non-Fatal Error in AER Capability\n"); 288 289 if (misc_stat & MSGF_MISC_SR_CORR_AER) 290 dev_err(dev, "Correctable Error in AER Capability\n"); 291 292 if (misc_stat & MSGF_MISC_SR_UR_DETECT) 293 dev_err(dev, "Unsupported request Detected\n"); 294 295 if (misc_stat & MSGF_MISC_SR_NON_FATAL_DEV) 296 dev_err(dev, "Non-Fatal Error Detected\n"); 297 298 if (misc_stat & MSGF_MISC_SR_FATAL_DEV) 299 dev_err(dev, "Fatal Error Detected\n"); 300 301 if (misc_stat & MSGF_MSIC_SR_LINK_AUTO_BWIDTH) 302 dev_info(dev, "Link Autonomous Bandwidth Management Status bit set\n"); 303 304 if (misc_stat & MSGF_MSIC_SR_LINK_BWIDTH) 305 dev_info(dev, "Link Bandwidth Management Status bit set\n"); 306 307 /* Clear misc interrupt status */ 308 nwl_bridge_writel(pcie, misc_stat, MSGF_MISC_STATUS); 309 310 return IRQ_HANDLED; 311 } 312 313 static void nwl_pcie_leg_handler(struct irq_desc *desc) 314 { 315 struct irq_chip *chip = irq_desc_get_chip(desc); 316 struct nwl_pcie *pcie; 317 unsigned long status; 318 u32 bit; 319 u32 virq; 320 321 chained_irq_enter(chip, desc); 322 pcie = irq_desc_get_handler_data(desc); 323 324 while ((status = nwl_bridge_readl(pcie, MSGF_LEG_STATUS) & 325 MSGF_LEG_SR_MASKALL) != 0) { 326 for_each_set_bit(bit, &status, PCI_NUM_INTX) { 327 virq = irq_find_mapping(pcie->legacy_irq_domain, bit); 328 if (virq) 329 generic_handle_irq(virq); 330 } 331 } 332 333 chained_irq_exit(chip, desc); 334 } 335 336 static void nwl_pcie_handle_msi_irq(struct nwl_pcie *pcie, u32 status_reg) 337 { 338 struct nwl_msi *msi; 339 unsigned long status; 340 u32 bit; 341 u32 virq; 342 343 msi = &pcie->msi; 344 345 while ((status = nwl_bridge_readl(pcie, status_reg)) != 0) { 346 for_each_set_bit(bit, &status, 32) { 347 nwl_bridge_writel(pcie, 1 << bit, status_reg); 348 virq = irq_find_mapping(msi->dev_domain, bit); 349 if (virq) 350 generic_handle_irq(virq); 351 } 352 } 353 } 354 355 static void nwl_pcie_msi_handler_high(struct irq_desc *desc) 356 { 357 struct irq_chip *chip = irq_desc_get_chip(desc); 358 struct nwl_pcie *pcie = irq_desc_get_handler_data(desc); 359 360 chained_irq_enter(chip, desc); 361 nwl_pcie_handle_msi_irq(pcie, MSGF_MSI_STATUS_HI); 362 chained_irq_exit(chip, desc); 363 } 364 365 static void nwl_pcie_msi_handler_low(struct irq_desc *desc) 366 { 367 struct irq_chip *chip = irq_desc_get_chip(desc); 368 struct nwl_pcie *pcie = irq_desc_get_handler_data(desc); 369 370 chained_irq_enter(chip, desc); 371 nwl_pcie_handle_msi_irq(pcie, MSGF_MSI_STATUS_LO); 372 chained_irq_exit(chip, desc); 373 } 374 375 static void nwl_mask_leg_irq(struct irq_data *data) 376 { 377 struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data); 378 unsigned long flags; 379 u32 mask; 380 u32 val; 381 382 mask = 1 << (data->hwirq - 1); 383 raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags); 384 val = nwl_bridge_readl(pcie, MSGF_LEG_MASK); 385 nwl_bridge_writel(pcie, (val & (~mask)), MSGF_LEG_MASK); 386 raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags); 387 } 388 389 static void nwl_unmask_leg_irq(struct irq_data *data) 390 { 391 struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data); 392 unsigned long flags; 393 u32 mask; 394 u32 val; 395 396 mask = 1 << (data->hwirq - 1); 397 raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags); 398 val = nwl_bridge_readl(pcie, MSGF_LEG_MASK); 399 nwl_bridge_writel(pcie, (val | mask), MSGF_LEG_MASK); 400 raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags); 401 } 402 403 static struct irq_chip nwl_leg_irq_chip = { 404 .name = "nwl_pcie:legacy", 405 .irq_enable = nwl_unmask_leg_irq, 406 .irq_disable = nwl_mask_leg_irq, 407 .irq_mask = nwl_mask_leg_irq, 408 .irq_unmask = nwl_unmask_leg_irq, 409 }; 410 411 static int nwl_legacy_map(struct irq_domain *domain, unsigned int irq, 412 irq_hw_number_t hwirq) 413 { 414 irq_set_chip_and_handler(irq, &nwl_leg_irq_chip, handle_level_irq); 415 irq_set_chip_data(irq, domain->host_data); 416 irq_set_status_flags(irq, IRQ_LEVEL); 417 418 return 0; 419 } 420 421 static const struct irq_domain_ops legacy_domain_ops = { 422 .map = nwl_legacy_map, 423 .xlate = pci_irqd_intx_xlate, 424 }; 425 426 #ifdef CONFIG_PCI_MSI 427 static struct irq_chip nwl_msi_irq_chip = { 428 .name = "nwl_pcie:msi", 429 .irq_enable = pci_msi_unmask_irq, 430 .irq_disable = pci_msi_mask_irq, 431 .irq_mask = pci_msi_mask_irq, 432 .irq_unmask = pci_msi_unmask_irq, 433 }; 434 435 static struct msi_domain_info nwl_msi_domain_info = { 436 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 437 MSI_FLAG_MULTI_PCI_MSI), 438 .chip = &nwl_msi_irq_chip, 439 }; 440 #endif 441 442 static void nwl_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) 443 { 444 struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data); 445 phys_addr_t msi_addr = pcie->phys_pcie_reg_base; 446 447 msg->address_lo = lower_32_bits(msi_addr); 448 msg->address_hi = upper_32_bits(msi_addr); 449 msg->data = data->hwirq; 450 } 451 452 static int nwl_msi_set_affinity(struct irq_data *irq_data, 453 const struct cpumask *mask, bool force) 454 { 455 return -EINVAL; 456 } 457 458 static struct irq_chip nwl_irq_chip = { 459 .name = "Xilinx MSI", 460 .irq_compose_msi_msg = nwl_compose_msi_msg, 461 .irq_set_affinity = nwl_msi_set_affinity, 462 }; 463 464 static int nwl_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, 465 unsigned int nr_irqs, void *args) 466 { 467 struct nwl_pcie *pcie = domain->host_data; 468 struct nwl_msi *msi = &pcie->msi; 469 int bit; 470 int i; 471 472 mutex_lock(&msi->lock); 473 bit = bitmap_find_free_region(msi->bitmap, INT_PCI_MSI_NR, 474 get_count_order(nr_irqs)); 475 if (bit < 0) { 476 mutex_unlock(&msi->lock); 477 return -ENOSPC; 478 } 479 480 for (i = 0; i < nr_irqs; i++) { 481 irq_domain_set_info(domain, virq + i, bit + i, &nwl_irq_chip, 482 domain->host_data, handle_simple_irq, 483 NULL, NULL); 484 } 485 mutex_unlock(&msi->lock); 486 return 0; 487 } 488 489 static void nwl_irq_domain_free(struct irq_domain *domain, unsigned int virq, 490 unsigned int nr_irqs) 491 { 492 struct irq_data *data = irq_domain_get_irq_data(domain, virq); 493 struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data); 494 struct nwl_msi *msi = &pcie->msi; 495 496 mutex_lock(&msi->lock); 497 bitmap_release_region(msi->bitmap, data->hwirq, 498 get_count_order(nr_irqs)); 499 mutex_unlock(&msi->lock); 500 } 501 502 static const struct irq_domain_ops dev_msi_domain_ops = { 503 .alloc = nwl_irq_domain_alloc, 504 .free = nwl_irq_domain_free, 505 }; 506 507 static int nwl_pcie_init_msi_irq_domain(struct nwl_pcie *pcie) 508 { 509 #ifdef CONFIG_PCI_MSI 510 struct device *dev = pcie->dev; 511 struct fwnode_handle *fwnode = of_node_to_fwnode(dev->of_node); 512 struct nwl_msi *msi = &pcie->msi; 513 514 msi->dev_domain = irq_domain_add_linear(NULL, INT_PCI_MSI_NR, 515 &dev_msi_domain_ops, pcie); 516 if (!msi->dev_domain) { 517 dev_err(dev, "failed to create dev IRQ domain\n"); 518 return -ENOMEM; 519 } 520 msi->msi_domain = pci_msi_create_irq_domain(fwnode, 521 &nwl_msi_domain_info, 522 msi->dev_domain); 523 if (!msi->msi_domain) { 524 dev_err(dev, "failed to create msi IRQ domain\n"); 525 irq_domain_remove(msi->dev_domain); 526 return -ENOMEM; 527 } 528 #endif 529 return 0; 530 } 531 532 static int nwl_pcie_init_irq_domain(struct nwl_pcie *pcie) 533 { 534 struct device *dev = pcie->dev; 535 struct device_node *node = dev->of_node; 536 struct device_node *legacy_intc_node; 537 538 legacy_intc_node = of_get_next_child(node, NULL); 539 if (!legacy_intc_node) { 540 dev_err(dev, "No legacy intc node found\n"); 541 return -EINVAL; 542 } 543 544 pcie->legacy_irq_domain = irq_domain_add_linear(legacy_intc_node, 545 PCI_NUM_INTX, 546 &legacy_domain_ops, 547 pcie); 548 of_node_put(legacy_intc_node); 549 if (!pcie->legacy_irq_domain) { 550 dev_err(dev, "failed to create IRQ domain\n"); 551 return -ENOMEM; 552 } 553 554 raw_spin_lock_init(&pcie->leg_mask_lock); 555 nwl_pcie_init_msi_irq_domain(pcie); 556 return 0; 557 } 558 559 static int nwl_pcie_enable_msi(struct nwl_pcie *pcie) 560 { 561 struct device *dev = pcie->dev; 562 struct platform_device *pdev = to_platform_device(dev); 563 struct nwl_msi *msi = &pcie->msi; 564 unsigned long base; 565 int ret; 566 int size = BITS_TO_LONGS(INT_PCI_MSI_NR) * sizeof(long); 567 568 mutex_init(&msi->lock); 569 570 msi->bitmap = kzalloc(size, GFP_KERNEL); 571 if (!msi->bitmap) 572 return -ENOMEM; 573 574 /* Get msi_1 IRQ number */ 575 msi->irq_msi1 = platform_get_irq_byname(pdev, "msi1"); 576 if (msi->irq_msi1 < 0) { 577 ret = -EINVAL; 578 goto err; 579 } 580 581 irq_set_chained_handler_and_data(msi->irq_msi1, 582 nwl_pcie_msi_handler_high, pcie); 583 584 /* Get msi_0 IRQ number */ 585 msi->irq_msi0 = platform_get_irq_byname(pdev, "msi0"); 586 if (msi->irq_msi0 < 0) { 587 ret = -EINVAL; 588 goto err; 589 } 590 591 irq_set_chained_handler_and_data(msi->irq_msi0, 592 nwl_pcie_msi_handler_low, pcie); 593 594 /* Check for msii_present bit */ 595 ret = nwl_bridge_readl(pcie, I_MSII_CAPABILITIES) & MSII_PRESENT; 596 if (!ret) { 597 dev_err(dev, "MSI not present\n"); 598 ret = -EIO; 599 goto err; 600 } 601 602 /* Enable MSII */ 603 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) | 604 MSII_ENABLE, I_MSII_CONTROL); 605 606 /* Enable MSII status */ 607 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) | 608 MSII_STATUS_ENABLE, I_MSII_CONTROL); 609 610 /* setup AFI/FPCI range */ 611 base = pcie->phys_pcie_reg_base; 612 nwl_bridge_writel(pcie, lower_32_bits(base), I_MSII_BASE_LO); 613 nwl_bridge_writel(pcie, upper_32_bits(base), I_MSII_BASE_HI); 614 615 /* 616 * For high range MSI interrupts: disable, clear any pending, 617 * and enable 618 */ 619 nwl_bridge_writel(pcie, 0, MSGF_MSI_MASK_HI); 620 621 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_HI) & 622 MSGF_MSI_SR_HI_MASK, MSGF_MSI_STATUS_HI); 623 624 nwl_bridge_writel(pcie, MSGF_MSI_SR_HI_MASK, MSGF_MSI_MASK_HI); 625 626 /* 627 * For low range MSI interrupts: disable, clear any pending, 628 * and enable 629 */ 630 nwl_bridge_writel(pcie, 0, MSGF_MSI_MASK_LO); 631 632 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_LO) & 633 MSGF_MSI_SR_LO_MASK, MSGF_MSI_STATUS_LO); 634 635 nwl_bridge_writel(pcie, MSGF_MSI_SR_LO_MASK, MSGF_MSI_MASK_LO); 636 637 return 0; 638 err: 639 kfree(msi->bitmap); 640 msi->bitmap = NULL; 641 return ret; 642 } 643 644 static int nwl_pcie_bridge_init(struct nwl_pcie *pcie) 645 { 646 struct device *dev = pcie->dev; 647 struct platform_device *pdev = to_platform_device(dev); 648 u32 breg_val, ecam_val, first_busno = 0; 649 int err; 650 651 breg_val = nwl_bridge_readl(pcie, E_BREG_CAPABILITIES) & BREG_PRESENT; 652 if (!breg_val) { 653 dev_err(dev, "BREG is not present\n"); 654 return breg_val; 655 } 656 657 /* Write bridge_off to breg base */ 658 nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_breg_base), 659 E_BREG_BASE_LO); 660 nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_breg_base), 661 E_BREG_BASE_HI); 662 663 /* Enable BREG */ 664 nwl_bridge_writel(pcie, ~BREG_ENABLE_FORCE & BREG_ENABLE, 665 E_BREG_CONTROL); 666 667 /* Disable DMA channel registers */ 668 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_PCIE_RX0) | 669 CFG_DMA_REG_BAR, BRCFG_PCIE_RX0); 670 671 /* Enable Ingress subtractive decode translation */ 672 nwl_bridge_writel(pcie, SET_ISUB_CONTROL, I_ISUB_CONTROL); 673 674 /* Enable msg filtering details */ 675 nwl_bridge_writel(pcie, CFG_ENABLE_MSG_FILTER_MASK, 676 BRCFG_PCIE_RX_MSG_FILTER); 677 678 err = nwl_wait_for_link(pcie); 679 if (err) 680 return err; 681 682 ecam_val = nwl_bridge_readl(pcie, E_ECAM_CAPABILITIES) & E_ECAM_PRESENT; 683 if (!ecam_val) { 684 dev_err(dev, "ECAM is not present\n"); 685 return ecam_val; 686 } 687 688 /* Enable ECAM */ 689 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) | 690 E_ECAM_CR_ENABLE, E_ECAM_CONTROL); 691 692 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) | 693 (pcie->ecam_value << E_ECAM_SIZE_SHIFT), 694 E_ECAM_CONTROL); 695 696 nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_ecam_base), 697 E_ECAM_BASE_LO); 698 nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_ecam_base), 699 E_ECAM_BASE_HI); 700 701 /* Get bus range */ 702 ecam_val = nwl_bridge_readl(pcie, E_ECAM_CONTROL); 703 pcie->last_busno = (ecam_val & E_ECAM_SIZE_LOC) >> E_ECAM_SIZE_SHIFT; 704 /* Write primary, secondary and subordinate bus numbers */ 705 ecam_val = first_busno; 706 ecam_val |= (first_busno + 1) << 8; 707 ecam_val |= (pcie->last_busno << E_ECAM_SIZE_SHIFT); 708 writel(ecam_val, (pcie->ecam_base + PCI_PRIMARY_BUS)); 709 710 if (nwl_pcie_link_up(pcie)) 711 dev_info(dev, "Link is UP\n"); 712 else 713 dev_info(dev, "Link is DOWN\n"); 714 715 /* Get misc IRQ number */ 716 pcie->irq_misc = platform_get_irq_byname(pdev, "misc"); 717 if (pcie->irq_misc < 0) 718 return -EINVAL; 719 720 err = devm_request_irq(dev, pcie->irq_misc, 721 nwl_pcie_misc_handler, IRQF_SHARED, 722 "nwl_pcie:misc", pcie); 723 if (err) { 724 dev_err(dev, "fail to register misc IRQ#%d\n", 725 pcie->irq_misc); 726 return err; 727 } 728 729 /* Disable all misc interrupts */ 730 nwl_bridge_writel(pcie, (u32)~MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK); 731 732 /* Clear pending misc interrupts */ 733 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MISC_STATUS) & 734 MSGF_MISC_SR_MASKALL, MSGF_MISC_STATUS); 735 736 /* Enable all misc interrupts */ 737 nwl_bridge_writel(pcie, MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK); 738 739 740 /* Disable all legacy interrupts */ 741 nwl_bridge_writel(pcie, (u32)~MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK); 742 743 /* Clear pending legacy interrupts */ 744 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_LEG_STATUS) & 745 MSGF_LEG_SR_MASKALL, MSGF_LEG_STATUS); 746 747 /* Enable all legacy interrupts */ 748 nwl_bridge_writel(pcie, MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK); 749 750 /* Enable the bridge config interrupt */ 751 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_INTERRUPT) | 752 BRCFG_INTERRUPT_MASK, BRCFG_INTERRUPT); 753 754 return 0; 755 } 756 757 static int nwl_pcie_parse_dt(struct nwl_pcie *pcie, 758 struct platform_device *pdev) 759 { 760 struct device *dev = pcie->dev; 761 struct resource *res; 762 763 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "breg"); 764 pcie->breg_base = devm_ioremap_resource(dev, res); 765 if (IS_ERR(pcie->breg_base)) 766 return PTR_ERR(pcie->breg_base); 767 pcie->phys_breg_base = res->start; 768 769 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcireg"); 770 pcie->pcireg_base = devm_ioremap_resource(dev, res); 771 if (IS_ERR(pcie->pcireg_base)) 772 return PTR_ERR(pcie->pcireg_base); 773 pcie->phys_pcie_reg_base = res->start; 774 775 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg"); 776 pcie->ecam_base = devm_pci_remap_cfg_resource(dev, res); 777 if (IS_ERR(pcie->ecam_base)) 778 return PTR_ERR(pcie->ecam_base); 779 pcie->phys_ecam_base = res->start; 780 781 /* Get intx IRQ number */ 782 pcie->irq_intx = platform_get_irq_byname(pdev, "intx"); 783 if (pcie->irq_intx < 0) 784 return pcie->irq_intx; 785 786 irq_set_chained_handler_and_data(pcie->irq_intx, 787 nwl_pcie_leg_handler, pcie); 788 789 return 0; 790 } 791 792 static const struct of_device_id nwl_pcie_of_match[] = { 793 { .compatible = "xlnx,nwl-pcie-2.11", }, 794 {} 795 }; 796 797 static int nwl_pcie_probe(struct platform_device *pdev) 798 { 799 struct device *dev = &pdev->dev; 800 struct nwl_pcie *pcie; 801 struct pci_host_bridge *bridge; 802 int err; 803 804 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie)); 805 if (!bridge) 806 return -ENODEV; 807 808 pcie = pci_host_bridge_priv(bridge); 809 810 pcie->dev = dev; 811 pcie->ecam_value = NWL_ECAM_VALUE_DEFAULT; 812 813 err = nwl_pcie_parse_dt(pcie, pdev); 814 if (err) { 815 dev_err(dev, "Parsing DT failed\n"); 816 return err; 817 } 818 819 err = nwl_pcie_bridge_init(pcie); 820 if (err) { 821 dev_err(dev, "HW Initialization failed\n"); 822 return err; 823 } 824 825 err = nwl_pcie_init_irq_domain(pcie); 826 if (err) { 827 dev_err(dev, "Failed creating IRQ Domain\n"); 828 return err; 829 } 830 831 bridge->sysdata = pcie; 832 bridge->ops = &nwl_pcie_ops; 833 834 if (IS_ENABLED(CONFIG_PCI_MSI)) { 835 err = nwl_pcie_enable_msi(pcie); 836 if (err < 0) { 837 dev_err(dev, "failed to enable MSI support: %d\n", err); 838 return err; 839 } 840 } 841 842 return pci_host_probe(bridge); 843 } 844 845 static struct platform_driver nwl_pcie_driver = { 846 .driver = { 847 .name = "nwl-pcie", 848 .suppress_bind_attrs = true, 849 .of_match_table = nwl_pcie_of_match, 850 }, 851 .probe = nwl_pcie_probe, 852 }; 853 builtin_platform_driver(nwl_pcie_driver); 854