1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * PCIe host controller driver for NWL PCIe Bridge 4 * Based on pcie-xilinx.c, pci-tegra.c 5 * 6 * (C) Copyright 2014 - 2015, Xilinx, Inc. 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/interrupt.h> 12 #include <linux/irq.h> 13 #include <linux/irqdomain.h> 14 #include <linux/kernel.h> 15 #include <linux/init.h> 16 #include <linux/msi.h> 17 #include <linux/of_address.h> 18 #include <linux/of_pci.h> 19 #include <linux/of_platform.h> 20 #include <linux/of_irq.h> 21 #include <linux/pci.h> 22 #include <linux/pci-ecam.h> 23 #include <linux/platform_device.h> 24 #include <linux/irqchip/chained_irq.h> 25 26 #include "../pci.h" 27 28 /* Bridge core config registers */ 29 #define BRCFG_PCIE_RX0 0x00000000 30 #define BRCFG_PCIE_RX1 0x00000004 31 #define BRCFG_INTERRUPT 0x00000010 32 #define BRCFG_PCIE_RX_MSG_FILTER 0x00000020 33 34 /* Egress - Bridge translation registers */ 35 #define E_BREG_CAPABILITIES 0x00000200 36 #define E_BREG_CONTROL 0x00000208 37 #define E_BREG_BASE_LO 0x00000210 38 #define E_BREG_BASE_HI 0x00000214 39 #define E_ECAM_CAPABILITIES 0x00000220 40 #define E_ECAM_CONTROL 0x00000228 41 #define E_ECAM_BASE_LO 0x00000230 42 #define E_ECAM_BASE_HI 0x00000234 43 44 /* Ingress - address translations */ 45 #define I_MSII_CAPABILITIES 0x00000300 46 #define I_MSII_CONTROL 0x00000308 47 #define I_MSII_BASE_LO 0x00000310 48 #define I_MSII_BASE_HI 0x00000314 49 50 #define I_ISUB_CONTROL 0x000003E8 51 #define SET_ISUB_CONTROL BIT(0) 52 /* Rxed msg fifo - Interrupt status registers */ 53 #define MSGF_MISC_STATUS 0x00000400 54 #define MSGF_MISC_MASK 0x00000404 55 #define MSGF_LEG_STATUS 0x00000420 56 #define MSGF_LEG_MASK 0x00000424 57 #define MSGF_MSI_STATUS_LO 0x00000440 58 #define MSGF_MSI_STATUS_HI 0x00000444 59 #define MSGF_MSI_MASK_LO 0x00000448 60 #define MSGF_MSI_MASK_HI 0x0000044C 61 62 /* Msg filter mask bits */ 63 #define CFG_ENABLE_PM_MSG_FWD BIT(1) 64 #define CFG_ENABLE_INT_MSG_FWD BIT(2) 65 #define CFG_ENABLE_ERR_MSG_FWD BIT(3) 66 #define CFG_ENABLE_MSG_FILTER_MASK (CFG_ENABLE_PM_MSG_FWD | \ 67 CFG_ENABLE_INT_MSG_FWD | \ 68 CFG_ENABLE_ERR_MSG_FWD) 69 70 /* Misc interrupt status mask bits */ 71 #define MSGF_MISC_SR_RXMSG_AVAIL BIT(0) 72 #define MSGF_MISC_SR_RXMSG_OVER BIT(1) 73 #define MSGF_MISC_SR_SLAVE_ERR BIT(4) 74 #define MSGF_MISC_SR_MASTER_ERR BIT(5) 75 #define MSGF_MISC_SR_I_ADDR_ERR BIT(6) 76 #define MSGF_MISC_SR_E_ADDR_ERR BIT(7) 77 #define MSGF_MISC_SR_FATAL_AER BIT(16) 78 #define MSGF_MISC_SR_NON_FATAL_AER BIT(17) 79 #define MSGF_MISC_SR_CORR_AER BIT(18) 80 #define MSGF_MISC_SR_UR_DETECT BIT(20) 81 #define MSGF_MISC_SR_NON_FATAL_DEV BIT(22) 82 #define MSGF_MISC_SR_FATAL_DEV BIT(23) 83 #define MSGF_MISC_SR_LINK_DOWN BIT(24) 84 #define MSGF_MSIC_SR_LINK_AUTO_BWIDTH BIT(25) 85 #define MSGF_MSIC_SR_LINK_BWIDTH BIT(26) 86 87 #define MSGF_MISC_SR_MASKALL (MSGF_MISC_SR_RXMSG_AVAIL | \ 88 MSGF_MISC_SR_RXMSG_OVER | \ 89 MSGF_MISC_SR_SLAVE_ERR | \ 90 MSGF_MISC_SR_MASTER_ERR | \ 91 MSGF_MISC_SR_I_ADDR_ERR | \ 92 MSGF_MISC_SR_E_ADDR_ERR | \ 93 MSGF_MISC_SR_FATAL_AER | \ 94 MSGF_MISC_SR_NON_FATAL_AER | \ 95 MSGF_MISC_SR_CORR_AER | \ 96 MSGF_MISC_SR_UR_DETECT | \ 97 MSGF_MISC_SR_NON_FATAL_DEV | \ 98 MSGF_MISC_SR_FATAL_DEV | \ 99 MSGF_MISC_SR_LINK_DOWN | \ 100 MSGF_MSIC_SR_LINK_AUTO_BWIDTH | \ 101 MSGF_MSIC_SR_LINK_BWIDTH) 102 103 /* Legacy interrupt status mask bits */ 104 #define MSGF_LEG_SR_INTA BIT(0) 105 #define MSGF_LEG_SR_INTB BIT(1) 106 #define MSGF_LEG_SR_INTC BIT(2) 107 #define MSGF_LEG_SR_INTD BIT(3) 108 #define MSGF_LEG_SR_MASKALL (MSGF_LEG_SR_INTA | MSGF_LEG_SR_INTB | \ 109 MSGF_LEG_SR_INTC | MSGF_LEG_SR_INTD) 110 111 /* MSI interrupt status mask bits */ 112 #define MSGF_MSI_SR_LO_MASK GENMASK(31, 0) 113 #define MSGF_MSI_SR_HI_MASK GENMASK(31, 0) 114 115 #define MSII_PRESENT BIT(0) 116 #define MSII_ENABLE BIT(0) 117 #define MSII_STATUS_ENABLE BIT(15) 118 119 /* Bridge config interrupt mask */ 120 #define BRCFG_INTERRUPT_MASK BIT(0) 121 #define BREG_PRESENT BIT(0) 122 #define BREG_ENABLE BIT(0) 123 #define BREG_ENABLE_FORCE BIT(1) 124 125 /* E_ECAM status mask bits */ 126 #define E_ECAM_PRESENT BIT(0) 127 #define E_ECAM_CR_ENABLE BIT(0) 128 #define E_ECAM_SIZE_LOC GENMASK(20, 16) 129 #define E_ECAM_SIZE_SHIFT 16 130 #define NWL_ECAM_VALUE_DEFAULT 12 131 132 #define CFG_DMA_REG_BAR GENMASK(2, 0) 133 #define CFG_PCIE_CACHE GENMASK(7, 0) 134 135 #define INT_PCI_MSI_NR (2 * 32) 136 137 /* Readin the PS_LINKUP */ 138 #define PS_LINKUP_OFFSET 0x00000238 139 #define PCIE_PHY_LINKUP_BIT BIT(0) 140 #define PHY_RDY_LINKUP_BIT BIT(1) 141 142 /* Parameters for the waiting for link up routine */ 143 #define LINK_WAIT_MAX_RETRIES 10 144 #define LINK_WAIT_USLEEP_MIN 90000 145 #define LINK_WAIT_USLEEP_MAX 100000 146 147 struct nwl_msi { /* MSI information */ 148 struct irq_domain *msi_domain; 149 unsigned long *bitmap; 150 struct irq_domain *dev_domain; 151 struct mutex lock; /* protect bitmap variable */ 152 int irq_msi0; 153 int irq_msi1; 154 }; 155 156 struct nwl_pcie { 157 struct device *dev; 158 void __iomem *breg_base; 159 void __iomem *pcireg_base; 160 void __iomem *ecam_base; 161 phys_addr_t phys_breg_base; /* Physical Bridge Register Base */ 162 phys_addr_t phys_pcie_reg_base; /* Physical PCIe Controller Base */ 163 phys_addr_t phys_ecam_base; /* Physical Configuration Base */ 164 u32 breg_size; 165 u32 pcie_reg_size; 166 u32 ecam_size; 167 int irq_intx; 168 int irq_misc; 169 u32 ecam_value; 170 u8 last_busno; 171 struct nwl_msi msi; 172 struct irq_domain *legacy_irq_domain; 173 struct clk *clk; 174 raw_spinlock_t leg_mask_lock; 175 }; 176 177 static inline u32 nwl_bridge_readl(struct nwl_pcie *pcie, u32 off) 178 { 179 return readl(pcie->breg_base + off); 180 } 181 182 static inline void nwl_bridge_writel(struct nwl_pcie *pcie, u32 val, u32 off) 183 { 184 writel(val, pcie->breg_base + off); 185 } 186 187 static bool nwl_pcie_link_up(struct nwl_pcie *pcie) 188 { 189 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PCIE_PHY_LINKUP_BIT) 190 return true; 191 return false; 192 } 193 194 static bool nwl_phy_link_up(struct nwl_pcie *pcie) 195 { 196 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PHY_RDY_LINKUP_BIT) 197 return true; 198 return false; 199 } 200 201 static int nwl_wait_for_link(struct nwl_pcie *pcie) 202 { 203 struct device *dev = pcie->dev; 204 int retries; 205 206 /* check if the link is up or not */ 207 for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { 208 if (nwl_phy_link_up(pcie)) 209 return 0; 210 usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); 211 } 212 213 dev_err(dev, "PHY link never came up\n"); 214 return -ETIMEDOUT; 215 } 216 217 static bool nwl_pcie_valid_device(struct pci_bus *bus, unsigned int devfn) 218 { 219 struct nwl_pcie *pcie = bus->sysdata; 220 221 /* Check link before accessing downstream ports */ 222 if (!pci_is_root_bus(bus)) { 223 if (!nwl_pcie_link_up(pcie)) 224 return false; 225 } else if (devfn > 0) 226 /* Only one device down on each root port */ 227 return false; 228 229 return true; 230 } 231 232 /** 233 * nwl_pcie_map_bus - Get configuration base 234 * 235 * @bus: Bus structure of current bus 236 * @devfn: Device/function 237 * @where: Offset from base 238 * 239 * Return: Base address of the configuration space needed to be 240 * accessed. 241 */ 242 static void __iomem *nwl_pcie_map_bus(struct pci_bus *bus, unsigned int devfn, 243 int where) 244 { 245 struct nwl_pcie *pcie = bus->sysdata; 246 247 if (!nwl_pcie_valid_device(bus, devfn)) 248 return NULL; 249 250 return pcie->ecam_base + PCIE_ECAM_OFFSET(bus->number, devfn, where); 251 } 252 253 /* PCIe operations */ 254 static struct pci_ops nwl_pcie_ops = { 255 .map_bus = nwl_pcie_map_bus, 256 .read = pci_generic_config_read, 257 .write = pci_generic_config_write, 258 }; 259 260 static irqreturn_t nwl_pcie_misc_handler(int irq, void *data) 261 { 262 struct nwl_pcie *pcie = data; 263 struct device *dev = pcie->dev; 264 u32 misc_stat; 265 266 /* Checking for misc interrupts */ 267 misc_stat = nwl_bridge_readl(pcie, MSGF_MISC_STATUS) & 268 MSGF_MISC_SR_MASKALL; 269 if (!misc_stat) 270 return IRQ_NONE; 271 272 if (misc_stat & MSGF_MISC_SR_RXMSG_OVER) 273 dev_err(dev, "Received Message FIFO Overflow\n"); 274 275 if (misc_stat & MSGF_MISC_SR_SLAVE_ERR) 276 dev_err(dev, "Slave error\n"); 277 278 if (misc_stat & MSGF_MISC_SR_MASTER_ERR) 279 dev_err(dev, "Master error\n"); 280 281 if (misc_stat & MSGF_MISC_SR_I_ADDR_ERR) 282 dev_err(dev, "In Misc Ingress address translation error\n"); 283 284 if (misc_stat & MSGF_MISC_SR_E_ADDR_ERR) 285 dev_err(dev, "In Misc Egress address translation error\n"); 286 287 if (misc_stat & MSGF_MISC_SR_FATAL_AER) 288 dev_err(dev, "Fatal Error in AER Capability\n"); 289 290 if (misc_stat & MSGF_MISC_SR_NON_FATAL_AER) 291 dev_err(dev, "Non-Fatal Error in AER Capability\n"); 292 293 if (misc_stat & MSGF_MISC_SR_CORR_AER) 294 dev_err(dev, "Correctable Error in AER Capability\n"); 295 296 if (misc_stat & MSGF_MISC_SR_UR_DETECT) 297 dev_err(dev, "Unsupported request Detected\n"); 298 299 if (misc_stat & MSGF_MISC_SR_NON_FATAL_DEV) 300 dev_err(dev, "Non-Fatal Error Detected\n"); 301 302 if (misc_stat & MSGF_MISC_SR_FATAL_DEV) 303 dev_err(dev, "Fatal Error Detected\n"); 304 305 if (misc_stat & MSGF_MSIC_SR_LINK_AUTO_BWIDTH) 306 dev_info(dev, "Link Autonomous Bandwidth Management Status bit set\n"); 307 308 if (misc_stat & MSGF_MSIC_SR_LINK_BWIDTH) 309 dev_info(dev, "Link Bandwidth Management Status bit set\n"); 310 311 /* Clear misc interrupt status */ 312 nwl_bridge_writel(pcie, misc_stat, MSGF_MISC_STATUS); 313 314 return IRQ_HANDLED; 315 } 316 317 static void nwl_pcie_leg_handler(struct irq_desc *desc) 318 { 319 struct irq_chip *chip = irq_desc_get_chip(desc); 320 struct nwl_pcie *pcie; 321 unsigned long status; 322 u32 bit; 323 324 chained_irq_enter(chip, desc); 325 pcie = irq_desc_get_handler_data(desc); 326 327 while ((status = nwl_bridge_readl(pcie, MSGF_LEG_STATUS) & 328 MSGF_LEG_SR_MASKALL) != 0) { 329 for_each_set_bit(bit, &status, PCI_NUM_INTX) 330 generic_handle_domain_irq(pcie->legacy_irq_domain, bit); 331 } 332 333 chained_irq_exit(chip, desc); 334 } 335 336 static void nwl_pcie_handle_msi_irq(struct nwl_pcie *pcie, u32 status_reg) 337 { 338 struct nwl_msi *msi; 339 unsigned long status; 340 u32 bit; 341 342 msi = &pcie->msi; 343 344 while ((status = nwl_bridge_readl(pcie, status_reg)) != 0) { 345 for_each_set_bit(bit, &status, 32) { 346 nwl_bridge_writel(pcie, 1 << bit, status_reg); 347 generic_handle_domain_irq(msi->dev_domain, bit); 348 } 349 } 350 } 351 352 static void nwl_pcie_msi_handler_high(struct irq_desc *desc) 353 { 354 struct irq_chip *chip = irq_desc_get_chip(desc); 355 struct nwl_pcie *pcie = irq_desc_get_handler_data(desc); 356 357 chained_irq_enter(chip, desc); 358 nwl_pcie_handle_msi_irq(pcie, MSGF_MSI_STATUS_HI); 359 chained_irq_exit(chip, desc); 360 } 361 362 static void nwl_pcie_msi_handler_low(struct irq_desc *desc) 363 { 364 struct irq_chip *chip = irq_desc_get_chip(desc); 365 struct nwl_pcie *pcie = irq_desc_get_handler_data(desc); 366 367 chained_irq_enter(chip, desc); 368 nwl_pcie_handle_msi_irq(pcie, MSGF_MSI_STATUS_LO); 369 chained_irq_exit(chip, desc); 370 } 371 372 static void nwl_mask_leg_irq(struct irq_data *data) 373 { 374 struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data); 375 unsigned long flags; 376 u32 mask; 377 u32 val; 378 379 mask = 1 << (data->hwirq - 1); 380 raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags); 381 val = nwl_bridge_readl(pcie, MSGF_LEG_MASK); 382 nwl_bridge_writel(pcie, (val & (~mask)), MSGF_LEG_MASK); 383 raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags); 384 } 385 386 static void nwl_unmask_leg_irq(struct irq_data *data) 387 { 388 struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data); 389 unsigned long flags; 390 u32 mask; 391 u32 val; 392 393 mask = 1 << (data->hwirq - 1); 394 raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags); 395 val = nwl_bridge_readl(pcie, MSGF_LEG_MASK); 396 nwl_bridge_writel(pcie, (val | mask), MSGF_LEG_MASK); 397 raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags); 398 } 399 400 static struct irq_chip nwl_leg_irq_chip = { 401 .name = "nwl_pcie:legacy", 402 .irq_enable = nwl_unmask_leg_irq, 403 .irq_disable = nwl_mask_leg_irq, 404 .irq_mask = nwl_mask_leg_irq, 405 .irq_unmask = nwl_unmask_leg_irq, 406 }; 407 408 static int nwl_legacy_map(struct irq_domain *domain, unsigned int irq, 409 irq_hw_number_t hwirq) 410 { 411 irq_set_chip_and_handler(irq, &nwl_leg_irq_chip, handle_level_irq); 412 irq_set_chip_data(irq, domain->host_data); 413 irq_set_status_flags(irq, IRQ_LEVEL); 414 415 return 0; 416 } 417 418 static const struct irq_domain_ops legacy_domain_ops = { 419 .map = nwl_legacy_map, 420 .xlate = pci_irqd_intx_xlate, 421 }; 422 423 #ifdef CONFIG_PCI_MSI 424 static struct irq_chip nwl_msi_irq_chip = { 425 .name = "nwl_pcie:msi", 426 .irq_enable = pci_msi_unmask_irq, 427 .irq_disable = pci_msi_mask_irq, 428 .irq_mask = pci_msi_mask_irq, 429 .irq_unmask = pci_msi_unmask_irq, 430 }; 431 432 static struct msi_domain_info nwl_msi_domain_info = { 433 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 434 MSI_FLAG_MULTI_PCI_MSI), 435 .chip = &nwl_msi_irq_chip, 436 }; 437 #endif 438 439 static void nwl_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) 440 { 441 struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data); 442 phys_addr_t msi_addr = pcie->phys_pcie_reg_base; 443 444 msg->address_lo = lower_32_bits(msi_addr); 445 msg->address_hi = upper_32_bits(msi_addr); 446 msg->data = data->hwirq; 447 } 448 449 static int nwl_msi_set_affinity(struct irq_data *irq_data, 450 const struct cpumask *mask, bool force) 451 { 452 return -EINVAL; 453 } 454 455 static struct irq_chip nwl_irq_chip = { 456 .name = "Xilinx MSI", 457 .irq_compose_msi_msg = nwl_compose_msi_msg, 458 .irq_set_affinity = nwl_msi_set_affinity, 459 }; 460 461 static int nwl_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, 462 unsigned int nr_irqs, void *args) 463 { 464 struct nwl_pcie *pcie = domain->host_data; 465 struct nwl_msi *msi = &pcie->msi; 466 int bit; 467 int i; 468 469 mutex_lock(&msi->lock); 470 bit = bitmap_find_free_region(msi->bitmap, INT_PCI_MSI_NR, 471 get_count_order(nr_irqs)); 472 if (bit < 0) { 473 mutex_unlock(&msi->lock); 474 return -ENOSPC; 475 } 476 477 for (i = 0; i < nr_irqs; i++) { 478 irq_domain_set_info(domain, virq + i, bit + i, &nwl_irq_chip, 479 domain->host_data, handle_simple_irq, 480 NULL, NULL); 481 } 482 mutex_unlock(&msi->lock); 483 return 0; 484 } 485 486 static void nwl_irq_domain_free(struct irq_domain *domain, unsigned int virq, 487 unsigned int nr_irqs) 488 { 489 struct irq_data *data = irq_domain_get_irq_data(domain, virq); 490 struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data); 491 struct nwl_msi *msi = &pcie->msi; 492 493 mutex_lock(&msi->lock); 494 bitmap_release_region(msi->bitmap, data->hwirq, 495 get_count_order(nr_irqs)); 496 mutex_unlock(&msi->lock); 497 } 498 499 static const struct irq_domain_ops dev_msi_domain_ops = { 500 .alloc = nwl_irq_domain_alloc, 501 .free = nwl_irq_domain_free, 502 }; 503 504 static int nwl_pcie_init_msi_irq_domain(struct nwl_pcie *pcie) 505 { 506 #ifdef CONFIG_PCI_MSI 507 struct device *dev = pcie->dev; 508 struct fwnode_handle *fwnode = of_node_to_fwnode(dev->of_node); 509 struct nwl_msi *msi = &pcie->msi; 510 511 msi->dev_domain = irq_domain_add_linear(NULL, INT_PCI_MSI_NR, 512 &dev_msi_domain_ops, pcie); 513 if (!msi->dev_domain) { 514 dev_err(dev, "failed to create dev IRQ domain\n"); 515 return -ENOMEM; 516 } 517 msi->msi_domain = pci_msi_create_irq_domain(fwnode, 518 &nwl_msi_domain_info, 519 msi->dev_domain); 520 if (!msi->msi_domain) { 521 dev_err(dev, "failed to create msi IRQ domain\n"); 522 irq_domain_remove(msi->dev_domain); 523 return -ENOMEM; 524 } 525 #endif 526 return 0; 527 } 528 529 static int nwl_pcie_init_irq_domain(struct nwl_pcie *pcie) 530 { 531 struct device *dev = pcie->dev; 532 struct device_node *node = dev->of_node; 533 struct device_node *legacy_intc_node; 534 535 legacy_intc_node = of_get_next_child(node, NULL); 536 if (!legacy_intc_node) { 537 dev_err(dev, "No legacy intc node found\n"); 538 return -EINVAL; 539 } 540 541 pcie->legacy_irq_domain = irq_domain_add_linear(legacy_intc_node, 542 PCI_NUM_INTX, 543 &legacy_domain_ops, 544 pcie); 545 of_node_put(legacy_intc_node); 546 if (!pcie->legacy_irq_domain) { 547 dev_err(dev, "failed to create IRQ domain\n"); 548 return -ENOMEM; 549 } 550 551 raw_spin_lock_init(&pcie->leg_mask_lock); 552 nwl_pcie_init_msi_irq_domain(pcie); 553 return 0; 554 } 555 556 static int nwl_pcie_enable_msi(struct nwl_pcie *pcie) 557 { 558 struct device *dev = pcie->dev; 559 struct platform_device *pdev = to_platform_device(dev); 560 struct nwl_msi *msi = &pcie->msi; 561 unsigned long base; 562 int ret; 563 int size = BITS_TO_LONGS(INT_PCI_MSI_NR) * sizeof(long); 564 565 mutex_init(&msi->lock); 566 567 msi->bitmap = kzalloc(size, GFP_KERNEL); 568 if (!msi->bitmap) 569 return -ENOMEM; 570 571 /* Get msi_1 IRQ number */ 572 msi->irq_msi1 = platform_get_irq_byname(pdev, "msi1"); 573 if (msi->irq_msi1 < 0) { 574 ret = -EINVAL; 575 goto err; 576 } 577 578 irq_set_chained_handler_and_data(msi->irq_msi1, 579 nwl_pcie_msi_handler_high, pcie); 580 581 /* Get msi_0 IRQ number */ 582 msi->irq_msi0 = platform_get_irq_byname(pdev, "msi0"); 583 if (msi->irq_msi0 < 0) { 584 ret = -EINVAL; 585 goto err; 586 } 587 588 irq_set_chained_handler_and_data(msi->irq_msi0, 589 nwl_pcie_msi_handler_low, pcie); 590 591 /* Check for msii_present bit */ 592 ret = nwl_bridge_readl(pcie, I_MSII_CAPABILITIES) & MSII_PRESENT; 593 if (!ret) { 594 dev_err(dev, "MSI not present\n"); 595 ret = -EIO; 596 goto err; 597 } 598 599 /* Enable MSII */ 600 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) | 601 MSII_ENABLE, I_MSII_CONTROL); 602 603 /* Enable MSII status */ 604 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) | 605 MSII_STATUS_ENABLE, I_MSII_CONTROL); 606 607 /* setup AFI/FPCI range */ 608 base = pcie->phys_pcie_reg_base; 609 nwl_bridge_writel(pcie, lower_32_bits(base), I_MSII_BASE_LO); 610 nwl_bridge_writel(pcie, upper_32_bits(base), I_MSII_BASE_HI); 611 612 /* 613 * For high range MSI interrupts: disable, clear any pending, 614 * and enable 615 */ 616 nwl_bridge_writel(pcie, 0, MSGF_MSI_MASK_HI); 617 618 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_HI) & 619 MSGF_MSI_SR_HI_MASK, MSGF_MSI_STATUS_HI); 620 621 nwl_bridge_writel(pcie, MSGF_MSI_SR_HI_MASK, MSGF_MSI_MASK_HI); 622 623 /* 624 * For low range MSI interrupts: disable, clear any pending, 625 * and enable 626 */ 627 nwl_bridge_writel(pcie, 0, MSGF_MSI_MASK_LO); 628 629 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_LO) & 630 MSGF_MSI_SR_LO_MASK, MSGF_MSI_STATUS_LO); 631 632 nwl_bridge_writel(pcie, MSGF_MSI_SR_LO_MASK, MSGF_MSI_MASK_LO); 633 634 return 0; 635 err: 636 kfree(msi->bitmap); 637 msi->bitmap = NULL; 638 return ret; 639 } 640 641 static int nwl_pcie_bridge_init(struct nwl_pcie *pcie) 642 { 643 struct device *dev = pcie->dev; 644 struct platform_device *pdev = to_platform_device(dev); 645 u32 breg_val, ecam_val, first_busno = 0; 646 int err; 647 648 breg_val = nwl_bridge_readl(pcie, E_BREG_CAPABILITIES) & BREG_PRESENT; 649 if (!breg_val) { 650 dev_err(dev, "BREG is not present\n"); 651 return breg_val; 652 } 653 654 /* Write bridge_off to breg base */ 655 nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_breg_base), 656 E_BREG_BASE_LO); 657 nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_breg_base), 658 E_BREG_BASE_HI); 659 660 /* Enable BREG */ 661 nwl_bridge_writel(pcie, ~BREG_ENABLE_FORCE & BREG_ENABLE, 662 E_BREG_CONTROL); 663 664 /* Disable DMA channel registers */ 665 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_PCIE_RX0) | 666 CFG_DMA_REG_BAR, BRCFG_PCIE_RX0); 667 668 /* Enable Ingress subtractive decode translation */ 669 nwl_bridge_writel(pcie, SET_ISUB_CONTROL, I_ISUB_CONTROL); 670 671 /* Enable msg filtering details */ 672 nwl_bridge_writel(pcie, CFG_ENABLE_MSG_FILTER_MASK, 673 BRCFG_PCIE_RX_MSG_FILTER); 674 675 /* This routes the PCIe DMA traffic to go through CCI path */ 676 if (of_dma_is_coherent(dev->of_node)) 677 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_PCIE_RX1) | 678 CFG_PCIE_CACHE, BRCFG_PCIE_RX1); 679 680 err = nwl_wait_for_link(pcie); 681 if (err) 682 return err; 683 684 ecam_val = nwl_bridge_readl(pcie, E_ECAM_CAPABILITIES) & E_ECAM_PRESENT; 685 if (!ecam_val) { 686 dev_err(dev, "ECAM is not present\n"); 687 return ecam_val; 688 } 689 690 /* Enable ECAM */ 691 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) | 692 E_ECAM_CR_ENABLE, E_ECAM_CONTROL); 693 694 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) | 695 (pcie->ecam_value << E_ECAM_SIZE_SHIFT), 696 E_ECAM_CONTROL); 697 698 nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_ecam_base), 699 E_ECAM_BASE_LO); 700 nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_ecam_base), 701 E_ECAM_BASE_HI); 702 703 /* Get bus range */ 704 ecam_val = nwl_bridge_readl(pcie, E_ECAM_CONTROL); 705 pcie->last_busno = (ecam_val & E_ECAM_SIZE_LOC) >> E_ECAM_SIZE_SHIFT; 706 /* Write primary, secondary and subordinate bus numbers */ 707 ecam_val = first_busno; 708 ecam_val |= (first_busno + 1) << 8; 709 ecam_val |= (pcie->last_busno << E_ECAM_SIZE_SHIFT); 710 writel(ecam_val, (pcie->ecam_base + PCI_PRIMARY_BUS)); 711 712 if (nwl_pcie_link_up(pcie)) 713 dev_info(dev, "Link is UP\n"); 714 else 715 dev_info(dev, "Link is DOWN\n"); 716 717 /* Get misc IRQ number */ 718 pcie->irq_misc = platform_get_irq_byname(pdev, "misc"); 719 if (pcie->irq_misc < 0) 720 return -EINVAL; 721 722 err = devm_request_irq(dev, pcie->irq_misc, 723 nwl_pcie_misc_handler, IRQF_SHARED, 724 "nwl_pcie:misc", pcie); 725 if (err) { 726 dev_err(dev, "fail to register misc IRQ#%d\n", 727 pcie->irq_misc); 728 return err; 729 } 730 731 /* Disable all misc interrupts */ 732 nwl_bridge_writel(pcie, (u32)~MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK); 733 734 /* Clear pending misc interrupts */ 735 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MISC_STATUS) & 736 MSGF_MISC_SR_MASKALL, MSGF_MISC_STATUS); 737 738 /* Enable all misc interrupts */ 739 nwl_bridge_writel(pcie, MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK); 740 741 742 /* Disable all legacy interrupts */ 743 nwl_bridge_writel(pcie, (u32)~MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK); 744 745 /* Clear pending legacy interrupts */ 746 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_LEG_STATUS) & 747 MSGF_LEG_SR_MASKALL, MSGF_LEG_STATUS); 748 749 /* Enable all legacy interrupts */ 750 nwl_bridge_writel(pcie, MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK); 751 752 /* Enable the bridge config interrupt */ 753 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_INTERRUPT) | 754 BRCFG_INTERRUPT_MASK, BRCFG_INTERRUPT); 755 756 return 0; 757 } 758 759 static int nwl_pcie_parse_dt(struct nwl_pcie *pcie, 760 struct platform_device *pdev) 761 { 762 struct device *dev = pcie->dev; 763 struct resource *res; 764 765 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "breg"); 766 pcie->breg_base = devm_ioremap_resource(dev, res); 767 if (IS_ERR(pcie->breg_base)) 768 return PTR_ERR(pcie->breg_base); 769 pcie->phys_breg_base = res->start; 770 771 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcireg"); 772 pcie->pcireg_base = devm_ioremap_resource(dev, res); 773 if (IS_ERR(pcie->pcireg_base)) 774 return PTR_ERR(pcie->pcireg_base); 775 pcie->phys_pcie_reg_base = res->start; 776 777 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg"); 778 pcie->ecam_base = devm_pci_remap_cfg_resource(dev, res); 779 if (IS_ERR(pcie->ecam_base)) 780 return PTR_ERR(pcie->ecam_base); 781 pcie->phys_ecam_base = res->start; 782 783 /* Get intx IRQ number */ 784 pcie->irq_intx = platform_get_irq_byname(pdev, "intx"); 785 if (pcie->irq_intx < 0) 786 return pcie->irq_intx; 787 788 irq_set_chained_handler_and_data(pcie->irq_intx, 789 nwl_pcie_leg_handler, pcie); 790 791 return 0; 792 } 793 794 static const struct of_device_id nwl_pcie_of_match[] = { 795 { .compatible = "xlnx,nwl-pcie-2.11", }, 796 {} 797 }; 798 799 static int nwl_pcie_probe(struct platform_device *pdev) 800 { 801 struct device *dev = &pdev->dev; 802 struct nwl_pcie *pcie; 803 struct pci_host_bridge *bridge; 804 int err; 805 806 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie)); 807 if (!bridge) 808 return -ENODEV; 809 810 pcie = pci_host_bridge_priv(bridge); 811 812 pcie->dev = dev; 813 pcie->ecam_value = NWL_ECAM_VALUE_DEFAULT; 814 815 err = nwl_pcie_parse_dt(pcie, pdev); 816 if (err) { 817 dev_err(dev, "Parsing DT failed\n"); 818 return err; 819 } 820 821 pcie->clk = devm_clk_get(dev, NULL); 822 if (IS_ERR(pcie->clk)) 823 return PTR_ERR(pcie->clk); 824 825 err = clk_prepare_enable(pcie->clk); 826 if (err) { 827 dev_err(dev, "can't enable PCIe ref clock\n"); 828 return err; 829 } 830 831 err = nwl_pcie_bridge_init(pcie); 832 if (err) { 833 dev_err(dev, "HW Initialization failed\n"); 834 return err; 835 } 836 837 err = nwl_pcie_init_irq_domain(pcie); 838 if (err) { 839 dev_err(dev, "Failed creating IRQ Domain\n"); 840 return err; 841 } 842 843 bridge->sysdata = pcie; 844 bridge->ops = &nwl_pcie_ops; 845 846 if (IS_ENABLED(CONFIG_PCI_MSI)) { 847 err = nwl_pcie_enable_msi(pcie); 848 if (err < 0) { 849 dev_err(dev, "failed to enable MSI support: %d\n", err); 850 return err; 851 } 852 } 853 854 return pci_host_probe(bridge); 855 } 856 857 static struct platform_driver nwl_pcie_driver = { 858 .driver = { 859 .name = "nwl-pcie", 860 .suppress_bind_attrs = true, 861 .of_match_table = nwl_pcie_of_match, 862 }, 863 .probe = nwl_pcie_probe, 864 }; 865 builtin_platform_driver(nwl_pcie_driver); 866