1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * PCIe host controller driver for NWL PCIe Bridge 4 * Based on pcie-xilinx.c, pci-tegra.c 5 * 6 * (C) Copyright 2014 - 2015, Xilinx, Inc. 7 */ 8 9 #include <linux/delay.h> 10 #include <linux/interrupt.h> 11 #include <linux/irq.h> 12 #include <linux/irqdomain.h> 13 #include <linux/kernel.h> 14 #include <linux/init.h> 15 #include <linux/msi.h> 16 #include <linux/of_address.h> 17 #include <linux/of_pci.h> 18 #include <linux/of_platform.h> 19 #include <linux/of_irq.h> 20 #include <linux/pci.h> 21 #include <linux/pci-ecam.h> 22 #include <linux/platform_device.h> 23 #include <linux/irqchip/chained_irq.h> 24 25 #include "../pci.h" 26 27 /* Bridge core config registers */ 28 #define BRCFG_PCIE_RX0 0x00000000 29 #define BRCFG_PCIE_RX1 0x00000004 30 #define BRCFG_INTERRUPT 0x00000010 31 #define BRCFG_PCIE_RX_MSG_FILTER 0x00000020 32 33 /* Egress - Bridge translation registers */ 34 #define E_BREG_CAPABILITIES 0x00000200 35 #define E_BREG_CONTROL 0x00000208 36 #define E_BREG_BASE_LO 0x00000210 37 #define E_BREG_BASE_HI 0x00000214 38 #define E_ECAM_CAPABILITIES 0x00000220 39 #define E_ECAM_CONTROL 0x00000228 40 #define E_ECAM_BASE_LO 0x00000230 41 #define E_ECAM_BASE_HI 0x00000234 42 43 /* Ingress - address translations */ 44 #define I_MSII_CAPABILITIES 0x00000300 45 #define I_MSII_CONTROL 0x00000308 46 #define I_MSII_BASE_LO 0x00000310 47 #define I_MSII_BASE_HI 0x00000314 48 49 #define I_ISUB_CONTROL 0x000003E8 50 #define SET_ISUB_CONTROL BIT(0) 51 /* Rxed msg fifo - Interrupt status registers */ 52 #define MSGF_MISC_STATUS 0x00000400 53 #define MSGF_MISC_MASK 0x00000404 54 #define MSGF_LEG_STATUS 0x00000420 55 #define MSGF_LEG_MASK 0x00000424 56 #define MSGF_MSI_STATUS_LO 0x00000440 57 #define MSGF_MSI_STATUS_HI 0x00000444 58 #define MSGF_MSI_MASK_LO 0x00000448 59 #define MSGF_MSI_MASK_HI 0x0000044C 60 61 /* Msg filter mask bits */ 62 #define CFG_ENABLE_PM_MSG_FWD BIT(1) 63 #define CFG_ENABLE_INT_MSG_FWD BIT(2) 64 #define CFG_ENABLE_ERR_MSG_FWD BIT(3) 65 #define CFG_ENABLE_MSG_FILTER_MASK (CFG_ENABLE_PM_MSG_FWD | \ 66 CFG_ENABLE_INT_MSG_FWD | \ 67 CFG_ENABLE_ERR_MSG_FWD) 68 69 /* Misc interrupt status mask bits */ 70 #define MSGF_MISC_SR_RXMSG_AVAIL BIT(0) 71 #define MSGF_MISC_SR_RXMSG_OVER BIT(1) 72 #define MSGF_MISC_SR_SLAVE_ERR BIT(4) 73 #define MSGF_MISC_SR_MASTER_ERR BIT(5) 74 #define MSGF_MISC_SR_I_ADDR_ERR BIT(6) 75 #define MSGF_MISC_SR_E_ADDR_ERR BIT(7) 76 #define MSGF_MISC_SR_FATAL_AER BIT(16) 77 #define MSGF_MISC_SR_NON_FATAL_AER BIT(17) 78 #define MSGF_MISC_SR_CORR_AER BIT(18) 79 #define MSGF_MISC_SR_UR_DETECT BIT(20) 80 #define MSGF_MISC_SR_NON_FATAL_DEV BIT(22) 81 #define MSGF_MISC_SR_FATAL_DEV BIT(23) 82 #define MSGF_MISC_SR_LINK_DOWN BIT(24) 83 #define MSGF_MSIC_SR_LINK_AUTO_BWIDTH BIT(25) 84 #define MSGF_MSIC_SR_LINK_BWIDTH BIT(26) 85 86 #define MSGF_MISC_SR_MASKALL (MSGF_MISC_SR_RXMSG_AVAIL | \ 87 MSGF_MISC_SR_RXMSG_OVER | \ 88 MSGF_MISC_SR_SLAVE_ERR | \ 89 MSGF_MISC_SR_MASTER_ERR | \ 90 MSGF_MISC_SR_I_ADDR_ERR | \ 91 MSGF_MISC_SR_E_ADDR_ERR | \ 92 MSGF_MISC_SR_FATAL_AER | \ 93 MSGF_MISC_SR_NON_FATAL_AER | \ 94 MSGF_MISC_SR_CORR_AER | \ 95 MSGF_MISC_SR_UR_DETECT | \ 96 MSGF_MISC_SR_NON_FATAL_DEV | \ 97 MSGF_MISC_SR_FATAL_DEV | \ 98 MSGF_MISC_SR_LINK_DOWN | \ 99 MSGF_MSIC_SR_LINK_AUTO_BWIDTH | \ 100 MSGF_MSIC_SR_LINK_BWIDTH) 101 102 /* Legacy interrupt status mask bits */ 103 #define MSGF_LEG_SR_INTA BIT(0) 104 #define MSGF_LEG_SR_INTB BIT(1) 105 #define MSGF_LEG_SR_INTC BIT(2) 106 #define MSGF_LEG_SR_INTD BIT(3) 107 #define MSGF_LEG_SR_MASKALL (MSGF_LEG_SR_INTA | MSGF_LEG_SR_INTB | \ 108 MSGF_LEG_SR_INTC | MSGF_LEG_SR_INTD) 109 110 /* MSI interrupt status mask bits */ 111 #define MSGF_MSI_SR_LO_MASK GENMASK(31, 0) 112 #define MSGF_MSI_SR_HI_MASK GENMASK(31, 0) 113 114 #define MSII_PRESENT BIT(0) 115 #define MSII_ENABLE BIT(0) 116 #define MSII_STATUS_ENABLE BIT(15) 117 118 /* Bridge config interrupt mask */ 119 #define BRCFG_INTERRUPT_MASK BIT(0) 120 #define BREG_PRESENT BIT(0) 121 #define BREG_ENABLE BIT(0) 122 #define BREG_ENABLE_FORCE BIT(1) 123 124 /* E_ECAM status mask bits */ 125 #define E_ECAM_PRESENT BIT(0) 126 #define E_ECAM_CR_ENABLE BIT(0) 127 #define E_ECAM_SIZE_LOC GENMASK(20, 16) 128 #define E_ECAM_SIZE_SHIFT 16 129 #define NWL_ECAM_VALUE_DEFAULT 12 130 131 #define CFG_DMA_REG_BAR GENMASK(2, 0) 132 #define CFG_PCIE_CACHE GENMASK(7, 0) 133 134 #define INT_PCI_MSI_NR (2 * 32) 135 136 /* Readin the PS_LINKUP */ 137 #define PS_LINKUP_OFFSET 0x00000238 138 #define PCIE_PHY_LINKUP_BIT BIT(0) 139 #define PHY_RDY_LINKUP_BIT BIT(1) 140 141 /* Parameters for the waiting for link up routine */ 142 #define LINK_WAIT_MAX_RETRIES 10 143 #define LINK_WAIT_USLEEP_MIN 90000 144 #define LINK_WAIT_USLEEP_MAX 100000 145 146 struct nwl_msi { /* MSI information */ 147 struct irq_domain *msi_domain; 148 unsigned long *bitmap; 149 struct irq_domain *dev_domain; 150 struct mutex lock; /* protect bitmap variable */ 151 int irq_msi0; 152 int irq_msi1; 153 }; 154 155 struct nwl_pcie { 156 struct device *dev; 157 void __iomem *breg_base; 158 void __iomem *pcireg_base; 159 void __iomem *ecam_base; 160 phys_addr_t phys_breg_base; /* Physical Bridge Register Base */ 161 phys_addr_t phys_pcie_reg_base; /* Physical PCIe Controller Base */ 162 phys_addr_t phys_ecam_base; /* Physical Configuration Base */ 163 u32 breg_size; 164 u32 pcie_reg_size; 165 u32 ecam_size; 166 int irq_intx; 167 int irq_misc; 168 u32 ecam_value; 169 u8 last_busno; 170 struct nwl_msi msi; 171 struct irq_domain *legacy_irq_domain; 172 raw_spinlock_t leg_mask_lock; 173 }; 174 175 static inline u32 nwl_bridge_readl(struct nwl_pcie *pcie, u32 off) 176 { 177 return readl(pcie->breg_base + off); 178 } 179 180 static inline void nwl_bridge_writel(struct nwl_pcie *pcie, u32 val, u32 off) 181 { 182 writel(val, pcie->breg_base + off); 183 } 184 185 static bool nwl_pcie_link_up(struct nwl_pcie *pcie) 186 { 187 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PCIE_PHY_LINKUP_BIT) 188 return true; 189 return false; 190 } 191 192 static bool nwl_phy_link_up(struct nwl_pcie *pcie) 193 { 194 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PHY_RDY_LINKUP_BIT) 195 return true; 196 return false; 197 } 198 199 static int nwl_wait_for_link(struct nwl_pcie *pcie) 200 { 201 struct device *dev = pcie->dev; 202 int retries; 203 204 /* check if the link is up or not */ 205 for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { 206 if (nwl_phy_link_up(pcie)) 207 return 0; 208 usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); 209 } 210 211 dev_err(dev, "PHY link never came up\n"); 212 return -ETIMEDOUT; 213 } 214 215 static bool nwl_pcie_valid_device(struct pci_bus *bus, unsigned int devfn) 216 { 217 struct nwl_pcie *pcie = bus->sysdata; 218 219 /* Check link before accessing downstream ports */ 220 if (!pci_is_root_bus(bus)) { 221 if (!nwl_pcie_link_up(pcie)) 222 return false; 223 } else if (devfn > 0) 224 /* Only one device down on each root port */ 225 return false; 226 227 return true; 228 } 229 230 /** 231 * nwl_pcie_map_bus - Get configuration base 232 * 233 * @bus: Bus structure of current bus 234 * @devfn: Device/function 235 * @where: Offset from base 236 * 237 * Return: Base address of the configuration space needed to be 238 * accessed. 239 */ 240 static void __iomem *nwl_pcie_map_bus(struct pci_bus *bus, unsigned int devfn, 241 int where) 242 { 243 struct nwl_pcie *pcie = bus->sysdata; 244 245 if (!nwl_pcie_valid_device(bus, devfn)) 246 return NULL; 247 248 return pcie->ecam_base + PCIE_ECAM_OFFSET(bus->number, devfn, where); 249 } 250 251 /* PCIe operations */ 252 static struct pci_ops nwl_pcie_ops = { 253 .map_bus = nwl_pcie_map_bus, 254 .read = pci_generic_config_read, 255 .write = pci_generic_config_write, 256 }; 257 258 static irqreturn_t nwl_pcie_misc_handler(int irq, void *data) 259 { 260 struct nwl_pcie *pcie = data; 261 struct device *dev = pcie->dev; 262 u32 misc_stat; 263 264 /* Checking for misc interrupts */ 265 misc_stat = nwl_bridge_readl(pcie, MSGF_MISC_STATUS) & 266 MSGF_MISC_SR_MASKALL; 267 if (!misc_stat) 268 return IRQ_NONE; 269 270 if (misc_stat & MSGF_MISC_SR_RXMSG_OVER) 271 dev_err(dev, "Received Message FIFO Overflow\n"); 272 273 if (misc_stat & MSGF_MISC_SR_SLAVE_ERR) 274 dev_err(dev, "Slave error\n"); 275 276 if (misc_stat & MSGF_MISC_SR_MASTER_ERR) 277 dev_err(dev, "Master error\n"); 278 279 if (misc_stat & MSGF_MISC_SR_I_ADDR_ERR) 280 dev_err(dev, "In Misc Ingress address translation error\n"); 281 282 if (misc_stat & MSGF_MISC_SR_E_ADDR_ERR) 283 dev_err(dev, "In Misc Egress address translation error\n"); 284 285 if (misc_stat & MSGF_MISC_SR_FATAL_AER) 286 dev_err(dev, "Fatal Error in AER Capability\n"); 287 288 if (misc_stat & MSGF_MISC_SR_NON_FATAL_AER) 289 dev_err(dev, "Non-Fatal Error in AER Capability\n"); 290 291 if (misc_stat & MSGF_MISC_SR_CORR_AER) 292 dev_err(dev, "Correctable Error in AER Capability\n"); 293 294 if (misc_stat & MSGF_MISC_SR_UR_DETECT) 295 dev_err(dev, "Unsupported request Detected\n"); 296 297 if (misc_stat & MSGF_MISC_SR_NON_FATAL_DEV) 298 dev_err(dev, "Non-Fatal Error Detected\n"); 299 300 if (misc_stat & MSGF_MISC_SR_FATAL_DEV) 301 dev_err(dev, "Fatal Error Detected\n"); 302 303 if (misc_stat & MSGF_MSIC_SR_LINK_AUTO_BWIDTH) 304 dev_info(dev, "Link Autonomous Bandwidth Management Status bit set\n"); 305 306 if (misc_stat & MSGF_MSIC_SR_LINK_BWIDTH) 307 dev_info(dev, "Link Bandwidth Management Status bit set\n"); 308 309 /* Clear misc interrupt status */ 310 nwl_bridge_writel(pcie, misc_stat, MSGF_MISC_STATUS); 311 312 return IRQ_HANDLED; 313 } 314 315 static void nwl_pcie_leg_handler(struct irq_desc *desc) 316 { 317 struct irq_chip *chip = irq_desc_get_chip(desc); 318 struct nwl_pcie *pcie; 319 unsigned long status; 320 u32 bit; 321 u32 virq; 322 323 chained_irq_enter(chip, desc); 324 pcie = irq_desc_get_handler_data(desc); 325 326 while ((status = nwl_bridge_readl(pcie, MSGF_LEG_STATUS) & 327 MSGF_LEG_SR_MASKALL) != 0) { 328 for_each_set_bit(bit, &status, PCI_NUM_INTX) { 329 virq = irq_find_mapping(pcie->legacy_irq_domain, bit); 330 if (virq) 331 generic_handle_irq(virq); 332 } 333 } 334 335 chained_irq_exit(chip, desc); 336 } 337 338 static void nwl_pcie_handle_msi_irq(struct nwl_pcie *pcie, u32 status_reg) 339 { 340 struct nwl_msi *msi; 341 unsigned long status; 342 u32 bit; 343 u32 virq; 344 345 msi = &pcie->msi; 346 347 while ((status = nwl_bridge_readl(pcie, status_reg)) != 0) { 348 for_each_set_bit(bit, &status, 32) { 349 nwl_bridge_writel(pcie, 1 << bit, status_reg); 350 virq = irq_find_mapping(msi->dev_domain, bit); 351 if (virq) 352 generic_handle_irq(virq); 353 } 354 } 355 } 356 357 static void nwl_pcie_msi_handler_high(struct irq_desc *desc) 358 { 359 struct irq_chip *chip = irq_desc_get_chip(desc); 360 struct nwl_pcie *pcie = irq_desc_get_handler_data(desc); 361 362 chained_irq_enter(chip, desc); 363 nwl_pcie_handle_msi_irq(pcie, MSGF_MSI_STATUS_HI); 364 chained_irq_exit(chip, desc); 365 } 366 367 static void nwl_pcie_msi_handler_low(struct irq_desc *desc) 368 { 369 struct irq_chip *chip = irq_desc_get_chip(desc); 370 struct nwl_pcie *pcie = irq_desc_get_handler_data(desc); 371 372 chained_irq_enter(chip, desc); 373 nwl_pcie_handle_msi_irq(pcie, MSGF_MSI_STATUS_LO); 374 chained_irq_exit(chip, desc); 375 } 376 377 static void nwl_mask_leg_irq(struct irq_data *data) 378 { 379 struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data); 380 unsigned long flags; 381 u32 mask; 382 u32 val; 383 384 mask = 1 << (data->hwirq - 1); 385 raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags); 386 val = nwl_bridge_readl(pcie, MSGF_LEG_MASK); 387 nwl_bridge_writel(pcie, (val & (~mask)), MSGF_LEG_MASK); 388 raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags); 389 } 390 391 static void nwl_unmask_leg_irq(struct irq_data *data) 392 { 393 struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data); 394 unsigned long flags; 395 u32 mask; 396 u32 val; 397 398 mask = 1 << (data->hwirq - 1); 399 raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags); 400 val = nwl_bridge_readl(pcie, MSGF_LEG_MASK); 401 nwl_bridge_writel(pcie, (val | mask), MSGF_LEG_MASK); 402 raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags); 403 } 404 405 static struct irq_chip nwl_leg_irq_chip = { 406 .name = "nwl_pcie:legacy", 407 .irq_enable = nwl_unmask_leg_irq, 408 .irq_disable = nwl_mask_leg_irq, 409 .irq_mask = nwl_mask_leg_irq, 410 .irq_unmask = nwl_unmask_leg_irq, 411 }; 412 413 static int nwl_legacy_map(struct irq_domain *domain, unsigned int irq, 414 irq_hw_number_t hwirq) 415 { 416 irq_set_chip_and_handler(irq, &nwl_leg_irq_chip, handle_level_irq); 417 irq_set_chip_data(irq, domain->host_data); 418 irq_set_status_flags(irq, IRQ_LEVEL); 419 420 return 0; 421 } 422 423 static const struct irq_domain_ops legacy_domain_ops = { 424 .map = nwl_legacy_map, 425 .xlate = pci_irqd_intx_xlate, 426 }; 427 428 #ifdef CONFIG_PCI_MSI 429 static struct irq_chip nwl_msi_irq_chip = { 430 .name = "nwl_pcie:msi", 431 .irq_enable = pci_msi_unmask_irq, 432 .irq_disable = pci_msi_mask_irq, 433 .irq_mask = pci_msi_mask_irq, 434 .irq_unmask = pci_msi_unmask_irq, 435 }; 436 437 static struct msi_domain_info nwl_msi_domain_info = { 438 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 439 MSI_FLAG_MULTI_PCI_MSI), 440 .chip = &nwl_msi_irq_chip, 441 }; 442 #endif 443 444 static void nwl_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) 445 { 446 struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data); 447 phys_addr_t msi_addr = pcie->phys_pcie_reg_base; 448 449 msg->address_lo = lower_32_bits(msi_addr); 450 msg->address_hi = upper_32_bits(msi_addr); 451 msg->data = data->hwirq; 452 } 453 454 static int nwl_msi_set_affinity(struct irq_data *irq_data, 455 const struct cpumask *mask, bool force) 456 { 457 return -EINVAL; 458 } 459 460 static struct irq_chip nwl_irq_chip = { 461 .name = "Xilinx MSI", 462 .irq_compose_msi_msg = nwl_compose_msi_msg, 463 .irq_set_affinity = nwl_msi_set_affinity, 464 }; 465 466 static int nwl_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, 467 unsigned int nr_irqs, void *args) 468 { 469 struct nwl_pcie *pcie = domain->host_data; 470 struct nwl_msi *msi = &pcie->msi; 471 int bit; 472 int i; 473 474 mutex_lock(&msi->lock); 475 bit = bitmap_find_free_region(msi->bitmap, INT_PCI_MSI_NR, 476 get_count_order(nr_irqs)); 477 if (bit < 0) { 478 mutex_unlock(&msi->lock); 479 return -ENOSPC; 480 } 481 482 for (i = 0; i < nr_irqs; i++) { 483 irq_domain_set_info(domain, virq + i, bit + i, &nwl_irq_chip, 484 domain->host_data, handle_simple_irq, 485 NULL, NULL); 486 } 487 mutex_unlock(&msi->lock); 488 return 0; 489 } 490 491 static void nwl_irq_domain_free(struct irq_domain *domain, unsigned int virq, 492 unsigned int nr_irqs) 493 { 494 struct irq_data *data = irq_domain_get_irq_data(domain, virq); 495 struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data); 496 struct nwl_msi *msi = &pcie->msi; 497 498 mutex_lock(&msi->lock); 499 bitmap_release_region(msi->bitmap, data->hwirq, 500 get_count_order(nr_irqs)); 501 mutex_unlock(&msi->lock); 502 } 503 504 static const struct irq_domain_ops dev_msi_domain_ops = { 505 .alloc = nwl_irq_domain_alloc, 506 .free = nwl_irq_domain_free, 507 }; 508 509 static int nwl_pcie_init_msi_irq_domain(struct nwl_pcie *pcie) 510 { 511 #ifdef CONFIG_PCI_MSI 512 struct device *dev = pcie->dev; 513 struct fwnode_handle *fwnode = of_node_to_fwnode(dev->of_node); 514 struct nwl_msi *msi = &pcie->msi; 515 516 msi->dev_domain = irq_domain_add_linear(NULL, INT_PCI_MSI_NR, 517 &dev_msi_domain_ops, pcie); 518 if (!msi->dev_domain) { 519 dev_err(dev, "failed to create dev IRQ domain\n"); 520 return -ENOMEM; 521 } 522 msi->msi_domain = pci_msi_create_irq_domain(fwnode, 523 &nwl_msi_domain_info, 524 msi->dev_domain); 525 if (!msi->msi_domain) { 526 dev_err(dev, "failed to create msi IRQ domain\n"); 527 irq_domain_remove(msi->dev_domain); 528 return -ENOMEM; 529 } 530 #endif 531 return 0; 532 } 533 534 static int nwl_pcie_init_irq_domain(struct nwl_pcie *pcie) 535 { 536 struct device *dev = pcie->dev; 537 struct device_node *node = dev->of_node; 538 struct device_node *legacy_intc_node; 539 540 legacy_intc_node = of_get_next_child(node, NULL); 541 if (!legacy_intc_node) { 542 dev_err(dev, "No legacy intc node found\n"); 543 return -EINVAL; 544 } 545 546 pcie->legacy_irq_domain = irq_domain_add_linear(legacy_intc_node, 547 PCI_NUM_INTX, 548 &legacy_domain_ops, 549 pcie); 550 of_node_put(legacy_intc_node); 551 if (!pcie->legacy_irq_domain) { 552 dev_err(dev, "failed to create IRQ domain\n"); 553 return -ENOMEM; 554 } 555 556 raw_spin_lock_init(&pcie->leg_mask_lock); 557 nwl_pcie_init_msi_irq_domain(pcie); 558 return 0; 559 } 560 561 static int nwl_pcie_enable_msi(struct nwl_pcie *pcie) 562 { 563 struct device *dev = pcie->dev; 564 struct platform_device *pdev = to_platform_device(dev); 565 struct nwl_msi *msi = &pcie->msi; 566 unsigned long base; 567 int ret; 568 int size = BITS_TO_LONGS(INT_PCI_MSI_NR) * sizeof(long); 569 570 mutex_init(&msi->lock); 571 572 msi->bitmap = kzalloc(size, GFP_KERNEL); 573 if (!msi->bitmap) 574 return -ENOMEM; 575 576 /* Get msi_1 IRQ number */ 577 msi->irq_msi1 = platform_get_irq_byname(pdev, "msi1"); 578 if (msi->irq_msi1 < 0) { 579 ret = -EINVAL; 580 goto err; 581 } 582 583 irq_set_chained_handler_and_data(msi->irq_msi1, 584 nwl_pcie_msi_handler_high, pcie); 585 586 /* Get msi_0 IRQ number */ 587 msi->irq_msi0 = platform_get_irq_byname(pdev, "msi0"); 588 if (msi->irq_msi0 < 0) { 589 ret = -EINVAL; 590 goto err; 591 } 592 593 irq_set_chained_handler_and_data(msi->irq_msi0, 594 nwl_pcie_msi_handler_low, pcie); 595 596 /* Check for msii_present bit */ 597 ret = nwl_bridge_readl(pcie, I_MSII_CAPABILITIES) & MSII_PRESENT; 598 if (!ret) { 599 dev_err(dev, "MSI not present\n"); 600 ret = -EIO; 601 goto err; 602 } 603 604 /* Enable MSII */ 605 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) | 606 MSII_ENABLE, I_MSII_CONTROL); 607 608 /* Enable MSII status */ 609 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) | 610 MSII_STATUS_ENABLE, I_MSII_CONTROL); 611 612 /* setup AFI/FPCI range */ 613 base = pcie->phys_pcie_reg_base; 614 nwl_bridge_writel(pcie, lower_32_bits(base), I_MSII_BASE_LO); 615 nwl_bridge_writel(pcie, upper_32_bits(base), I_MSII_BASE_HI); 616 617 /* 618 * For high range MSI interrupts: disable, clear any pending, 619 * and enable 620 */ 621 nwl_bridge_writel(pcie, 0, MSGF_MSI_MASK_HI); 622 623 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_HI) & 624 MSGF_MSI_SR_HI_MASK, MSGF_MSI_STATUS_HI); 625 626 nwl_bridge_writel(pcie, MSGF_MSI_SR_HI_MASK, MSGF_MSI_MASK_HI); 627 628 /* 629 * For low range MSI interrupts: disable, clear any pending, 630 * and enable 631 */ 632 nwl_bridge_writel(pcie, 0, MSGF_MSI_MASK_LO); 633 634 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_LO) & 635 MSGF_MSI_SR_LO_MASK, MSGF_MSI_STATUS_LO); 636 637 nwl_bridge_writel(pcie, MSGF_MSI_SR_LO_MASK, MSGF_MSI_MASK_LO); 638 639 return 0; 640 err: 641 kfree(msi->bitmap); 642 msi->bitmap = NULL; 643 return ret; 644 } 645 646 static int nwl_pcie_bridge_init(struct nwl_pcie *pcie) 647 { 648 struct device *dev = pcie->dev; 649 struct platform_device *pdev = to_platform_device(dev); 650 u32 breg_val, ecam_val, first_busno = 0; 651 int err; 652 653 breg_val = nwl_bridge_readl(pcie, E_BREG_CAPABILITIES) & BREG_PRESENT; 654 if (!breg_val) { 655 dev_err(dev, "BREG is not present\n"); 656 return breg_val; 657 } 658 659 /* Write bridge_off to breg base */ 660 nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_breg_base), 661 E_BREG_BASE_LO); 662 nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_breg_base), 663 E_BREG_BASE_HI); 664 665 /* Enable BREG */ 666 nwl_bridge_writel(pcie, ~BREG_ENABLE_FORCE & BREG_ENABLE, 667 E_BREG_CONTROL); 668 669 /* Disable DMA channel registers */ 670 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_PCIE_RX0) | 671 CFG_DMA_REG_BAR, BRCFG_PCIE_RX0); 672 673 /* Enable Ingress subtractive decode translation */ 674 nwl_bridge_writel(pcie, SET_ISUB_CONTROL, I_ISUB_CONTROL); 675 676 /* Enable msg filtering details */ 677 nwl_bridge_writel(pcie, CFG_ENABLE_MSG_FILTER_MASK, 678 BRCFG_PCIE_RX_MSG_FILTER); 679 680 /* This routes the PCIe DMA traffic to go through CCI path */ 681 if (of_dma_is_coherent(dev->of_node)) 682 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_PCIE_RX1) | 683 CFG_PCIE_CACHE, BRCFG_PCIE_RX1); 684 685 err = nwl_wait_for_link(pcie); 686 if (err) 687 return err; 688 689 ecam_val = nwl_bridge_readl(pcie, E_ECAM_CAPABILITIES) & E_ECAM_PRESENT; 690 if (!ecam_val) { 691 dev_err(dev, "ECAM is not present\n"); 692 return ecam_val; 693 } 694 695 /* Enable ECAM */ 696 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) | 697 E_ECAM_CR_ENABLE, E_ECAM_CONTROL); 698 699 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) | 700 (pcie->ecam_value << E_ECAM_SIZE_SHIFT), 701 E_ECAM_CONTROL); 702 703 nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_ecam_base), 704 E_ECAM_BASE_LO); 705 nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_ecam_base), 706 E_ECAM_BASE_HI); 707 708 /* Get bus range */ 709 ecam_val = nwl_bridge_readl(pcie, E_ECAM_CONTROL); 710 pcie->last_busno = (ecam_val & E_ECAM_SIZE_LOC) >> E_ECAM_SIZE_SHIFT; 711 /* Write primary, secondary and subordinate bus numbers */ 712 ecam_val = first_busno; 713 ecam_val |= (first_busno + 1) << 8; 714 ecam_val |= (pcie->last_busno << E_ECAM_SIZE_SHIFT); 715 writel(ecam_val, (pcie->ecam_base + PCI_PRIMARY_BUS)); 716 717 if (nwl_pcie_link_up(pcie)) 718 dev_info(dev, "Link is UP\n"); 719 else 720 dev_info(dev, "Link is DOWN\n"); 721 722 /* Get misc IRQ number */ 723 pcie->irq_misc = platform_get_irq_byname(pdev, "misc"); 724 if (pcie->irq_misc < 0) 725 return -EINVAL; 726 727 err = devm_request_irq(dev, pcie->irq_misc, 728 nwl_pcie_misc_handler, IRQF_SHARED, 729 "nwl_pcie:misc", pcie); 730 if (err) { 731 dev_err(dev, "fail to register misc IRQ#%d\n", 732 pcie->irq_misc); 733 return err; 734 } 735 736 /* Disable all misc interrupts */ 737 nwl_bridge_writel(pcie, (u32)~MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK); 738 739 /* Clear pending misc interrupts */ 740 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MISC_STATUS) & 741 MSGF_MISC_SR_MASKALL, MSGF_MISC_STATUS); 742 743 /* Enable all misc interrupts */ 744 nwl_bridge_writel(pcie, MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK); 745 746 747 /* Disable all legacy interrupts */ 748 nwl_bridge_writel(pcie, (u32)~MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK); 749 750 /* Clear pending legacy interrupts */ 751 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_LEG_STATUS) & 752 MSGF_LEG_SR_MASKALL, MSGF_LEG_STATUS); 753 754 /* Enable all legacy interrupts */ 755 nwl_bridge_writel(pcie, MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK); 756 757 /* Enable the bridge config interrupt */ 758 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_INTERRUPT) | 759 BRCFG_INTERRUPT_MASK, BRCFG_INTERRUPT); 760 761 return 0; 762 } 763 764 static int nwl_pcie_parse_dt(struct nwl_pcie *pcie, 765 struct platform_device *pdev) 766 { 767 struct device *dev = pcie->dev; 768 struct resource *res; 769 770 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "breg"); 771 pcie->breg_base = devm_ioremap_resource(dev, res); 772 if (IS_ERR(pcie->breg_base)) 773 return PTR_ERR(pcie->breg_base); 774 pcie->phys_breg_base = res->start; 775 776 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcireg"); 777 pcie->pcireg_base = devm_ioremap_resource(dev, res); 778 if (IS_ERR(pcie->pcireg_base)) 779 return PTR_ERR(pcie->pcireg_base); 780 pcie->phys_pcie_reg_base = res->start; 781 782 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg"); 783 pcie->ecam_base = devm_pci_remap_cfg_resource(dev, res); 784 if (IS_ERR(pcie->ecam_base)) 785 return PTR_ERR(pcie->ecam_base); 786 pcie->phys_ecam_base = res->start; 787 788 /* Get intx IRQ number */ 789 pcie->irq_intx = platform_get_irq_byname(pdev, "intx"); 790 if (pcie->irq_intx < 0) 791 return pcie->irq_intx; 792 793 irq_set_chained_handler_and_data(pcie->irq_intx, 794 nwl_pcie_leg_handler, pcie); 795 796 return 0; 797 } 798 799 static const struct of_device_id nwl_pcie_of_match[] = { 800 { .compatible = "xlnx,nwl-pcie-2.11", }, 801 {} 802 }; 803 804 static int nwl_pcie_probe(struct platform_device *pdev) 805 { 806 struct device *dev = &pdev->dev; 807 struct nwl_pcie *pcie; 808 struct pci_host_bridge *bridge; 809 int err; 810 811 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie)); 812 if (!bridge) 813 return -ENODEV; 814 815 pcie = pci_host_bridge_priv(bridge); 816 817 pcie->dev = dev; 818 pcie->ecam_value = NWL_ECAM_VALUE_DEFAULT; 819 820 err = nwl_pcie_parse_dt(pcie, pdev); 821 if (err) { 822 dev_err(dev, "Parsing DT failed\n"); 823 return err; 824 } 825 826 err = nwl_pcie_bridge_init(pcie); 827 if (err) { 828 dev_err(dev, "HW Initialization failed\n"); 829 return err; 830 } 831 832 err = nwl_pcie_init_irq_domain(pcie); 833 if (err) { 834 dev_err(dev, "Failed creating IRQ Domain\n"); 835 return err; 836 } 837 838 bridge->sysdata = pcie; 839 bridge->ops = &nwl_pcie_ops; 840 841 if (IS_ENABLED(CONFIG_PCI_MSI)) { 842 err = nwl_pcie_enable_msi(pcie); 843 if (err < 0) { 844 dev_err(dev, "failed to enable MSI support: %d\n", err); 845 return err; 846 } 847 } 848 849 return pci_host_probe(bridge); 850 } 851 852 static struct platform_driver nwl_pcie_driver = { 853 .driver = { 854 .name = "nwl-pcie", 855 .suppress_bind_attrs = true, 856 .of_match_table = nwl_pcie_of_match, 857 }, 858 .probe = nwl_pcie_probe, 859 }; 860 builtin_platform_driver(nwl_pcie_driver); 861